Test Circuit, Display Panel and Display Device

Abstract

The present application discloses a test circuit, a display panel, and a display device. The test circuit includes: a substrate; a first wire layer disposed on the substrate, the first wire layer including a first wire extending in a first direction; a second wire layer located on a side of the first wire layer away from the substrate, the second wire layer including a second wire extending in a second direction, the second wire including an overlapping section, and a positive projection of the overlapping section on the substrate and a positive projection of the first wire layer on the substrate are at least partially overlapped; an electrostatic discharge portion disposed on at least one side of the overlapping section in the second direction, and the electrostatic discharge portion is configured to discharge static electricity of the second wire. In the test circuit provided by the embodiments of the present application, the electrostatic discharge portion is disposed on at least one side of the overlapping section in the second direction, and the electrostatic discharge portion can discharge the static electricity on the second wire, thereby improving the problem that the static electricity is conducted to the overlapping section to break down the first wire.

Description

Technical Field

[0001] The present application relates to the field of displays, and particularly to a test circuit, a display panel, and a display device. Background Art

[0002] With the continuous update of display panel technology, small-sized display panels are gradually developing towards being thinner, lighter, having a higher screen-to-body ratio, ultra-narrow bezels, or even borderless. A display panel with a traditional structure usually includes a display area and a non-display area located on the periphery of the display area. In display technology, in order to reduce the size of the non-display area, a multi-layer circuit structure is provided. However, the multi-layer circuit structure results in poor anti-static strike resistance of the display panel. There will be capacitance between two stacked wires, and static electricity may break down the wires through this capacitance, resulting in a low yield of the display panel. Summary of the Invention

[0003] Embodiments of the present application provide a test circuit, a display panel, and a display device, aiming to improve the yield of the display panel.

[0004] An embodiment of the first aspect of the present application provides a test circuit. The test circuit includes: a substrate; a first wire layer disposed on the substrate, the first wire layer including a first wire extending in a first direction; a second wire layer located on a side of the first wire layer away from the substrate, the second wire layer including a second wire extending in a second direction, the second wire including an overlapping section, and a positive projection of the overlapping section on the substrate and a positive projection of the first wire layer on the substrate are overlapped; an electrostatic discharge part disposed on at least one side of the overlapping section in the second direction, and the electrostatic discharge part is used for discharging the static electricity of the second wire.

[0005] According to an embodiment of the first aspect of the present application, the electrostatic discharge part includes a discharge wire, the discharge wire includes a main body part and an electrostatic discharge end disposed at one end of the main body part, and at least a part of a positive projection of the electrostatic discharge end on the substrate overlaps at least a part of a positive projection of the second wire on the substrate.

[0006] According to any of the foregoing embodiments of the first aspect of the present application, the discharge wire and the second wire are insulated or the discharge wire and the second wire are connected by vias.

[0007] According to any of the foregoing embodiments of the first aspect of the present application, the discharge wire is disposed on the first wire layer.

[0008] According to any of the foregoing embodiments of the first aspect of the present application, the number of the electrostatic discharge ends is multiple, the multiple electrostatic discharge ends are arranged side by side and spaced apart in the second direction and connected to the main body part, and positive projections of each electrostatic discharge end on the substrate respectively overlap at least a part of a positive projection of the second wire on the substrate.

[0009] According to any of the foregoing embodiments of the first aspect of the present application, in a direction away from the main body portion, the extension width of the static electricity release end gradually decreases in the second direction.

[0010] According to any of the foregoing embodiments of the first aspect of the present application, the static electricity release portion further includes a release capacitor, and the release capacitor includes a first electrode plate and a second electrode plate stacked in the thickness direction of the substrate, and one of the first electrode plate and the second electrode plate is electrically connected to the release wire.

[0011] According to any of the foregoing embodiments of the first aspect of the present application, both the first electrode plate and the release wire are located in the first wire layer and are connected to each other.

[0012] According to any of the foregoing embodiments of the first aspect of the present application, the second electrode plate is located in the third wire layer, and the third wire layer is located between the first wire layer and the second wire layer.

[0013] According to any of the foregoing embodiments of the first aspect of the present application, there are at least two release wires, and the static electricity release ends of the at least two release wires are located on both sides of the overlapping section in the second direction, and the first electrode plate is connected between the release wires where the static electricity release ends located on both sides of the overlapping section in the second direction are located.

[0014] According to any of the foregoing embodiments of the first aspect of the present application, the overlapping area of the orthographic projections of the first electrode plate and the second electrode plate on the substrate is greater than or equal to the overlapping area of the overlapping section and the first wire on the substrate.

[0015] According to any of the foregoing embodiments of the first aspect of the present application, the number of the second wires is multiple, the overlapping sections of the multiple second wires are arranged at intervals in the first direction, and static electricity release portions are arranged on at least one side in the second direction of the overlapping section of each second wire.

[0016] According to any of the foregoing embodiments of the first aspect of the present application, the release capacitors of the multiple static electricity release portions are connected in parallel with each other.

[0017] According to any of the foregoing embodiments of the first aspect of the present application, the second electrode plates of the release capacitors of the multiple static electricity release portions are connected in parallel with each other.

[0018] According to any of the foregoing embodiments of the first aspect of the present application, the test circuit further includes a power supply line, and the second electrode plate is connected to the power supply line.

[0019] According to any of the foregoing embodiments of the first aspect of the present application, the overlapping area of the orthographic projections of the overlapping section and the first wire on the substrate is greater than or equal to 450 μm 2 。

[0020] According to any of the foregoing embodiments of the first aspect of the present application, the line width of the first wire is greater than or equal to 30 μm, and the line width of the second wire is greater than or equal to 15 μm.

[0021] According to any of the aforementioned embodiments of the first aspect of the present application, the electrostatic release unit includes a transistor, the transistor includes a source, a drain and a gate, and the drain and the gate are connected to each other;

[0022] The test circuit further includes a power signal line, one of the source and the drain of the transistor is electrically connected to the second conductive line, and the other is electrically connected to the power signal line.

[0023] According to any of the above embodiments of the first aspect of the present application, the power signal line includes a first signal line, a source and a second wire are electrically connected, a drain and the first signal line are electrically connected, and a voltage on the second wire is greater than V Gh +n|V Th |, where V Gh is the voltage on the first signal line, V Th is the on-state voltage of the source and drain of the transistor, and n is the number of transistors connected between the second wire and the first signal line.

[0024] According to any of the above embodiments of the first aspect of the present application, the power signal line includes a second signal line, the source is electrically connected to the second signal line, the drain is electrically connected to the second wire, and the voltage on the second wire is less than V GL -m|V Th |, where V GL is the voltage on the second signal line, V Th is the on-state voltage of the source and drain of the transistor, and m is the number of transistors connected between the second wire and the second signal line.

[0025] According to any of the aforementioned embodiments of the first aspect of the present application, more than two transistors are connected between the second wire and the power signal line.

[0026] According to any of the aforementioned embodiments of the first aspect of the present application, the source and the drain are located in the second wire layer.

[0027] According to any of the aforementioned implementations of the first aspect of the present application, the gate is located in the first wire layer.

[0028] According to any of the aforementioned embodiments of the first aspect of the present application, it further includes a chip pad and a test pad, and at least part of the second wire is connected between the chip pad and the test pad;

[0029] At least one electrostatic release portion is located on a side of the chip pad away from the overlapping section on the second conductive line connected thereto, and / or at least one electrostatic release portion is located between the overlapping section and the test pad.

[0030] An embodiment of the second aspect of the present application further provides a display panel, comprising a test circuit of any one of the above-mentioned embodiments of the first aspect.

[0031] According to an embodiment of the second aspect of the present application, the display panel includes a display area and a cutting area, and at least part of the test circuit is located in the display area or the cutting area.

[0032] According to any one of the foregoing embodiments of the second aspect of the present application, at least part of the first wire is located in the cutting area.

[0033] According to any one of the foregoing embodiments of the second aspect of the present application, at least part of the electrostatic discharge part is located in the cutting area.

[0034] According to any one of the foregoing embodiments of the second aspect of the present application, the first wire is a detection wire and is used to transmit a data control signal.

[0035] According to any one of the foregoing embodiments of the second aspect of the present application, the second wire includes a clock wire.

[0036] An embodiment of the second aspect of the present application further provides a display device, which is formed by the display panel of any one of the foregoing first aspect embodiments.

[0037] In the test circuit provided by the embodiment of the present application, the test circuit includes a substrate and a first wire layer, a second wire layer, and an electrostatic discharge part disposed on the substrate. The first wire layer includes a first wire, and the second wire layer includes a second wire. Since the first wire and the second wire extend in different directions, an overlapping section of the second wire overlaps at least part of the first wire. The second wire layer is located on a side of the first wire layer away from the substrate. During the preparation process of the second wire layer, since the second wire layer is exposed to the air, static electricity is likely to be generated on the second wire layer. Since the overlapping section of the second wire layer and the first wire layer are at least partially overlapped, a parasitic capacitance is generated between the overlapping section and the first wire layer, and static electricity is easily discharged through the overlapping section to break down the first wire, resulting in poor connection of the first wire. In the test circuit provided by the embodiment of the present application, an electrostatic discharge part is disposed on at least one side of the overlapping section in the second direction, and the electrostatic discharge part can release the static electricity on the second wire, thereby improving the problem that the static electricity is conducted to the overlapping section to break down the first wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] By reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, other features, objects, and advantages of the present application will become more apparent, wherein the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0039] Figure 1 A top view schematic diagram of a display panel showing an embodiment of the present application;

[0040] Figure 2 is Figure 1 A partial enlarged view of the Q area in one example;

[0041] Figure 3 is Figure 2 a partial cross-sectional view at F-F in

[0042] Figure 4 is Figure 2 a partially enlarged structural schematic diagram of region P in

[0043] Figure 5 in another embodiment Figure 2 a partially enlarged structural schematic diagram at P in

[0044] Figure 6 in yet another embodiment Figure 2 a partially enlarged structural schematic diagram at P in

[0045] Figure 7 in yet another embodiment Figure 1 a partially enlarged structural schematic diagram at Q in

[0046] Figure 8 is Figure 7 a partially enlarged structural schematic diagram at I in

[0047] Figure 9 is Figure 7 a partially enlarged structural schematic diagram at I in another embodiment

[0048] Figure 10 in yet another embodiment Figure 7 a partially enlarged structural schematic diagram at I in

[0049] Figure 11 in still another embodiment Figure 7 a partially enlarged structural schematic diagram at I in

[0050] Explanation of reference numerals:

[0051] 100, display panel; 100a, test circuit;

[0052] 10, substrate;

[0053] 20, first wire layer; 21, first wire;

[0054] 30, second wire layer; 31, second wire; 311, overlapping section;

[0055] 40, electrostatic discharge part; 41, discharge wire; 411, electrostatic discharge end; 412, main body part; 42, discharge capacitor; 421, first electrode plate; 422, second electrode plate; 43, transistor; 431, source electrode; 432, drain electrode; 433, gate electrode;

[0056] 50, third wire layer;

[0057] 60, Power signal line; 61, First signal line; 62, Second signal line;

[0058] 70, Test pad;

[0059] 80, Chip pad;

[0060] AA, Display area; NA, Non-display area; GP, Chip pad area; CA, Cutting area; LA, Trace area; CP, Test pad area;

[0061] X, First direction; Y, Second direction; Z, Thickness direction. Detailed implementation mode

[0062] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0063] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0064] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or region.

[0065] With the continuous update of display panel technology, small-sized display panels are gradually developing towards being thinner, lighter, having a higher screen-to-body ratio, ultra-narrow bezels, and even borderless. In order to narrow the bezel of the display device, in related technologies, the lighting test (Cell Test; CT) circuit on the display panel is set on the side of the integrated circuit (IC) pins of the display device away from the display area. After the CT test is completed, the CT circuit is selectively removed by secondary cutting.

[0066] When the CT circuit is set below the IC pins, the scan control signal line (such as the clock signal line) will overlap with the detection wires included in the CT circuit, which results in the formation of a parasitic capacitance between the scan control signal line and the detection wires. The detection wires include, for example, a red test line for testing red sub-pixels, a green test line for testing green sub-pixels, and a blue test line for testing blue sub-pixels.

[0067] The inventors found that during the preparation process of the display panel, the scan control signal line is located above the detection wires, that is, the scan control signal is prepared after the detection wires are prepared. And the scan control signal line will be exposed to the air for a period of time during the manufacturing process, which makes it extremely easy for static electricity to accumulate on the scan control signal line. The static electricity will charge the parasitic capacitance formed between the scan control signal line and the detection wires. When the charge quantity on the parasitic capacitance is large enough, according to ΔV = ΔQ / C, where ΔV is the voltage difference at the overlapping position of the scan control signal line and the detection wires, ΔQ is the charge quantity, and C is the capacitance. When the voltage difference is large, it is extremely easy to break down the detection wires, resulting in a micro short circuit between the scan control signal line and the detection wires, and in the subsequent manufacturing process, due to the heat generated by the short circuit of the wiring, the display device will malfunction and the screen cannot work.

[0068] The inventors further studied and found that among the detection wires, especially in the red test line and the green test line, due to the smaller line widths of the red test line and the green test line, the plate area of the parasitic capacitance is smaller. According to ΔV = ΔQ / C, the voltage difference will be larger, so the red test line and the green test line are more likely to be broken down.

[0069] To solve the above problems, the embodiments of the present application provide a test circuit, a display panel, and a display device. The following will describe the embodiments of the display panel and the display device with reference to the accompanying drawings.

[0070] The embodiments of the present application provide a display panel, and the display panel may be an Organic Light Emitting Diode (OLED) display panel.

[0071] Please refer to Figures 1 to 3 , Figure 1 which shows a top view schematic diagram of a display panel 100 according to an embodiment of the present application.Figure 2 An exemplary Figure 1 partial enlarged view of the Q region in Figure 3 is Figure 2 a cross-sectional view taken along line F-F in

[0072] As Figures 1 to 3 shown, the display panel 100 provided by an embodiment of the present application includes a test circuit 100a.

[0073] There are various ways to set the test circuit 100a. Please continue to refer to Figures 1 to 3 , the test circuit 100a for the display panel 100 provided by an embodiment of the present application includes: a substrate 10, a first wire layer 20, a second wire layer 30, and an electrostatic discharge part 40; the first wire layer 20 is disposed on the substrate 10, and the first wire layer 20 includes a first wire 21 extending along a first direction; the second wire layer 30 is located on a side of the first wire layer 20 away from the substrate 10, the second wire layer 30 includes a second wire 31 extending along a second direction, the second wire 31 includes an overlapping section 311, and a positive projection of the overlapping section 311 on the substrate 10 and a positive projection of the first wire layer 20 on the substrate 10 are overlapped; the electrostatic discharge part 40 is disposed on at least one side of the overlapping section 311 in the second direction, and the electrostatic discharge part 40 is used to release the static electricity of the second wire 31.

[0074] In the test circuit 100a for the display panel 100 provided by an embodiment of the present application, the display panel 100 includes a substrate 10 and a first wire layer 20, a second wire layer 30, and an electrostatic discharge part 40 disposed on the substrate 10. The first wire layer 20 includes a first wire 21, and the second wire layer 30 includes a second wire 31. Since the first wire 21 and the second wire 31 extend in different directions, at least a part of the overlapping section 311 of the second wire 31 overlaps with the first wire 21. The second wire layer 30 is located on a side of the first wire layer 20 away from the substrate 10. During the preparation process of the second wire layer 30, since the second wire layer 30 is exposed to the air, static electricity is likely to be generated on the second wire layer 30. Since at least a part of the overlapping section 311 of the second wire layer 30 and the first wire layer 20 are overlapped, a parasitic capacitance is generated between the overlapping section 311 and the first wire layer 20, and the static electricity is easily discharged through the overlapping section 311 to break down the first wire 21, resulting in poor connection of the first wire 21. In the test circuit 100a provided by an embodiment of the present application, the electrostatic discharge part 40 is disposed on at least one side of the overlapping section 311 in the second direction, and the electrostatic discharge part 40 can release the static electricity on the second wire 31, thereby improving the problem that the static electricity is conducted to the overlapping section 311 to break down the first wire 21.

[0075] The substrate 10 can be arranged in various ways. Optionally, the substrate 10 includes a substrate, which can be made of a light-transmitting material such as glass or polyimide (PI). The substrate 10 can also include a support layer on the side of the substrate facing away from the first conductive line layer 20, and the support layer can include a steel plate layer and / or a foam layer. A buffer layer and other layer structures can also be provided between the substrate and the first conductive line layer 20.

[0076] The first conductive line 21 can be arranged in various ways. For example, the first conductive line 21 is the above-mentioned detection conductive line CT. The second conductive line 31 can be arranged in various ways. For example, the second conductive line 31 is the above-mentioned scan control signal line GIP.

[0077] In these alternative embodiments, the electrostatic discharge unit 40 can discharge the static electricity on the scan control signal line GIP, reduce the amount of static electricity transmitted to the overlapping section 311, and thus improve the problem of the detection conductive line CT being broken down.

[0078] Optionally, the detection conductive line CT includes a first detection conductive line CT-R, a second detection conductive line CT-G, and a third detection conductive line CT-B. At least a part of the first detection conductive line CT-R, the second detection conductive line CT-G, and the third detection conductive line CT-B all extend in the first direction, and the parts of the first detection conductive line CT-R, the second detection conductive line CT-G, and the third detection conductive line CT-B that extend in the first direction are arranged side by side in the second direction.

[0079] Optionally, the second conductive line 31 includes overlapping sections 311 that respectively overlap with the first detection conductive line CT-R, the second detection conductive line CT-G, and the third detection conductive line CT-B. The electrostatic discharge unit 40 is located on at least one side of all the overlapping sections 311 in the second direction to reduce the risk of transmitting to any one of the overlapping sections 311 and breaking down any one of the first detection conductive line CT-R, the second detection conductive line CT-G, and the third detection conductive line CT-B.

[0080] Optionally, the scan control signal line GIP includes a first signal line ECK1, a second signal line ECK2, a third signal line SIN, a fourth signal line SCK1, and a fifth signal line SCK2. At least a part of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 extends in the second direction, and the parts of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 that extend in the second direction are arranged side by side in the first direction. Overlap segments 311 are provided on each of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2, and electrostatic discharge parts 40 are provided on at least one side in the second direction of the overlap segments 311 of each of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2.

[0081] Optionally, an insulating layer is provided between the first conductive layer 20 and the second conductive layer 30 to ensure insulation between the first conductor 21 and the second conductor 31 and prevent short-circuit connection between the first conductor 21 and the second conductor 31.

[0082] Optionally, please continue to refer to Figures 1 to 3 , the display panel 100 further includes a display area AA and a non-display area NA surrounding the display area AA. The first conductor 21 and the overlap segment 311 are both located in the non-display area NA.

[0083] Please refer to Figures 2 to 4 , Figure 4 is Figure 2 a schematic diagram of a partial enlarged structure of the P region in

[0084] As Figures 2 to 4 shown, in some alternative embodiments, the electrostatic discharge part 40 includes a discharge wire 41. The discharge wire 41 includes a main body part 412 and an electrostatic discharge end 411 provided at one end of the main body part 412, and at least a part of the orthographic projection of the electrostatic discharge end 411 on the substrate 100 overlaps at least a part of the orthographic projection of the second conductor 31 on the substrate 100.

[0085] In these alternative embodiments, at least a part of the orthographic projection of the electrostatic discharge end 411 of the discharge wire 41 and the second conductor 31 overlaps, so that static electricity can be conducted to the electrostatic discharge end 411 and the static electricity can be discharged through the electrostatic discharge end 411. Moreover, the setting method of the electrostatic discharge part 40 is simple, which is convenient for the preparation of the electrostatic discharge part 40.

[0086] There are various ways to set the connection between the release wire 41 and the second wire 31. For example, an insulating layer is provided between the release wire 41 and the second wire 31, and the release wire 41 and the second wire 31 can be insulated from each other and a parasitic capacitance is formed.

[0087] Alternatively, in some other alternative embodiments, an insulating layer is provided between the release wire 41 and the second wire 31, and an opening is provided on the insulating layer. The release wire 41 and the second wire 31 are connected through a via hole, that is, the release wire 41 and the second wire 31 are electrically connected, so that the static electricity on the second wire 31 can be directly conducted to the release wire 41 and the static electricity is released through the release wire 41.

[0088] There are various ways to set the layer position of the release wire 41. Optionally, the release wire 41 can be arranged on the same layer as the first wire 21, that is, the release wire 41 is located in the first wire layer 20, so that the release wire 41 can be prepared synchronously with the first wire 21, which can simplify the preparation method of the display template and improve the preparation efficiency of the test circuit 100a. In some other alternative embodiments, the release wire 41 and the first wire 21 can also be arranged on different layers.

[0089] There are various ways to set the static electricity release end 411, such as Figure 4 As shown, each release wire 41 can include a static electricity release end 411.

[0090] In some other alternative embodiments, please refer to Figure 2 and Figure 5 , Figure 5 is a partial enlarged structural schematic diagram of the P position in another embodiment Figure 2 .

[0091] In some other alternative embodiments, such as Figure 2 and Figure 5 shown, the number of the static electricity release ends 411 is multiple. The multiple static electricity release ends 411 are arranged side by side at intervals in the second direction and are connected to the main body portion 412. The orthographic projections of the respective static electricity release ends 411 on the substrate 100 at least partially overlap with the orthographic projection of the second wire 31 on the substrate 100.

[0092] In these alternative embodiments, by connecting multiple static electricity release ends 411 to the main body portion 412 and each static electricity release end 411 overlaps with the second wire 31, the release ability of the release wire 41 can be improved, so that the release wire 41 can release more static electricity.

[0093] Please refer to Figure 2 and Figure 6 , Figure 6 is a partial enlarged structural schematic diagram of the P position in yet another embodiment Figure 2 .

[0094] In some alternative embodiments, such as Figure 2 and Figure 6 shown, along the direction away from the main body portion 412, the extending width of the static electricity release end 411 gradually decreases in the second direction. This can further improve the static electricity release ability of the static electricity release end 411.

[0095] Please continue to refer to Figure 2 , in some alternative embodiments, the static electricity release portion 40 further includes a release capacitor 42. The release capacitor 42 includes a first electrode plate 421 and a second electrode plate 422 stacked along the thickness direction of the substrate 10, and one of the first electrode plate 421 and the second electrode plate 422 is electrically connected to the release wire 41.

[0096] In these alternative embodiments, the release wire 41 is connected to the first electrode plate 421 or the second electrode plate 422 of the release capacitor 42, so that static electricity can be conducted by the release wire 41 and stored in the release capacitor 42, which can improve the static electricity release ability of the static electricity release portion 40.

[0097] There are various setting positions for the first electrode plate 421 and the second electrode plate 422. In some alternative embodiments, both the first electrode plate 421 and the release wire 41 are located in the first wire layer 20 and are electrically connected. Such a setting enables the first electrode plate 421, the release wire 41, and the first wire 21 to be formed in the same process step, which can effectively improve the preparation efficiency of the test circuit 100a.

[0098] Optionally, the second electrode plate 422 is located in the third wire layer 50, and the third wire layer 50 is located between the first wire layer 20 and the second wire layer 30. That is, the second electrode plate 422 is located on the side of the third wire layer 50 facing the substrate 10. During the preparation process of the test circuit 100a, when the second wire layer 30 is exposed to the air, it can prevent the second electrode plate 422 from being exposed to the air, thereby avoiding the accumulation of static electricity on the second electrode plate 422, so that the release capacitor 42 can store more static electricity accumulated on the second wire 31.

[0099] In some other embodiments, the third wire layer 50 can also be located between the first wire layer 20 and the substrate 10.

[0100] Optionally, a first insulating layer is provided between the first wire layer 20 and the third wire layer 50, and a second insulating layer is provided between the third wire layer 50 and the second wire layer 30 to ensure that the first wire 21, the first electrode plate 421, the second wire 31, and the second electrode plate 422 are insulated from each other in pairs.

[0101] In some alternative embodiments, there are at least two release wires 41, and the static electricity release ends 411 of the at least two release wires 41 are located on both sides of the overlapping section 311 in the second direction.

[0102] In these alternative embodiments, release conductors 41 are correspondingly arranged on both sides of the overlapping section 311 in the second direction. Therefore, it is possible to reduce the static electricity generated on both sides of the overlapping section 311 in the second direction from being conducted to the position where the overlapping section 311 is located, further improving the static electricity release ability of the static electricity release portion 40 and improving the problem of the first conductor 21 being broken down.

[0103] Optionally, the first electrode plate 421 is connected between the release conductors 41 where the two static electricity release ends 411 located on both sides of the overlapping section 311 in the second direction are located. This enables the static electricity generated on both sides of the overlapping section 311 in the second direction to be conducted to the release capacitor 42, further improving the static electricity release ability of the static electricity release portion 40 and better improving the problem of the first conductor 21 being broken down.

[0104] In some alternative embodiments, the overlapping area of the projections of the overlapping section 311 and the first conductor 21 on the substrate 10 is greater than or equal to 450 μm 2 . For example, the overlapping area of the projections of the overlapping section 311 and the first conductor 21 on the substrate 10 is 15 μm × 30 μm; or the overlapping area of the projections of the overlapping section 311 and the first conductor 21 on the substrate 10 is 15 μm × 45 μm; or the overlapping area of the projections of the overlapping section 311 and the first conductor 21 on the substrate 10 is 15 μm × 60 μm. In these alternative embodiments, the larger the overlapping area of the projections of the overlapping section 311 and the first conductor 21 on the substrate 10, the larger the parasitic capacitance C formed between the overlapping section 311 and the first conductor 21. According to ΔV = ΔQ / C, the smaller the pressure difference formed between the overlapping section 311 and the first conductor 21, and the less likely it is to be broken down.

[0105] Optionally, the line width of the first conductor 21 is greater than 30 μm. The line width of the second conductor 31 is usually 15 μm. When the line width of the first conductor 21 is greater than 30 μm, it can ensure that the overlapping area of the projections of the overlapping section 311 and the first conductor 21 on the substrate 10 is greater than or equal to 450 μm 2 , and it is less likely to be broken down. Optionally, the line width of the second conductor 31 is greater than or equal to 15 μm.

[0106] In some alternative embodiments, the overlapping area of the projections of the first electrode plate 421 and the second electrode plate 422 on the substrate 10 is greater than or equal to the overlapping area of the projections of the overlapping section 311 and the first conductor 21 on the substrate 10. This enables the capacitance of the release capacitor 42 to be greater than the capacitance of the parasitic capacitance formed between the overlapping section 311 and the first conductor 21, and can further reduce the load at the parasitic capacitance, thereby improving the problem of the first conductor 21 being broken down.

[0107] There are various ways to set the number of the second conductors 31. For example, the number of the second conductors 31 can be only one.

[0108] In some other alternative embodiments, the number of the second conductors 31 is multiple. For example, as described above, the second conductors 31 may include a first signal line ECK1, a second signal line ECK2, a third signal line SIN, a fourth signal line SCK1, and a fifth signal line SCK2. The first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 all include overlapping segments 311, and the overlapping segments 311 of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 are arranged at intervals in the first direction. That is, the overlapping segments 311 of the multiple second conductors 31 are arranged at intervals in the first direction, and static electricity release parts 40 are arranged on at least one side of the overlapping segments 311 of each second conductor 31 in the second direction.

[0109] In these alternative embodiments, the number of the second conductors 31 is multiple, and the second conductors 31 all overlap with the first conductor 21 to form overlapping segments 311. The overlapping segments 311 of each second conductor 31 overlap with different positions of the first conductor 21, and there is a risk of being broken down by parasitic capacitance at different positions of the first conductor 21. In this embodiment, static electricity release parts 40 are arranged on at least one side of each overlapping segment 311 in the second direction, which can improve the risk of breakdown at different positions on the first conductor 21.

[0110] Optionally, the second plates 422 of the release capacitors 42 of the multiple static electricity release parts 40 are connected in parallel with each other. This enables the static electricity on different second plates 422 to conduct with each other, further improving the static electricity release ability of the static electricity release parts 40.

[0111] In some alternative embodiments, the test circuit 100a further includes a power supply line Vdd, and the second plate 422 is connected to the power supply line. The power supply line has the characteristic of stable signal, making the signal on the release capacitor 42 stable and capable of avoiding the disturbance caused by the unstable signal of the release capacitor 42.

[0112] Please refer to Figure 1 、 Figures 7 to 9 , Figure 7 which is the schematic diagram of the partial enlarged structure at Q in Figure 1 in another embodiment, Figure 8 is Figure 7 the schematic diagram of the partial enlarged structure at I in Figure 9 is Figure 7 the schematic diagram of the partial enlarged structure at I in another embodiment.

[0113] In some other embodiments, such as Figure 1 、 Figures 7 to 9As shown, the electrostatic discharge part 40 includes a transistor 43. The transistor 43 includes a source electrode 431, a drain electrode 432, and a gate electrode 433, and the drain electrode 432 and the gate electrode 433 are in communication with each other. The test circuit 100a further includes a power supply signal line 60. One of the source electrode 431 and the drain electrode 432 of the transistor 43 is electrically connected to the second wire 31, and the other is electrically connected to the power supply signal line 60.

[0114] In these alternative embodiments, when static electricity is generated on the second wire 31, the static electricity on the second wire 31 can be conducted to the power supply signal line 60 through the transistor 43. The type of the transistor 43 can be an N-type transistor or a P-type transistor. In the embodiments of the present application, the transistor 43 is taken as an example of a P-type transistor for illustration.

[0115] There are various ways to set the power supply signal line 60, such as Figure 8 As shown, the power supply signal line 60 can be the first signal line 61. The source electrode 431 is electrically connected to the second wire 31, and the drain electrode 432 is electrically connected to the first signal line 61. For example, when there are n transistors 43 connected between the second wire 31 and the first signal line 61, if the voltage V 31 on the second wire 31 is greater than V Gh +n|V Th |, then the n transistors 43 are turned on, and the voltage on the second wire 31 will pass through the n transistors 43 to the first signal line 61. Therefore, the voltage V 31 on the second wire 31 is less than or equal to V Gh +n|V Th . Where V Gh is the voltage on the first signal line 61. For example, the first signal line 61 is a high-level signal line, V Gh is 7V, and V Th is the conduction voltage between the source electrode 431 and the drain electrode 432 of the transistor 43.

[0116] In these alternative embodiments, by reasonably setting the number of transistors 43, that is, by changing the number of n in V Gh +n|V Th |, the voltage V 31 on the second wire 31 can be limited to an appropriate voltage value.

[0117] In some other embodiments, as Figure 9 shown, the power supply signal line 60 can be the second signal line 62. The source electrode 431 is electrically connected to the second signal line 62, and the drain electrode 432 is electrically connected to the second wire 31.

[0118] In these alternative embodiments, when there are m transistors 43 connected between the second wire 31 and the second signal line 62, if the voltage V 31 on the second wire 31 is less than VGL -m|V Th |, then m transistors 43 are turned on, and the voltage of the second signal line 62 will pass through the m transistors 43 to the second wire 31. Therefore, the voltage V on the second wire 31 31 is greater than or equal to V GL -m|V Th |, where V GL is the voltage on the second signal line 62. For example, the second signal line 62 is a low-level signal line, V GL is -7V, and V Th is the conduction voltage of the source 431 and the drain 432 of the transistor 43.

[0119] In these alternative embodiments, by reasonably setting the number of transistors 43, that is, by changing the number of m in V GL -m|V Th |, the voltage V on the second wire 31 31 can be limited to a suitable voltage value.

[0120] Please refer to Figure 7 and Figure 10 , Figure 10 which is a schematic diagram of the partial enlarged structure at I in another embodiment Figure 7 .

[0121] Optionally, as shown in Figure 7 and Figure 10 , the power supply signal line 60 can include either the first signal line 61 or the second signal line 62. In these embodiments, when the electrostatic potential energy on the second wire 31 is higher than that of the first signal line 61, the static electricity can conduct to the first signal line 61. When the static electricity on the second wire 31 is lower than that of the first signal line 61, the holes on the second signal line 62 can conduct to the second wire 31 and neutralize the static electricity on the second wire 31 to reduce the static electricity. The static voltage on the second wire 31 is greater than or equal to V GL -|V Th |, and less than or equal to V Gh +|V Th |.

[0122] Optionally, as shown in Figure 11 , there are more than two transistors 43 connected between the second wire 31 and the power supply signal line 60. For example, there are two transistors 43 arranged between the second wire 31 and the second signal line 62, and two transistors 43 arranged between the second wire 31 and the first signal line 61. Then the static voltage on the second wire 31 is greater than or equal to V GL -2|V Th |, and less than or equal to V Gh +2|V Th|. The electrostatic potential on the second conductor 31 can be limited to a smaller range.

[0123] Optionally, the source 431 and the drain 432 are located in the second wire layer 30 , so that the second wire 31 can be prepared and formed in the same process as the source 431 and the drain 432 , and the second wire 31 can be easily connected to the source 431 or the drain 432 .

[0124] Optionally, the gate 433 is located in the first conductive line layer 20 , so that the gate 433 and the first conductive line 21 can be manufactured and formed in the same process, which helps to improve the manufacturing efficiency of the test circuit 100 a .

[0125] Optionally, the transistor 43 also includes a first semiconductor part, the test circuit 100a also includes a driving transistor TFT, the driving transistor TFT includes a second semiconductor part, and the first semiconductor part and the second semiconductor part are arranged in the same layer, so that the first semiconductor part and the second semiconductor part can be prepared and formed in the same process flow, which can further improve the preparation efficiency of the test circuit 100a.

[0126] Optionally, the source 431 and drain 432 of the driving transistor may be disposed in the same layer as the source 431 and drain 432 of the transistor 43. The gate 433 of the driving transistor may be disposed in the same layer as the gate 433 of the transistor 43, which can further improve the manufacturing efficiency of the test circuit 100a.

[0127] In some optional embodiments, the test circuit 100 a further includes a chip pad 80 and a test pad 70 , and at least a portion of the second conductive line 31 is connected between the chip pad 80 and the test pad 70 .

[0128] The static electricity release portion 40 may be disposed at various locations. For example, at least one static electricity release portion 40 is located on a side of the chip pad 80 away from the overlapping section of the second wire 31 connected thereto, so as to release static electricity generated on the chip pad 80 .

[0129] And / or, at least one static electricity releasing portion 40 is located between the overlapping section 311 and the test pad 70 , so as to release static electricity generated by the test pad 70 and reduce the amount of static electricity transmitted from the test pad 70 to the overlapping section 311 .

[0130] And / or, at least one static electricity release portion 40 is located between the overlapping section 311 and the chip pad 80 , which can reduce the amount of static electricity conducted from the chip pad 80 to the overlapping section 311 .

[0131] Optional, please continue to Figure 3, in the direction away from the display area AA, the non-display area NA includes a chip pad area GP, a cutting area CA, a wiring area LA, and a test pad area CP arranged in sequence. The chip pad 80 is located in the pad area GA, the first wire 21 is located in the wiring area LA, and the test pad 70 is located in the test pad area CP. When cutting the display panel 100 to form a display panel, the wiring area LA and the test pad area CP can be cut off to achieve a narrow border design of the display panel.

[0132] In some alternative embodiments, the display panel 100 further includes a cutting area CA, and at least part of the test circuit 100a is located in the cutting area CA. When cutting the display panel 100 to form a display device, at least part of the test circuit 100a can be cut off, which can reduce the area of the non-display area of the display device and achieve a narrow border design of the display device.

[0133] Optionally, the electrostatic discharge part 40 is located in the cutting area CA. When cutting the display panel 100 to form a display device, the electrostatic discharge part 40 can be cut off, which can reduce the area of the non-display area of the display device and achieve a narrow border design of the display device.

[0134] Optionally, the display panel 100 can be a display mother board including a plurality of display areas AA, and the display mother board includes the above-mentioned cutting area CA. When processing the display mother board to form a display board for preparing a display screen, the above-mentioned electrostatic discharge part 40 can be cut, that is, the display board for preparing a display screen may not include the electrostatic discharge part 40.

[0135] Optionally, in some other embodiments, the display panel 100 can also be a display board for preparing a display screen, that is, the display panel 100 does not include the cutting area CA, and the electrostatic discharge part 40 can also be located in the non-cutting area of the display panel 100, that is, the electrostatic discharge part 40 can be a display board for preparing a display screen.

[0136] In some alternative embodiments, the first wire 21 is located in the cutting area CA. When cutting the display panel 100 to form a display device, the first wire 21 can be cut off, which can reduce the area of the non-display area of the display device and achieve a narrow border design of the display device.

[0137] As above, the first wire 21 can be a detection wire and is used to transmit a control signal. The first wire 21 is used to perform a lighting test on the display device before cutting to form the display device. The first wire 21 is not required during the use of the display device, so the first wire 21 can be located in the cutting area CA.

[0138] An embodiment of the present invention further provides a display device, which includes the display panel of any one of the above-mentioned first aspect embodiments. Therefore, the display device provided by the second aspect embodiment of the present invention has the beneficial effects of the display panel of any one of the above-mentioned first aspect embodiments, which will not be elaborated herein.

[0139] The display device in the embodiment of the present invention includes, but is not limited to, devices with display functions such as mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline telephones, and consoles.

[0140] In accordance with the embodiments of the present application as described above, these embodiments do not describe all details in detail, nor do they limit the invention to only specific embodiments. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A test circuit, characterized in that, include: substrate; A first wire layer, disposed on the substrate, the first wire layer comprising first wires extending along a first direction; a second wire layer, located on a side of the first wire layer away from the substrate, the second wire layer comprising a second wire extending along a second direction, the second wire being a scanning control signal line, the second wire comprising an overlapping segment, an orthographic projection of the overlapping segment on the substrate and an orthographic projection of the first wire layer on the substrate being arranged to overlap; an electrostatic release portion, disposed on at least one side of the overlapping section in the second direction, the electrostatic release portion being used to release static electricity of the second wire, the electrostatic release portion comprising a release wire, the release wire comprising a main body and an electrostatic release end disposed at one end of the main body, and an orthographic projection of the electrostatic release end on the substrate at least partially overlaps with an orthographic projection of the second wire on the substrate; Among them, the electrostatic release part also includes a release capacitor, and the release capacitor includes a first electrode plate and a second electrode plate stacked along the thickness direction of the substrate, and one of the first electrode plate and the second electrode plate is electrically connected to the release wire, and the overlapping area of ​​the orthographic projections of the first electrode plate and the second electrode plate on the substrate is greater than or equal to the overlapping area of ​​the orthographic projections of the overlapping segment and the first wire on the substrate. There are at least two release wires, and the electrostatic release ends of at least two release wires are located on both sides of the overlapping segment in the second direction. The first electrode is connected between the release wires where the electrostatic release ends of the overlapping segment in the second direction are located.

2. The test circuit according to claim 1, wherein The release conductor and the second conductor are insulated from each other or the release conductor and the second conductor are connected via a via hole.

3. The test circuit according to claim 1, wherein The release wire is arranged in the first wire layer.

4. The test circuit according to claim 1, characterized in that, There are multiple electrostatic release ends, which are arranged side by side and spaced apart along the second direction and connected to the main body. The orthographic projection of each electrostatic release end on the substrate at least partially overlaps with the orthographic projection of the second wire on the substrate.

5. The test circuit according to claim 1, wherein Along the direction away from the main body, the extension width of the static electricity release end in the second direction gradually decreases.

6. The test circuit according to claim 1, characterized in that, The first electrode plate and the release wire are both located in the first wire layer and are electrically connected.

7. The test circuit according to claim 1, wherein The second electrode plate is located in a third wire layer, and the third wire layer is located between the first wire layer and the second wire layer.

8. The test circuit according to claim 1, characterized in that There are a plurality of second conductive lines, the overlapping sections of the plurality of second conductive lines are arranged at intervals along the first direction, and each overlapping section is provided with the electrostatic release portion on at least one side of the second direction.

9. The test circuit according to claim 1, wherein The discharge capacitors of the plurality of electrostatic discharge units are connected in parallel to each other.

10. The test circuit according to claim 9, wherein, The second electrode plates of the release capacitors of the plurality of electrostatic release units are connected in parallel with each other.

11. The test circuit according to claim 10, wherein The test circuit also includes a power line, and the second electrode plate is connected to the power line.

12. The test circuit according to claim 1, characterized in that, The overlapping area of the overlapping segment and the orthographic projection of the first conductor on the substrate is greater than or equal to 450 μm 2 .

13. The test circuit according to claim 12, characterized in that, The line width of the first conductive line is greater than or equal to 30 μm, and the line width of the second conductive line is greater than or equal to 15 μm.

14. The test circuit according to claim 1, wherein Also comprising a chip pad and a test pad, at least part of the second wire is connected between the chip pad and the test pad; At least one of the static electricity release parts is located on one side of the overlapping section of the chip pad facing away from the second wire connected thereto. And / or, at least one of the static electricity release parts is located between the overlapping section and the test pad.

15. A display panel, characterized in that, The display panel includes the test circuit according to any one of claims 1-14.

16. The display panel according to claim 15, wherein The display panel includes a display area and a cutting area, and at least part of the test circuit is located in the display area or the cutting area.

17. The display panel according to claim 16, wherein The first wire is located in the cutting area.

18. The display panel according to claim 16, wherein The static electricity release part is located in the cutting area.

19. The display panel according to claim 16, wherein, The first wire is a detection wire and is used for transmitting a data control signal.

20. The display panel according to claim 16, wherein, The second wire includes a clock wire.

21. A display device, characterized in that, A display panel according to any one of claims 15-20 is included.

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