A gate driving circuit, a display panel and a gate driving method thereof

Abstract

The present application discloses a gate drive circuit, a display panel, and a gate drive method thereof. The gate drive circuit provided by the present application includes a control module, a voltage stabilization module, and an output module, wherein the control module receives a clock signal and an input signal and is electrically connected to a control node, and the control module is used to control the potential of the control node according to the clock signal and the input signal; the voltage stabilization module is electrically connected to the control node and is used to maintain the potential of the control node; the output module is electrically connected to the control node and is used to output a gate drive signal according to the potential of the control node. The present application uses a smaller number of transistors to achieve control of the gate drive signal, thereby optimizing the structure of the gate drive circuit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a gate driving method thereof. Background Art

[0002] The gate driver on array (GOA) circuit is a crucial component of today's display panels. Thin-film transistors (TFTs) are fabricated on the array substrate as switches, allowing the display panel's gate driver circuit to be fabricated on the array substrate, enabling progressive scanning of the gates. Because the GOA circuit reduces process steps and lowers costs, it is widely used in display panel manufacturing.

[0003] Currently, most display devices use low-temperature polysilicon (LTPS) panel technology. LTPS display panels offer advantages such as high resolution, high response speed, and high brightness. However, they have the disadvantages of high production costs and high power consumption. To address this, low-temperature polycrystalline silicon oxide (LTPO) panel technology has emerged. LTPO panel technology integrates low-temperature polysilicon transistors and oxide transistors on a single display panel. LTPO display panels not only have the advantages of LTPS display panels, but also have the advantages of low production costs and low power consumption.

[0004] However, the LTPO GOA circuit includes a GOA circuit that outputs an N-type drive signal, a GOA circuit that outputs a P-type drive signal, and a GOA circuit that outputs a light-emitting drive signal. Therefore, compared with the LTPS GOA circuit, the LTPO GOA circuit requires more devices to achieve driving, making it relatively more difficult to meet the panel market's requirements for narrow bezels or full screens. Summary of the Invention

[0005] The present application provides a gate drive circuit, a display panel, and a driving method thereof, which can optimize the structure of the gate drive circuit and realize the control of the gate drive signal; at the same time, the number of thin-film transistors can be reduced, which is conducive to meeting the process requirements of narrow-frame or full-screen display panels.

[0006] In a first aspect, the present application provides a gate drive circuit, comprising a control module, a voltage stabilization module, and an output module;

[0007] The control module receives a clock signal and an input signal and is electrically connected to a control node. The control module is used to control the potential of the control node according to the clock signal and the input signal.

[0008] The voltage stabilizing module is electrically connected to the control node, and is used to maintain the potential of the control node;

[0009] The output module is electrically connected to the control node, and is configured to output a gate driving signal according to the potential of the control node.

[0010] In the gate drive circuit provided in the present application, the output module includes a pull-up output control unit and a pull-down output control unit;

[0011] The pull-up output control unit receives a high potential signal and is electrically connected to the control node, and the pull-up output control module is used to pull up the gate drive signal based on the potential of the control node;

[0012] The pull-down output control unit receives a low potential signal and is electrically connected to the control node. The pull-down output control unit is used to pull down the gate driving signal according to the potential of the control node.

[0013] In the gate drive circuit provided in the present application, the pull-up output control unit includes a first P-type transistor, the gate of the first P-type transistor is electrically connected to the control node, one of the source and the drain of the first P-type transistor is connected to the high-voltage signal, and the other of the source and the drain of the first P-type transistor is electrically connected to the output node.

[0014] In the gate drive circuit provided in the present application, the pull-down output control unit includes an N-type transistor, the gate of the N-type transistor is electrically connected to the control node, one of the source and the drain of the N-type transistor is connected to the low-voltage signal, and the other of the source and the drain of the N-type transistor is electrically connected to the output node.

[0015] In the gate drive circuit provided in the present application, the control module includes a second P-type transistor, the gate of the second P-type transistor is connected to the clock signal, one of the source and the drain of the second P-type transistor is connected to the input signal, and the other of the source and the drain of the second P-type transistor is electrically connected to the control node.

[0016] In the gate driving circuit provided in the present application, the voltage stabilizing module includes a bootstrap capacitor, one end of the bootstrap capacitor is electrically connected to the control node, and the other end of the bootstrap capacitor is connected to the high potential signal.

[0017] In the gate drive circuit provided in the present application, the gate drive circuit also includes a leakage suppression module, which is connected to the leakage suppression control signal and is electrically connected to the control node and the output module. The leakage suppression module is used to suppress leakage of the control node based on the gate drive signal and the leakage suppression control signal.

[0018] In the gate drive circuit provided in the present application, the leakage suppression module includes a third P-type transistor and a fourth P-type transistor;

[0019] wherein the gate of the third P-type transistor is connected to the gate drive signal, one of the source and the drain of the third P-type transistor is connected to a high potential signal, and the other of the source and the drain of the third P-type transistor is electrically connected to one of the source and the drain of the fourth P-type transistor;

[0020] The gate of the fourth P-type transistor is connected to the leakage suppression control signal, and the other of the source and the drain of the fourth P-type transistor is electrically connected to the control node.

[0021] In a second aspect, the present application provides a display panel, comprising:

[0022] An input signal line, the input signal line being used to provide an input signal;

[0023] A clock signal line, wherein the clock signal line is used to provide a clock signal;

[0024] And any gate driving circuit provided in the present application, the gate driving circuit is electrically connected to the input signal line and the clock signal line.

[0025] The display panel provided in the present application also includes a leakage suppression control signal line, which is used to provide a leakage suppression control signal, and a gate drive circuit provided in the present application, which includes a control module, a voltage stabilization module, an output module and a leakage suppression module, and the gate drive circuit is also electrically connected to the input signal line, the clock signal line and the leakage suppression control signal line.

[0026] In a third aspect, the present application provides a gate driving method for a display panel, comprising:

[0027] In the pre-charging stage, the voltage stabilizing module controls the potential of the control node to pull down the gate drive signal;

[0028] In the pull-up stage, the control module controls the potential of the control node to pull up the gate drive signal;

[0029] In the pull-up maintaining stage, the voltage stabilizing module maintains the potential of the control node during the pull-up stage, so as to maintain the gate driving signal at the gate driving signal during the pull-up stage;

[0030] In the pull-down stage, the control module controls the potential of the control node to pull down the gate drive signal.

[0031] The gate driving method of the display panel provided in the present application further includes:

[0032] In the pull-down maintaining stage, the voltage stabilizing module maintains the potential of the control node to maintain the gate driving signal as the gate driving signal in the pull-down stage;

[0033] In the control node pull-up stage, the leakage suppression module controls the potential of the control node to suppress leakage of the control node.

[0034] The gate drive circuit, display panel and gate drive method provided by the present application, access the clock signal and the input signal through the control module to control and adjust the potential of the control node, the voltage stabilizing module is electrically connected to the control node to maintain the potential of the control node, and the output module outputs the gate drive signal based on the potential of the control node, thereby realizing the control of the gate drive signal. On the other hand, the present application uses a smaller number of transistors to realize the control of the gate drive signal, thereby optimizing the structure of the gate drive circuit, so that the gate drive circuit provided by the present application can meet the production needs of narrow-frame display panels or full-screen display panels. On the other hand, the gate drive circuit provided by the present application also includes a leakage suppression module, which is used to maintain the potential of the control node based on the gate drive signal and the leakage suppression control signal, so that the potential of the control node is not affected by the leakage problem of the transistor, thereby improving the stability of the gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a first structure of a gate drive circuit provided in an embodiment of the present application;

[0036] Figure 2 A second structural diagram of the gate drive circuit provided in an embodiment of the present application;

[0037] Figure 3 for Figure 2 The structural diagram of the control module shown;

[0038] Figure 4 for Figure 2 The structural diagram of the pull-up control output unit shown;

[0039] Figure 5 for Figure 2 The structural diagram of the pull-down control output unit shown;

[0040] Figure 6 for Figure 2 The structural diagram of the voltage stabilizing module shown;

[0041] Figure 7 for Figure 2 A circuit diagram of a gate drive circuit shown in FIG.

[0042] Figure 8 A timing diagram of a gate drive circuit provided in an embodiment of the present application;

[0043] Figure 9 for Figure 7 The gate drive circuit shown in Figure 8 Schematic diagram of the path of the pre-charge stage under the driving timing shown;

[0044] Figure 10 for Figure 7 The gate drive circuit shown in Figure 8 Schematic diagram of the path of the pull-up stage under the driving timing shown;

[0045] Figure 11 for Figure 7 The gate drive circuit shown in Figure 8 Schematic diagram of the path of the pull-up maintenance phase under the driving timing shown;

[0046] Figure 12 for Figure 7 The gate drive circuit shown in Figure 8 Schematic diagram of the path during the pull-down phase under the driving timing shown;

[0047] Figure 13 A third structural diagram of the gate drive circuit provided in an embodiment of the present application;

[0048] Figure 14 for Figure 13 The structural diagram of the leakage suppression module shown;

[0049] Figure 15 for Figure 13 A circuit diagram of a gate drive circuit shown in FIG.

[0050] Figure 16 for Figure 15 The gate drive circuit shown in Figure 8 Schematic diagram of the path of the pre-charge stage under the driving timing shown;

[0051] Figure 17 for Figure 15 The gate drive circuit shown in Figure 8 Schematic diagram of the path of the pull-up stage under the driving timing shown;

[0052] Figure 18 for Figure 15 The gate drive circuit shown in Figure 8 A schematic diagram of the path of the first pull-up maintenance phase under the driving timing shown;

[0053] Figure 19 for Figure 15 The gate drive circuit shown in Figure 8 A schematic diagram of the path of the second pull-up maintenance phase under the driving timing shown;

[0054] Figure 20 for Figure 15 The gate drive circuit shown in Figure 8 A schematic diagram of the path of the third pull-up maintenance phase under the driving timing shown;

[0055] Figure 21 for Figure 15 The gate drive circuit shown in Figure 8 Schematic diagram of the path during the pull-down phase under the driving timing shown;

[0056] Figure 22 for Figure 15 The gate drive circuit shown in Figure 8 Schematic diagram of the path of the pull-down maintenance phase under the driving timing shown;

[0057] Figure 23 for Figure 15 The gate drive circuit shown in Figure 8 Schematic diagram of the path of the control node pull-up stage under the driving timing shown. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0059] In addition, the terms "first," "second," and the like in the specification, claims, and drawings of this application are used to distinguish between different objects rather than to describe a specific order. Furthermore, the terms "include," "include," and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions.

[0060] It should be noted that the source and drain of the transistors used in all embodiments of the present invention are symmetrical, so their sources and drains are interchangeable. A P-type transistor is turned on when the gate is at a low potential and is turned off when the gate is at a high potential, while an N-type transistor is turned on when the gate is at a high potential and is turned off when the gate is at a low potential.

[0061] In some embodiments, see Figure 1 , Figure 1 This is a schematic diagram of the first structure of the gate drive circuit provided in the embodiment of the present application. Figure 1 As shown, the gate drive circuit 10 provided in the embodiment of the present application includes a control module 100, a voltage stabilizing module 200, and an output module 300. The control module 100 receives the clock signal CK1 and the input signal SU and is electrically connected to the control node P. The voltage stabilizing module 200 is electrically connected to the control node P. The output module 300 is electrically connected to the control node P.

[0062] In this embodiment, the control module 100 is used to control the potential of the control node P according to the clock signal CK1 and the input signal SU. The voltage regulator module 200 is used to maintain the potential of the control node P. The output module 300 is used to output a gate drive signal according to the potential of the control node P.

[0063] The gate drive circuit 10 provided in this embodiment receives the clock signal CK1 and the input signal SU through the control module 100 to control and adjust the potential of the control node P. The voltage stabilization module 200 maintains the potential of the control node P, so that the output module 300 controls the gate drive signal G(n) based on the potential of the control node P.

[0064] In some embodiments, see Figure 2 , Figure 2 This is a second structural diagram of the gate drive circuit provided in the embodiment of the present application. Figure 2 As shown, the gate drive circuit 10 provided in the embodiment of the present application includes a control module 100, a voltage stabilizing module 200 and an output module 300. The difference between this embodiment and the previous embodiment is that: in this embodiment, the output module 300 includes a pull-down output control unit 301 and a pull-up output control unit 302. The pull-down output control unit 301 is connected to the low potential signal VGL and is electrically connected to the control node P. The pull-down output control unit 301 is used to pull down the gate drive signal G(n) based on the potential of the control node P. The pull-up output control unit 302 is connected to the high potential signal VGH and is electrically connected to the control node P. The pull-up output control unit 302 is used to pull up the gate drive signal G(n) based on the potential of the control node P.

[0065] The gate drive circuit 10 provided in this embodiment receives the clock signal CK1 and the input signal SU through the control module 100 to control and adjust the potential of the control node P. The voltage stabilization module 200 maintains the potential of the control node P. As a result, the pull-down output control unit 301 in the output module 300 performs pull-down control on the gate drive signal G(n) based on the potential of the control node P, and the pull-up output control unit 302 in the output module 300 performs pull-up control on the gate drive signal G(n) based on the potential of the control node P. Thus, the gate drive circuit 10 controls the gate drive signal G(n).

[0066] In some embodiments, see Figure 3 , Figure 3 for Figure 2 The structure diagram of the pull-down output control unit is shown in FIG. Figure 3 As shown, the gate drive circuit 10 provided in the embodiment of the present application includes a control module 100, a voltage stabilizing module 200, and an output module 300, wherein the output module 300 includes a pull-down output control unit 301 and a pull-up output control unit 302. The difference between this embodiment and the previous embodiment is that in this embodiment, the pull-down output control unit 301 includes an N-type transistor T2. Specifically, the gate of the N-type transistor T2 is electrically connected to the control node P, one of the source and the drain of the N-type transistor T2 is connected to the low potential signal VGL, and the other of the source and the drain of the N-type transistor is electrically connected to the output node Q, so that the N-type transistor T2 provides the low potential signal VGL to the output node Q according to the potential of the control node P, thereby performing pull-down control on the gate drive signal G(n).

[0067] In some embodiments, see Figure 4 , Figure 4 for Figure 2 The structure diagram of the pull-up output control unit is shown in FIG. Figure 4 As shown, the gate drive circuit 10 provided in the embodiment of the present application includes a control module 100, a voltage stabilizing module 200 and an output module 300, wherein the output module 300 includes a pull-down output control unit 301 and a pull-up output control unit 302. The difference between this embodiment and the previous embodiment is that in this embodiment, the pull-up output control unit 302 includes a first P-type transistor T3. Specifically, the gate of the first P-type transistor T3 is electrically connected to the control node P, one of the source and the drain of the first P-type transistor T3 is connected to the high potential signal VGH, and the other of the source and the drain of the first P-type transistor T3 is electrically connected to the output node Q, so that the first P-type transistor T3 provides the high potential signal VGH to the output node Q according to the potential of the control node P, thereby performing pull-up control on the gate drive signal G(n).

[0068] In some embodiments, see Figure 5 , Figure 5 for Figure 2 The structural diagram of the control module is shown in FIG. Figure 5 As shown, the gate drive circuit 10 provided in an embodiment of the present application includes a control module 100, a voltage stabilization module 200, and an output module 300, wherein the control module 100 includes a second P-type transistor T1. Specifically, the gate of the second P-type transistor T1 is connected to the clock signal CK1, one of the source and drain of the second P-type transistor T1 is connected to the input signal SU, and the other of the source and drain of the second P-type transistor T1 is electrically connected to the control node P. The second P-type transistor T1 provides the input signal SU to the control node P according to the clock signal CK1, thereby controlling the potential of the control node P.

[0069] In some embodiments, see Figure 6 , Figure 6 for Figure 2 The schematic diagram of the voltage stabilizing module is shown in FIG. Figure 6 As shown, the gate drive circuit 10 provided in the embodiment of the present application includes a control module 100, a voltage stabilizing module 200, and an output module 300. The voltage stabilizing module 200 includes a bootstrap capacitor C. Specifically, one end of the bootstrap capacitor C is electrically connected to the control node P, and the other end of the bootstrap capacitor C is connected to the high potential signal VGH. The bootstrap capacitor C is used to maintain the potential of the control node P.

[0070] In a specific embodiment, see Figure 7 , Figure 7 for Figure 2 The circuit diagram of the gate drive circuit is shown in FIG. Figure 7 The gate driving circuit 10 is shown to include a control module 100 , a voltage regulating module 200 and an output module 300 .

[0071] The control module 100 includes a second P-type transistor T1 , the voltage stabilizing module 200 includes a bootstrap capacitor C, and the output module 300 includes an N-type transistor T2 and a first P-type transistor T3 .

[0072] Specifically, the gate of the second P-type transistor T1 is connected to the clock signal CK1, one of the source and drain of the second P-type transistor T1 is connected to the output signal SU, and the other of the source and drain of the second P-type transistor T1 is electrically connected to the control node P. One end of the bootstrap capacitor C is connected to the high potential signal VGH, and the other end of the bootstrap capacitor C is electrically connected to the control node P. The gate of the N-type transistor T2 is electrically connected to the control node P, one of the source and drain of the N-type transistor T2 is connected to the low potential signal VGL, and the other of the source and drain of the N-type transistor T2 is electrically connected to the output node Q. The gate of the first P-type transistor T3 is electrically connected to the control node P, one of the source and drain of the first P-type transistor T3 is connected to the high potential signal VGH, and the other of the source and drain of the first P-type transistor T3 is electrically connected to the output node Q. The potential of the output node Q is the gate drive signal G(n).

[0073] In some embodiments, the first P-type transistor and the second P-type transistor are low-temperature polysilicon transistors, and the N-type transistor is one of an oxide transistor, a low-temperature polysilicon transistor, and an oxide device with high mobility. The oxide transistor has a small leakage current, and the low-temperature polysilicon transistor has a high carrier mobility. Therefore, the gate drive circuit provided in the present application utilizes the advantages of both, which is conducive to realizing a display panel with low-frequency drive, high resolution, high response speed, high pixel density, and high aperture ratio, thereby meeting the requirements of a narrow-border display panel or a full-screen display panel.

[0074] In some embodiments, see Figure 8 , Figure 8 This is a timing diagram of the gate drive circuit provided in the embodiment of the present application. Figure 8 As shown, the timing cycle includes the combination of the input signal SU and the clock signal CK1, which corresponds to the pre-charge phase t1, the pull-up phase t2, the pull-up maintenance phase t3 and the pull-down phase t4.

[0075] In some embodiments, during the pre-charging stage t1 , the input signal SU and the clock signal CK1 are both at high levels.

[0076] In some embodiments, during the pull-up phase t2 , the input signal SU and the clock signal CK1 are both at low levels.

[0077] In some embodiments, during the pull-up holding stage t3 , the input signal SU and the clock signal CK1 are both at high levels.

[0078] In some embodiments, during the pull-down phase t4 , the input signal SU is at a high level, and the clock signal CK1 is at a low level.

[0079] For details, please refer to Figures 7 to 9 , Figure 9 for Figure 7 The gate drive circuit shown in Figure 8 Schematic diagram of the path of the pre-charging stage under the driving timing shown. In the pre-charging stage t1, the input signal SU and the clock signal CK1 are both high-potential signals VGH. The second P-type transistor T1 is turned off under the control of the high-potential signal VGH of the clock signal CK1. One end of the bootstrap capacitor C is connected to the high-potential signal VGH, and the other end of the bootstrap capacitor C is electrically connected to the control node P, so that the bootstrap capacitor C provides the high-potential signal VGH to the control node P. Based on the control node P being a high-potential signal VGH, the first P-type transistor T3 is turned off under the control of the high-potential signal VGH of the control node P, and the N-type transistor T2 is turned on under the control of the high-potential signal VGH of the control node P, so that the N-type transistor T2 provides a low-potential signal VGL to the output node Q, and then the gate drive signal G(n) is a low-potential signal VGL.

[0080] For details, please refer to Figures 7 and 8 as well as Figure 10 , Figure 10 for Figure 7 The gate drive circuit shown in Figure 8 The schematic diagram of the path of the pull-up phase under the driving timing is shown. During the pull-up phase t2, the input signal SU and the clock signal CK1 are both low-voltage signals VGL. The second P-type transistor T1 is turned on under the control of the low-voltage signal VGL of the clock signal CK1, thereby providing the input signal SU, which is the low-voltage signal VGL, to the control node P. Based on the low-voltage signal VGL at the control node P, the N-type transistor T2 is turned off under the control of the low-voltage signal VGL at the control node P, and the first P-type transistor T3 is turned on under the control of the low-voltage signal VGL at the control node P, thereby providing the high-voltage signal VGH to the output node Q, thereby pulling the gate drive signal G(n) up to the high-voltage signal VGH.

[0081] For details, please refer to Figures 7 and 8 as well as Figure 11 , Figure 11 for Figure 7 The gate drive circuit shown in Figure 8The schematic diagram of the path of the pull-up maintenance phase under the driving timing shown. During the pull-up maintenance phase t3, the input signal SU and the clock signal CK1 are both high-voltage signals VGH. The second P-type transistor T1 is turned off under the control of the high-voltage signal VGH of the clock signal CK1. Under the voltage regulation of the bootstrap capacitor C, the control node P maintains the low-voltage signal VGL of the control node P during the pull-up phase t2. Based on the low-voltage signal VGL of the control node P, the N-type transistor T2 is turned off under the control of the low-voltage signal VGL of the control node P, and the first P-type transistor T3 is turned on under the control of the low-voltage signal VGL of the control node P. As a result, the first P-type transistor provides the high-voltage signal VGH to the output node Q, and the gate drive signal G(n) is maintained at the high-voltage signal VGH.

[0082] For details, please refer to Figures 7 and 8 as well as Figure 12 , Figure 12 for Figure 7 The gate drive circuit shown in Figure 8 The schematic diagram of the path of the pull-down phase under the driving timing is shown. During the pull-down phase t4, the input signal SU is a high-voltage signal VGH, and the clock signal CK1 is a low-voltage signal VGL. The second P-type transistor T1 is turned on under the control of the low-voltage signal VGL of the clock signal CK1, thereby providing the input signal SU, which is a high-voltage signal VGH, to the control node P. Based on the high-voltage signal VGH at the control node P, the first P-type transistor T3 is turned off under the control of the high-voltage signal VGH at the control node P, and the N-type transistor T2 is turned on under the control of the high-voltage signal VGH at the control node P. Therefore, the N-type transistor T3 provides the low-voltage signal VGL to the output node Q, thereby pulling the gate drive signal G(n) down to the low-voltage signal VGL.

[0083] In some embodiments, see Figure 13 , Figure 13 This is a third structural diagram of the gate drive circuit provided in the embodiment of the present application. Figure 13 As shown, the gate drive circuit 20 includes a control module 100, a voltage stabilization module 200, an output module 300, and a leakage suppression module 400. The third structural schematic diagram provided in the embodiment of the present application differs from the first and second structural schematic diagrams described above in that it also includes a leakage suppression module 400. The leakage suppression module 400 receives the leakage suppression control signal CK2 and is electrically connected to the output module 300 and the control node P. The leakage suppression module 400 is used to suppress leakage at the control node P based on the gate drive signal G(n) and the leakage suppression control signal CK2.

[0084] In some embodiments, see Figure 14 , Figure 14 for Figure 13The structural diagram of the leakage suppression module is shown in FIG. Figure 14 As shown, the leakage suppression module 400 includes a third P-type transistor T4 and a fourth P-type transistor T5. Specifically, the gate of the third P-type transistor T4 is connected to the gate drive signal G(n), one of the source and drain of the third P-type transistor T4 is connected to the high potential signal VGH, and the other of the source and drain of the third P-type transistor T4 is electrically connected to one of the source and drain of the fourth P-type transistor T5. The gate of the fourth P-type transistor T5 is connected to the leakage suppression control signal CK2, and the other of the source and drain of the fourth P-type transistor T5 is electrically connected to the control node P. Therefore, based on the gate drive signal G(n), the third P-type transistor T4 provides the high potential signal VGH to one of the source and drain of the fourth P-type transistor T5. Subsequently, based on the leakage suppression control signal CK2, the fourth P-type transistor T5 provides the high potential signal VGH to the control node P, thereby suppressing the potential of the control node P from decreasing over time due to transistor leakage.

[0085] In a specific embodiment, see Figure 15 , Figure 15 for Figure 13 The circuit diagram of the gate drive circuit is shown in FIG. Figure 7 The gate driving circuit 20 is shown to include a control module 100 , a voltage stabilizing module 200 , an output module 300 and a leakage suppression module 400 .

[0086] The control module 100 includes a second P-type transistor T1 , the voltage stabilizing module 200 includes a bootstrap capacitor C, the output module 300 includes an N-type transistor T2 and a first P-type transistor T3 , and the leakage suppression module 400 includes a third P-type transistor T4 and a fourth P-type transistor T5 .

[0087] Specifically, the gate of the second P-type transistor T1 is connected to the clock signal CK1, one of the source and drain of the second P-type transistor T1 is connected to the output signal SU, and the other of the source and drain of the second P-type transistor T1 is electrically connected to the control node P. One end of the bootstrap capacitor C is connected to the high potential signal VGH, and the other end of the bootstrap capacitor C is electrically connected to the control node P. The gate of the N-type transistor T2 is electrically connected to the control node P, one of the source and drain of the N-type transistor T2 is connected to the low potential signal VGL, and the other of the source and drain of the N-type transistor T2 is electrically connected to the output node Q. The gate of the first P-type transistor T3 is electrically connected to the control node P, one of the source and drain of the first P-type transistor T3 is connected to the high potential signal VGH, and the other of the source and drain of the first P-type transistor T3 is electrically connected to the output node Q. The potential of the output node Q is the gate drive signal G(n). The gate of the third P-type transistor T4 is electrically connected to the output node Q, one of the source and drain of the third P-type transistor T4 is connected to the high potential signal VGH, and the other of the source and drain of the third P-type transistor T4 is electrically connected to one of the source and drain of the fourth P-type transistor T5. The gate of the fourth P-type transistor T5 is connected to the leakage suppression control signal CK2, and the other of the source and drain of the fourth P-type transistor T5 is electrically connected to the control node P. The potential of the output node Q is the gate drive signal G(n). Thus, the gate drive circuit 20 performs pull-up control or pull-down control on the gate drive signal G(n). On the other hand, the leakage suppression module 400 can suppress the leakage problem of the transistor caused by long-term operation, thereby keeping the potential of the control node P stable.

[0088] In some embodiments, see Figure 8 as well as Figures 13 to 15 .like Figure 8 As shown, the timing cycle includes the combination of the input signal SU, the clock signal CK1 and the leakage suppression control signal CK2, which corresponds to the pre-charging stage t1, the pull-up stage t2, the first pull-up maintenance stage t31, the second pull-up maintenance stage t32, the third pull-up maintenance stage t33, the pull-down stage t4, the pull-down maintenance stage t5 and the control node pull-up stage t6.

[0089] In some embodiments, during the pre-charging stage t1 , the input signal SU, the clock signal CK1 , and the leakage suppression control signal CK2 are all at high levels.

[0090] In some embodiments, during the pull-up phase t2 , the input signal SU and the clock signal CK1 are at a low level, and the leakage suppression control signal CK2 is at a high level.

[0091] In some embodiments, during the first pull-up maintaining stage t31 , the input signal SU, the clock signal CK1 , and the leakage suppression control signal CK2 are all at high levels.

[0092] In some embodiments, during the second pull-up maintaining stage t32 , the leakage suppression control signal CK2 is at a low level, and the input signal SU and the clock signal CK1 are at a high level.

[0093] In some embodiments, during the third pull-up maintaining stage t33 , the input signal SU, the clock signal CK1 , and the leakage suppression control signal CK2 are all at high levels.

[0094] In some embodiments, during the pull-down phase t4 , the clock signal CK1 is at a low level, and the input signal SU and the leakage suppression control signal CK2 are at high levels.

[0095] In some embodiments, during the pull-down maintenance phase t5 , the input signal SU, the clock signal CK1 , and the leakage suppression control signal CK2 are all at high levels.

[0096] In some embodiments, during the control node pull-up phase t6 , the leakage suppression control signal CK2 is at a low level, and the input signal SU and the clock signal CK are at a high level.

[0097] For details, please refer to Figure 8 、 Figure 15 as well as Figure 16 , Figure 16 for Figure 15 The gate drive circuit shown in Figure 8 A schematic diagram of the path during the pre-charge phase under the driving timing is shown. During the pre-charge phase t1, the input signal SU, the clock signal CK1, and the leakage suppression control signal CK2 are all high-voltage signals VGH. The second P-type transistor T1 is turned off under the control of the high-voltage signal VGH of the clock signal CK1. One end of the bootstrap capacitor C is connected to the high-voltage signal VGH, and the other end of the bootstrap capacitor C is electrically connected to the control node P, so that the bootstrap capacitor C provides the high-voltage signal VGH to the control node P. Based on the high-voltage signal VGH at the control node P, the first P-type transistor T3 is turned off under the control of the high-voltage signal VGH at the control node P, and the N-type transistor T2 is turned on under the control of the high-voltage signal VGH at the control node P. As a result, the N-type transistor T2 provides the low-voltage signal VGL to the output node Q, and the gate drive signal G(n) is thus low-voltage signal VGL. Based on the low-voltage signal VGL at the output node Q, the third P-type transistor T4 is turned on under the control of the low-voltage signal VGL at the output node Q, and the fourth P-type transistor T5 is turned off under the control of the high-voltage signal VGH of the leakage suppression control signal CK2.

[0098] For details, please refer to Figure 8 、 Figure 15as well as Figure 17 , Figure 17 for Figure 15 The gate drive circuit shown in Figure 8 The diagram shows a schematic diagram of the pull-up phase during the drive timing. During pull-up phase t2, the input signal SU and the clock signal CK1 are both low signals (VGL), and the leakage suppression control signal CK2 is high. The second P-type transistor T1 is turned on by the low signal VGL of the clock signal CK1, thereby providing the input signal SU, which is a low signal (VGL), to the control node P. Based on the low signal VGL at the control node P, the N-type transistor T2 is turned off by the low signal VGL at the control node P. The first P-type transistor T3 is turned on by the low signal VGL at the control node P, thereby providing the high signal VGH to the output node Q. This pulls the gate drive signal G(n) up to a high signal (VGH). Based on the high signal VGH at the output node Q, the third P-type transistor T4 is turned off by the high signal VGH at the output node Q, and the fourth P-type transistor T5 is turned off by the high signal VGH of the leakage suppression control signal CK2.

[0099] For details, please refer to Figure 8 、 Figure 15 as well as Figure 18 , Figure 18 for Figure 15 The gate drive circuit shown in Figure 8 The schematic diagram of the path for the first pull-up sustain phase under the driving timing is shown. During the first pull-up sustain phase t31, the input signal SU, the clock signal CK1, and the leakage suppression control signal CK2 are all high voltage signals VGH. The second P-type transistor T1 is turned off under the control of the high voltage signal VGH of the clock signal CK1. Under the voltage regulation of the bootstrap capacitor C, the control node P is maintained at the low voltage signal VGL of the control node P during the pull-up phase t2. Because the control node P is at the low voltage signal VGL, the N-type transistor T2 is turned off under the control of the low voltage signal VGL of the control node P. The first P-type transistor T3 is turned on under the control of the low voltage signal VGL of the control node P. As a result, the first P-type transistor provides the high voltage signal VGH to the output node Q, thereby maintaining the gate drive signal G(n) at the high voltage signal VGH. Because the output node Q is at the high voltage signal VGH, the third P-type transistor T4 is turned off under the control of the high voltage signal VGH of the output node Q. The fourth P-type transistor T5 is turned off under the control of the high voltage signal VGH of the leakage suppression control signal CK2.

[0100] For details, please refer to Figure 8 、 Figure 15 as well as Figure 19 , Figure 19 for Figure 15The gate drive circuit shown in Figure 8 The schematic diagram of the path for the second pull-up maintenance phase under the driving timing is shown. During the second pull-up maintenance phase t32, the leakage suppression control signal CK2 is a low signal VGL, and the input signal SU and the clock signal CK1 are high signals VGH. The second P-type transistor T1 is turned off under the control of the high signal VGH of the clock signal CK1. Under the voltage regulation of the bootstrap capacitor C, the control node P is maintained at the low signal VGL of the control node P during the pull-up phase t2. Due to the low signal VGL of the control node P, the N-type transistor T2 is turned off under the control of the low signal VGL of the control node P, and the first P-type transistor T3 is turned on under the control of the low signal VGL of the control node P. As a result, the first P-type transistor provides the high signal VGH to the output node Q, thereby maintaining the gate drive signal G(n) at the high signal VGH. Due to the high signal VGH of the output node Q, the third P-type transistor T4 is turned off under the control of the high signal VGH of the output node Q, and the fourth P-type transistor T5 is turned on under the control of the low signal VGL of the leakage suppression control signal CK2.

[0101] For details, please refer to Figure 8 、 Figure 15 as well as Figure 20 , Figure 20 for Figure 15 The gate drive circuit shown in Figure 8 The schematic diagram of the path of the third pull-up maintenance phase under the driving timing is shown. During the third pull-up maintenance phase t33, the input signal SU, the clock signal CK1, and the leakage suppression control signal CK2 are all high voltage signals VGH. The second P-type transistor T1 is turned off under the control of the high voltage signal VGH of the clock signal CK1. Under the voltage regulation of the bootstrap capacitor C, the control node P is maintained at the low voltage signal VGL of the control node P during the pull-up phase t2. Due to the low voltage signal VGL of the control node P, the N-type transistor T2 is turned off under the control of the low voltage signal VGL of the control node P, and the first P-type transistor T3 is turned on under the control of the low voltage signal VGL of the control node P. As a result, the first P-type transistor provides the high voltage signal VGH to the output node Q, thereby maintaining the gate drive signal G(n) at the high voltage signal VGH. Due to the high voltage signal VGH of the output node Q, the third P-type transistor T4 is turned off under the control of the high voltage signal VGH of the output node Q, and the fourth P-type transistor T5 is turned off under the control of the high voltage signal VGH of the leakage suppression control signal CK2.

[0102] For details, please refer to Figure 8 、 Figure 15 as well as Figure 21 , Figure 21 for Figure 15 The gate drive circuit shown in Figure 8The diagram shows a schematic diagram of the pull-down phase during the driving sequence. During pull-down phase t4, the clock signal CK1 is at a low voltage level (VGL), and the input signal SU and the leakage suppression control signal CK2 are at high voltage levels (VGH). The second P-type transistor T1 is turned on by the low voltage level (VGL) of the clock signal CK1, thereby providing the input signal SU, which is a high voltage level (VGH), to the control node P. Based on the high voltage level (VGH) of the control node P, the first P-type transistor T3 is turned off by the high voltage level (VGH) of the control node P, and the N-type transistor T2 is turned on by the high voltage level (VGH) of the control node P. Consequently, the N-type transistor T3 provides the low voltage level (VGL) to the output node Q, thereby pulling the gate drive signal G(n) down to a low voltage level (VGL). Based on the low voltage level (VGL) of the output node Q, the third P-type transistor T4 is turned on by the low voltage level (VGL) of the output node Q, and the fourth P-type transistor T5 is turned off by the high voltage level (VGH) of the leakage suppression control signal CK2.

[0103] For details, please refer to Figure 8 、 Figure 15 as well as Figure 22 , Figure 22 for Figure 15 The gate drive circuit shown in Figure 8 The schematic diagram of the pull-down sustain phase in the driving sequence shown is shown. During the pull-down sustain phase t5, the input signal SU, the clock signal CK1, and the leakage suppression control signal CK2 are all high signals VGH. The second P-type transistor T1 is turned off under the control of the high signal VGH of the clock signal CK1. Under the voltage regulation of the bootstrap capacitor C, the control node P maintains the high signal VGH of the control node P during the pull-down phase t4. Because the control node P is at the high signal VGH, the first P-type transistor T3 is turned off under the control of the high signal VGH of the control node P, and the N-type transistor T2 is turned on under the control of the high signal VGH of the control node P. As a result, the N-type transistor T3 provides the low signal VGL to the output node Q, thereby maintaining the gate drive signal G(n) at the low signal VGL. Because the output node Q is at the low signal VGL, the third P-type transistor T4 is turned on under the control of the low signal VGL of the output node Q, and the fourth P-type transistor T5 is turned off under the control of the high signal VGH of the leakage suppression control signal CK2.

[0104] For details, please refer to Figure 8 、 Figure 15 as well as Figure 23 , Figure 23 for Figure 15 The gate drive circuit shown in Figure 8The schematic diagram of the path during the control node pull-up phase under the driving timing shown. During the control node pull-up phase t6, the leakage suppression control signal CK2 is a low-level signal VGL, and the input signal SU and the clock signal CK are high-level signals VGH. The second P-type transistor T1 is turned off under the control of the high-level signal VGH of the clock signal CK1. Under the voltage regulation of the bootstrap capacitor C, the control node P maintains the high-level signal VGH of the control node P during the pull-down maintenance phase t5. Based on the high-level signal VGH of the control node P, the first P-type transistor T3 is turned off under the control of the high-level signal VGH of the control node P, and the N-type transistor T2 is turned on under the control of the high-level signal VGH of the control node P. As a result, the N-type transistor T3 provides the low-level signal VGL to the output node Q, thereby maintaining the gate drive signal G(n) at the low-level signal VGL. Based on the output node Q being a low potential signal VGL, the third P-type transistor T4 is turned on under the control of the low potential signal VGL of the output node Q, and the fourth P-type transistor T5 is turned on under the control of the low potential signal VGL of the leakage suppression control signal CK2, so that the third P-type transistor T4 provides the high potential signal VGH to the fourth P-type transistor T5, and then the fourth P-type transistor T5 provides the high potential signal VGH to the control node P to maintain the control node P as the high potential signal VGH, thereby suppressing the problem of the potential of the control node P gradually decreasing due to leakage of the transistor due to long-term operation.

[0105] In some embodiments, as Figure 8 As shown, the cycles of the control signal CK1 and the leakage suppression control signal CK2 are the same, and there is a preset phase difference between the clock signal CK1 and the leakage suppression control signal CK2.

[0106] In some embodiments, the first P-type transistor, the second P-type transistor, the third P-type transistor, and the fourth P-type transistor are low-temperature polysilicon transistors, and the N-type transistor is an oxide transistor, a low-temperature polysilicon transistor, and an oxide device with high mobility. The oxide transistor has a smaller leakage current, and the low-temperature polysilicon transistor has a higher carrier mobility. Therefore, the gate drive circuit provided in the present application utilizes the advantages of both, which is conducive to realizing a display panel with low-frequency drive, high resolution, high response speed, high pixel density, and high aperture ratio, thereby meeting the requirements of a narrow-border display panel or a full-screen display panel.

[0107] The present application also provides a display panel including an input signal line and a clock signal line. The input signal line is used to provide an input signal, and the clock signal line is used to provide a clock signal. A gate drive circuit is electrically connected to the input signal line and the clock signal line.

[0108] The present application also provides another display panel, comprising an input signal line, a clock signal line, and a leakage suppression control signal line. The input signal line is used to provide an input signal, the clock signal line is used to provide a clock signal, and the leakage suppression control signal line is used to provide a leakage suppression control signal. A gate drive circuit is electrically connected to the input signal line, the clock signal line, and the leakage suppression control signal line.

[0109] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: It includes a control module, a voltage stabilizing module and an output module; among which, The control module receives a clock signal and an input signal and is electrically connected to a control node. The control module is used to control the potential of the control node according to the clock signal and the input signal. The voltage stabilizing module is electrically connected to the control node, and is used to maintain the potential of the control node; The output module is electrically connected to the control node, and is used to output a gate drive signal according to the potential of the control node; The output module includes a pull-up output control unit and a pull-down output control unit; The pull-up output control unit receives a high potential signal and is electrically connected to the control node, and is used to pull up the gate drive signal based on the potential of the control node; The pull-down output control unit receives a low potential signal and is electrically connected to the control node. The pull-down output control unit is used to pull down the gate driving signal according to the potential of the control node.

2. The gate drive circuit according to claim 1, wherein: The pull-up output control unit includes a first P-type transistor; The gate of the first P-type transistor is electrically connected to the control node, one of the source and the drain of the first P-type transistor is connected to the high potential signal, and the other of the source and the drain of the first P-type transistor is electrically connected to the output node.

3. The gate drive circuit according to claim 2, wherein: The pull-down output control unit includes an N-type transistor; The gate of the N-type transistor is electrically connected to the control node, one of the source and the drain of the N-type transistor is connected to the low potential signal, and the other of the source and the drain of the N-type transistor is electrically connected to the output node.

4. The gate drive circuit according to claim 1, wherein: The control module includes a second P-type transistor; The gate of the second P-type transistor is connected to the clock signal, one of the source and the drain of the second P-type transistor is connected to the input signal, and the other of the source and the drain of the second P-type transistor is electrically connected to the control node.

5. The gate driving circuit according to claim 1, wherein: The voltage stabilizing module includes a bootstrap capacitor, one end of the bootstrap capacitor is electrically connected to the control node, and the other end of the bootstrap capacitor is connected to a high potential signal.

6. The gate driving circuit according to claim 1, wherein: The gate drive circuit further includes a leakage suppression module, The leakage suppression module receives a leakage suppression control signal and is electrically connected to the control node and the output module. The leakage suppression module is used to suppress leakage of the control node based on the gate drive signal and the leakage suppression control signal.

7. The gate driving circuit according to claim 6, wherein: The leakage suppression module includes a third P-type transistor and a fourth P-type transistor; wherein, The gate of the third P-type transistor is connected to the gate drive signal, one of the source and the drain of the third P-type transistor is connected to a high potential signal, and the other of the source and the drain of the third P-type transistor is electrically connected to one of the source and the drain of the fourth P-type transistor; The gate of the fourth P-type transistor is connected to the leakage suppression control signal, and the other of the source and the drain of the fourth P-type transistor is electrically connected to the control node.

8. A display panel, characterized in that: include: An input signal line, the input signal line being used to provide an input signal; A clock signal line, wherein the clock signal line is used to provide a clock signal; as well as The gate drive circuit according to any one of claims 1 to 7, wherein the gate drive circuit is electrically connected to the input signal line and the clock signal line.

9. A gate driving method for a display panel as claimed in claim 8, characterized in that: include: In the pre-charging stage, the voltage stabilizing module controls the potential of the control node to pull down the gate drive signal; In the pull-up stage, the control module controls the potential of the control node to pull up the gate drive signal; In the pull-up maintaining stage, the voltage stabilizing module maintains the potential of the control node during the pull-up stage, so as to maintain the gate driving signal at the gate driving signal during the pull-up stage; In the pull-down stage, the control module controls the potential of the control node to pull down the gate drive signal.

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