Wafer calibration method, device, equipment and storage medium
By using an automatic adjustment mechanism to identify alignment marks with lower precision during wafer calibration, the problem of machine downtime caused by alignment marks being covered is solved, wafer alignment efficiency and equipment capacity are improved, and labor costs are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-15
- Publication Date
- 2026-06-19
AI Technical Summary
In existing technologies, because subtle differences in alignment marks or wafer dimensions are difficult to detect manually, alignment marks are often obscured during alignment and correction, leading to machine downtime, increased labor costs, and reduced equipment capacity.
By controlling the defect inspection machine to scan the wafer surface with a first preset positioning accuracy, a first preset alignment mark is obtained. If the error fails, an automatic adjustment mechanism is triggered to adjust the lens to identify the second preset alignment mark with lower accuracy, and use it as the target for alignment pattern calibration, thereby improving alignment efficiency and intelligence.
It effectively avoids equipment downtime caused by alignment failure, improves the efficiency and intelligence of wafer alignment, reduces labor costs, and increases equipment capacity.
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