Wafer calibration method, device, equipment and storage medium

By using an automatic adjustment mechanism to identify alignment marks with lower precision during wafer calibration, the problem of machine downtime caused by alignment marks being covered is solved, wafer alignment efficiency and equipment capacity are improved, and labor costs are reduced.

CN114843219BActive Publication Date: 2026-06-19CHANGXIN MEMORY TECH INC

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CHANGXIN MEMORY TECH INC
Filing Date
2022-04-15
Publication Date
2026-06-19

AI Technical Summary

Technical Problem

In existing technologies, because subtle differences in alignment marks or wafer dimensions are difficult to detect manually, alignment marks are often obscured during alignment and correction, leading to machine downtime, increased labor costs, and reduced equipment capacity.

Method used

By controlling the defect inspection machine to scan the wafer surface with a first preset positioning accuracy, a first preset alignment mark is obtained. If the error fails, an automatic adjustment mechanism is triggered to adjust the lens to identify the second preset alignment mark with lower accuracy, and use it as the target for alignment pattern calibration, thereby improving alignment efficiency and intelligence.

🎯Benefits of technology

It effectively avoids equipment downtime caused by alignment failure, improves the efficiency and intelligence of wafer alignment, reduces labor costs, and increases equipment capacity.

✦ Generated by Eureka AI based on patent content.

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Abstract

Embodiments of the present disclosure relate to a wafer calibration method, device, equipment and storage medium. The method comprises: controlling a defect inspection machine to scan an alignment surface of a target wafer on a machine bearing surface with a first preset positioning accuracy; adjusting the position of the target wafer to obtain a first preset alignment mark in a lens of the machine, wherein the first preset alignment mark is located at a first preset position of the alignment surface; if the first preset alignment mark fails to be obtained, triggering an automatic adjustment mechanism to adjust the lens to scan the alignment surface with a second preset positioning accuracy, identifying a second preset alignment mark on the alignment surface in the lens, and taking the second preset alignment mark as a target alignment pattern to calibrate the position of the target wafer, wherein the second preset positioning accuracy is less than the first preset positioning accuracy. The embodiments of the present disclosure improve the efficiency and intelligence of wafer alignment, improve equipment productivity and reduce labor costs.
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