Wafer calibration method, device, equipment and storage medium
By using an automatic adjustment mechanism to identify alignment marks with lower precision during wafer calibration, the problem of machine downtime caused by alignment marks being covered is solved, wafer alignment efficiency and equipment capacity are improved, and labor costs are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-15
- Publication Date
- 2026-06-19
AI Technical Summary
In existing technologies, because subtle differences in alignment marks or wafer dimensions are difficult to detect manually, alignment marks are often obscured during alignment and correction, leading to machine downtime, increased labor costs, and reduced equipment capacity.
By controlling the defect inspection machine to scan the wafer surface with a first preset positioning accuracy, a first preset alignment mark is obtained. If the error fails, an automatic adjustment mechanism is triggered to adjust the lens to identify the second preset alignment mark with lower accuracy, and use it as the target for alignment pattern calibration, thereby improving alignment efficiency and intelligence.
It effectively avoids equipment downtime caused by alignment failure, improves the efficiency and intelligence of wafer alignment, reduces labor costs, and increases equipment capacity.
Smart Images
Figure CN114843219B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a wafer calibration method, apparatus, device, and storage medium. Background Technology
[0002] With the rapid development of integrated circuit technology, the market has placed higher demands on the performance and reliability of semiconductor products. However, with continuous process optimization, factors such as the increasing number of stacked film layers in the semiconductor structure or changes in film layer thickness can lead to partial obscuring of alignment marks in different film layers or changes in the actual size of the wafer. Since wafer alignment and positioning generally use alignment marks as a reference, changes in alignment marks or wafer size can cause alignment failures.
[0003] However, since subtle differences in alignment marks or wafer dimensions are generally difficult to detect manually, if alignment marks are obscured during the alignment process, manual alignment correction is the only option, causing machine downtime, wasting engineers' time, increasing labor costs, and reducing equipment capacity. Summary of the Invention
[0004] Therefore, it is necessary to provide a wafer calibration method, apparatus, equipment, and storage medium that can effectively avoid equipment downtime due to alignment failure, improve the efficiency and intelligence of wafer alignment, increase equipment capacity, and reduce labor costs.
[0005] To achieve the above and other related objectives, a first aspect of this disclosure provides a wafer calibration method, comprising: controlling a defect inspection machine to scan an alignment surface of a target wafer on a machine bearing surface with a first preset positioning accuracy; adjusting the position of the target wafer to acquire a first preset alignment mark in the lens of the scanning machine, wherein the first preset alignment mark is located at a first preset position on the alignment surface; if acquiring the first preset alignment mark fails, triggering an automatic adjustment mechanism to adjust the lens to scan the alignment surface with a second preset positioning accuracy, identifying the second preset alignment mark on the alignment surface in the lens, and using the second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer, wherein the second preset positioning accuracy is less than the first preset positioning accuracy.
[0006] In the wafer calibration method described above, after the defect inspection machine scans the alignment surface of the target wafer on the machine bearing surface with a first preset positioning accuracy, the position of the target wafer is adjusted to obtain a first preset alignment mark on the alignment surface of the target wafer in the lens of the scanning machine, thereby achieving intelligent alignment. If obtaining the first preset alignment mark fails, an automatic adjustment mechanism is triggered, and the lens is adjusted to scan the alignment surface of the target wafer with a second preset positioning accuracy that is lower. The second preset alignment mark on the alignment surface is identified in the lens, and the position of the target wafer is calibrated using the second preset alignment mark as the target alignment pattern. The second preset positioning accuracy is less than the first preset positioning accuracy. If the first preset alignment mark is not obtained with the first preset positioning accuracy, an automatic adjustment mechanism is triggered. The lens is automatically adjusted to a second preset positioning accuracy with a lower accuracy to identify and obtain a second preset alignment mark on the alignment surface. The second preset alignment mark is then used as the target alignment pattern to calibrate the position of the target wafer. This avoids equipment downtime caused by the failure to align with the first preset alignment mark due to factors such as the increasing number of stacked films or changes in film thickness in the semiconductor structure. By triggering the automatic adjustment mechanism and obtaining the second preset alignment mark, the position of the target wafer is automatically calibrated, improving the efficiency and intelligence of wafer alignment, increasing equipment capacity, and reducing labor costs.
[0007] According to some embodiments of this disclosure, the step of identifying a second preset alignment mark on an alignment surface in a lens includes: adjusting the lens to obtain a first alignment area on the alignment surface with a second preset positioning accuracy, and identifying a second alignment area in the first alignment area according to a first preset rule; adjusting the lens to scan the second alignment area with a third preset positioning accuracy, and identifying and obtaining a second preset alignment mark in the second alignment area according to a second preset rule; wherein the difference between the first preset positioning accuracy and the third preset positioning accuracy is within a first preset error range. If the acquisition of the first preset alignment mark with the first preset positioning accuracy fails, an automatic adjustment mechanism is triggered. The lens is adjusted to acquire a first alignment area on the alignment surface with a second preset positioning accuracy that is lower. For example, the first alignment area includes multiple complete dies. In the first alignment area, a second alignment area is identified according to at least one rule, such as sequential recognition, reverse recognition, or recognition of dies with coded target marks. The lens is then adjusted to scan the second alignment area with a third preset positioning accuracy that is similar to the first preset positioning accuracy. In the second alignment area, the second preset alignment mark is identified and acquired according to at least one rule, such as sequential recognition, reverse recognition, or recognition of dies with coded target marks. The position of the target wafer is automatically calibrated, improving the efficiency and intelligence of wafer alignment, increasing equipment capacity, and reducing labor costs.
[0008] According to some embodiments of this disclosure, the step of calibrating the position of a target wafer using a second preset alignment mark as the target alignment pattern includes: adjusting the lens to a fourth preset positioning accuracy and using the second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer; wherein the first preset positioning accuracy is less than the fourth preset positioning accuracy. In this embodiment, after obtaining the second preset alignment mark, the lens is adjusted to a fourth preset positioning accuracy, which is higher than the first preset positioning accuracy, and the second preset alignment mark is used as the target alignment pattern, for example, a right angle in the dicing corner or a right angle in the wafer edge corner, to automatically calibrate the position of the target wafer, thereby improving the efficiency and intelligence of wafer alignment, increasing equipment capacity, and reducing labor costs.
[0009] According to some embodiments of this disclosure, the second preset alignment mark includes: a corner region of a storage array area within the alignment surface; and / or, a corner region of a measurement pattern within the alignment surface. By using the corner region of a storage array area within the alignment surface, and / or, the corner region of a measurement pattern within the alignment surface, as the alignment pattern, since the corner region / corner region generally includes at least two intersecting edges, using at least these two intersecting edges as alignment reference lines can effectively reduce the difficulty of automatic alignment and improve alignment efficiency.
[0010] According to some embodiments of this disclosure, the measurement pattern is located in the dicing channel between adjacent dies within the alignment surface, avoiding the situation where the device crashes due to the failure of alignment with the second preset alignment mark caused by factors such as the continuous increase in the number of stacked films or changes in film thickness in the semiconductor structure.
[0011] According to some embodiments of this disclosure, if a first preset alignment mark is obtained, the lens is adjusted to calibrate the position of the target wafer with a third preset positioning accuracy and the first preset alignment mark as the target alignment pattern. This achieves automatic calibration of the target wafer position by obtaining the first preset alignment mark with the first preset positioning accuracy, thereby improving the efficiency and intelligence of wafer alignment, increasing equipment capacity, and reducing labor costs.
[0012] According to some embodiments of this disclosure, the first alignment region includes a plurality of bare pieces within the alignment surface; the second alignment region includes a bare piece from the first alignment region, thereby reducing the difficulty of obtaining the second alignment region and improving the efficiency of obtaining the second alignment region.
[0013] According to some embodiments of this disclosure, the step of identifying and obtaining a second preset alignment identifier in the second alignment region according to a second preset rule includes: obtaining an identification code of the target alignment pattern; traversing the codes of each storage array region in the second alignment region, wherein the codes of different storage array regions are different; and determining at least one corner region of the storage array region corresponding to the code with the same identification code as the second preset alignment identifier. Since at least one corner region of the storage array region corresponding to the code with the same identification code generally includes at least two intersecting edges, using at least these two intersecting edges as alignment reference lines can effectively reduce the difficulty of automatic alignment and improve the efficiency of alignment.
[0014] According to some embodiments of this disclosure, the corner region includes a first side and a second side that are perpendicular to each other; the step of calibrating the position of the target wafer with a second preset alignment mark as the target alignment pattern includes: calibrating the position of the target wafer with the first side, the second side and the perpendicular point of the two as the target alignment pattern, and using these two intersecting sides as alignment reference lines, which can effectively reduce the difficulty of automatic alignment and improve the efficiency of alignment.
[0015] According to some embodiments of this disclosure, the first preset alignment mark is located in the dicing channel of the target wafer to avoid the situation where the second preset alignment mark fails to align due to factors such as the continuous increase in the number of stacked films or changes in film thickness in the semiconductor structure, which could cause equipment downtime.
[0016] A second aspect of this disclosure provides a wafer calibration apparatus, including a scanning control module, a first preset alignment mark acquisition module, and a calibration module. The scanning control module controls a defect inspection machine to scan the alignment surface of a target wafer on the machine's support surface with a first preset positioning accuracy. The first preset alignment mark acquisition module adjusts the position of the target wafer to acquire a first preset alignment mark in the lens of the scanning machine, wherein the first preset alignment mark is located at a first preset position on the alignment surface. If the acquisition of the first preset alignment mark fails, the calibration module triggers an automatic adjustment mechanism, adjusts the lens to scan the alignment surface with a second preset positioning accuracy, identifies the second preset alignment mark on the alignment surface in the lens, and uses the second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer, wherein the second preset positioning accuracy is less than the first preset positioning accuracy.
[0017] According to some embodiments of this disclosure, the calibration module includes a second preset alignment mark acquisition unit. The second preset alignment mark acquisition unit is used to adjust the lens to acquire a first alignment area on the alignment surface with a second preset positioning accuracy, and to identify a second alignment area in the first alignment area according to a first preset rule; and to adjust the lens to scan the second alignment area with a third preset positioning accuracy, and to identify and acquire a second preset alignment mark in the second alignment area according to the second preset rule; wherein the difference between the first preset positioning accuracy and the third preset positioning accuracy is within a first preset error range.
[0018] According to some embodiments of this disclosure, the calibration module further includes a calibration unit, which is used to adjust the lens to calibrate the position of the target wafer with a fourth preset positioning accuracy and a second preset alignment mark as the target alignment pattern; wherein the first preset positioning accuracy is less than the fourth preset positioning accuracy.
[0019] A third aspect of this disclosure provides an apparatus including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of any of the methods described above.
[0020] A fourth aspect of this disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.
[0021] In the aforementioned wafer calibration method, apparatus, equipment, and storage medium, after the scanning control module controls the defect inspection machine to scan the alignment surface of the target wafer on the machine bearing surface with a first preset positioning accuracy, the first preset alignment mark acquisition module adjusts the position of the target wafer to acquire the first preset alignment mark on the alignment surface of the target wafer in the lens of the scanning machine, thereby achieving intelligent alignment. If the acquisition of the first preset alignment mark fails, the calibration module triggers an automatic adjustment mechanism, adjusts the lens to scan the alignment surface of the target wafer with a second preset positioning accuracy that is lower, and identifies the second preset alignment mark on the alignment surface in the lens. Using the second preset alignment mark as the target alignment pattern, the position of the target wafer is calibrated. The second preset positioning accuracy is less than the first preset positioning accuracy. If the first preset alignment mark is not obtained with the first preset positioning accuracy, an automatic adjustment mechanism is triggered. The lens is automatically adjusted to a second preset positioning accuracy with a lower accuracy to identify and obtain a second preset alignment mark on the alignment surface. The second preset alignment mark is then used as the target alignment pattern to calibrate the position of the target wafer. This avoids equipment downtime caused by the failure to align with the first preset alignment mark due to factors such as the increasing number of stacked films or changes in film thickness in the semiconductor structure. By triggering the automatic adjustment mechanism and obtaining the second preset alignment mark, the position of the target wafer is automatically calibrated, improving the efficiency and intelligence of wafer alignment, increasing equipment capacity, and reducing labor costs. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic flowchart of a wafer calibration method provided in one embodiment of the present disclosure;
[0024] Figure 2 This is a schematic flowchart of a wafer calibration method provided in another embodiment of the present disclosure;
[0025] Figure 3 This is a schematic diagram illustrating the failure to acquire the first preset alignment mark in the lens field of view in one embodiment of this disclosure;
[0026] Figure 4a This is a schematic diagram of the first aligned region in the field of view of the lens in one embodiment of the present disclosure;
[0027] Figure 4b This is a schematic diagram of the second alignment region in the lens field of view in one embodiment of the present disclosure;
[0028] Figure 4c This is a schematic diagram of a second preset alignment mark in the field of view of the lens in one embodiment of the present disclosure;
[0029] Figure 5 This is a flowchart of a wafer calibration method provided in yet another embodiment of the present disclosure;
[0030] Figure 6 This is a schematic diagram of the structure of a wafer calibration device provided in one embodiment of the present disclosure;
[0031] Figure 7 This is a schematic diagram of the structure of a wafer calibration device provided in another embodiment of the present disclosure;
[0032] Explanation of reference numerals in the attached figures:
[0033] 50. Wafer calibration device; 51. Scan control module; 52. First preset alignment mark acquisition module; 53. Calibration module; 531. Second preset alignment mark acquisition unit; 532. Calibration unit. Detailed Implementation
[0034] To facilitate understanding of the embodiments of this disclosure, a more complete description of the embodiments of this disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of this disclosure are shown in the drawings. However, the embodiments of this disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein in the description of embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure.
[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0038] In the semiconductor integrated circuit manufacturing process, some typical defects, such as bridging and defocusing, occur after photolithography, which can affect the yield of semiconductor integrated circuits to varying degrees. Therefore, defect inspection after photolithography is essential. For example, in the 12-inch wafer production process, the optical microscope (OM) in the defect inspection machine emits incident light onto the target wafer and receives the reflected light. Then, it determines whether the target wafer surface has photoresist based on the surface absorbance, which is the difference between the incident light and the reflected light. If photoresist is detected, the machine pauses defect inspection. Engineers, based on the prompts on the defect inspection machine screen, change the wafer defect inspection program to a low-voltage electrical flow program for wafers with photoresist. This avoids errors from manual judgment of the wafer surface condition, prevents the risk of photoresist damage during defect inspection, and reduces labor costs.
[0039] However, due to factors such as the increasing number of stacked film layers in the semiconductor structure or changes in film layer thickness, alignment marks in different film layers may be partially obscured, or the actual size of the wafer may change. These subtle changes cannot be detected by the absorbance of the target wafer surface. If alignment marks are obscured during the alignment correction process, manual alignment correction is required, leading to machine downtime, wasting engineers' time, increasing labor costs, and reducing equipment capacity. Therefore, the embodiments of this disclosure aim to provide a wafer calibration method, apparatus, device, and storage medium that can effectively avoid machine downtime due to alignment failure, improve the efficiency and intelligence of wafer alignment, increase equipment capacity, and reduce labor costs.
[0040] Please see Figure 1 This disclosure provides a wafer calibration method, including the following steps:
[0041] Step S10: Control the defect inspection machine to scan the alignment surface of the target wafer on the machine bearing surface with a first preset positioning accuracy;
[0042] Step S20: Adjust the position of the target wafer to obtain a first preset alignment mark in the lens of the scanning machine, wherein the first preset alignment mark is located at a first preset position on the alignment surface;
[0043] Step S30: If the acquisition of the first preset alignment mark fails, an automatic adjustment mechanism is triggered. The lens is adjusted to scan the alignment surface with a second preset positioning accuracy. The second preset alignment mark on the alignment surface is identified in the lens. The position of the target wafer is calibrated using the second preset alignment mark as the target alignment pattern. The second preset positioning accuracy is less than the first preset positioning accuracy.
[0044] As an example, please continue reading Figure 1 During the defect inspection process on the target wafer, after the defect inspection machine scans the alignment surface of the target wafer on the machine bearing surface with a first preset positioning accuracy, it adjusts the position of the target wafer to obtain the first preset alignment mark on the alignment surface of the target wafer in the lens of the scanning machine to achieve intelligent alignment. If the acquisition of the first preset alignment mark fails, an automatic adjustment mechanism is triggered, and the lens is adjusted to scan the alignment surface of the target wafer with a second preset positioning accuracy with a lower positioning accuracy. The second preset alignment mark on the alignment surface is identified in the lens, and the position of the target wafer is calibrated using the second preset alignment mark as the target alignment pattern. If the first preset alignment mark is not obtained with the first preset positioning accuracy, an automatic adjustment mechanism is triggered. The lens is automatically adjusted to a second preset positioning accuracy with a lower accuracy to identify and obtain a second preset alignment mark on the alignment surface. The second preset alignment mark is then used as the target alignment pattern to calibrate the position of the target wafer. This avoids equipment downtime caused by the failure to align with the first preset alignment mark due to factors such as the increasing number of stacked films or changes in film thickness in the semiconductor structure. By triggering the automatic adjustment mechanism and obtaining the second preset alignment mark, the position of the target wafer is automatically calibrated, improving the efficiency and intelligence of wafer alignment, increasing equipment capacity, and reducing labor costs.
[0045] As an example, please continue reading Figure 1 The first preset alignment mark is located at the first preset position on the alignment surface. The first preset position can be located in the middle area of the alignment surface of the target wafer. The first preset alignment mark can be a central crosshair cursor. The two intersecting edges of the central crosshair cursor are used as alignment reference lines, which can effectively reduce the difficulty of automatic alignment and improve the efficiency of alignment.
[0046] As an example, please continue reading Figure 1The second preset alignment marker includes: a corner area of a storage array region within the alignment surface; and / or a corner area of a measurement pattern within the alignment surface. Since the corner area / corner area generally includes at least two intersecting edges, using at least these two intersecting edges as alignment reference lines can effectively reduce the difficulty of automatic alignment and improve alignment efficiency.
[0047] As an example, please continue reading Figure 1 The measurement pattern is located in the dicing channel between adjacent dies within the alignment surface, avoiding the situation where the second preset alignment mark fails to align due to factors such as the continuous increase in the number of stacked films or changes in film thickness in the semiconductor structure, which could cause the equipment to crash.
[0048] For example, please refer to Figure 2 and Figure 3 In step S31, during the process of determining whether the first preset alignment mark has been successfully acquired, if the image displayed in the lens field of view is as follows... Figure 3 As shown, if obtaining the first preset alignment mark fails, an automatic adjustment mechanism is triggered, including performing the following steps in step S30 to identify the second preset alignment mark on the alignment surface in the lens:
[0049] Step S32: Adjust the lens to obtain a first alignment area on the alignment surface with a second preset positioning accuracy, and identify a second alignment area in the first alignment area according to a first preset rule;
[0050] Step S34: Adjust the lens to scan the second alignment area with a third preset positioning accuracy, and identify and obtain the second preset alignment mark in the second alignment area according to the second preset rule; wherein the difference between the first preset positioning accuracy and the third preset positioning accuracy is within the first preset error range.
[0051] For example, please refer to Figure 2 , Figures 4a-4c The first preset error range can include zero or near-zero numbers. If the acquisition of the first preset alignment mark with the first preset positioning accuracy fails, an automatic adjustment mechanism is triggered. The lens is adjusted to acquire a first alignment area on the alignment surface with a second preset positioning accuracy, which is lower. For example... Figure 4a As shown, the first alignment region includes six complete dies. Within the first alignment region, a second alignment region is identified according to at least one of the following preset rules: sequential identification, reverse identification, or identification of dies whose codes contain target identifiers. For example, the corner region of the memory array coded as "I" is obtained as the second alignment region according to the ascending order of the die codes. Figure 4bAs shown; the lens is then adjusted to a third preset positioning accuracy, which is approximately the same as the first preset positioning accuracy, and the second alignment area is scanned. Within the second alignment area, according to a second preset rule, such as sequential recognition, reverse recognition, or recognition of raw film containing the target identifier, at least one rule is used to identify and obtain the second preset alignment identifier. Figure 4c Using the corner area with the intersection of the "+" symbol as the vertex as the target alignment pattern, the position of the target wafer is automatically calibrated, improving the efficiency and intelligence of wafer alignment, increasing equipment capacity and reducing labor costs.
[0052] As an example, please continue reading Figure 2 , Figures 4a-4c The step of identifying and obtaining a second preset alignment identifier in the second alignment region according to a second preset rule includes: obtaining the identification code of the target alignment pattern; traversing the codes of each storage array region in the second alignment region, where different storage array regions have different codes; and determining at least one corner region of the storage array region corresponding to the code with the same identification code as the second preset alignment identifier. Since at least one corner region of the storage array region corresponding to the code with the same identification code generally includes at least two intersecting edges, using at least these two intersecting edges as alignment reference lines can effectively reduce the difficulty of automatic alignment and improve alignment efficiency.
[0053] For example, please refer to Figure 5 Step S30, which uses the second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer, further includes the following steps:
[0054] Step S36: Adjust the lens to align the target wafer with the fourth preset positioning accuracy and the second preset alignment mark as the target alignment pattern; wherein the first preset positioning accuracy is less than the fourth preset positioning accuracy.
[0055] As an example, please continue reading Figure 5 After acquiring the second preset alignment mark, the lens is adjusted to a fourth preset positioning accuracy, which is higher than the first preset positioning accuracy, and the second preset alignment mark is used as the target alignment pattern, such as a right angle in the corner of the dicing channel or a right angle in the corner of the wafer edge. The position of the target wafer is automatically calibrated, which improves the efficiency and intelligence of wafer alignment, increases equipment capacity and reduces labor costs.
[0056] As an example, please continue reading Figure 5The corner area includes a first side and a second side that are perpendicular to each other; the step of calibrating the position of the target wafer with the second preset alignment mark as the target alignment pattern includes: calibrating the position of the target wafer with the first side, the second side and the perpendicular point of the two as the target alignment pattern, and using these two intersecting sides as alignment reference lines, which can effectively reduce the difficulty of automatic alignment and improve the efficiency of alignment.
[0057] As an example, please continue reading Figure 5 The first preset alignment mark is located within the dicing channel of the target wafer to avoid equipment downtime caused by the failure of alignment with the second preset alignment mark due to factors such as the continuous increase in the number of stacked films or changes in film thickness in the semiconductor structure.
[0058] As an example, please continue reading Figure 5 The second preset alignment mark includes: a corner area of a storage array region within the alignment surface or a corner area of a measurement pattern within the alignment surface, or both a corner area of a storage array region within the alignment surface and a corner area of a measurement pattern within the alignment surface. By using the corner area of a storage array region within the alignment surface and / or the corner area of a measurement pattern within the alignment surface as the alignment pattern, since the corner area / corner area generally includes at least two intersecting edges, using at least these two intersecting edges as alignment reference lines can effectively reduce the difficulty of automatic alignment and improve alignment efficiency.
[0059] As an example, please continue reading Figure 5 The measurement pattern is located in the dicing channel between adjacent dies within the alignment surface, avoiding the situation where the second preset alignment mark fails to align due to factors such as the continuous increase in the number of stacked films or changes in film thickness in the semiconductor structure, which could cause the equipment to crash.
[0060] As an example, please continue reading Figure 5 After adjusting the target wafer position in step S20 to obtain the first preset alignment mark in the lens of the scanning machine, the following steps are also included:
[0061] In step S40, if the first preset alignment mark is obtained, the lens is adjusted to calibrate the position of the target wafer with the third preset positioning accuracy and the first preset alignment mark as the target alignment pattern.
[0062] As an example, please continue reading Figure 5 After obtaining the first preset alignment mark, the lens is adjusted to calibrate the position of the target wafer with the third preset positioning accuracy and the first preset alignment mark as the target alignment pattern. This achieves automatic calibration of the target wafer position by obtaining the first preset alignment mark with the first preset positioning accuracy, thereby improving the efficiency and intelligence of wafer alignment, increasing equipment capacity and reducing labor costs.
[0063] For example, please refer to Figure 6 A wafer calibration device 50 includes a scanning control module 51, a first preset alignment mark acquisition module 52, and a calibration module 53. The scanning control module 51 controls a defect inspection machine to scan the alignment surface of a target wafer on the machine's support surface with a first preset positioning accuracy. The first preset alignment mark acquisition module 52 adjusts the position of the target wafer to acquire the first preset alignment mark in the lens of the scanning machine, wherein the first preset alignment mark is located at a first preset position on the alignment surface. If the acquisition of the first preset alignment mark fails, the calibration module 53 triggers an automatic adjustment mechanism, adjusts the lens to scan the alignment surface with a second preset positioning accuracy, identifies the second preset alignment mark on the alignment surface in the lens, and uses the second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer, wherein the second preset positioning accuracy is less than the first preset positioning accuracy.
[0064] As an example, please continue reading Figure 6 The first preset alignment mark is located at a first preset position on the alignment surface of the target wafer. The first preset position can be located in the middle area of the alignment surface of the target wafer. The first preset alignment mark can be a central crosshair cursor. The two intersecting edges of the central crosshair cursor are used as alignment reference lines, which can effectively reduce the difficulty of automatic alignment and improve the efficiency of alignment.
[0065] As an example, please continue reading Figure 6 The second preset alignment marker includes: a corner area of a storage array region within the alignment surface; and / or a corner area of a measurement pattern within the alignment surface. Since the corner area / corner area generally includes at least two intersecting edges, using at least these two intersecting edges as alignment reference lines can effectively reduce the difficulty of automatic alignment and improve alignment efficiency.
[0066] As an example, please continue reading Figure 6 The measurement pattern is located in the dicing channel between adjacent dies within the alignment surface, avoiding the situation where the second preset alignment mark fails to align due to factors such as the continuous increase in the number of stacked films or changes in film thickness in the semiconductor structure, which could cause the equipment to crash.
[0067] For example, please refer to Figure 7The calibration module 53 includes a second preset alignment mark acquisition unit 531, which is used to adjust the lens to acquire a first alignment area on the alignment surface with a second preset positioning accuracy, and to identify a second alignment area in the first alignment area according to a first preset rule; and to adjust the lens to scan the second alignment area with a third preset positioning accuracy, and to identify and acquire a second preset alignment mark in the second alignment area according to a second preset rule; wherein the difference between the first preset positioning accuracy and the third preset positioning accuracy is within the first preset error range.
[0068] For example, please refer to Figure 7 , Figures 4a-4c The first preset error range can include zero or near-zero numbers. If the calibration module 53 fails to acquire the first preset alignment mark with the first preset positioning accuracy, it triggers an automatic adjustment mechanism to adjust the lens to acquire a first alignment area on the alignment surface with a second preset positioning accuracy that is lower. For example... Figure 4a As shown, the first alignment region includes six complete dies. Within the first alignment region, a second alignment region is identified according to at least one of the following preset rules: sequential identification, reverse identification, or identification of dies whose codes contain target identifiers. For example, the corner region of the memory array coded as "I" is obtained as the second alignment region according to the ascending order of the die codes. Figure 4b As shown in the diagram; the calibration module 53 readjusts the lens to a third preset positioning accuracy that is approximately the same as the first preset positioning accuracy, scans the second alignment area, and identifies and obtains the second preset alignment mark in the second alignment area according to a second preset rule, such as sequential recognition, reverse recognition, or recognition of bare film containing the target identifier in the code, for example... Figure 4c Using the corner area with the intersection of the "+" symbol as the vertex as the target alignment pattern, the position of the target wafer is automatically calibrated, improving the efficiency and intelligence of wafer alignment, increasing equipment capacity and reducing labor costs.
[0069] As an example, please continue reading Figure 7 , Figures 4a-4c The second preset alignment identifier acquisition unit 531 is configured to perform the following steps: acquire the identification code of the target alignment pattern; traverse the codes of each storage array region in the second alignment region, where different storage array regions have different codes; and determine at least one corner region of the storage array region corresponding to the code with the same identification code as the second preset alignment identifier. Since at least one corner region of the storage array region corresponding to the code with the same identification code generally includes at least two intersecting edges, using at least these two intersecting edges as alignment reference lines can effectively reduce the difficulty of automatic alignment and improve alignment efficiency.
[0070] As an example, please continue reading Figure 7The calibration module 53 also includes a calibration unit 532, which is used to adjust the lens to calibrate the position of the target wafer with a fourth preset positioning accuracy and a second preset alignment mark as the target alignment pattern; wherein the first preset positioning accuracy is less than the fourth preset positioning accuracy.
[0071] As an example, please continue reading Figure 7 After the second preset alignment mark acquisition unit 531 acquires the second preset alignment mark, the calibration unit 532 adjusts the lens to a fourth preset positioning accuracy, which is higher than the first preset positioning accuracy, and uses the second preset alignment mark as the target alignment pattern, such as a right angle in the corner of the dicing channel or a right angle in the corner of the wafer edge, to automatically calibrate the position of the target wafer, thereby improving the efficiency and intelligence of wafer alignment, increasing equipment capacity and reducing labor costs.
[0072] As an example, please continue reading Figure 7 The corner area includes a first side and a second side that are perpendicular to each other; the calibration unit 532 uses a second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer, which includes: using the first side, the second side and the perpendicular point of the two as the target alignment pattern to calibrate the position of the target wafer. Using these two intersecting sides as alignment reference lines can effectively reduce the difficulty of automatic alignment and improve the efficiency of alignment.
[0073] As an example, please continue reading Figures 6-7During the defect inspection process of the target wafer, after the scanning control module 51 controls the defect inspection machine to scan the alignment surface of the target wafer on the machine bearing surface with a first preset positioning accuracy, the first preset alignment mark acquisition module 52 adjusts the position of the target wafer to acquire the first preset alignment mark of the alignment surface of the target wafer in the lens of the scanning machine, so as to achieve intelligent alignment. If the acquisition of the first preset alignment mark fails, the calibration module 53 triggers the automatic adjustment mechanism, adjusts the lens to scan the alignment surface of the target wafer with a second preset positioning accuracy with a lower positioning accuracy, and identifies the second preset alignment mark on the alignment surface in the lens. The second preset alignment mark is used as the target alignment pattern to calibrate the position of the target wafer. The second preset positioning accuracy is less than the first preset positioning accuracy. If the first preset alignment mark is not obtained with the first preset positioning accuracy, an automatic adjustment mechanism is triggered. The lens is automatically adjusted to a second preset positioning accuracy with a lower accuracy to identify and obtain a second preset alignment mark on the alignment surface. The second preset alignment mark is then used as the target alignment pattern to calibrate the position of the target wafer. This avoids equipment downtime caused by the failure to align with the first preset alignment mark due to factors such as the increasing number of stacked films or changes in film thickness in the semiconductor structure. By triggering the automatic adjustment mechanism and obtaining the second preset alignment mark, the position of the target wafer is automatically calibrated, improving the efficiency and intelligence of wafer alignment, increasing equipment capacity, and reducing labor costs.
[0074] Furthermore, in some embodiments of this disclosure, a wafer calibration device is provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method described in any of the above embodiments.
[0075] Furthermore, in some embodiments of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the above embodiments.
[0076] In the aforementioned wafer calibration equipment or storage medium, during the defect detection process of the target wafer, after controlling the defect inspection machine to scan the alignment surface of the target wafer on the machine bearing surface with a first preset positioning accuracy, the position of the target wafer is adjusted to obtain the first preset alignment mark on the alignment surface of the target wafer in the lens of the scanning machine, thereby achieving intelligent alignment. If the acquisition of the first preset alignment mark fails, an automatic adjustment mechanism is triggered, and the lens is adjusted to scan the alignment surface of the target wafer with a second preset positioning accuracy that is lower, and the second preset alignment mark on the alignment surface is identified in the lens. The second preset alignment mark is used as the target alignment pattern to calibrate the position of the target wafer. If the first preset alignment mark is not obtained with the first preset positioning accuracy, an automatic adjustment mechanism is triggered. The lens is automatically adjusted to a second preset positioning accuracy with a lower accuracy to identify and obtain a second preset alignment mark on the alignment surface. The second preset alignment mark is then used as the target alignment pattern to calibrate the position of the target wafer. This avoids equipment downtime caused by the failure to align with the first preset alignment mark due to factors such as the increasing number of stacked films or changes in film thickness in the semiconductor structure. By triggering the automatic adjustment mechanism and obtaining the second preset alignment mark, the position of the target wafer is automatically calibrated, improving the efficiency and intelligence of wafer alignment, increasing equipment capacity, and reducing labor costs.
[0077] It should be understood that, although Figure 1 , Figure 2 and Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, although... Figure 1 , Figure 2 and Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0078] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this disclosure can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.
[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0080] The above-described embodiments are merely illustrative of several implementation methods of the present disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent for the embodiments of the present disclosure should be determined by the appended claims.
Claims
1. A wafer calibration method, characterized in that, include: The defect inspection machine is controlled to scan the alignment surface of the target wafer on the machine bearing surface with a first preset positioning accuracy; The position of the target wafer is adjusted to obtain a first preset alignment mark in the lens of the scanning machine, wherein the first preset alignment mark is located at a first preset position on the alignment surface; If the acquisition of the first preset alignment mark fails, an automatic adjustment mechanism is triggered to adjust the lens to scan the alignment surface with a second preset positioning accuracy, identify the second preset alignment mark on the alignment surface in the lens, and use the second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer, wherein the second preset positioning accuracy is less than the first preset positioning accuracy. The step of identifying the second preset alignment mark on the alignment surface in the lens includes: The lens is adjusted to obtain a first alignment area on the alignment surface with the second preset positioning accuracy, and a second alignment area is identified in the first alignment area according to the first preset rule. The lens is adjusted to scan the second alignment area with a third preset positioning accuracy, and the second preset alignment mark is identified and obtained in the second alignment area according to the second preset rule; wherein the difference between the first preset positioning accuracy and the third preset positioning accuracy is within the first preset error range; The second preset alignment identifier includes: The corner area of a storage array region within the alignment surface; and / or The corner area of a measurement pattern within the alignment surface.
2. The wafer calibration method according to claim 1, characterized in that, The step of calibrating the position of the target wafer using the second preset alignment mark as the target alignment pattern includes: The lens is adjusted to a fourth preset positioning accuracy and a second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer; wherein the first preset positioning accuracy is less than the fourth preset positioning accuracy.
3. The wafer calibration method according to claim 1, characterized in that, The measurement pattern is located in the cut path between adjacent blanks within the alignment surface.
4. The wafer calibration method according to any one of claims 2-3, characterized in that: If the first preset alignment mark is obtained, the lens is adjusted to calibrate the position of the target wafer with the third preset positioning accuracy and the first preset alignment mark as the target alignment pattern.
5. The wafer calibration method according to any one of claims 2-3, characterized in that, The first alignment region includes a plurality of bare pieces within the alignment surface; the second alignment region includes one bare piece from the first alignment region.
6. The wafer calibration method according to claim 5, characterized in that, The step of identifying and obtaining the second preset alignment identifier in the second alignment region according to the second preset rule includes: Obtain the identification code of the target aligned with the graphic; Traverse the encoding of each storage array region in the second alignment region, as the encodings of different storage array regions are different; At least one corner region of the storage array area corresponding to the same code as the identification code is determined as the second preset alignment identifier.
7. The wafer calibration method according to claim 6, characterized in that, The corner region includes a first side and a second side that are perpendicular to each other; the step of calibrating the position of the target wafer using the second preset alignment mark as the target alignment pattern includes: The position of the target wafer is calibrated by using the first side, the second side, and their perpendicular point as the target alignment pattern.
8. The wafer calibration method according to any one of claims 1-3, characterized in that, The first preset alignment mark is located within the dicing channel of the target wafer.
9. A wafer calibration device, characterized in that, include: The scanning control module is used to control the defect inspection machine to scan the alignment surface of the target wafer on the machine bearing surface with a first preset positioning accuracy; The first preset alignment mark acquisition module is used to adjust the position of the target wafer to acquire the first preset alignment mark in the lens of the scanning machine, wherein the first preset alignment mark is located at a first preset position on the alignment surface; The calibration module is used to trigger an automatic adjustment mechanism if the acquisition of the first preset alignment mark fails, adjust the lens to scan the alignment surface with a second preset positioning accuracy, identify the second preset alignment mark on the alignment surface in the lens, and use the second preset alignment mark as the target alignment pattern to calibrate the position of the target wafer, wherein the second preset positioning accuracy is less than the first preset positioning accuracy. The calibration module includes: The second preset alignment mark acquisition unit is used to adjust the lens to acquire a first alignment area on the alignment surface with the second preset positioning accuracy, and to identify a second alignment area in the first alignment area according to a first preset rule; and The lens is adjusted to scan the second alignment area with a third preset positioning accuracy, and the second preset alignment mark is identified and obtained in the second alignment area according to the second preset rule; wherein the difference between the first preset positioning accuracy and the third preset positioning accuracy is within the first preset error range; The second preset alignment identifier includes: The corner area of a storage array region within the alignment surface; and / or The corner area of a measurement pattern within the alignment surface.
10. The wafer calibration apparatus according to claim 9, characterized in that, The calibration module also includes: The calibration unit is used to adjust the lens to calibrate the position of the target wafer with a fourth preset positioning accuracy and a second preset alignment mark as the target alignment pattern; wherein the first preset positioning accuracy is less than the fourth preset positioning accuracy.
11. A wafer calibration device, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.
12. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, which is executed by a processor, implements the steps of the method according to any one of claims 1 to 8.