A control method for a DC-DC converter and a control chip module thereof

Abstract

The present invention discloses a control method for a DC-DC converter and a control chip module thereof, wherein the control method comprises: s [k-1] Calculate T of the current switching cycle 2crm [k], calculate T of the current switching cycle u [k], determine the mode used in the current switching cycle, calculate T1[k], T2[k], T s [k], obtains a reset signal and modulates a PWM signal. The control chip module includes a control algorithm component, a comparator, and a PWM modulation component. The present invention reduces losses and improves conversion efficiency in both step-up and step-down operating conditions, saving hardware costs and further improving the converter's conversion efficiency. High-precision sampling can be achieved even under light loads, allowing the selection of smaller sampling resistors.

Description

Technical Field

[0001] The present invention belongs to the technical field of non-isolated power supplies, and in particular relates to a control method for a DC-DC converter and a control chip module thereof. Background Art

[0002] In non-isolated power conversion situations that require both boost and buck, four-switch Buck-Boost DC-DC converters are widely used, such as battery charging, photovoltaic grid connection, power factor correction, etc. Figure 1A As shown, the DC-DC converter includes four switches Q1-Q4, an inductor L1, and an input capacitor C in and output capacitor C o . Input voltage V during operation in Can be less than or greater than the output voltage V o , that is, it has the function of step-up and step-down conversion.

[0003] One of the existing technologies for controlling the converter is to use partition mode switching control: when V in >V o When Q3 is normally open, Q4 is normally closed, Q1 and Q2 are complementary switches, working in Buck mode, Q1 is the main switch tube, and Q2 is the synchronous rectifier tube; when V in <V o When V in With V o When approaching, it operates in a special transition mode. Except under extremely light load conditions, the inductor typically operates in continuous current mode (CCM). Although synchronous rectifiers Q2 and Q3 can achieve zero voltage switching (ZVS), the main switches Q1 and Q4 operate in hard-on mode, resulting in high switching losses and limiting the increase in switching frequency. To reduce the size of the inductor, it is usually necessary to increase the switching frequency, but this hard-switching control method cannot meet this requirement. Furthermore, this type of control method inherently suffers from the uneven switching between operating modes. To address this smooth switching issue, the controller implementation is more complex.

[0004] Another control method in the prior art is to have all four switches switch at high frequency. By controlling the inductor current in the reverse direction at the right time, the main switches Q1 and Q4 can also achieve zero-voltage switching (ZVS), thus enabling all four switches to achieve soft switching. Because soft switching reduces switching losses, especially when using silicon carbide (SiC) or gallium nitride (GaN) semiconductor devices, which have extremely low turn-off energy, controlling them to operate at zero-voltage switching (ZVS) results in extremely low switching losses and significantly increases the switching frequency, thereby improving the converter's conversion efficiency and power density. However, this results in larger inductor current ripple, resulting in a higher effective current value at the same output power, which increases the circuit's conduction losses.

[0005] Current detection is the basis for realizing the above control method. The existing typical current detection schemes are as follows: Figures 1B to 1D In order to achieve ZVS control of the switch tubes Q1 and Q4, it is necessary to detect whether the inductor current is negative when Q2 or Q3 is turned off. Usually, a resistor R is connected in series between the source of Q2 tube and ground. sens Perform current detection, such as Figure 1B As shown. Since the current on Q2 tube cannot fully reflect the inductor current information, for example, when Q2 tube is turned off and works in Boost mode. Figure 1C Another current detection scheme is given, which is to insert R in series between the source parallel connection point of Q2 and Q4 and ground. sens Whether working in Buck mode or Boost mode, the peak value of the inductor current can be detected, which can achieve ZVS control and timely cycle-by-cycle overcurrent protection. However, since the source is separated from the ground, it is not conducive to the heat dissipation of Q2 and Q4. In addition, in order to sample the output current, a resistor R is usually connected in series with the output port. osens ,like Figure 1B As shown, this will increase conduction losses and hardware cost. Figure 1D Another current detection solution is given, which is to insert R in series with the inductor branch. sens , the complete inductor current can be detected, which can realize both ZVS control and cycle-by-cycle overcurrent protection. However, due to R sens The voltages at both ends are PWM high-frequency jump voltages, which place high demands on the differential op amp and are also relatively expensive.

[0006] The typical working waveform is shown in Figure 2, where Figure 2A V o <V in The working waveform when Figure 2B V o >V inThe working waveform of the time, the PWM signals corresponding to Q1 to Q4 in the figure are PWM1 to PWM4 respectively. As can be seen from the figure, a switching cycle consists of four segments, namely T1, T2, T3, and T4, which represent the time when Q1 and Q4, Q1 and Q3, Q2 and Q3, and Q2 and Q4 are turned on together, respectively. Therefore, T s =T1+T2+T3+T4. Figure 2A As an example, the ZVS control method of the prior art is described. In the T1 period, Q1 and Q4 are turned on, and V in Applied to the inductor, the inductor current i L Rising to I1; Q1 and Q3 are turned on during T2, (V in -V o ) is applied to the inductor, the inductor current i L Rising to I2; in the T3 period, Q2 and Q3 are turned on, -V o Applied to the inductor, the inductor current i L Descending, when it drops to -I ZVS PWM3 is turned off and the T3 period ends. Since the inductor current is negative at this moment (i L =-I ZVS ), this current charges the parasitic capacitance of Q3 and discharges the parasitic capacitance of Q4. The drain-source voltage V ds3 Rising, Q4's drain-source voltage V ds4 Falling, when V ds4 When the voltage drops to zero, PWM4 is turned on and Q4 achieves ZVS. During the T4 period, Q2 and Q4 are turned on, and approximately zero voltage is applied to the inductor. The inductor current i L Maintain at -I ZVS Similarly, at the end of T4, which is the beginning of the next switching cycle, Q1 also achieves ZVS. Since the inductor current remains unchanged during T4, this operating mode is called discontinuous mode (DCM). Figure 2B The situation and Figure 2A The main difference is in the T2 period, because V o >V in , the inductor current drops from I1 to I2, and the rest of the period is similar. The detailed process will not be repeated here. All switches can also achieve ZVS. It should be noted that under the premise of achieving ZVS, I ZVS The smaller the better, which is beneficial to improving the conversion efficiency of the converter. Therefore, I ZVS It is usually set to the minimum current value that can achieve ZVS.

[0007] However, compared with the CCM mode, the inductor current ripple in the ZVS working mode is larger, and the effective value of the current is larger at the same output power. Although the ZVS control reduces the switching loss, it increases the conduction loss of the converter. Therefore, under the premise of achieving ZVS, how to minimize the effective value of the inductor current becomes a control problem that needs to be solved urgently. Due to the existence of multiple control degrees of freedom, different combinations of T1 and T2 can output the same power. In order to minimize the effective value of the inductor current at the same power, thereby reducing the conduction loss of the converter, one strategy of the prior art is to adopt a soft switching control strategy with a fixed switching frequency, and use a table lookup method to obtain the T1 and T2 combinations under different working conditions to minimize the effective value of the current. However, this implementation method requires the controller to have a large amount of storage space, especially for different input and output voltage ranges, a large amount of T1 and T2 combination data needs to be stored, so the controller cost is relatively high. In order to simplify the implementation, a method of calculating T1 in the prior art is: when V o <=V in When I1=I ZVS For this reason When V o >V in When controlling I2=I ZVS For this reason According to the inductor "volt-second balance" principle, V in (T1+T2)=V o (T2+T3), it can be deduced that at this time In summary, T1 can be directly calculated using an analytical expression without storing a lookup table.

[0008] Another degree of control freedom T2 is used to control the output power. The larger T2 is, the greater the output power is. As the power increases, T4 is s The proportion of T4 will become smaller. When T4 decreases to zero, the converter enters the critical mode (CRM) operation, as shown in Figure 3. At this time, a switching cycle only includes T1, T2, and T3, that is, T s =T1+T2+T3. Among them, T2 reaches its maximum value T 2max ,like Figure 3A As shown, when V o <=V in hour, like Figure 3B As shown, when V o >V in hour, In summary, In addition, the existing technology adopts a fixed switching period T when DCM is used. s To calculate T 2max , which means that for a given set of V inand V o Under the condition, when the converter output power increases and enters CRM mode, T2 will remain unchanged. However, the converter efficiency under this control strategy is not optimal, especially when V in and V o When approaching.

[0009] In addition to achieving ZVS control, it is usually necessary to perform closed-loop control on the output and / or input current of the converter to obtain better control performance. In the prior art, a sampling resistor is usually inserted in series in the output and / or input circuit to directly detect the output and / or input current. Taking the output current detection as an example, Figure 4 As shown, a resistor R is usually connected in series in the output circuit. osens , the accuracy of direct detection is relatively high, but it will increase the conduction loss and hardware cost.

[0010] Therefore, how to ensure the soft switching of DC-DC converter while minimizing the effective value of inductor current, making the conversion efficiency optimal and easy to achieve while saving costs is an urgent problem to be solved. Summary of the Invention

[0011] In view of this, one of the objectives of the present invention is to provide a control method for a DC-DC converter, which saves costs while reducing losses to maximize conversion efficiency.

[0012] To achieve the above object, the present invention provides a first aspect of a control method for a DC-DC converter, comprising:

[0013] According to T s [k-1] Calculate T of the current switching cycle 2crm [k]; where T 2crm [k] is the duration of time during which the first and third switch tubes are turned on together in the kth switching cycle in the CRM mode. k is a positive integer. The CRM mode is a critical mode. T s [k-1] is the total duration of the (k-1)th switching cycle;

[0014] Get T u [k]; where T u [k] is the reference value of T2[k] corresponding to the DCM mode of the kth switching cycle. T2[k] is the duration during which the first and third switches are turned on together in the kth switching cycle. The DCM mode is the discontinuous mode.

[0015] According to T 2crm [k] and T u The size relationship of [k] determines the mode adopted in the current switching cycle and T2[k];

[0016] According to Vo With V in , calculate T1[k]; where T1[k] is the duration of the first switch tube and the fourth switch tube being turned on together in the kth switching cycle, V o is the output voltage sampling value, V in is the input voltage sampling value;

[0017] According to the mode adopted in the current switching cycle, calculate T s [k]; where T s [k] is the total duration of the kth switching cycle;

[0018] According to i L with I ZVS The size relationship is used to determine whether the reset signal is valid; among them, i L is the inductor current signal, I ZVS To achieve the minimum current in zero voltage switching mode, ZVS is the zero voltage switching mode;

[0019] According to T1[k], T2[k], T s [k] and reset signal, modulate the PWM signal, and use the PWM signal to control the opening and closing of the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube.

[0020] Preferably, calculate the T of the current switching cycle 2crm [k], specifically:

[0021] Calculate T according to formula (1) 2crm [k]:

[0022]

[0023] Where: L is the inductance value of the inductor.

[0024] Preferably, if T 2crm [k]>T 2max , then T 2crm [k] = T 2max , where T 2max It is the preset maximum value of T2[k] duration.

[0025] Preferably, T u [k] is generated by a closed-loop regulator, which can be a current closed-loop regulator or a voltage closed-loop regulator. The regulator typically employs a proportional-integral (PI) regulator, which is well known and will not be described in detail here.

[0026] Preferably, according to T 2crm [k] and T u The relationship between the size of [k] determines the mode adopted in the current switching cycle and T2[k], specifically:

[0027] If T u [k]≤T 2crm [k], the current switching cycle adopts DCM mode, and T2[k]=T u [k];

[0028] If T u [k]>T 2crm [k], the current switching cycle adopts CRM mode, and T2[k]=T 2crm [k].

[0029] Preferably, according to when V o With V in The relationship between the size of the two is to calculate T1[k], specifically:

[0030] If V o >V in , then calculate T1[k] according to formula (2):

[0031]

[0032] If V o ≤V in , then calculate T1[k] according to formula (3):

[0033]

[0034] Where: ΔT2[k]=T u [k]-T2[k].

[0035] Preferably, T is calculated according to the mode adopted in the current switching cycle. s [k], specifically:

[0036] If the current switching cycle adopts DCM mode, then T s [k] gradually decreases to T s0 , T s0 The preset value of the switching cycle length in DCM mode;

[0037] If the current switching cycle adopts CRM mode, calculate T according to formula (4) s [k]:

[0038]

[0039] Preferably, T s [k] gradually decreases to T s0 Specifically, calculate T according to formula (5.1) s [k]:

[0040] T s [k] = Ts [k-1]+m(T s0 -T s [k-1]) (5.1);

[0041] Where: m is the preset switching cycle change ratio coefficient, 0 <m<1。

[0042] Preferably, T s [k] gradually decreases to T s0 Specifically, calculate T according to formula (5.2) s [k]:

[0043] T s [k] = T s [k-1]-ΔT s (5.2);

[0044] Where: ΔT s is the preset switching cycle change step.

[0045] Judge T s [k] and T s0 The size relationship, if T s [k] <T s0 , then set T s [k] = T s0 .

[0046] Preferably, according to i L with I ZVS The size relationship is used to determine whether the reset signal is valid, specifically:

[0047] when i L ≤(-I ZVS ), the reset signal is valid;

[0048] when i L >(-I ZVS ), the reset signal is invalid.

[0049] Preferably, according to T1[k], T2[k], T s [k] and reset signal, modulate the PWM signal, and use the PWM signal to control the opening and closing of the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube, specifically:

[0050] In the kth switching cycle, the first switch tube and the fourth switch tube are turned on together during the first T1[k] duration; and then the first switch tube and the third switch tube are turned on together during the subsequent T2[k] duration.

[0051] During the subsequent time period, until the reset signal becomes valid, the second switch tube and the third switch tube are turned on together;

[0052] If the mode adopted in the current switching cycle is the DCM mode, after the reset signal is valid, the second switch tube and the fourth switch tube are turned on together.

[0053] Preferably, the method further comprises: calculating I according to I1 and I2 out_est and / or I in_est ;

[0054] Among them, I out_est is the estimated output current, I in_est is the estimated value of input current,

[0055] When the fourth switch is turned off, I1 is recorded. I1 is the inductor current at the end of the T1 period.

[0056] I2 is recorded when the first switch tube is turned off. I2 is the inductor current at the end of the T2 period.

[0057] Preferably, I is calculated according to formula (6) in_est :

[0058]

[0059] Preferably, the time duration T from the start of the current switching cycle to the reset signal becoming valid is obtained. c [k];

[0060] Calculate T3[k] according to formula (7):

[0061] T3[k]=T c [k]-(T1[k]+T2[k]) (7);

[0062] Calculate I according to formula (8) out_est :

[0063]

[0064] Preferably, I is calculated according to formula (9) out_est :

[0065]

[0066] Preferably, I is calculated according to formula (10) out_est :

[0067]

[0068] And / or, calculate I according to formula (11) in_est :

[0069]

[0070] Preferably, the actual output current value is used to calculate Iout_est Perform linear fitting calibration and / or use actual input current values ​​to compare I in_est Perform linear fit calibration.

[0071] A second aspect of the present invention provides a control chip module for a DC-DC converter, comprising: a control algorithm component, a comparator, and a PWM modulation component;

[0072] The control algorithm component receives the sampled V in 、V o signal and the preset reference output voltage V ref Or reference output current I ref Signal;

[0073] Control algorithm components according to T s [k-1] Calculate T of the current switching cycle 2crm [k]; where T 2crm [k] is the duration of time during which the first and third switch tubes are turned on together in the kth switching cycle in the CRM mode. k is a positive integer. The CRM mode is a critical mode. T s [k-1] is the total duration of the (k-1)th switching cycle;

[0074] The control algorithm component is based on the preset reference output voltage V ref Or reference output current I ref The closed-loop regulator calculates T of the current switching cycle u [k]; where T u [k] is the reference value of T2[k] corresponding to the DCM mode of the kth switching cycle. T2[k] is the duration during which the first and third switches are turned on together in the kth switching cycle. The DCM mode is the discontinuous mode.

[0075] Control algorithm components according to T 2crm [k] and T u The size relationship of [k] determines the mode adopted in the current switching cycle and T2[k];

[0076] The control algorithm components are based on V o With V in , calculate T1[k]; where T1[k] is the duration of the first switch tube and the fourth switch tube being turned on together in the kth switching cycle, V o is the output voltage sampling value, V in is the input voltage sampling value;

[0077] The control algorithm component calculates T according to the mode adopted in the current switching cycle. s [k]; where T s [k] is the total duration of the switching cycle;

[0078] The control algorithm component converts T1[k], T2[k], T s [k] Output to PWM modulation component;

[0079] The comparator is based on i L with I ZVS The size relationship between the output reset signal to the PWM modulation component; where i L is the inductor current signal, I ZVS To achieve the minimum current in zero voltage switching mode, ZVS is the zero voltage switching mode;

[0080] The PWM modulation component is based on T1[k], T2[k], T s [k] and reset signal, modulate the PWM signal, and use the PWM signal to control the opening and closing of the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube.

[0081] A third aspect of the present invention provides a DC-DC converter module comprising: a four-port Buck circuit network, a four-port Boost circuit network, an inductor, and a detection resistor;

[0082] The four-port Buck circuit network includes a Buck bridge arm, an input capacitor, a voltage input positive port and a voltage input ground port;

[0083] The Buck bridge arm and the input capacitor are electrically connected in parallel;

[0084] The voltage input positive terminal and the voltage input ground terminal are electrically connected to two ends of the input capacitor respectively;

[0085] The Buck bridge arm includes a first switching tube and a second switching tube connected in series;

[0086] The source of the second switch tube is electrically connected to the voltage input ground port;

[0087] The four-port Boost circuit network includes a Boost bridge arm, an output capacitor, a voltage output positive port and a voltage output ground port;

[0088] The Boost bridge arm and the output capacitor are electrically connected in parallel;

[0089] The voltage output positive port and the voltage output ground port are electrically connected to two ends of the output capacitor respectively;

[0090] The Boost bridge arm includes a third switch tube and a fourth switch tube connected in series;

[0091] The source of the fourth switch tube is electrically connected to the voltage output ground port;

[0092] The two ends of the inductor are electrically connected to the PWM voltage port of the Buck bridge arm and the PWM voltage port of the Boost bridge arm respectively;

[0093] The two ends of the detection resistor are electrically connected to the source of the second switching tube and the source of the fourth switching tube respectively;

[0094] Preferably, it also includes: a Buck driver chip and a Boost driver chip;

[0095] The Buck driver chip is electrically connected to the gate of the first switch tube and the gate of the second switch tube respectively, and the Buck driver chip is used to drive the first switch tube and the second switch tube;

[0096] The Boost driver chip is electrically connected to the gate of the third switch tube and the gate of the fourth switch tube respectively; the Boost driver chip is used to drive the third switch tube and the fourth switch tube.

[0097] Preferably, it also includes a control chip module of the DC-DC converter as described above; a voltage detection voltage divider resistor, the voltage detection voltage divider resistor is used to obtain the sampled V in 、V o signal; the control chip module outputs the PWM signal to the driver chip.

[0098] The present invention has the following beneficial effects:

[0099] (1) Regardless of whether it is a step-up or step-down operation mode, the control method of the present invention can reduce losses compared with the prior art, that is, improve the conversion efficiency;

[0100] (2) Using the existing inductor current information under ZVS control to indirectly estimate the output and / or input current through a software algorithm, thereby saving hardware costs and further improving the conversion efficiency of the converter;

[0101] (3) By extending the switching cycle, high-precision sampling can be achieved even under light loads, and a smaller sampling resistor can be selected, which greatly reduces both loss and size;

[0102] (4) The current flowing through the detection resistor and the inductor is equal in magnitude and opposite in direction. Therefore, the complete current information in the inductor can be obtained based on the voltage across the detection resistor without the need for additional input or output current sampling resistors and operational amplifiers. Compared with existing technologies, this can reduce conduction losses and save hardware costs.

[0103] (5) Cycle-by-cycle overcurrent protection can be achieved by using the inductor peak current information obtained through the detection resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0105] Figures 1A to 1D It is a circuit diagram of a DC-DC converter in the prior art;

[0106] Figure 2A and Figure 2B This is a working waveform diagram of a DC-DC converter in DCM mode in the prior art;

[0107] Figure 3A and Figure 3B This is a working waveform diagram of a DC-DC converter in the CRM mode in the prior art;

[0108] Figure 4 A circuit diagram for detecting output current in the prior art;

[0109] Figures 5A to 5C This is a circuit diagram of a DC-DC converter module according to a first embodiment of the present invention;

[0110] Figure 6 This is a schematic diagram of a control chip module according to a second embodiment of the present invention;

[0111] Figure 7 This is a flow chart of a control method for a DC-DC converter disclosed in Embodiment 2 of the present invention;

[0112] Figures 8A to 8D This is a comparison diagram of the working waveform in the CRM mode of the second embodiment of the present invention and the prior art;

[0113] 9A to 9F Schematic diagram of calculating output current estimated value / input current estimated value according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0114] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0115] Example 1

[0116] Figures 5A to 5CThe DC-DC converter module of the embodiment of the present invention is shown; the DC-DC converter module includes two four-port circuit networks, namely a four-port Buck circuit network and a four-port Boost circuit network, as well as an inductor L1 and a detection resistor R sens The four-port Buck circuit network includes a Buck bridge arm formed by two switch tubes (Q1 and Q2) connected in series and a capacitor (C in ), V in+ and V in- They are the voltage input positive port and the voltage input ground port respectively, SW1 is the PWM voltage port of the Buck bridge arm; the four-port Boost circuit network includes a boost bridge arm composed of two switch tubes (Q3 and Q4) in series and a capacitor (C o ), V out and PGND are the voltage output positive terminal and voltage output ground terminal respectively, SW2 is the PWM voltage terminal of the Boost bridge arm. The two ends of L1 are connected to SW1 and SW2 respectively. sens Connect Q at both ends 2S and Q 4S , where Q 2S is the source of Q2, Q 4S It is the source of Q4. 2S With the voltage input ground port V in- Electrical connection, Q 4S Electrically connected to the voltage output ground port PGND. Figures 1B to 1D By comparison, the voltage input ground port and the voltage output ground port are separated by the resistor R sens Separation is an obvious feature that distinguishes the present invention from the prior art.

[0117] According to the circuit principle, R sens The current flowing through L1 (i L ) are equal in magnitude and opposite in direction, so R sens The voltage across the L1 circuit reflects the complete current information in L1. Its functions include:

[0118] 1) Using inductor valley current information to achieve ZVS control;

[0119] 2) Using inductor peak current information to implement cycle-by-cycle overcurrent protection;

[0120] 3) Combining the switch state and the inductor current sampling signal, the average current at the input or output port can be estimated for feedback control or external reporting of converter operating status information without the need for additional input or output current sampling resistors and operational amplifiers. Compared with existing technologies, this can reduce conduction losses and save hardware costs.

[0121] compared to Figure 1C In the prior art shown, since the sources of Q2 and Q4 are directly electrically connected to the voltage input and output ground ports respectively, their heat can be conducted away through their source pads via the large area of ​​ground plane copper. Therefore, the heat dissipation effect of Q2 and Q4 in the embodiment of the present invention is better.

[0122] compared to Figure 1D The prior art shown in FIG. sens Connecting the two ends to the voltage input and voltage output ground ports, respectively, reduces the common-mode rejection requirements of the differential op amp and results in relatively low cost. Therefore, the embodiments of the present invention achieve high sampling accuracy and full current information sampling through a simple and practical method. This provides an effective and solid foundation for further development of various embodiments and the realization of high-quality, intelligent converter products.

[0123] In some other embodiments, such as Figure 5B As shown, the power module (Power Block) also includes a driver IC (Driver IC), an NTC temperature detection resistor, and corresponding input and output pins. The driver IC provides PWM control signals to the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube.

[0124] In some other embodiments, such as Figure 5C As shown, the power module also includes: a control chip (Control IC), input and output voltage detection voltage divider resistors (R1-R4).

[0125] Example 2

[0126] This embodiment discloses a control chip module framework structure and control method of a DC-DC converter. Figure 6 As shown, the control chip module structure includes a control algorithm component, a comparator and a PWM modulation component. Among them, the control algorithm component receives a signal V that reflects the input voltage. in 、Reflect the output voltage signal V o , and the current reference signal I that reflects the power ref , generating a signal T1 reflecting the turn-on delay time of Q3 and Q1, a signal T2 reflecting the common conduction time of Q3 and Q1, and a switching cycle signal T s The comparator unit receives the signal i that reflects the inductor current. L and threshold signal I ZVS , when i L Less than or equal to -I ZVS When the reset signal R3 is output, the PWM modulation unit receives T1, T2, T s, and the reset signal R3, generate corresponding PWM signals PWM1-PWM4, which are used to drive and control the switch tubes Q1-Q4 respectively.

[0127] It should be noted that in order to avoid the inconvenience of negative current signal operation, it is usually possible to L with -I ZVS If a positive bias is superimposed, the positive bias will be canceled out when the magnitudes are compared.

[0128] Figure 7 The flow of the control method in this embodiment is shown, which includes the following steps:

[0129] S1: According to T s [k-1] Calculate T of the current switching cycle 2crm [k]; where T 2crm [k] is the duration of time during which the first and third switch tubes are turned on together in the kth switching cycle in the CRM mode. k is a positive integer. The CRM mode is a critical mode. T s [k-1] is the total duration of the (k-1)th switching cycle.

[0130] In a preferred embodiment, T is calculated according to the following formula 2crm [k]:

[0131] Where: L is the inductance of the inductor. If T 2crm [k]>T 2max , then T 2crm [k] = T 2max , where T 2max It is the preset maximum value of T2[k] duration.

[0132] S2: Get T u [k]; where T u [k] is the reference value of T2[k] corresponding to the DCM mode of the kth switching cycle, T2[k] is the duration of the joint conduction of the first switch tube and the third switch tube in the kth switching cycle, and the DCM mode is the discontinuous mode; T u [k] is generated by a closed-loop regulator, which is a current closed-loop regulator or a voltage closed-loop regulator.

[0133] In a preferred embodiment, T u [k] is generated by a voltage closed-loop regulator; in other embodiments, T u [k] can also be generated by a current closed-loop regulator; wherein the closed-loop regulator can adopt a proportional-integral (PI) regulator.

[0134] S3: Judge T u Is [k] greater than T? 2crm[k], if yes, then enter CRM mode, and T2[k]=T 2crm [k]; if not, enter DCM mode, and T2[k] = T u [k].

[0135] S4: Calculate phase shift T1[k]: Determine V o Is it greater than V in , if so, then If not, then Where: ΔT2[k]=T u [k]-T2[k].

[0136] S5: Calculate the switching period T s [k]: If it is DCM mode, then T s [k] gradually decreases to T s0 , where T s0 is the preset value of the switching cycle length in DCM mode. If it is CRM mode,

[0137] S6: According to T1[k], T2[k], T s [k], and the reset signal R3, modulate the PWM signal; specifically: in the kth switching cycle, the first switch tube and the fourth switch tube are turned on together during the first T1[k] duration; then, during the subsequent T2[k] duration, the first switch tube and the third switch tube are turned on together;

[0138] During the subsequent period, until the reset signal R3 is valid, the second switch tube and the third switch tube are both turned on;

[0139] If the mode adopted in the current switching cycle is the DCM mode, after the reset signal R3 is valid, the second switch tube and the fourth switch tube are turned on together.

[0140] S7: Estimate output current I out_est and / or input current I in_est .

[0141] This embodiment is simulated, as shown in FIG. Figure 8A As shown, set V in =21V, V o =20V, output current is 3.2A, I ZVS =1.9A, the control method of the present invention reduces the switching frequency by 31.6%, which greatly reduces the switching loss. In addition, it can be seen that I1=I ZVS , which is lower than that of the existing technology, so the turn-off loss of Q4 is also lower.

[0142] like Figure 8B As shown, set V in =19V, Vo =20V, output current is 3.2A, I ZVS =1.9A, the switching frequency is reduced by 38.1% by adopting the control method of the present invention. In addition, it can be seen that I2=I ZVS , which is lower than that of the prior art, so the turn-off loss of Q1 is also lower. In summary, whether it is a step-up or step-down operation mode, the control method of the present invention can reduce the loss, that is, improve the conversion efficiency, compared with the prior art.

[0143] like Figure 8C 、 Figure 8D As shown, set V in =8V, V o =20V, output current is 5A, I ZVS =1.9A. By comparison, it can be seen that both I1 and I2 of the present invention are smaller than those of the prior art, resulting in lower turn-off currents and losses for Q4 and Q1. Furthermore, the effective value of the inductor current is also lower (from 16.6A to 14.5A), resulting in lower conduction losses for the converter.

[0144] Feedback control or external reporting of the converter's operating status requires output current and / or input current information. Existing technologies generally use resistors to directly detect the output current and / or input current. While direct detection offers high accuracy, it increases conduction losses and hardware costs. This embodiment infers the output current and / or input current from the inductor current waveform, eliminating the need for additional sampling resistors in conventional current measurement solutions. 9A to 9F The output current estimated value I is calculated in this embodiment. out_est and / or the estimated input current I in_est The principle of out_est is the average value of the current flowing through Q3 after being filtered by the output capacitor. Similarly, I in_est is the average value of the current flowing through Q1 after being filtered by the input capacitor. out_est Take the following example to illustrate. Figure 9A and Figure 9B It can be seen that due to the switching transient process, the actual current of Q3 contains oscillations, which is difficult to detect accurately. Therefore, this embodiment uses the area equivalence principle to calculate the output current estimate value I using the inductor current and the switching state. out_est Specifically, ignoring the switching process, when PWM3 is turned on, the average current i flowing through Q3 tube is Q3 =i L , when PWM3 is turned off i Q3 =0, while I out_est for i Q3 The average value after filtering by the output capacitor, according to the area equivalence principle, i Q3 The average value within one switching cycle is the estimated value of the output current Similarly, reference Figure 9E and Figure 9F , the estimated value of the input current can be calculated Among them, I1 and I2 are the inductor currents at the end of time periods T1 and T2, that is, the inductor currents when Q4 and Q1 are turned off.

[0145] In a preferred embodiment, the comparator event is used to capture the current PWM counter value to obtain the time length T from the start of the current switching cycle to the time when the reset signal R3 becomes valid. c , and calculate T3 = T c -(T1+T2).

[0146] In some other embodiments, the controller does not have the function of capturing the PWM counter value through the comparator event, so T3 cannot be directly obtained. However, T1 and T2 are existing control variables, and the inductor "volt-second balance" principle can be used to replace T3 with a variable. Using I1, I2, T1, T2, V in and V o calculate

[0147] In some other embodiments, such as Figure 9B As shown, in order to avoid the influence of the oscillating current generated during the switching process of the device on the sampling accuracy. s1 , occurs before Q4 turns off and leaves enough time T for sampling between the turn-off time and the turn-off time sample , that is, T s1 =T Q4off -T sample I2 sampling time T s2 , occurs before Q1 turns off and leaves enough time T for sampling between the turn-off time and the turn-off time sample , that is, T s2 =T Q1off -T sample The difference between the actual current and the sampling time caused by the sampling advance can be compensated by calculating the lead time, the inductance, and the inductor voltage drop. The calculation of this compensation factor is well known in the art and will not be described in detail here.

[0148] In some other embodiments, in order to save high-frequency current sampling and ADC, the inductor current mathematical model can also be combined to calculate and / or

[0149] In order to improve the accuracy of calculating the estimated value of the output current, this embodiment calibrates the output current, records the estimated value and the actual current value at two different output current operating points, uses the linear fitting method to obtain the proportional coefficient a and the bias coefficient b, and stores them in the controller. During formal operation, the estimated value is corrected using "y=ax+b", where x is the estimated value and y is the corrected estimated value, so that the estimated value is closer to the actual value. Furthermore, the output current can be calibrated under different input and / or output voltage conditions, and multiple sets of (a, b) calibration coefficients are stored in the controller. During formal operation, according to the current actual input and / or output voltage, a set of (a, b) is obtained by looking up the table for correction. Similarly, the input current can also be calibrated, which will not be repeated here.

[0150] In order to improve the accuracy of current estimation, the sampled values ​​I1 and I2 or the estimated value I1 within multiple switching cycles can also be used to calculate the current estimation accuracy. out_est and I in_est Perform digital filtering, such as low-pass filtering, sliding average, etc.

[0151] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control method for a DC-DC converter, wherein the DC-DC converter comprises a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, and an inductor, wherein: The steps include: According to T s [k-1] Calculate T of the current switching cycle 2crm [k]; where T 2crm [k] is the duration of time during which the first and third switch tubes are turned on together in the kth switching cycle in the CRM mode. k is a positive integer. The CRM mode is a critical mode. T s [k-1] is the total duration of the (k-1)th switching cycle; Get T u [k]; where T u [k] is the reference value of T2[k] corresponding to the DCM mode of the k-th switching cycle, and T2[k] is the duration during which the first switch tube and the third switch tube are turned on together in the k-th switching cycle. The DCM mode is a discontinuous mode; According to T 2crm [k] and T u The size relationship of [k] determines the mode adopted in the current switching cycle and T2[k]; According to V o With V in , calculate T1[k]; where T1[k] is the duration of the first switch tube and the fourth switch tube being turned on together in the kth switching cycle, V o is the output voltage sampling value, V in is the input voltage sampling value; According to the mode adopted in the current switching cycle, calculate T s [k]; where T s [k] is the total duration of the kth switching cycle; According to i L with I ZVS The size relationship is used to determine whether the reset signal is valid; among them, i L is the inductor current signal, I ZVS To achieve the minimum current in zero voltage switching mode, ZVS is the zero voltage switching mode; According to T1[k], T2[k], T s [k] and reset signal, modulate the PWM signal, and use the PWM signal to control the opening and closing of the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube.

2. The control method according to claim 1, wherein: The calculation of T2crm[k] of the current switching cycle is specifically as follows: Calculate T according to formula (1) 2crm [k]: （1）； Where: L is the inductance value of the inductor.

3. The control method according to claim 2, wherein: If T 2crm [k] > T 2max , then T 2crm [k] = T 2max , where T 2max It is the preset maximum value of T2[k] duration.

4. The control method according to claim 1, wherein: The T u [k] is generated by a closed-loop regulator, which is a current closed-loop regulator or a voltage closed-loop regulator.

5. The control method according to claim 1, wherein: According to T 2crm [k] and T u The relationship between the size of [k] determines the mode adopted in the current switching cycle and T2[k], specifically: If T u [k] ≤ T 2crm [k], the current switching cycle adopts DCM mode, and T2[k] = T u [k]; If T u [k] > T 2crm [k], the current switching cycle adopts CRM mode, and T2[k] = T 2crm [k].

6. The control method according to claim 1, wherein: According to the o With V in The relationship between the size of the two is to calculate T1[k], specifically: If V o > V in , then calculate T1[k] according to formula (2): （2）； If V o ≤ V in , then calculate T1[k] according to formula (3): （3）； Where: ΔT2[k] = T u [k] - T2[k], L is the inductance of the inductor.

7. The control method according to claim 1, wherein: According to the mode adopted in the current switching cycle, T is calculated. s [k], specifically: If the current switching cycle adopts DCM mode, then T s [k] gradually decreases to T s0 , the T s0 The preset value of the switching cycle length in DCM mode; If the current switching cycle adopts CRM mode, calculate T according to formula (4) s [k]: （4）。 8. The control method according to claim 7, wherein: The T s [k] gradually decreases to T s0 , specifically: Calculate T according to formula (5.1) s [k]: T s [k] = T s [k-1] + m(T s0 - T s [k-1]) (5.1); Where: m is the preset switching cycle change ratio coefficient, 0 <m<1。 9. The control method according to claim 7, characterized in that: The T s [k] gradually decreases to T s0 , specifically: Calculate T according to formula (5.2) s [k]: T s [k] = T s [k-1] - ΔT s (5.2); Where: ΔTs is the preset switching cycle change step; And, judge T s [k] and T s0 The size relationship, if T s [k] < T s0 , then set T s [k] = T s0 .

10. The control method according to claim 1, characterized in that: According to i L with I ZVS The size relationship is used to determine whether the reset signal is valid, specifically: when i L ≤ -I ZVS When , the reset signal is valid; when i L > -I ZVS When , the reset signal is invalid.

11. The control method according to claim 1, wherein: The method according to T1[k], T2[k], T s [k] and reset signal, modulate the PWM signal, and use the PWM signal to control the opening and closing of the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube, specifically: In the kth switching cycle, the first switch tube and the fourth switch tube are turned on together during the first T1[k] duration; and then the first switch tube and the third switch tube are turned on together during the subsequent T2[k] duration. During the subsequent time period, until the reset signal becomes valid, the second switch tube and the third switch tube are turned on together; If the mode adopted in the current switching cycle is the DCM mode, after the reset signal is valid, the second switch tube and the fourth switch tube are turned on together.

12. The control method according to claim 1, wherein: Also includes: Calculate I based on I1 and I2 out_est and / or I in_est ; Among them, I out_est is the estimated output current, I in_est is the estimated value of input current, When the fourth switch tube is turned off, I1 is recorded, where I1 is the inductor current at the moment when the fourth switch tube is turned off; I2 is recorded when the first switch tube is turned off, where I2 is the inductor current at the moment when the first switch tube is turned off.

13. The control method according to claim 12, characterized in that: Calculate I according to formula (6) in_est : （6）； Among them, T s , T1, and T2 are respectively the total duration of a switching cycle, the duration during which the first switch tube and the fourth switch tube are turned on together, and the duration during which the first switch tube and the third switch tube are turned on together.

14. The control method according to claim 12, wherein: Get the time T from the start of the current switching cycle to when the reset signal becomes valid c [k]; Calculate T3[k] according to formula (7): T3[k] = T c [k] - (T1[k] + T2[k]) (7); Calculate I according to formula (8) out_est : （8）； Among them, T s , T1, and T2 are respectively the total duration of a switching cycle, the duration during which the first switch tube and the fourth switch tube are turned on together, and the duration during which the first switch tube and the third switch tube are turned on together.

15. The control method according to claim 12, wherein: Calculate I according to formula (9) out_est : （9）； Among them, T s , T1, and T2 are respectively the total duration of a switching cycle, the duration during which the first switch tube and the fourth switch tube are turned on together, and the duration during which the first switch tube and the third switch tube are turned on together.

16. The control method according to claim 1, characterized in that: Also includes: Calculate I according to formula (10) out_est : （10）； Among them, I out_est is the estimated value of output current; And / or, calculate I according to formula (11) in_est : （11）； Among them, I in_est is the estimated value of input current, T s T1, T2 are respectively the total duration of a switching cycle, the duration during which the first switch tube and the fourth switch tube are turned on together, and the duration during which the first switch tube and the third switch tube are turned on together, and L is the inductance value of the inductor.

17. The control method according to any one of claims 12 to 16, characterized in that: Also includes: Use the actual output current value to compare I out_est Perform linear fitting calibration and / or use actual input current values ​​to compare I in_est Perform linear fit calibration.

18. A control chip module for a DC-DC converter, characterized in that: include: Control algorithm components, comparators and PWM modulation components; The control algorithm component is used to receive the sampled V in 、V o signal and the preset reference output voltage V ref Or reference output current I ref ; The control algorithm component is based on T s [k-1] Calculate T of the current switching cycle 2crm [k]; where T 2crm [k] is the duration of time during which the first and third switch tubes are turned on together in the kth switching cycle in the CRM mode. k is a positive integer. The CRM mode is a critical mode. T s [k-1] is the total duration of the (k-1)th switching cycle; The control algorithm component calculates T of the current switching cycle u [k]; where T u [k] is the reference value of T2[k] corresponding to the DCM mode of the k-th switching cycle, and T2[k] is the duration during which the first switch tube and the third switch tube are turned on together in the k-th switching cycle. The DCM mode is a discontinuous mode; The control algorithm component is based on T 2crm [k] and T u The size relationship of [k] determines the mode adopted in the current switching cycle and T2[k]; The control algorithm component is based on V o With V in , calculate T1[k]; where T1[k] is the duration of the first switch tube and the fourth switch tube being turned on together in the kth switching cycle, V o is the output voltage sampling value, V in is the input voltage sampling value; The control algorithm component calculates T according to the mode adopted in the current switching cycle. s [k]; where T s [k] is the total duration of the kth switching cycle; The control algorithm component converts T1[k], T2[k], T s [k] Output to PWM modulation component; The comparator is based on i L with I ZVS The size relationship between the output reset signal to the PWM modulation component; where i L is the inductor current signal, I ZVS To achieve the minimum current in zero voltage switching mode, ZVS is the zero voltage switching mode; The PWM modulation component is based on T1[k], T2[k], T s [k] and reset signal, modulate the PWM signal, and use the PWM signal to control the opening and closing of the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube.

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