Staging memory access requests

Abstract

Temporarily storing a memory access request includes: receiving a memory access request for dynamic random access memory; storing the memory access request in a temporary buffer; and moving the memory access request from the temporary buffer to the command queue.

Description

Background Technology

[0001] The command queue stores memory access requests before execution. Increased arbitration and storage pressure on the command queue leads to performance degradation. Attached Figure Description

[0002] Figure 1 This is a block diagram of an exemplary processor for temporarily storing memory access requests according to some implementation schemes.

[0003] Figure 2 This is a flowchart of an exemplary method for temporarily storing memory access requests according to some implementation schemes.

[0004] Figure 3 This is a flowchart of an exemplary method for temporarily storing memory access requests according to some implementation schemes.

[0005] Figure 4 This is a flowchart of an exemplary method for temporarily storing memory access requests according to some implementation schemes.

[0006] Figure 5 This is a flowchart of an exemplary method for temporarily storing memory access requests according to some implementation schemes.

[0007] Figure 6 This is a flowchart of an exemplary method for temporarily storing buffer arbitration according to some implementation schemes.

[0008] Figure 7 This is a flowchart of an exemplary method for temporarily storing buffer arbitration according to some implementation schemes.

[0009] Figure 8 This is a flowchart of an exemplary method for temporarily storing buffer arbitration according to some implementation schemes.

[0010] Figure 9 This is a flowchart of an exemplary method for temporarily storing buffer arbitration according to some implementation schemes.

[0011] Figure 10 This is a flowchart of an exemplary method for temporarily storing buffer arbitration according to some implementation schemes.

[0012] Figure 11 This is a flowchart of an exemplary method for temporarily storing buffer arbitration according to some implementation schemes.

[0013] Figure 12 This is a flowchart of an exemplary method for temporarily storing buffer arbitration according to some implementation schemes.

[0014] Figure 13This is a flowchart of an exemplary method for temporarily storing buffer arbitration according to some implementation schemes. Detailed Implementation

[0015] In some implementations, the method of pausing a memory access request includes receiving a memory access request for dynamic random access memory; storing the memory access request in a temporary buffer; and moving the memory access request from the temporary buffer to a command queue.

[0016] In some embodiments, the method includes selecting a memory access request from a command queue and executing the memory access request. In some embodiments, the method includes receiving another memory access request; determining that a scratch buffer is full; and storing the other memory access request in the command queue instead of storing it in the scratch buffer. In some embodiments, the method includes selecting a memory access request from a plurality of memory access requests in the scratch buffer for moving to the command queue based on one or more arbitration rules. In some embodiments, selecting a memory access request based on one or more arbitration rules includes selecting the memory access request based on one or more of the following: open dynamic random access memory pages, library group rotation, the request type of the memory access request, or subchannel balancing.

[0017] In some implementations, a memory management unit for pausing memory access requests performs the following steps: receiving a memory access request for dynamic random access memory; storing the memory access request in a temporary buffer; and moving the memory access request from the temporary buffer to a command queue.

[0018] In some implementations, these steps include selecting a memory access request from a command queue and executing the memory access request. In some implementations, these steps include receiving another memory access request; determining that a scratch buffer is full; and storing the other memory access request in the command queue without storing the other memory access request in the scratch buffer. In some implementations, these steps include selecting a memory access request from a plurality of memory access requests in the scratch buffer for moving to the command queue based on one or more arbitration rules. In some implementations, selecting a memory access request based on one or more arbitration rules includes selecting the memory access request based on one or more of the following: open dynamic random access memory pages, library group rotation, the request type of the memory access request, or subchannel balancing.

[0019] In some implementations, a processor for temporarily storing memory access requests includes a memory management unit to perform the following steps: receiving a memory access request for dynamic random access memory; storing the memory access request in a temporary buffer; and moving the memory access request from the temporary buffer to a command queue.

[0020] In some implementations, these steps include selecting a memory access request from a command queue and executing the memory access request. In some implementations, these steps include receiving another memory access request; determining that a scratch buffer is full; and storing the other memory access request in the command queue without storing the other memory access request in the scratch buffer. In some implementations, these steps include selecting a memory access request from a plurality of memory access requests in the scratch buffer for moving to the command queue based on one or more arbitration rules. In some implementations, selecting a memory access request based on one or more arbitration rules includes selecting the memory access request based on one or more of the following: open dynamic random access memory pages, library group rotation, the request type of the memory access request, or subchannel balancing.

[0021] In some implementations, a system for temporarily storing memory access requests includes a device having a processor that includes a memory management unit to perform the following steps: receiving a memory access request for dynamic random access memory; storing the memory access request in a temporary buffer; and moving the memory access request from the temporary buffer to a command queue.

[0022] In some implementations, these steps include selecting a memory access request from a command queue and executing the memory access request. In some implementations, these steps include receiving another memory access request; determining that a scratch buffer is full; and storing the other memory access request in the command queue without storing the other memory access request in the scratch buffer. In some implementations, these steps include selecting a memory access request from a plurality of memory access requests in the scratch buffer for moving to the command queue based on one or more arbitration rules. In some implementations, selecting a memory access request based on one or more arbitration rules includes selecting the memory access request based on one or more of the following: open dynamic random access memory pages, library group rotation, the request type of the memory access request, or subchannel balancing.

[0023] Figure 1This is a block diagram of a non-limiting exemplary processor 100 according to some embodiments. The exemplary processor 100 may be implemented in various computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, etc. The processor 100 includes a memory management unit 102. The memory management unit 102 receives memory access requests (e.g., requests to read and / or write data to a specific region of memory). The memory management unit 102 also performs a translation from a virtual memory address in the memory access request to a physical memory address in order to execute the memory access request.

[0024] The memory management unit 102 includes a command queue 104. The command queue 104 stores memory access requests when a memory access request is received (e.g., from the central processing unit or other component of the processor 100) before executing an access to the dynamic random access memory 106. Although the dynamic random access memory 106 is shown as separate from the processor 100, it should be understood that the dynamic random access memory 106 may include on-chip dynamic random access memory 106 (e.g., as part of the processor 100). Where the dynamic random access memory 106 includes multiple libraries, the memory management unit 102 may include multiple command queues 104, each command queue corresponding to a corresponding library.

[0025] Memory management unit 102 uses one or more schemes, such as First-Come, First-Served (FCFS), First-Ready, First-Come, First-Served (FR-FCFS), First-In, First-Out (FIFO), etc., to select memory access requests from command queue 104 for execution. Memory management unit 102 includes a command queue arbitrator 108 that selects memory access requests from command queue 104 for execution using one or more rules. For example, one or more rules are based on timing or clock information (e.g., the age of the memory access request). As another example, one or more rules are based on page table 110. For example, memory access requests that result in a page table 110 hit are preferentially selected from command queue 104 for execution.

[0026] In existing methods, memory access requests received by the memory management unit 102 are directly placed in the command queue 104 for subsequent execution. To improve performance and alleviate pressure on the command queue 104, the memory management unit 102 includes a temporary buffer 112. Memory access requests received by the memory management unit 102 are placed in the temporary buffer 112. Then, a temporary buffer arbitrator 114 selects a memory access request from the temporary buffer 112 based on one or more arbitration rules to move it to the command queue 104.

[0027] In some implementations, the arbitration rule is based on the dynamic random access memory (DRAM) page 106 targeted by the memory access request. For example, when the overhead required to close and open a page is reduced, a memory access request targeting an open DRAM page 106 is prioritized to move to command queue 104. As another example, a memory access request targeting a DRAM page 106 that is also targeted by another memory access request in command queue 104 and will therefore be opened when the selected memory access request is executed.

[0028] In some implementations, arbitration rules are based on library group rotation or rank rotation. For example, in the case where the dynamic random access memory 106 includes multiple libraries, memory access requests are selected from the temporary buffer 112 to be added to the command queue 104 such that consecutively added requests do not target the same library. For example, a memory access request targeting a first group is moved to the command queue 104, then a memory access request targeting a second group is moved to the command queue 104. Another memory access request targeting the first library is then added to the command queue 104, and so on. In some implementations, memory access requests are selected to target different ranks within the same or different libraries, or alternatively, to target different subchannels of the dynamic random access memory 106 (e.g., subchannel balancing).

[0029] In some implementations, the arbitration rules are based on the request type of the memory access request (e.g., read or write). Because there is computational overhead in switching between reading and writing to the dynamic random access memory 106, read requests and / or write requests are combined as part of a request “burst” moving to the command queue 104. Therefore, a set of read requests and / or a set of write requests can be executed sequentially.

[0030] In some implementations, the memory management unit 102 determines that the temporary buffer 112 is full. Therefore, the memory management unit 102 stores the received memory access request directly in the command queue 104 instead of storing the received memory access request in the temporary buffer 112.

[0031] To further explain, Figure 2A flowchart illustrating an exemplary method for temporarily storing a memory access request according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) receiving 202 a memory access request 204 for dynamic random access memory 106. The memory access request 204 includes a request to read data from or write data to the dynamic random access memory 106. The memory access request 204 is received via a data structure or other interconnect that couples the memory management unit 102 to a central processing unit or other component.

[0032] Figure 2 The method also includes (for example, by memory management unit 102) storing memory access request 204 206 in temporary buffer 112. Figure 2 The method also includes moving memory access request 204 from scratch buffer 112 to command queue 104. Moving memory access request 204 208 includes removing memory access request 204 from scratch buffer 112 and storing memory access request 204 in command queue 104. In some embodiments, memory access request 204 is moved in response to the number of memory access requests 204 in scratch buffer 112 reaching a threshold. In some embodiments, memory access request 204 is moved in response to the number of memory access requests 204 in command queue 104 falling below a threshold. In some embodiments, memory access request 204 is moved in response to the age of memory access request 204 (e.g., the time when memory access request 204 was received) reaching a threshold. In some embodiments, memory access request 204 is moved in response to satisfying one or more arbitration rules.

[0033] To further explain, Figure 3 A flowchart illustrating an exemplary method for temporarily storing a memory access request according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) receiving 202 a memory access request 204 for dynamic random access memory 106; storing 206 the memory access request 204 in a temporary buffer 112; and moving 208 the memory access request 204 from the temporary buffer 112 to a command queue 104.

[0034] Figure 3 Methods and Figure 2 The difference is that, Figure 3The method also includes (e.g., memory access request 204 selected from command queue 104 by memory management unit 102 of processor 100). Memory access request 204 is selected from command queue 104 using one or more schemes, such as First-Come, First-Served (FCFS), First-Ready, First-Come, First-Served (FR-FCFS), First-In, First-Out (FIFO), etc. In some embodiments, memory management unit 102 includes command queue arbitrator 108 that selects memory access requests from command queue 104 for execution using one or more rules. For example, one or more rules are based on timing or clock information (e.g., the age of the memory access request). As another example, one or more rules are based on page table 110. For example, memory access requests that result in a page table 110 hit are preferentially selected from command queue 104 for execution.

[0035] Figure 3 Methods and Figure 2 The difference is that, Figure 3 The method also includes (for example, by memory management unit 102) executing memory access request 204 304. Executing memory access request 204 304 includes reading data from the dynamic random access memory 106 address specified in memory access request 204 and / or writing data to the dynamic random access memory 106 address specified in memory access request 204.

[0036] To further explain, Figure 4 A flowchart illustrating an exemplary method for temporarily storing a memory access request according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) receiving 202 a memory access request 204 for dynamic random access memory 106; storing 206 the memory access request 204 in a temporary buffer 112; and moving 208 the memory access request 204 from the temporary buffer 112 to a command queue 104.

[0037] Figure 4 Methods and Figure 2 The difference is that, Figure 4 The method also includes receiving another memory access request 402 404. Figure 4 Methods and Figure 2 The difference also lies in, Figure 4 The method also includes determining that the 406 temporary buffer 112 is full. The temporary buffer 112 includes a predefined amount of memory for storing a predefined maximum number of memory access requests. Therefore, determining that the 406 temporary buffer 112 is full includes determining that the temporary buffer 112 is storing a predefined maximum number of memory access requests.

[0038] Figure 4 Methods and Figure 2 The difference also lies in, Figure 4 The method also includes storing another memory access request 404 408 in command queue 104 instead of storing the other memory access request 404 in temporary buffer 112. Therefore, temporary buffer 112 is bypassed when it is full.

[0039] To further explain, Figure 5 A flowchart illustrating an exemplary method for temporarily storing a memory access request according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) receiving 202 a memory access request 204 for dynamic random access memory 106; storing 206 the memory access request 204 in a temporary buffer 112; and moving 208 the memory access request 204 from the temporary buffer 112 to a command queue 104.

[0040] Figure 5 Methods and Figure 2 The difference is that, Figure 5 The method also includes (e.g., by memory management unit 102, by the temporary buffer arbitrator 114 of memory management unit 102) selecting 502 memory access requests 204 from multiple memory access requests in temporary buffer 112 based on one or more arbitration rules so as to move them to command queue 104.

[0041] In some implementations, the arbitration rule is based on the dynamic random access memory (DRAM) page 106 targeted by the memory access request. For example, when the overhead required to close and open a page is reduced, a memory access request targeting an open DRAM page 106 is prioritized to move to command queue 104. As another example, a memory access request targeting a DRAM page 106 that is also targeted by another memory access request in command queue 104 and will therefore be opened when the selected memory access request is executed.

[0042] In some implementations, arbitration rules are based on library group rotation or rank rotation. For example, in the case where the dynamic random access memory 106 includes multiple libraries, memory access requests are selected from the temporary buffer 112 to be added to the command queue 104 such that consecutively added requests do not target the same library. For example, a memory access request targeting a first group is moved to the command queue 104, then a memory access request targeting a second group is moved to the command queue 104. Another memory access request targeting the first library is then added to the command queue 104, and so on. In some implementations, memory access requests are selected to target different ranks within the same or different libraries. Memory access requests are also selected to optionally target different subchannels of the dynamic random access memory 106 (e.g., subchannel balancing).

[0043] In some implementations, the arbitration rules are based on the request type of the memory access request (e.g., read or write). Because there is computational overhead in switching between reading and writing to the dynamic random access memory 106, read requests and / or write requests are combined as part of a request “burst” moving to the command queue 104. Therefore, a set of read requests and / or a set of write requests are executed consecutively.

[0044] To further explain, Figure 6 A flowchart illustrating an exemplary method for temporary storage of buffer arbitration according to an embodiment of the present disclosure is provided, the method including (e.g., by a memory management unit 102 of processor 100) storing 602 plurality of memory access requests in a temporary storage buffer 112. The memory access requests include requests to read data from or write data to dynamic random access memory 106. The memory access requests are transmitted via data structures or other interconnects that couple the memory management unit 102 to a central processing unit or other component.

[0045] Figure 6The method also includes selecting memory access request 608 from a plurality of memory access requests in the scratch buffer 112 based on one or more arbitration rules. For example, the scratch buffer arbitrator 114 selects memory access request 608 based on one or more arbitration rules. The arbitration rules are applied to various attributes and / or other attributes of memory access requests stored in the scratch buffer 112, memory access requests stored in the command queue 104, and page table 110. For example, the arbitration rules are based on the request type of the memory access request in the scratch buffer 112 and / or command queue 104, the currently open dynamic random access memory 106 page, the library group to which the memory access request in the scratch buffer 112 and / or command queue 104 is targeted, the refresh status of the library or page to which the memory access request in the scratch buffer 112 and / or command queue 104 is targeted, and / or the sub-channel to which the memory access request in the scratch buffer 112 and / or command queue 104 is targeted.

[0046] Figure 6 The method also includes moving memory access request 608 from scratch buffer 112 to command queue 104. Moving memory access request 608 includes deleting memory access request 608 from scratch buffer 112 and / or freeing a portion of scratch buffer 112 containing memory access request 608 for subsequent rewriting. Moving memory access request 608 also includes adding memory access request 608 to command queue 104. Therefore, memory access request 608 is later executed by memory management unit 102 from command queue 104.

[0047] To further explain, Figure 7 A flowchart illustrating an exemplary method for queuing buffer arbitration according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) storing 602 plurality of memory access requests in a queuing buffer 112; selecting a memory access request 608 from the plurality of memory access requests in the queuing buffer 112 based on one or more arbitration rules; and moving the memory access request 608 from the queuing buffer 112 610 to a command queue 104.

[0048] Figure 7 Methods and Figure 6The difference lies in that selecting memory access requests 608 from a plurality of memory access requests in the temporary buffer 112 based on one or more arbitration rules includes selecting 702 bursts of memory access requests of the same request type, wherein the burst of memory access requests includes memory access requests 608. A burst of memory access requests includes multiple memory access requests of the same type (e.g., read or write). Memory access requests in a burst of memory access requests are selected so that they are moved to the command queue 104 consecutively and / or at least partially simultaneously, such that the memory access requests in the burst of memory access requests are subsequently executed consecutively and / or at least partially simultaneously. For example, a burst of read requests is executed without executing intermediate write requests. As another example, a burst of write requests is executed without executing intermediate read requests. Since switching between executing read and write requests to the dynamic random access memory 106 incurs computational overhead, this computational overhead is avoided by executing multiple memory access requests of the same request type. Therefore, memory access request 608 is selected based on other memory access requests of the same request type that have already been added to command queue 104, and / or based on other memory access requests of the same request type that are subsequently added to command queue 104 as part of a memory access request burst stored in temporary buffer 112.

[0049] To further explain, Figure 8 A flowchart illustrating an exemplary method for queuing buffer arbitration according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) storing 602 plurality of memory access requests in a queuing buffer 112; selecting a memory access request 608 from the plurality of memory access requests in the queuing buffer 112 based on one or more arbitration rules; and moving the memory access request 608 from the queuing buffer 112 610 to a command queue 104.

[0050] Figure 8 Methods and Figure 6The difference lies in that selecting a memory access request 608 from a plurality of memory access requests in the temporary buffer 112 based on one or more arbitration rules includes selecting the memory access request 608 based on one or more of the following: the library targeted by another memory access request, the class targeted by another memory access request, or the memory subchannel targeted by another memory access request. For example, in some embodiments, memory access requests are added to command queue 104 such that the executed memory access requests are optionally targeted at a different DRAM 106 class or library (e.g., class balancing, library balancing). In other embodiments, memory access requests are added to command queue 104 such that the executed memory access requests are targeted at DRAM 106 subchannels in a balanced manner. Therefore, memory access requests 608 are selected based on the class, library, or subchannel targeted by memory access requests already added to command queue 104 (e.g., queued memory access commands targeting different classes, libraries, or subchannels). The memory access request 608 is also selected based on the level, library, or subchannel targeted by the memory access request that is later added to the command queue 104 in the temporary buffer 112 (e.g., a temporary memory access command targeting a different level, library, or subchannel).

[0051] To further explain, Figure 9 A flowchart illustrating an exemplary method for queuing buffer arbitration according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) storing 602 plurality of memory access requests in a queuing buffer 112; selecting a memory access request 608 from the plurality of memory access requests in the queuing buffer 112 based on one or more arbitration rules; and moving the memory access request 608 from the queuing buffer 112 610 to a command queue 104.

[0052] Figure 9 Methods and Figure 6The difference lies in that selecting memory access request 608 from a plurality of memory access requests in the temporary buffer 112 based on one or more arbitration rules includes selecting memory access request 608 based on the page of dynamic random access memory 106 targeted by another memory access request 902. If the executed memory access request targets a page that is not currently open, there is overhead in closing the currently open page and opening the target page. Executing a memory access request that targets the same (e.g., open) page reduces this overhead. Therefore, in some embodiments, memory access request 608 is selected based on the page targeted by an already executed memory access request (e.g., an already opened page). In some embodiments, memory access request 608 is selected based on the page targeted by a memory access request to be executed before the selected memory access request 608, stored in the command queue 104, such that when the selected memory access request 608 is executed, the target page will be opened. In some implementations, memory access request 608 is selected based on the page targeted by another memory access request that will subsequently be selected for movement to command queue 104, stored in temporary buffer 112, such that the target page is opened when the other memory access request is executed.

[0053] To further explain, Figure 10 A flowchart illustrating an exemplary method for queuing buffer arbitration according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) storing 602 plurality of memory access requests in a queuing buffer 112; selecting a memory access request 608 from the plurality of memory access requests in the queuing buffer 112 based on one or more arbitration rules; and moving the memory access request 608 from the queuing buffer 112 610 to a command queue 104.

[0054] Figure 10 Methods and Figure 6 The difference lies in the fact that selecting memory access request 608 from a plurality of memory access requests in the temporary buffer 112 based on one or more arbitration rules includes selecting memory access request 1002 based on a priority value. In some embodiments, the priority value is an explicit priority value (e.g., a priority tier) assigned to memory access request 608. In other embodiments, the priority value is calculated based on attributes of the memory access request, such as the age of the memory access request (e.g., the time when a given memory access request was generated or received by memory management unit 102).

[0055] To further explain, Figure 11A flowchart illustrating an exemplary method for queuing buffer arbitration according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) storing 602 plurality of memory access requests in a queuing buffer 112; selecting a memory access request 608 from the plurality of memory access requests in the queuing buffer 112 based on one or more arbitration rules; and moving the memory access request 608 from the queuing buffer 112 610 to a command queue 104.

[0056] Figure 11 Methods and Figure 6 The difference lies in that, based on one or more arbitration rules, the selection of memory access request 608 from the plurality of memory access requests in the scratch buffer 112 includes identifying 1102 another memory access request associated with the first page miss in the scratch buffer 112. In other words, the execution of the other memory access request will result in a page miss and the corresponding computational overhead. For example, the page table 110 is accessed to determine that the execution of the other memory access request will result in a page miss.

[0057] Figure 11 Methods and Figure 6 The difference also lies in the fact that selecting memory access requests 608 from the multiple memory access requests in the scratch buffer 112 based on one or more arbitration rules also includes identifying queued memory access requests in the command queue 104 that are associated with a second page miss that is different from the first page miss. For example, a queued memory access request is identified as having the same request type as another memory access request in the scratch buffer and targeting the same dynamic random access memory group, but would result in a different row page miss.

[0058] Figure 11 Methods and Figure 6 The difference lies in that selecting a memory access request 608 from a plurality of memory access requests in the scratch buffer 112 based on one or more arbitration rules also includes selecting the memory access request 608 in response to identifying another memory access request and queuing memory access requests. In other words, the memory access request 608 is selected over other memory access requests in the scratch buffer 112 associated with a first page miss.

[0059] To further explain, Figure 12A flowchart illustrating an exemplary method for queuing buffer arbitration according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) storing 602 plurality of memory access requests in a queuing buffer 112; selecting a memory access request 608 from the plurality of memory access requests in the queuing buffer 112 based on one or more arbitration rules; and moving the memory access request 608 from the queuing buffer 112 610 to a command queue 104.

[0060] Figure 12 Methods and Figure 6 The difference lies in that, based on one or more arbitration rules, memory access request 608 from the plurality of memory access requests selected from scratch buffer 112 includes another memory access request identified 1202 in scratch buffer 112 that is associated with the first page conflict. In other words, the execution of the other memory access request will result in a page conflict and corresponding computational overhead. For example, page table 110 is accessed to determine that the execution of the other memory access request will result in a page conflict.

[0061] Figure 12 Methods and Figure 6 The difference also lies in the fact that selecting memory access requests 608 from the multiple memory access requests in the scratch buffer 112 based on one or more arbitration rules also includes identifying queued memory access requests in the command queue 104 that are associated with a second page conflict different from the first page conflict. For example, a queued memory access request is identified as having the same request type as another memory access request in the scratch buffer 112 and targeting the same dynamic random access memory group, but will result in a different row page conflict.

[0062] Figure 12 Methods and Figure 6 The difference lies in that the selection of memory access request 608 from the plurality of memory access requests in the scratch buffer 112 based on one or more arbitration rules also includes selecting 1206 memory access requests 608 in response to identifying another memory access request and queuing memory access requests. In other words, memory access request 608 is selected with priority over other memory access requests in the scratch buffer 112 associated with the first page conflict.

[0063] To further explain, Figure 13A flowchart illustrating an exemplary method for pausing memory access requests according to an embodiment of the present disclosure is provided. The method includes (e.g., by a memory management unit 102 of processor 100) storing 602 plurality of memory access requests in a pausing buffer 112; selecting a memory access request 608 from the plurality of memory access requests based on one or more arbitration rules; and moving the memory access request 608 from the pausing buffer 112 610 to a command queue 104.

[0064] Figure 13 Methods and Figure 6 The difference lies in that, based on one or more arbitration rules, memory access request 608 from among 606 multiple memory access requests selected from the temporary buffer 112 includes page hit requests identified in the command queue 104. Page hit requests include memory access requests targeting currently open pages of dynamic random access memory 106. Figure 13 Methods and Figure 6 The difference lies in the fact that, based on one or more arbitration rules, memory access request 608 is selected from 606 multiple memory access requests in the staging buffer 112, including selecting memory access request 608 based on whether it is another page hit request. In other words, memory access request 608 is selected for moving to command queue 104 with priority over other memory access requests that would result in a page miss. Therefore, staging buffer 112 will hold page conflict requests. In some implementations, memory access request 608 is selected for moving to command queue 104 such that command queue 104 preferentially holds no more than one memory access request per library.

[0065] In view of the foregoing description, the reader will recognize that the benefits of pausing memory access requests according to the embodiments of this disclosure include:

[0066] ● By using additional temporary buffers to reduce command queue pressure, the performance of the computing system is improved.

[0067] ● By optimally selecting memory access requests to add to the command queue, computational overhead is reduced, thereby improving the performance of the computing system.

[0068] Exemplary embodiments of this disclosure are described primarily in the context of a full-featured computer system used for temporarily storing memory access requests. However, those skilled in the art will recognize that this disclosure can also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium can be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include disks in hard disk drives or floppy disks, optical discs for optical drives, magnetic tapes, and other media that will conceive of those skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means will be able to perform the steps of the methods of this disclosure as embodied in a computer program product. Those skilled in the art will also recognize that while some of the exemplary embodiments described in this specification are directed to software installed on and executed on computer hardware, alternative embodiments implemented as firmware or hardware are also fully within the scope of this disclosure.

[0069] This disclosure can be a system, method, and / or computer program product. A computer program product may include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform aspects of this disclosure.

[0070] A computer-readable storage medium can be a tangible means capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanical encoding devices (e.g., punched cards or raised structures in slots on which instructions are recorded), and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transient signal, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0071] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0072] Computer-readable program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. As a standalone software package, the computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be (e.g., via the Internet using an Internet service provider) to an external computer. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by personalizing the electronic circuitry with status information from the computer-readable program instructions in order to perform various aspects of this disclosure.

[0073] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0074] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, establish means for implementing the functions / actions specified in one or more boxes of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other means to function in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions that implement aspects of the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0075] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0076] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this respect, each block in a flowchart or block diagram may represent a module, segment, or portion comprising one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions mentioned in the blocks may occur in a different order than those shown in the drawings. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a system based on dedicated hardware that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0077] As will be understood from the foregoing description, modifications and changes can be made to various embodiments of this disclosure. The descriptions in this specification are for illustrative purposes only and should not be construed as limiting. The scope of this disclosure is limited only by the language of the appended claims.

Claims

1. A processor comprising: one or more processor cores, and a memory management unit configured to: store a plurality of memory access requests in a staging buffer; select between a first memory access request and a second memory access request from the plurality of memory access requests in the staging buffer to move to a command queue based on one or more arbitration rules, wherein the one or more arbitration rules apply to one or more attributes of a plurality of memory access requests already in the command queue; and move the selected memory access request from the staging buffer to the command queue.

2. The processor of claim 1, wherein the memory management unit is further configured to: select the memory access request from the command queue; and execute the memory access request.

3. The processor of claim 1, wherein the memory management unit is further configured to: receive a third memory access request; determine that the staging buffer is full; and store the third memory access request in the command queue without storing the third memory access request in the staging buffer.

4. The processor of claim 1, wherein the memory management unit is further configured to select between a first memory access request and a second memory access request based on the one or more arbitration rules by selecting the memory access request based on an open dynamic random access memory page.

5. The processor of claim 1, wherein the memory management unit is further configured to select between a first memory access request and a second memory access request based on the one or more arbitration rules by selecting the memory access request from the staging buffer based on determining that one or more of a bank, rank, and memory subchannel of the selected memory access request is different from one or more of a bank, rank, and memory subchannel of another memory access request already existing in the command queue.

6. The processor of claim 1, wherein the memory management unit is further configured to select between a first memory access request and a second memory access request based on the one or more arbitration rules by selecting the memory access request based on a request type of the memory access request.

7. The processor of claim 1, wherein the memory management unit is further configured to select the memory access request based on one or more arbitration rules by selecting the memory access request based on subchannel balancing.

8. A system comprising: a processor and a dynamic random access memory, wherein the processor is coupled to the dynamic random access memory through a memory management unit, and the memory management unit is configured to: store a plurality of the memory access requests in a staging buffer; select between a first memory access request and a second memory access request from the plurality of memory access requests in the staging buffer to move to a command queue based on one or more arbitration rules, wherein the one or more arbitration rules apply to one or more attributes of a plurality of memory access requests already in the command queue; and move the selected memory access request from the staging buffer to the command queue. selecting, based on one or more arbitration rules, between a first memory access request and a second memory access request of the plurality of memory access requests in the staging buffer to move to a command queue, wherein the one or more arbitration rules apply to one or more attributes of a plurality of memory access requests already in the command queue; and moving the selected memory access request from the staging buffer to the command queue.

9. The system of claim 8, wherein the memory management unit is further configured to: select the memory access request from the command queue; and execute the memory access request.

10. The system of claim 8, wherein the memory management unit is further configured to: receive a third memory access request; determine that the staging buffer is full; and store the third memory access request in the command queue without storing the third memory access request in the staging buffer.

11. The system of claim 8, wherein the memory management unit is further configured to select between a first memory access request and a second memory access request based on the one or more arbitration rules by selecting the memory access request based on one or more of an open dynamic random access memory page, a bank group rotation, a request type of the memory access request, or a sub-channel balancing.

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