Chip operation data collection method, device, electronic device and storage medium

Abstract

The present disclosure proposes a method, device, electronic device and storage medium for collecting chip operation data, which relates to the field of image detection technology. The method includes: traversing the test cases in the simulation log to obtain basic simulation data from the traversed test cases; determining the simulation type of the test case, and based on the basic simulation data of the test case, filling the initial data collection table corresponding to the simulation type to generate a first data collection table; after the traversal is completed, for each simulation type, the first data collection table is completed based on the simulation type to generate a second data collection table corresponding to the simulation type. According to different simulation types, the log file is automatically analyzed to increase the efficiency and accuracy of verification and improve the quality of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of image detection technology, and in particular to a method, device, electronic device, and storage medium for collecting chip operation data. Background Art

[0002] With the improvement of chip performance, the scale of system-on-chip (SOC) design is getting larger and larger. The performance of SOC chips has been greatly improved, and the demand for SOC performance verification is also increasing.

[0003] In current technology, the test cases for SOC performance verification are characterized by a large number and multiple modes. Each test case must be simulated multiple times according to different configuration modes. The number of simulated log files (logs) is huge, and the analysis cost is very high. Therefore, automated log analysis is crucial.

[0004] Public content

[0005] The present disclosure aims to solve one of the technical problems in the related art at least to a certain extent.

[0006] To this end, one purpose of the present disclosure is to provide a method for collecting chip operation data.

[0007] The second objective of the present disclosure is to provide a device for collecting chip operation data.

[0008] A third objective of the present disclosure is to provide an electronic device.

[0009] A fourth object of the present disclosure is to provide a non-transitory computer-readable storage medium.

[0010] To achieve the above-mentioned purpose, the first aspect of the present disclosure proposes a method for collecting chip operation data, including: traversing the test cases in the simulation log to obtain basic simulation data from the traversed test cases; determining the simulation type of the test case, and based on the basic simulation data of the test case, filling the initial data collection table corresponding to the simulation type to generate a first data collection table; after the traversal is completed, for each simulation type, the first data collection table is completed based on the simulation type to generate a second data collection table corresponding to the simulation type.

[0011] According to one embodiment of the present disclosure, the chip operation data collection method also includes: classifying test cases based on simulation type, and obtaining a test case group belonging to the same simulation type; obtaining delay data for each test case in the test case group; for each simulation type, based on the delay data belonging to the simulation type, completing the first data collection table of the simulation type, and generating a second data collection table corresponding to the simulation type.

[0012] According to one embodiment of the present disclosure, the method for collecting chip operation data also includes: obtaining at least one parameter among the maximum read delay, minimum read delay, maximum write delay, minimum write delay, average read delay and average write delay from the delay data belonging to the simulation type; writing the obtained at least one parameter into a first data collection table corresponding to the simulation type, and generating a second data collection table corresponding to the simulation type.

[0013] According to one embodiment of the present disclosure, the chip operation data collection method also includes: in response to the simulation type being a delay type, obtaining a first test case whose simulation type belongs to the delay type; obtaining the first delay data of the specified main thread corresponding to the first test case and all slave threads corresponding to the specified main thread; completing the first data collection table based on the first delay data, and generating a second data collection table corresponding to the delay type.

[0014] According to one embodiment of the present disclosure, the chip operation data collection method also includes: in response to the simulation type being a single main thread type, obtaining a second test case whose simulation type belongs to the single main thread type; obtaining access data of the single main thread corresponding to the second test case and each slave thread corresponding to the single main thread; generating analysis data corresponding to the single main thread type based on the access data; completing the first data collection table based on the analysis data, and generating a second data collection table corresponding to the single main thread type.

[0015] According to one embodiment of the present disclosure, the chip operation data collection method also includes: in response to the simulation type being a multi-main thread type, obtaining a third test case whose simulation type belongs to the multi-main thread type; obtaining the second delay data of all main threads corresponding to the third test case and the slave threads corresponding to the main threads; completing the first data collection table based on the second delay data, and generating a second data collection table corresponding to the multi-main thread type.

[0016] According to one embodiment of the present disclosure, the chip operation data collection method also includes: obtaining a simulation directory of the test case; determining the target log data of successful simulation in the simulation directory; determining the test case functional configuration data and bandwidth data based on the target log data; and determining the basic simulation data of the test case based on the functional configuration data and bandwidth data.

[0017] According to one embodiment of the present disclosure, the chip operation data collection method further includes: filling the function configuration data into a first data collection table; screening the test cases based on the bandwidth data, and filling the bandwidth data of the screened test cases into the first data collection table.

[0018] According to one embodiment of the present disclosure, the chip operation data collection method further includes: determining the read throughput, write throughput and total throughput of the target log data according to the bandwidth data; and filling the first data collection table based on the read throughput, write throughput and total throughput.

[0019] To achieve the above-mentioned purpose, the second aspect embodiment of the present disclosure proposes a chip operation data collection device, including: a traversal module, used to traverse the test cases in the simulation log to obtain basic simulation data from the traversed test cases; a first generation module, used to determine the simulation type of the test case, and based on the basic simulation data of the test case, fill in the initial data collection table corresponding to the simulation type to generate a first data collection table; a second generation module, used to, after the traversal is completed, complete the first data collection table for each simulation type based on the simulation type to generate a second data collection table corresponding to the simulation type.

[0020] To achieve the above-mentioned purpose, the third aspect embodiment of the present disclosure proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to implement the chip operation data collection method as described in the first aspect embodiment of the present disclosure.

[0021] To achieve the above-mentioned purpose, the fourth embodiment of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to implement the chip operation data collection method as described in the first embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of a chip operation data collection method according to an embodiment of the present disclosure;

[0023] Figure 2 is a diagrammatic illustration of a method for collecting chip operation data according to one embodiment of the present disclosure;

[0024] Figure 3 is a schematic diagram of another chip operation data collection method according to an embodiment of the present disclosure;

[0025] Figure 4 is a schematic diagram of another chip operation data collection method according to an embodiment of the present disclosure;

[0026] Figure 5 is a diagrammatic illustration of another chip operation data collection method according to an embodiment of the present disclosure;

[0027] Figure 6is a diagrammatic illustration of a method for collecting chip operation data according to one embodiment of the present disclosure;

[0028] Figure 7 is a diagrammatic illustration of another chip operation data collection method according to an embodiment of the present disclosure;

[0029] Figure 8 is a diagrammatic illustration of a method for collecting chip operation data according to one embodiment of the present disclosure;

[0030] Figure 9 is a diagrammatic illustration of another chip operation data collection method according to an embodiment of the present disclosure;

[0031] Figure 10 This is a schematic diagram of a device for collecting chip operation data according to one embodiment of the present disclosure;

[0032] Figure 11 is a schematic diagram of an electronic device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0034] During the chip development process, after the customer determines the functional requirements, the actual system personnel are divided into various subsystems according to the functions. The subsystems are further divided into functional modules and implemented by the design team. The verification personnel verify the design functions and analyze the design defects based on the verification results. The design defects are handed over to the designers for correction. After verification that there are no loopholes, it is handed over to the back-end personnel for synthesis, layout and wiring.

[0035] As can be seen from the above steps, verification is as important as, or even more important than, design, and is a crucial guarantee for producing high-quality chips. As the scale of system-on-chip (SOC) designs continues to grow, the performance of SOC chips has been greatly improved, and the number of verification log files has also increased significantly. Therefore, automated analysis of these log files is necessary to increase verification efficiency and accuracy, thereby improving chip quality.

[0036] Figure 1 A schematic diagram of an exemplary embodiment of a chip operation data collection method proposed in the present disclosure is shown as follows: Figure 1 As shown, the chip operation data collection method includes the following steps:

[0037] S101, traversing the test cases in the simulation log to obtain basic simulation data from the traversed test cases.

[0038] Chip design can be divided into front-end (logic design) and back-end (physical design). Verification is a special aspect of the chip development process, running parallel to the entire chip design process, independent yet independent of requirements definition, synthesis, and physical implementation. Verification's purpose lies in providing critical feedback during iterations of the design and implementation process, specifically addressing performance deficiencies, design code functional defects, and overall chip integration errors.

[0039] In the disclosed embodiments, simulation logs can be generated by simulating and verifying chip functions. The verification method in the prior art is primarily dynamic verification. Dynamic verification involves using a simulator to stimulate and relax digital circuits and verify the results. It should be noted that the simulator may include a stimulus generator, a clock, a detector, and a comparator. The simulator may be pre-designed or an existing simulator, and no limitation is imposed herein.

[0040] In the disclosed embodiments, input parameters are test function points that need to be processed, thus forming a test case. For example, the path of a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) accessing a Double Data Rate (DDR) synchronous dynamic random access memory is a test function point, and thus constitutes a test case class.

[0041] The simulation log generated after verification can include multiple test cases. These test cases can be categorized into different types based on the simulation purpose. For example, they can be divided into latency, single-master, and multi-master types. The latency type tests the latency of all nodes in the chip. The single-master type tests the performance of each master to each slave in the chip, i.e., without interference from other devices in the chip bus system. The multi-master type tests various scenarios in which multiple master devices operate simultaneously.

[0042] In the embodiments of the present disclosure, the basic simulation data may include multiple types, for example, it may include bandwidth information, function configuration data and delay information in the simulation file, etc., which are not limited here and can be set according to actual needs.

[0043] S102: Determine a simulation type of the test case, and fill an initial data collection table corresponding to the simulation type based on basic simulation data of the test case to generate a first data collection table.

[0044] In the embodiment of the present disclosure, different simulation types correspond to a data collection table, which is used to classify test cases to facilitate subsequent data analysis. Therefore, after obtaining the test case, it is necessary to determine the simulation type of the test case to facilitate placing the basic simulation data of the test case into the corresponding data collection table.

[0045] The simulation type of the test case can be set in advance, and the simulation type of the test case can be determined directly, or it can be determined by the test case. For example, the simulation type of the test case can be determined by determining the effects that different test cases need to achieve.

[0046] It should be noted that a test case only simulates the simulation type corresponding to the test case. Therefore, after the simulation is completed, the simulation log corresponding to the test case only contains one simulation type.

[0047] Furthermore, after determining the simulation type, the basic simulation data of the test case obtained is input into the initial data collection table corresponding to the simulation type to achieve the purpose of generating the first data collection table and updating the first data collection table. According to the name of the test case, the basic simulation data of the test case is input into the table corresponding to each row to generate the following table: Figure 2 The table shown.

[0048] S103 , after the traversal is completed, for each first data collection table of the simulation type, the first data collection table is completed based on the simulation type to generate a second data collection table corresponding to the simulation type.

[0049] After obtaining the first data collection table, it is necessary to extract and analyze the data of the test cases based on the simulation type, and complete the first data collection table to generate the second data collection table. It should be noted that different simulation types may require different data to be extracted. For example, when the simulation type is delay type, it is necessary to perform special slave delay statistics for the test cases of the specified master accessing all slave lines (Slave) configuration type in the SOC system, that is, to count all slave values in the SOC system; when the simulation type is single master thread type, after parsing each test case, the next step is to compile and summarize the overall report information of all masters accessing memory slave paths in the SOC chip system, that is, to further organize the test case reports of each master access path to obtain a global performance report of the SOC chip; when the simulation type is multi-master thread type, for all master access main memory delay test cases, the delay value from each master to each slave is counted and summarized in a table.

[0050] In the disclosed embodiment, the test cases in the simulation log are first traversed to obtain basic simulation data from the traversed test cases. Then, the simulation type of the test case is determined, and based on the basic simulation data of the test case, the initial data collection table corresponding to the simulation type is filled to generate a first data collection table. Finally, after the traversal is completed, the first data collection table for each simulation type is completed based on the simulation type to generate a second data collection table corresponding to the simulation type. Thus, the log file is automatically analyzed according to the different simulation types, thereby increasing the efficiency and accuracy of verification and improving the quality of the chip.

[0051] In the above embodiment, based on the simulation type, the first data collection table is completed to generate the second data collection table corresponding to the simulation type. Figure 3 Explaining further, the method includes:

[0052] S301 , classifying test cases based on simulation types, and obtaining test case groups belonging to the same simulation type.

[0053] In the embodiment of the present disclosure, after obtaining the classified test case group, it is also necessary to filter out the log data of simulation failures of each test case to increase the validity of the data, reduce the data size, and reduce the cost of data processing.

[0054] S302: Obtain delay data of each test case in the test case group.

[0055] In the disclosed embodiments, latency data includes read latency and / or write latency. Read latency and write latency are the delays incurred by the chip when reading or writing data, and to some extent, they can reflect the chip's performance. Therefore, further processing of the read latency and / or write latency values can provide a basis for subsequent verification.

[0056] It should be noted that different simulation types require different delay data. For example, when the simulation type is delay type, special slave delay statistics are required for test cases of specified master accessing all slave line (Slave) configuration types in the SOC system; when the simulation type is single-master thread type, the next step after parsing each test case is to organize and summarize the delay values of all masters accessing memory slave paths in the SOC chip system; when the simulation type is multi-master thread type, for all delay test cases of masters accessing the main memory, the delay values from each master to each slave are counted and summarized in a table.

[0057] After obtaining the delay value, it can be further processed to obtain at least one parameter among the maximum read delay, minimum read delay, maximum write delay, minimum write delay, average read delay, and average write delay from the simulation-type delay data. This can provide more detailed data for subsequent verification, reduce costs, and improve verification efficiency.

[0058] S303 : For each simulation type, based on the delay data belonging to the simulation type, completing the first data collection table of the simulation type, and generating a second data collection table corresponding to the simulation type.

[0059] In the disclosed embodiment, test cases are first classified based on simulation type, and a test case group belonging to the same simulation type is obtained. Then, delay data for each test case in the test case group is obtained. Finally, for each simulation type, the first data collection table for the simulation type is completed based on the delay data belonging to the simulation type, and a second data collection table corresponding to the simulation type is generated. Thus, according to different simulation types, delay data corresponding to the simulation log data of each simulation type is obtained, providing more effective data for subsequent chip performance analysis and optimization, reducing verification costs and improving verification efficiency.

[0060] In the above embodiment, based on the simulation type, the first data collection table is completed to generate the second data collection table corresponding to the simulation type. Figure 4 Explaining further, the method includes:

[0061] S401 : In response to a simulation type being a delay type, obtaining a first test case whose simulation type belongs to the delay type.

[0062] It is understandable that different simulation types may have simulation data with different characteristics and focuses. Therefore, different data processing methods need to be adopted for different simulation types.

[0063] In the embodiment of the present disclosure, when it is necessary to generate the second data collection table corresponding to the delay type, it is necessary to first summarize the first test cases to facilitate analysis and data extraction.

[0064] S402: Obtain first delay data of a designated main thread corresponding to a first test case and all slave threads corresponding to the designated main thread.

[0065] In an embodiment of the present disclosure, after obtaining the first test case, a simulation directory with the simulation type of the first test case expanded is obtained, a target log file of successful simulation is filtered from the simulation directory, and the first delay data of the specified main thread and all slave threads corresponding to the specified main thread are obtained from the target log file.

[0066] It should be noted that the first delay data may include multiple types, including display delay, processor maximum delay, average delay, etc.

[0067] S403: Completing the first data collection table based on the first delay data to generate a second data collection table corresponding to the delay type.

[0068] In the embodiment of the present disclosure, after the first delay data is collected, the first delay data may be analyzed and processed to generate the required data and input into the initial data collection table to generate a second data collection table corresponding to the delay type, such as Figure 5 It should be noted that the first delay data can be classified, summed, and averaged. For example, the data table can be used for analysis and processing to generate the following data:

[0069] The maximum latency of the bus cpu, cpu_Rmax_latency=38.333365ns,

[0070] Minimum delay min_latency=8.333350ns,

[0071] Average latency avg_latency = 38.267998ns.

[0072] In the disclosed embodiment, first, in response to the simulation type being a delay type, a first test case of the delay type is obtained. Then, first delay data for a designated master thread corresponding to the first test case and all slave threads corresponding to the designated master thread are obtained. Finally, the first delay data is input into an initial data collection table to generate a second data collection table corresponding to the delay type. Thus, by separately analyzing and summarizing delay-type test cases, it is possible to better determine whether the delay-type data is normal and any problems it contains, thereby enabling better chip optimization.

[0073] In the above embodiment, based on the simulation type, the first data collection table is completed to generate the second data collection table corresponding to the simulation type. Figure 6 Explaining further, the method includes:

[0074] S601: In response to the simulation type being a single main thread type, obtaining a second test case whose simulation type is a single main thread type.

[0075] In the embodiment of the present disclosure, when it is necessary to generate the second data collection table corresponding to the single main thread type, it is necessary to first summarize the first test cases, so as to facilitate the analysis and data extraction of the test cases of the single main thread type.

[0076] S602: Obtain access data of a single master thread corresponding to the second test case and each slave thread corresponding to the single master thread.

[0077] In the disclosed embodiment, after parsing each test case, the next step is to compile and summarize the overall report information for all master access memory slave paths in the SOC chip system. This is done by further compiling the test case reports for each master access path to obtain a global performance report for the SOC chip.

[0078] S603: Generate analysis data corresponding to the single main thread type based on the access data.

[0079] like Figure 7 As shown, for single-master thread test cases, the next step after parsing each test case is to organize and summarize the overall report information of all masters accessing memory slave paths in the SOC chip system.

[0080] S604: Complete the first data collection table based on the analysis data to generate a second data collection table corresponding to the single main thread type.

[0081] In the embodiment of the present disclosure, after collecting the first delay data, the first delay data can be analyzed and processed to generate the required data and input into the initial data collection table to generate a second data collection table corresponding to the delay type. The throughput and write throughput can also be read and analyzed, and the maximum, minimum and average values can be marked and imported into the table to generate the following data: Figure 7 The table shown.

[0082] In the disclosed embodiment, in response to the simulation type being a single-main-thread type, access data for the single-main-thread and each slave thread corresponding to the single-main-thread is collected for all test cases in the initial data collection table. Analysis data corresponding to the single-main-thread type is generated based on the access data. Finally, the analysis data is input into the initial data collection table to generate a second data collection table corresponding to the single-main-thread type. Thus, by separately analyzing and summarizing test cases of the single-main-thread type, problems with the single-main-thread type data can be better identified, providing a foundation for subsequent optimization.

[0083] In the above embodiment, based on the simulation type, the first data collection table is completed to generate the second data collection table corresponding to the simulation type. Figure 8 Explaining further, the method includes:

[0084] S801: In response to the simulation type being a multi-main-thread type, obtaining a third test case whose simulation type is a multi-main-thread type.

[0085] In the embodiment of the present disclosure, when it is necessary to generate the second data collection table corresponding to the single main thread type, it is necessary to first summarize the first test cases, so as to facilitate the analysis and data extraction of the test cases of the single main thread type.

[0086] S802: Obtain second delay data of all main threads corresponding to the third test case and slave threads corresponding to the main threads.

[0087] In an embodiment of the present disclosure, after obtaining the third test case, a simulation directory expanded with the simulation type of the first test case is obtained, a target log file of successful simulation is filtered from the simulation directory, and the second delay data of the specified main thread and all slave threads corresponding to the specified main thread are obtained from the target log file.

[0088] After the delay data is obtained, the second delay data may be analyzed to obtain the read data and write data from each master thread to each slave thread in the second delay data, and the data are compiled into a table.

[0089] S803: Complete the first data collection table based on the second delay data to generate a second data collection table corresponding to the multi-main thread type.

[0090] In the disclosed embodiment, in response to the simulation type being a multi-main-thread type, a third test case of the multi-main-thread type is obtained, second delay data for all master threads corresponding to the third test case and the slave threads corresponding to the master threads is obtained, and finally, the second delay data is input into the initial data collection table to generate a second data collection table. Thus, by separately analyzing and summarizing the test cases of the multi-main-thread type, the data of the multi-main-thread type can be more accurately analyzed and refined, thereby improving the efficiency and accuracy of data analysis.

[0091] In the above embodiment, the basic simulation data of the test case can also be obtained by Figure 9 Explaining further, the method includes:

[0092] S901, obtain the simulation directory of the test case.

[0093] In the embodiment of the present disclosure, after the simulation is completed, a simulation directory for each test case will be generated. It should be noted that each test case will only perform the test of the simulation type corresponding to the test case, so the generated simulation directory also corresponds to the corresponding test type.

[0094] S902: Determine the target log data of successful simulation in the simulation directory.

[0095] After obtaining the simulation directory, the simulation directory is screened and the target log files with successful simulations are selected as the text for subsequent data processing. In this way, by screening the simulation directory, the amount of data to be processed can be reduced, the cost can be reduced, and the accuracy of data processing can be improved.

[0096] S903: Determine test case function configuration data and bandwidth data based on the target log data.

[0097] In the embodiments of the present disclosure, the functional configuration data may include multiple types, for example, whether the low pin count bus (LPC) function is enabled, whether the firewall function is enabled, the read-write ratio value, whether the address is continuous, etc., which are not limited here and are specifically limited according to actual simulation needs.

[0098] In the embodiment of the present disclosure, the bandwidth information in the target log file can be parsed and filled into the row corresponding to the simulation mode and the column corresponding to the bandwidth. For example,

[0099] Bus cpu_W bandwidth: 12791.070794MB / s,

[0100] Bandwidth of bus cpu_R: 12799.989760MB / s.

[0101] S904: Determine basic simulation data for the test case based on the functional configuration data and the bandwidth data.

[0102] In the embodiment of the present disclosure, after obtaining the main mode data, bandwidth data and / or delay data, the main mode data may be analyzed and processed to generate more complete basic simulation data.

[0103] Optionally, bandwidth data can be compared with a set threshold. If the bandwidth data meets the designed threshold, the test case is marked as passed. If the bandwidth data does not meet the designed threshold, the test case is marked as failed, and the initial data collection table is populated based on the marking. Thus, by comparing bandwidth data with the set threshold, loan data is marked, facilitating subsequent processing and improving data processing efficiency.

[0104] Optionally, the read throughput, write throughput, and total throughput of the target log file may be determined according to the bandwidth data, and the first data collection table may be updated based on the read throughput, write throughput, and total throughput.

[0105] Optionally, the maximum read delay, minimum read delay, maximum write delay, minimum write delay, average read delay and average write delay in the target log file can also be determined based on the delay data, and the second data collection table can be updated based on the maximum read delay, minimum read delay, maximum write delay, minimum write delay, average read delay and average write delay.

[0106] In the disclosed embodiment, a simulation directory for a test case is first obtained, and then a target log file in the simulation directory that has been successfully simulated is determined. The target log file is then screened based on the functional configuration to obtain the functional configuration data. The bandwidth data and delay data for the test case are then determined based on the target log file. Finally, the basic simulation data for the test case is determined based on the primary mode data, bandwidth data, and / or delay data. Thus, by screening the test case and determining the basic simulation data for the test case, the amount of data ultimately verified can be reduced, thereby improving the accuracy and cost of verification.

[0107] Furthermore, after obtaining the second data collection tables of the three simulation types, the second data collection tables of the different simulation types can be analyzed separately to determine whether the chip has performance unsatisfactory problems, design code functional defects, whole chip integration errors, etc. based on the analysis results, and make corrections based on the problems found.

[0108] Corresponding to the chip operation data collection methods provided in the above-mentioned embodiments, an embodiment of the present disclosure also provides a chip operation data collection device. Since the chip operation data collection device provided in the embodiment of the present disclosure corresponds to the chip operation data collection methods provided in the above-mentioned embodiments, the implementation method of the above-mentioned chip operation data collection method is also applicable to the chip operation data collection device provided in the embodiment of the present disclosure, and will not be described in detail in the following embodiments.

[0109] Figure 10 FIG10 is a schematic diagram of a chip operation data collection device proposed in the present disclosure. As shown in FIG10 , the chip operation data collection device 1000 includes: a traversal module 1010 , a first generation module 1020 and a second generation module 1030 .

[0110] The traversal module 1010 is used to traverse the test cases in the simulation log to obtain basic simulation data from the traversed test cases.

[0111] The first generating module 1020 is configured to determine a simulation type of the test case and fill in an initial data collection table corresponding to the simulation type based on basic simulation data of the test case to generate a first data collection table.

[0112] The second generating module 1030 is configured to, after the traversal is completed, complete the first data collection table for each simulation type based on the simulation type to generate a second data collection table corresponding to the simulation type.

[0113] In one embodiment of the present disclosure, the second generation module 1030 is further used to: classify test cases based on the simulation type, and obtain a test case group belonging to the same simulation type; obtain delay data for each test case in the test case group; for each simulation type, based on the delay data belonging to the simulation type, complete the first data collection table of the simulation type, and generate a second data collection table corresponding to the simulation type.

[0114] In one embodiment of the present disclosure, the second generation module 1030 is further used to: obtain at least one parameter among the maximum read delay, minimum read delay, maximum write delay, minimum write delay, average read delay and average write delay from the delay data belonging to the simulation type; write the obtained at least one parameter into the first data collection table corresponding to the simulation type, and generate a second data collection table corresponding to the simulation type.

[0115] In one embodiment of the present disclosure, the second generation module 1030 is further used to: in response to the simulation type being a delay type, obtain a first test case whose simulation type belongs to the delay type; obtain first delay data of a specified main thread corresponding to the first test case and all slave threads corresponding to the specified main thread; complete the first data collection table based on the first delay data, and generate a second data collection table corresponding to the delay type.

[0116] In one embodiment of the present disclosure, the second generation module 1030 is further used to: in response to the simulation type being a single main thread type, obtain a second test case whose simulation type belongs to the single main thread type; obtain access data of the single main thread corresponding to the second test case and each slave thread corresponding to the single main thread; generate analysis data corresponding to the single main thread type based on the access data; complete the first data collection table based on the analysis data, and generate a second data collection table corresponding to the single main thread type.

[0117] In one embodiment of the present disclosure, the second generation module 1030 is further used to: in response to the simulation type being a multi-main thread type, obtain a third test case whose simulation type belongs to the multi-main thread type; obtain second delay data of all main threads corresponding to the third test case and slave threads corresponding to the main threads; complete the first data collection table based on the second delay data, and generate a second data collection table corresponding to the multi-main thread type.

[0118] In one embodiment of the present disclosure, the traversal module 1010 is further used to: obtain a simulation directory of a test case; determine target log data of successful simulation in the simulation directory; obtain functional configuration data based on the target log data; determine the test case functional configuration data and bandwidth data based on the target log data; and determine basic simulation data of the test case based on the functional configuration data and bandwidth data.

[0119] In one embodiment of the present disclosure, the first generating module 1020 is further configured to: fill the function configuration data into the first data collection table; filter the test cases based on the bandwidth data, and fill the bandwidth data of the filtered test cases into the first data collection table.

[0120] In one embodiment of the present disclosure, the first generation module 1020 is further configured to: determine the read throughput, write throughput, and total throughput of the target log data according to the bandwidth data; and fill the first data collection table based on the read throughput, write throughput, and total throughput.

[0121] In order to implement the above embodiment, the present disclosure also provides an electronic device 1100, such as Figure 11As shown, the electronic device 1100 includes: a processor 1101 and a memory 1102 communicatively connected to the processor, the memory 1102 stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor 1101 to implement the chip operation data collection method as described in the first aspect of the embodiment of the present disclosure.

[0122] In order to implement the above embodiments, the embodiments of the present disclosure further propose a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to implement the chip operation data collection method as described in the first aspect of the embodiment of the present disclosure.

[0123] In order to implement the above embodiments, the embodiments of the present disclosure further provide a computer program product, including a computer program. When the computer program is executed by a processor, it implements the chip operation data collection method as described in the first embodiment of the present disclosure.

[0124] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present disclosure.

[0125] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0126] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0127] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and are not to be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A method for collecting chip operation data, characterized in that: include: Traversing the test cases in the simulation log to obtain basic simulation data from the traversed test cases; Determining a simulation type of the test case, and filling an initial data collection table corresponding to the simulation type based on basic simulation data of the test case to generate a first data collection table; After the traversal is completed, for each simulation type, the first data collection table is completed based on the simulation type to generate a second data collection table corresponding to the simulation type; The step of completing the first data collection table based on the simulation type to generate a second data collection table corresponding to the simulation type includes: Classifying the test cases based on the simulation type to obtain a test case group belonging to the same simulation type; Obtaining delay data for each test case in the test case group; For each of the simulation types, based on the delay data belonging to the simulation type, the first data collection table of the simulation type is completed to generate a second data collection table corresponding to the simulation type; The step of completing the first data collection table based on the simulation type to generate a second data collection table corresponding to the simulation type includes: In response to the simulation type being a delay type, obtaining a first test case whose simulation type belongs to the delay type; Obtain first delay data of a designated main thread corresponding to the first test case and all slave threads corresponding to the designated main thread; Completing the first data collection table based on the first delay data to generate a second data collection table corresponding to the delay type; The step of completing the first data collection table based on the simulation type to generate a second data collection table corresponding to the simulation type includes: In response to the simulation type being a single main thread type, obtaining a second test case whose simulation type belongs to the single main thread type; Obtain access data of a single main thread corresponding to the second test case and each slave thread corresponding to the single main thread; generating analysis data corresponding to the single main thread type based on the access data; Completing the first data collection table based on the analysis data to generate a second data collection table corresponding to the single main thread type; The step of completing the first data collection table based on the simulation type to generate a second data collection table corresponding to the simulation type includes: In response to the simulation type being a multi-main-thread type, obtaining a third test case whose simulation type belongs to the multi-main-thread type; Obtain second delay data of all main threads corresponding to the third test case and slave threads corresponding to the main threads; The first data collection table is completed based on the second delay data to generate a second data collection table corresponding to the multi-main thread type.

2. The method according to claim 1, characterized in that The delay data includes: read delay and / or write delay, wherein the first data collection table of the simulation type is supplemented based on the delay data belonging to the simulation type to generate a second data collection table corresponding to the simulation type, including: Obtaining at least one parameter of a maximum read delay, a minimum read delay, a maximum write delay, a minimum write delay, an average read delay, and an average write delay from the delay data belonging to the simulation type; The at least one acquired parameter is written into a first data collection table corresponding to the simulation type, and a second data collection table corresponding to the simulation type is generated.

3. The method according to claim 1, characterized in that The traversing of the test cases in the simulation log to obtain basic simulation data from the traversed test cases further includes: Obtaining a simulation directory of the test case; Determine target log data of successful simulation in the simulation directory; Determining the test case function configuration data and bandwidth data based on the target log data; Basic simulation data for the test case is determined based on the functional configuration data and the bandwidth data.

4. The method according to claim 3, characterized in that The method of filling the initial data collection table corresponding to the simulation type based on the basic simulation data of the test case to generate a first data collection table further includes: Filling the function configuration data into the first data collection table; The test cases are screened based on the bandwidth data, and the bandwidth data of the screened test cases are filled into the first data collection table.

5. The method according to claim 4, characterized in that The step of filling the first data collection table with the bandwidth data of the test cases of the filtered and deleted content includes: Determine the read throughput, write throughput, and total throughput of the target log data according to the bandwidth data; The first data collection table is filled based on the read throughput, the write throughput, and the total throughput.

6. A device for collecting chip operation data, characterized in that: include: A traversal module, configured to traverse the test cases in the simulation log to obtain basic simulation data from the traversed test cases; A first generating module is configured to determine a simulation type of the test case and, based on basic simulation data of the test case, fill an initial data collection table corresponding to the simulation type to generate a first data collection table; a second generating module configured to, after the traversal is completed, complete the first data collection table for each simulation type based on the simulation type to generate a second data collection table corresponding to the simulation type; The second generating module is further configured to: Classifying the test cases based on the simulation type to obtain a test case group belonging to the same simulation type; Obtaining delay data for each test case in the test case group; For each of the simulation types, based on the delay data belonging to the simulation type, the first data collection table of the simulation type is completed to generate a second data collection table corresponding to the simulation type; The second generating module is further configured to: In response to the simulation type being a delay type, obtaining a first test case whose simulation type belongs to the delay type; Obtain first delay data of a designated main thread corresponding to the first test case and all slave threads corresponding to the designated main thread; Completing the first data collection table based on the first delay data to generate a second data collection table corresponding to the delay type; The second generating module is further configured to: In response to the simulation type being a single main thread type, obtaining a second test case whose simulation type belongs to the single main thread type; Obtain access data of a single main thread corresponding to the second test case and each slave thread corresponding to the single main thread; generating analysis data corresponding to the single main thread type based on the access data; Completing the first data collection table based on the analysis data to generate a second data collection table corresponding to the single main thread type; The second generating module is further configured to: In response to the simulation type being a multi-main-thread type, obtaining a third test case whose simulation type belongs to the multi-main-thread type; Obtain second delay data of all main threads corresponding to the third test case and slave threads corresponding to the main threads; The first data collection table is completed based on the second delay data to generate a second data collection table corresponding to the multi-main thread type.

7. The device according to claim 6, characterized in that The second generating module is further configured to: Obtaining at least one parameter of a maximum read delay, a minimum read delay, a maximum write delay, a minimum write delay, an average read delay, and an average write delay from the delay data belonging to the simulation type; The at least one acquired parameter is written into a first data collection table corresponding to the simulation type, and a second data collection table corresponding to the simulation type is generated.

8. The device according to claim 6, characterized in that The traversal module is also used to: Obtaining a simulation directory of the test case; Determine target log data of successful simulation in the simulation directory; The function configuration obtains function configuration data based on the target log data; Determining the test case function configuration data and bandwidth data based on the target log data; Basic simulation data for the test case is determined based on the functional configuration data and the bandwidth data.

9. An electronic device, characterized in that: Including memory and processor; The processor reads the executable program code stored in the memory to run a program corresponding to the executable program code, so as to implement the method according to any one of claims 1 to 5.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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