Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display, in the first display stage, the data signal writing frequency of the subpixels of the first display area and the second display area is the same; in the second display stage, the data signal writing frequency of the subpixels of the first display area is less than the data signal writing frequency of the subpixels of the second display area; the display area comprises first-type data lines and second-type data lines, each subpixel is electrically connected with the first-type data lines through a first switch module, and the subpixels in the first display area are further electrically connected with the second-type data lines through a second switch module; in the first display stage, the first-type data lines transmit data signals to the subpixels; in the second display stage, the first-type data lines transmit data signals to the subpixels in the second display area, and the second-type data lines transmit data signals to the subpixels in the first display area, so that the power consumption of a product with different display requirements in different display areas is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, more particularly, to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the display effect of display products is constantly improved, so that the application of display products is more and more widely.

[0003] With the progress of display technology, users have higher and higher requirements for the picture quality displayed by display devices. Generally, the higher the picture quality of display devices (i.e., the clearer the picture), the higher the screen refresh frequency. The refresh frequency of a display panel refers to the frequency of updating the display picture of the display panel. At present, one refresh frequency of a display panel is 60 Hz (Hertz), that is, the display picture of the display panel is updated 60 times per second.

[0004] When some areas of a display panel need to display static pictures, and the remaining areas still need to display dynamic pictures normally, the areas with different display requirements in the related technology can only be refreshed at a fixed frequency. Such a setting inevitably leads to an increase in the overall power consumption of the display panel. SUMMARY

[0005] Therefore, the present application provides a display panel and a display device, aiming to reduce the power consumption of the display panel when different display areas have different display requirements.

[0006] In a first aspect, the present application provides a display panel, comprising a display area, the display area comprising at least one first display area and at least one second display area, the first display area and the second display area each comprising a plurality of sub-pixels; the display panel comprising a first display stage and a second display stage, in the first display stage, the data signal writing frequency of the sub-pixels of the first display area and the second display area is the same; in the second display stage, the data signal writing frequency of the sub-pixels of the first display area is less than the data signal writing frequency of the sub-pixels of the second display area.

[0007] The display area comprises first-type data lines and second-type data lines, each of the sub-pixels is electrically connected to the first-type data lines through a first switch module, and the sub-pixels in the first display area are further electrically connected to the second-type data lines through a second switch module; in the first display stage, the first-type data lines transmit data signals to the sub-pixels; in the second display stage, the first-type data lines transmit data signals to the sub-pixels in the second display area, and the second-type data lines transmit data signals to the sub-pixels in the first display area.

[0008] In a second aspect, the present application provides a display device comprising the display panel provided by the first aspect of the present application.

[0009] Compared with the related art, the display panel and the display device provided by the present application at least achieve the following beneficial effects:

[0010] In the display panel and the display device provided by the embodiments of the present application, the display area comprises a first display area and a second display area, in the first display stage, the sub-pixels in the first display area and the second display area are displayed by using the same data signal writing frequency; in the second display stage, the first display area can be displayed by using a lower data signal writing frequency (lower than the data signal writing frequency of the second display area), for example, the first display area can display a static picture or a picture with a lower refresh frequency, and the second display area still displays a normal dynamic picture. In the second display stage, the present application reduces the data signal writing frequency of the first display area which needs to display a static picture or a picture with a lower refresh frequency, so that the power consumption of the product can be reduced to a certain extent. In addition, the present application sets two types of data lines in the display area, wherein the first type of data line is used for transmitting data signals to the sub-pixels in the first display area and the second display area in the first display stage, in the second display stage, the second type of data line is used for transmitting data signals to the sub-pixels in the first display area, and the first type of data line is still used for transmitting data signals to the sub-pixels in the second display area. The way of distinguishing and setting the data lines corresponding to the sub-pixels in the first display area and the second display area in the second display stage can reduce the frequency of transmitting data signals to the first display area by the second type of data line, so as to be beneficial to further reducing the power consumption of the product in the second display stage.

[0011] Of course, any product implementing the present application does not necessarily need to achieve all the technical effects mentioned above at the same time.

[0012] Other characteristics and advantages of the present application will become apparent from the following detailed description of exemplary embodiments thereof, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings incorporated in and forming a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the application.

[0014] Figure 1 Fig. 1 shows a structure schematic diagram of a display panel provided by an embodiment of the present application;

[0015] Figure 2 Fig. 2 shows a connection schematic diagram of a data line and a sub-pixel in the first display area;

[0016] Figure 3Fig. 1 shows a connection diagram of a single sub-pixel in the first display area and the first type of data line and the second type of data line;

[0017] Figure 4 Fig. 2 shows another structure diagram of the display panel provided by the embodiment of the present application;

[0018] Figure 5 Fig. 3 shows a connection diagram of the sub-pixels connected with the same second type of data line;

[0019] Figure 6 Fig. 4 shows a film layer diagram of the second type of data line provided by the embodiment of the present application;

[0020] Figure 7 Fig. 5 shows another film layer diagram of the second type of data line provided by the embodiment of the present application;

[0021] Figure 8 Fig. 6 shows another connection diagram of the data line and the sub-pixel in the second display area;

[0022] Figure 9 Fig. 7 shows a connection diagram of the driving circuit in the sub-pixel and the first type of data line and the second type of data line provided by the embodiment of the present application;

[0023] Figure 10 Fig. 8 shows a setting diagram of the gate driving unit in the display panel provided by the embodiment of the present application;

[0024] Figure 11 Fig. 9 shows another connection diagram of the driving circuit in the sub-pixel and the first type of data line and the second type of data line provided by the embodiment of the present application;

[0025] Figure 12 Fig. 10 shows another setting diagram of the gate driving unit in the display panel provided by the embodiment of the present application;

[0026] Figure 13 Fig. 11 shows a corresponding relationship diagram of the light emitting control unit and the display area in the display panel provided by the embodiment of the present application;

[0027] Figure 14 Fig. 12 shows a structure diagram of the display device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0028] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, numerical expressions, and numerical values set forth in these embodiments are not intended to limit the scope of the present application unless otherwise specifically stated.

[0029] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0030] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0031] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0032] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0033] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0034] Figure 1 The diagram shown is a structural schematic of a display panel provided in an embodiment of the present invention. Figure 2 The diagram shown illustrates one possible connection between data lines and sub-pixels in the first display area. Figure 3 The diagram shown illustrates one possible connection between a single sub-pixel in the first display area and the first and second type of data lines. Please refer to the diagram. Figures 1 to 3 This invention provides a display panel 100, including a display area AA, which includes at least one first display area AA1 and at least one second display area AA2. Both the first display area AA1 and the second display area AA2 include a plurality of sub-pixels P. The display panel 100 includes a first display stage and a second display stage. In the first display stage, the data signal writing frequency of the sub-pixels P in the first display area AA1 and the second display area AA2 is the same. In the second display stage, the data signal writing frequency of the sub-pixels P in the first display area AA1 is less than the data signal writing frequency of the sub-pixels P in the second display area AA2.

[0035] The display area AA includes the first type of data line D1 and the second type of data line D2, each sub-pixel P is electrically connected with the first type of data line D1 through the first switch module K1, and the sub-pixel P in the first display area AA1 is further electrically connected with the second type of data line D2 through the second switch module K2; in the first display stage, the first type of data line D1 transmits the data signal to the sub-pixel P; in the second display stage, the first type of data line D1 transmits the data signal to the sub-pixel P in the second display area AA2, and the second type of data line D2 transmits the data signal to the sub-pixel P in the first display area AA1.

[0036] It should be noted that, Figure 1 The display panel of the present application is only taken as an example of a rectangular structure, and in some other embodiments of the present application, the shape of the display panel can also be circular, elliptical or other, which is not specifically limited in the present application. Figure 1 Only a scheme in which the display panel includes one first display area AA1 and one second display area AA2 is shown, and the number of the first display area AA1 and the second display area AA2 actually contained in the display panel of the present application is not limited, and the specific positional relationship of the first display area AA1 and the second display area AA2 in the display panel is also not limited, that is, the number and arrangement of the first display area AA1 and the second display area AA2 can be flexibly set according to actual needs, for example Figure 4 A scheme in which the display panel includes one second display area AA2 and two first display areas AA1 arranged on both sides of the second display area AA2 is shown, wherein, Figure 4 Another structural schematic diagram of the display panel provided by the embodiment of the present application is shown. In addition, Figure 1 and Figure 4 In the first display area AA1, only a rectangular shape is taken as an example for illustration, and in some other embodiments of the present application, the shape of the first display area AA1 can also be other, such as circular, elliptical and the like, which is not specifically limited in the present application. Alternatively, the first display area AA1 is a display area that can display a static picture or a picture with a low refresh frequency in the second display stage of the display panel, and when applied to a display product, for example, applied to a mobile phone or a watch or the like, in the second display stage, the first display area AA1 can display information such as time, weather and the like, and in the first display stage, the first display area AA1 and the second display area AA2 can jointly display a dynamic picture with the same refresh frequency, thereby meeting different application requirements of the display product.

[0037] It can be understood that, Figure 1 and Figure 4 In the display area AA, only one sub-pixel P is shown, which does not represent the number, size, shape and arrangement of the actual sub-pixel P, Figure 2Only the connection of the sub-pixel P in the first display area AA1 with the first type of data line D1 and the second type of data line D2 is shown, and the number, size, shape and arrangement of the sub-pixel P actually contained in the first display area AA1 are not limited.

[0038] Specifically, referring to Figures 1 to 4 In the display panel provided by the embodiment of the present application, the display area AA includes the first display area AA1 and the second display area AA2, in the first display stage, the sub-pixels P in the first display area AA1 and the second display area AA2 are displayed by using the same data signal writing frequency; in the second display stage, the first display area AA1 can be displayed by using a lower data signal writing frequency (lower than the data signal writing frequency of the second display area AA2), for example, the first display area AA1 can display a static picture or a picture with a lower refresh frequency, and the second display area AA2 still displays a normal dynamic picture. In the second display stage, the data signal writing frequency of the first display area AA1 which needs to display a static picture or a picture with a lower refresh frequency is reduced, so that the power consumption of the product can be reduced to a certain extent.

[0039] In addition, two types of data lines are arranged in the display area AA, wherein the first type of data line D1 is used for transmitting data signals to the sub-pixels P in the first display area AA1 and the second display area AA2 in the first display stage; in the second display stage, the second type of data line D2 is used for transmitting data signals to the sub-pixels P in the first display area AA1, and the first type of data line D1 is still used for transmitting data signals to the sub-pixels P in the second display area AA2. The way of distinguishing and arranging the data lines corresponding to the sub-pixels P in the first display area AA1 and the second display area AA2 in the second display stage can reduce the frequency of the second type of data line D2 transmitting data signals to the first display area AA1, so as to further reduce the power consumption of the product in the second display stage.

[0040] It should be noted that, in the second display stage, the manner that the data signal write frequency of the first display area AA1 is lower than the data signal write frequency of the first display area AA1 is applicable to the case that the first display area AA1 of the display panel displays by using the same refresh frequency, and is also applicable to the case that the first display area AA1 and the second display area AA2 of the display panel display by using different refresh frequencies. Whether the refresh frequencies of the first display area AA1 and the second display area AA2 are the same or not, the manner that the data signal write frequency of the first display area AA1 is reduced in the second display stage is beneficial to reducing the overall power consumption of the display panel. Of course, in the second display stage, the refresh frequency of the first display area AA1 is set to be lower than the refresh frequency of the second display area AA2 while the data signal write frequency of the first display area AA1 is set to be lower than the data signal write frequency of the second display area AA2, which is more beneficial to reducing the overall power consumption of the display panel.

[0041] Please refer to Figure 2 In an optional embodiment of the present application, the number of the second type of data lines D2 is less than the number of the first type of data lines D1.

[0042] When the sub-pixels P are arranged in the array as shown in Figure 2 Optionally, in the display panel, the sub-pixels P located in the same column are connected to the same first type of data line D1, and the sub-pixels P in the same row correspond to different first type of data lines D1 respectively, that is, the number of the first type of data lines D1 corresponds to the number of columns of the sub-pixels P. In order to reduce the power consumption of the first display area AA1 in the second display stage, an embodiment of the present application introduces the second type of data line D2 for providing the data signal to the sub-pixels P in the second display area AA2 in the second display stage. Optionally, an embodiment of the present application limits the number of the second type of data lines D2 to be less than the number of the first type of data lines D1, that is, different second type of data lines D2 do not need to be introduced for each column of the sub-pixels P, but at least two columns of the sub-pixels P in the first display area AA1 are connected to the same second type of data line D2, which is beneficial to reducing the wiring complexity when the second type of data line D2 is introduced in the display panel. In addition, since the refresh frequency in the second display stage is low, the displayed picture is a fixed picture or a dynamic picture with a small change frequency, so even if the sub-pixels P in different columns are connected to the same second type of data line, the display effect of the first display area AA1 in the second display stage can still be ensured.

[0043] Please refer to Figure 2 and Figure 3 In an optional embodiment of the present application, the sub-pixels P form a plurality of pixel rows and a plurality of pixel columns, and in the first display area AA1, the sub-pixels P in at least M pixel rows are electrically connected to the same second type of data line D2 through the second switch module K2, and 2≤M≤20.

[0044] Specifically, when the array of sub-pixels P in the display panel is arranged to form a plurality of pixel rows and a plurality of pixel columns, the data signals transmitted from the data lines to the sub-pixels P in the first display stage are different from the data signals transmitted from the data lines to the sub-pixels P in the second display stage. Figure 2 and Figure 3 It can be obviously seen that the first type of data lines D1 and the second type of data lines D2 are connected to the sub-pixels P in different manners. The same first type of data line D1 is electrically connected to the sub-pixels P in the same column, and the sub-pixels P in different columns are connected to different data lines respectively. The same second type of data line D2 is electrically connected to the sub-pixels P in at least two pixel rows, for example, the same second type of data line D2 is electrically connected to the sub-pixels P in the first and second pixel rows. Figure 2 In the illustrated embodiment, part of the second type of data lines D2 are electrically connected to the sub-pixels P in part of the pixel rows in the odd rows, and part of the second type of data lines D2 are electrically connected to the sub-pixels P in part of the pixel rows in the even rows. Of course, in some other embodiments of the present application, the same second type of data line D2 can also be electrically connected to the sub-pixels P in several continuous pixel rows, which is not limited in the present application.

[0045] In the second display stage, the sub-pixels P in the at least two pixel rows connected to the same second type of data line D2 can all transmit data signals through the second type of data line D2. Assuming that the same second type of data line D2 is connected to two pixel rows, when the sub-pixels P in the first pixel row are scanned, the signals transmitted by the second type of data line D2 correspond to the data signals of the sub-pixels P in the first pixel row; when the sub-pixels P in the second pixel row are scanned, the signals transmitted by the second type of data line D2 correspond to the data signals of the sub-pixels P in the second pixel row. Since the frequency of the signal change on the same second type of data line D2 is also reduced in the second display stage, it is beneficial to reduce the power consumption of the display panel in the second display stage. Of course, if the data signals of the sub-pixels P in the two pixel rows are consistent, the data signals on the second type of data line D2 will not need to change, which is more beneficial to reduce the overall power consumption of the display panel.

[0046] Figure 5 It is shown as a connection diagram of the sub-pixels P connected to the same second type of data line D2. Please refer to Figure 5 In an optional embodiment of the present application, each second switch module K2 connected to the same second type of data line D2 is connected to the same control signal terminal.

[0047] Specifically, in the first display area AA1 of the display panel provided by the embodiment of the present application, the sub-pixel P is electrically connected with the first type of data line D1 through the first switch module K1 and is electrically connected with the second type of data line D2 through the second switch module. In the first display stage, the first switch module K1 is turned on, and the first type of data line D1 provides the data signal to the sub-pixel P; in the second display stage, the second switch module K2 is turned on, and the second type of data line D2 provides the data signal to the sub-pixel P. In the embodiment of the present application, the control end of the second switch module K2 corresponding to the sub-pixel P electrically connected with the same second type of data line D2 is connected with the same control signal end K0, and the conduction state of each sub-pixel P connected with the same second type of data line D2 and the second type of data line D2 can be controlled through the same control signal end K0, thereby being beneficial to simplifying the overall circuit complexity of the display panel after the second type of data line D2 and the second switch module K2 are introduced.

[0048] Please combine Figure 2 and Figure 5 In an optional embodiment of the present application, the number of sub-pixels P connected with the same second type of data line D2 is greater than the number of sub-pixels P connected with the same first type of data line D1; and the impedance of the same second type of data line D2 is less than the impedance of the same first type of data line D1.

[0049] Specifically, in the embodiment of the present application, the number of sub-pixels P connected with the same second type of data line D2 is greater than the number of sub-pixels P connected with the same first type of data line D1, that is, the load connected with the second type of data line D2 is greater than the load connected with the first type of data line D1. Therefore, the impedance of the second type of data line D2 and the impedance of the first type of data line D1 are differentially set, so that the impedance of the same second type of data line D2 is less than the impedance of the same first type of data line D1, to balance the load difference between the first type of data line D1 and the second type of data line D2, reduce or avoid the phenomenon of display unevenness caused by the load difference between the two, and thus be beneficial to improving the overall display uniformity of the display panel.

[0050] Figure 6 As shown is a film layer schematic view of the second type of data line D2 provided by the embodiment of the present application, please refer to Figure 6 In an optional embodiment of the present application, the same second type of data line D2 includes a first line segment L1 and a second line segment L2 arranged in different layers, and the first line segment L1 and the second line segment L2 are connected in parallel through a connection hole.

[0051] Specifically, to realize that the impedance of the same second type of data line D2 is less than the impedance of the same first type of data line D1, the embodiment adopts the parallel connection of the first line segment L1 and the second line segment L2 to form the same second type of data line D2, thereby effectively reducing the impedance of the same second type of data line D2 itself, wherein the first line segment L1 and the second line segment L2 are arranged in different layers and connected by at least two connection holes.

[0052] It can be understood that, Figure 6 Only the scheme in which the first line segment L1 and the second line segment L2 are connected by two connection vias is shown, and in some other embodiments of the present application, for example, please refer to Figure 7 The first line segment L1 and the second line segment L2 can also be electrically connected by three or more connection vias, and the more the number of connection vias, the more conducive to reducing the impedance of the same second type of data line D2, wherein, Figure 7 Another film layer diagram of the second type of data line D2 provided by the embodiment of the present application is shown.

[0053] In addition, Figure 6 And Figure 7 The embodiment shown only shows the scheme in which the same second type of data line D2 includes the first line segment L1 and the second line segment L2 arranged in different layers, and in some other embodiments of the present application, the same second type of data line D2 can also include three or more line segments arranged in different layers to further reduce the impedance of the second type of data line D2.

[0054] Figure 8 Another connection diagram of the data line and the sub-pixel in the second display area is shown, Figure 8 The embodiment shown shows a scheme in which one second type of data line D2 is connected with two adjacent rows of sub-pixels P, and another second type of data line D2 is connected with another two adjacent rows of sub-pixels P.

[0055] Please refer to Figure 8 In an optional embodiment of the present application, the extension directions of the first type of data line D1 and the second type of data line D2 are the same, and in the first display area AA1, N first type of data lines D1 are arranged between two adjacent second type of data lines D2, 2≤N≤20.

[0056] Specifically, when the second type of data lines D2 are introduced on the display panel, the extension direction of the second type of data lines D2 can be set to be the same as the extension direction of the first type of data lines D1, so as to simplify the wiring complexity of the first type of data lines D1 and the second type of data lines D2. Since the number of the second type of data lines D2 is less than the number of the first type of data lines D1 in the present case, when the second type of data lines D2 are laid out, N first type of data lines D1 are arranged between every two adjacent second type of data lines D2, that is, one second type of data line D2 is arranged every N first type of data lines D1, and optionally, the number of the first type of data lines D1 arranged between any two adjacent second type of data lines D2 is equal, thus being conducive to improving the overall uniformity of the arrangement of the second type of data lines D2. Figure 8 The scheme that four first type of data lines D1 are arranged between two adjacent second type of data lines D2 is taken as an example for illustration, and the actual number of the first type of data lines D1 contained between the two adjacent second type of data lines D2 is not limited, and in some other embodiments of the present application, the number of the first type of data lines D1 arranged between the two adjacent second type of data lines D2 can also be other.

[0057] Figure 9 Fig. 1 shows a connection diagram of a driving circuit in a sub-pixel P and the first type of data lines D1 and the second type of data lines D2 according to an embodiment of the present application, and Fig. 2 shows a connection diagram of a driving circuit in a sub-pixel P and the first type of data lines D1 and the second type of data lines D2 according to another embodiment of the present application. Figure 9 In an optional embodiment of the present application, the sub-pixel P includes a pixel driving circuit, and the pixel driving circuit includes a first node N1, a second node N2, a third node N3, a fourth node N4, a driving transistor M0, a data writing module 11, a first node reset module 12, a compensation module 13, a fourth node reset module 14, and a diode D0, wherein the data writing module 11 includes a first switch module K1; the gate of the driving transistor M0 and the first node reset module 12 are connected to the first node N1, the source of the driving transistor M0 and the data writing module 11 are connected to the second node N2, the drain of the driving transistor M0 is connected to the third node N3, the compensation module 13 is connected between the third node N3 and the first node N1, the third node N3 is coupled to the fourth node N4; the diode D0 and the fourth node reset module 14 are connected to the fourth node N4.

[0058] In the first display area AA1, the second switch module K2 is connected to the second node N2.

[0059] Specifically, Figure 9The pixel driving circuit of the sub-pixel P in the embodiment shown includes seven transistors, which does not limit the actual structure of the pixel driving circuit, and the pixel driving circuit can also be embodied in other structures in some other embodiments of the present application. Alternatively, the transistor in the data writing module 11 can correspond to the first switch module K1 mentioned in the above embodiment. The second switch module K2 in the embodiment of the present application is connected to the second node N2 of the pixel driving circuit. Alternatively, the working process of the pixel driving circuit includes three stages, namely, an initialization stage, a data writing stage and an emitting stage. In the initialization stage, the first node N1 and the fourth node N4 in the pixel driving circuit are reset by the first node reset module 12 and the fourth node reset module 14, respectively. In the data writing stage, the data signal is written into the sub-pixel P by the first type of data line D1 and the data writing module 11, or the data signal is written into the sub-pixel P by the second type of data line D2 and the second switch module K2. In the emitting stage, the driving transistor M0 forms a driving current to drive the diode to emit light.

[0060] In the first display stage, the transmission of the data signal in the first display area AA1 is from the first type of data line D1 to the data writing module 11 and then to the second node N2. In the second display stage, the transmission of the data signal in the first display area AA1 is from the second type of data line D2 to the second switch module K2 and then to the second node N2. In the second display stage, the frequency of the data signal transmitted to the sub-pixel P in the first display area AA1 during the static picture display process can be controlled by controlling the on-off frequency of the second switch module K2, that is, the frequency of the data signal transmitted to the sub-pixel P can be adaptively reduced to reduce the power consumption of the display panel in the second display stage, thereby reducing the overall power consumption of the display panel.

[0061] Continuing to refer to Figure 9 In an optional embodiment of the present application, in the first display stage, the second switch module K2 is multiplexed as a second node reset module; in the data writing stage of the second display stage, in the first display area AA1, the data writing module 11 is closed and the second switch module K2 is turned on.

[0062] Specifically, in the first display stage, the first display area AA1 and the second display area AA2 display regular pictures with the same refresh frequency. In the data writing stage, the first type of data line D1 provides data signals to the sub-pixels P in the first display area AA1 and the second display area AA2, and the second type of data line D2 is closed, i.e., the second type of data line D2 does not write data signals to the data line. Optionally, before the data writing stage, a second node resetting stage is further included. At this time, the second switch module K2 is multiplexed as a second node resetting module, which is used to transmit a resetting signal to the second node N2 in the second node resetting stage, so as to reset the second node N2 in the pixel driving circuit. When the second node N2 is reset, the bias state of the driving transistor M0 can be adjusted by using the corresponding resetting signal, so as to reduce the influence of the signal of the previous frame on the signal of the current frame, thereby making the display picture of the current frame closer to the expected picture, and thus the display accuracy of the display panel is improved. In the embodiment of the present application, the second switch module K2 is multiplexed as the second node resetting module, and a separate module does not need to be introduced into the display panel, so that the overall circuit complexity of the display panel is simplified.

[0063] With reference to the foregoing Figure 9 In an optional embodiment of the present application, in the first display area AA1, the control end of the data writing module 11, the first node resetting module 12, the compensation module 13 and the fourth node resetting module 14 in the pixel driving circuit are respectively connected to different control signal ends.

[0064] Specifically, in the pixel driving circuit corresponding to the sub-pixel P in the first display area AA1, the control signal end connected to the data writing module 11 and the control signal end connected to the compensation module 13 are two independent control signal ends, which are respectively connected to the control signal ends S2 and S2N; the control ends connected to the first node resetting module 12 and the fourth node resetting module 14 are also two independent control signal ends, which are respectively connected to the control signal ends S1N and S1. That is to say, the above four modules are turned on or turned off under the control of different control signal ends. This design makes the control of the above four modules more flexible, for example, the on-off frequency of different modules can be flexibly controlled. For example, in the second display stage, for a certain row of sub-pixels P, in the same time period, when the first node resetting module 12 resets the first node N1 three times in the second display area, the first node resetting module 12 can be controlled to reset the first node N1 only once in the first display area, which is equivalent to reducing the reset frequency of the first node N1 in the first display area in the second display stage. When the reset frequency is reduced, the corresponding power consumption is also reduced, thereby reducing the overall power consumption of the display panel.

[0065] It should be noted that the mode that the control terminals of the data writing module 11, the first node resetting module 12, the compensation module 13 and the fourth node resetting module 14 in the pixel driving circuit are respectively connected with different control signal terminals is especially suitable for the case that the first display area AA1 and the second display area AA2 adopt different refresh frequencies for display in the second display stage, that is, the first display area AA1 adopts a lower refresh frequency, and the second display area AA2 still adopts a higher refresh frequency. When the first display area AA1 adopts a lower refresh frequency for display, the writing frequency of the data signal is reduced, which is more conducive to reducing the overall power consumption of the display panel. Of course, when the first display area AA1 and the second display area AA2 adopt the same refresh frequency, the control terminals of the data writing module 11, the first node resetting module 12, the compensation module 13 and the fourth node resetting module 14 in the pixel driving circuit can also be respectively connected with different control signal terminals.

[0066] Figure 10 Fig. 1 shows a setting diagram of a gate driving unit in a display panel provided by an embodiment of the present application. Please refer to Figure 10 In an optional embodiment of the present application, the display panel further comprises a plurality of first gate driving units (VSR11-VSR15, etc.) and a plurality of second gate driving units (VSR21-VSR25, etc.) corresponding to the first display area AA1 and the second display area AA2. The plurality of first gate driving units are cascaded, and the plurality of second gate driving units are cascaded. The first gate driving unit at the first stage and the second gate driving unit at the first stage are connected with different start trigger signal terminals, which are start trigger signal terminals STV1 and STV2 respectively.

[0067] Please refer to Figure 1 、 Figure 4 、 Figures 9 to 10 The control terminal of the first node resetting module 12 and the control terminal of the compensation module 13 are respectively connected with the output terminals of the first gate driving units at different stages; and the control terminal of the fourth node resetting module 14 and the control terminal of the data writing module 11 are respectively connected with the output terminals of the second gate driving units at different stages.

[0068] Specifically, two groups of gate driving units are introduced for the sub-pixels P in the first display area AA1 and the sub-pixels P in the second display area AA2, that is, the first gate driving unit (VSR11-VSR15, etc.) and the second gate driving unit (VSR21-VSR25, etc.) are arranged for the sub-pixels P in the first display area AA1, and the first gate driving unit and the second gate driving unit are also arranged for the sub-pixels P in the second display area AA2, and the first gate driving unit at the first stage and the second gate driving unit at the first stage are respectively connected to different start trigger signal terminals, so that the scanning start time of the first gate driving unit and the second gate driving unit can be controlled through different start trigger signal terminals. The control terminal of the first node reset module 12 and the control terminal of the compensation module 13 in the pixel driving circuit are respectively connected to the output terminals of the first gate driving units at different stages, and optionally, when the control terminal of the first node reset module 12 is connected to the output terminal of the first gate driving unit at the current stage, the control terminal of the compensation module 13 is connected to the output terminal of the first gate driving unit at the next stage, so that the compensation module 13 is started after the reset of the first node N1 is completed. The control terminal of the fourth node reset module 14 and the control terminal of the data writing module 11 in the pixel driving circuit are respectively connected to the output terminals of the second gate driving units at different stages, and optionally, when the control terminal of the fourth node reset module 14 is connected to the output terminal of the second gate driving unit at the current stage, the control terminal of the data writing module 11 is connected to the output terminal of the second gate driving circuit at the next stage, so that the data writing module 11 is started after the reset of the fourth node N4 is completed.

[0069] It should be noted that, Figure 10 Only the scheme of arranging the first gate driving unit and the second gate driving unit on the same side of the display area AA is shown, and in some other embodiments of the present application, the first gate driving unit and the second gate driving unit can also be arranged on the non-display sides of the opposite sides of the display area AA. In addition, Figure 10 The shown embodiment only shows the scheme that the display panel includes one group of first gate driving units and one group of second gate driving units, and in some other embodiments of the present application, two groups of first gate driving units and two groups of second gate driving units can also be introduced in the display panel, and the sub-pixels P on the display panel are driven in a double-side driving manner to improve the driving capability of the whole display panel.

[0070] Figure 11 The shown is another connection diagram between the driving circuit in the sub-pixel P and the first type data line D1 and the second type data line D2 provided by the embodiment of the present application, please refer to Figure 11In an alternative embodiment of the present application, in the second display area AA2, the control terminals of the data writing module 11 and the compensation module 13 in the pixel driving circuit are connected to the first control signal terminal S1, and the control terminals of the first node reset module 12 and the fourth node reset module 14 are connected to the second control signal terminal S2.

[0071] Specifically, Figure 11 In the illustrated embodiment, the control terminals of the data writing module 11 and the compensation module 13 in the pixel driving circuit are connected to the same control signal terminal, i.e., both are connected to the first control signal terminal S1, so that the data writing module 11 and the compensation module 13 can be controlled to be turned on or turned off simultaneously through the same first control signal terminal S1. In addition, the control terminals of the first node reset module 12 and the fourth node reset module 14 are connected to the same control signal terminal, i.e., both are connected to the second control signal terminal S2, so that the first node reset module 12 and the fourth node reset module 14 can be controlled to be turned on or turned off simultaneously through the same second control signal terminal S2. For the pixel driving circuit corresponding to the same sub-pixel P, the first node reset module 12 and the fourth node reset module 14 are usually turned on first to reset the first node N1 and the fourth node N4, and then the data writing module 11 and the compensation module 13 are turned on to perform data writing operation on the sub-pixel P.

[0072] Figure 12 Fig. 4 shows another setting diagram of the gate driving unit in the display panel provided by the embodiment of the present application, which is described with reference to Figure 1 、 Figure 4 and Figure 12 In an alternative embodiment of the present application, a plurality of gate driving units (VSR1-VSR5, etc.) corresponding to the first display area AA1 and the second display area AA2 are further included, and the plurality of gate driving units are cascaded. The gate driving unit VSR1 at the first stage is connected to the start trigger signal terminal STV, Figure 11 The first control signal terminal S1 and the second control signal terminal S2 are respectively connected to the output terminals of the gate driving units at different stages.

[0073] Specifically, Figure 12The scheme of introducing a set of gate driving units for the display panel is shown, the first control signal end connected with the data writing module 11 and the compensation module 13 and the second control signal end connected with the first node reset module 12 and the fourth node reset module 14 are respectively connected with the output ends of the gate driving units of different levels. For example, when the second control signal end S2 corresponding to the first node reset module 12 and the fourth node reset module 14 is connected with the output end of the gate driving unit of the current level, the first control signal end S1 connected with the data writing module 11 and the compensation module 13 will be connected with the output end of the gate driving unit of the next level, so that the data signal writing is performed after the first node N1 and the fourth node N4 are reset, so as to improve the display accuracy of the display panel.

[0074] It should be noted that when the display panel adopts a set of gate driving units to scan the sub-pixels P in the first display area AA1 and the second display area AA2 of the display panel, the scanning frequencies corresponding to the first display area AA1 and the second display area AA2 are the same. Due to the introduction of the second type of data signal line D2 and the second switch module K2, the data signal writing frequency of the first display area AA1 in the second display stage can be reduced through the second switch module K2, so that the overall power consumption of the display panel can also be reduced.

[0075] It should be noted that, Figure 12 Only the scheme of introducing a set of gate driving units in the display panel and arranging the gate driving units on the same side of the display area AA is shown, and in some other embodiments of the present application, two sets of gate driving units can also be introduced in the display panel, and the sub-pixels P on the display panel are driven in a double-side driving manner to improve the overall driving capability of the display panel.

[0076] Please refer to Figure 13 , Figure 13 The corresponding relationship diagram between the light emitting control unit and the display area AA in the display panel provided by the embodiment of the present application is shown, in an optional embodiment of the present application, the pixel driving circuit further includes a light emitting control module, the display panel further includes a plurality of first light emitting control units (such as Emit11-Emit13) arranged correspondingly with the pixel driving circuits in the first display area AA1 and a plurality of second light emitting control units (such as Emit21-Emit23) arranged correspondingly with the pixel driving circuits in the second display area AA2, wherein the plurality of first light emitting control units are cascaded, the plurality of second light emitting control units are cascaded, the first light emitting control unit at the first level and the second light emitting control unit at the first level are connected with different start trigger signal ends, and are respectively connected with the start trigger signal ends STV01 and STV02.

[0077] Specifically, in the first display area AA1, the signal of the control end of the light emitting control module in the pixel driving circuit is provided by the first light emitting control unit; in the second display area AA2, the control signal of the light emitting control module in the pixel driving circuit is provided by the second light emitting control unit. The first light emitting control unit at the first level and the second light emitting control unit at the second level in the first display area AA1 and the second display area AA2 are connected to different start trigger signal ends STV01 and STV02 respectively, so as to control the starting light emitting time of the sub-pixel in the first display area AA1 and the second display area AA2 respectively, thereby realizing flexible control of the starting light emitting time of different display areas AA, and meeting the same frequency refresh requirement and different frequency refresh requirement of different display areas AA.

[0078] Based on the same inventive concept, the application further provides a display device, Figure 14 As shown is a structural schematic diagram of a display device provided by an embodiment of the application, which comprises the display panel provided by the above-mentioned embodiments of the application. In the first display stage, the first display area and the second display area of the display device adopt the same data signal writing frequency, and optionally, the same refresh frequency is adopted for display. In the second display stage, the first display area can display a static picture or a dynamic picture with a lower refresh frequency, at this time, the data signal writing frequency of the first display area is set to be lower than the data signal writing frequency of the second display area, thereby being beneficial to reducing the overall power consumption of the display device.

[0079] It should be noted that the embodiments of the display device provided by the application can refer to the above-mentioned embodiments of the display panel, which will not be described herein. The display device provided by the embodiments of the application can be embodied as a mobile phone, a watch, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and any product or component with display function. It is especially suitable for display products with different refresh frequency requirements of different display areas AA.

[0080] In summary, the display panel and the display device provided by the application at least achieve the following beneficial effects:

[0081] In the display panel and the display device provided by the embodiment of the present application, the display area comprises a first display area and a second display area, in the first display stage, the sub-pixels in the first display area and the second display area are displayed by using the same data signal writing frequency; in the second display stage, the first display area can be displayed by using a lower data signal writing frequency (lower than the data signal writing frequency of the second display area), for example, the first display area can display static pictures or pictures with a lower refresh frequency, and the second display area still displays normal dynamic pictures. In the second display stage, the present application reduces the data signal writing frequency of the first display area which needs to display static pictures or pictures with a lower refresh frequency, so that the power consumption of the product can be reduced to a certain extent. In addition, the present application sets two types of data lines in the display area, wherein the first type of data line is used for transmitting data signals to the sub-pixels in the first display area and the second display area in the first display stage, in the second display stage, the second type of data line is used for transmitting data signals to the sub-pixels in the first display area, and the first type of data line is still used for transmitting data signals to the sub-pixels in the second display area. In the second display stage, the corresponding data lines of the sub-pixels in the first display area and the second display area are set in a differentiated manner, so that the frequency of the second type of data line for transmitting data signals to the first display area can be reduced, thereby being beneficial to further reducing the power consumption of the product in the second display stage.

[0082] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, but not for limiting the scope of the present application. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises a display area, the display area comprises at least one first display area and at least one second display area, the first display area and the second display area each comprise a plurality of sub-pixels; the display panel comprises a first display stage and a second display stage, in the first display stage, the data signal writing frequency of the sub-pixels of the first display area and the second display area is the same; in the second display stage, the data signal writing frequency of the sub-pixels of the first display area is less than the data signal writing frequency of the sub-pixels of the second display area, and at the same time, the refresh frequency of the first display area is lower than the refresh frequency of the second display area; The display area comprises first type data lines and second type data lines, each of the sub-pixels is electrically connected to the first type data lines through a first switch module, and the sub-pixels in the first display area are further electrically connected to the second type data lines through a second switch module; in the first display stage, the first type data lines transmit data signals to the sub-pixels; in the second display stage, the first type data lines transmit data signals to the sub-pixels in the second display area, and the second type data lines transmit data signals to the sub-pixels in the first display area; The sub-pixels form a plurality of pixel rows and a plurality of pixel columns, in the first display area, the sub-pixels in at least M pixel rows are electrically connected to the same second type data line through the second switch modules, 2≤M≤20, and the same first type data line is electrically connected to the sub-pixels in the same column.

2. The display panel of claim 1, wherein, The number of the second type data lines is less than the number of the first type data lines.

3. The display panel of claim 1, wherein, Each of the second switch modules connected to the same second type data line is connected to the same control signal terminal.

4. The display panel of claim 1, wherein, The number of the sub-pixels connected to the same second type data line is greater than the number of the sub-pixels connected to the same first type data line, and the impedance of the same second type data line is less than the impedance of the same first type data line.

5. The display panel of claim 4, wherein, The same second type data line comprises a first line segment and a second line segment arranged in different layers, and the first line segment and the second line segment are connected in parallel through a connection hole.

6. The display panel of claim 1, wherein, The extension directions of the first type data lines and the second type data lines are the same, and in the first display area, N first type data lines are arranged between any two second type data lines, 2≤N≤20.

7. The display panel of claim 1, wherein, The sub-pixels comprise a pixel driving circuit, the pixel driving circuit comprises a first node, a second node, a third node, a fourth node, a driving transistor, a data writing module, a first node reset module, a compensation module, a fourth node reset module and a diode, the data writing module comprises the first switch module; the gate of the driving transistor and the first node reset module are connected to the first node, the source of the driving transistor and the data writing module are connected to the second node, the drain of the driving transistor is connected to the third node, the compensation module is connected between the third node and the first node, and the third node is coupled to the fourth node; the diode and the fourth node reset module are connected to the fourth node; In the first display area, the second switch module is connected to the second node.

8. The display panel of claim 7, wherein, In the first display stage, the second switch module is multiplexed as a second node reset module; in a data writing stage of the second display stage, in the first display area, the data writing module is turned off, and the second switch module is turned on.

9. The display panel of claim 7, wherein, In the first display area, control ends of the data writing module, the first node reset module, the compensation module and the fourth node reset module in the pixel driving circuit are respectively connected to different control signal ends.

10. The display panel of claim 9, wherein, Further comprising a plurality of first gate driving units and a plurality of second gate driving units corresponding to the first display area and the second display area, the plurality of first gate driving units are cascaded, the plurality of second gate driving units are cascaded, a first-stage first gate driving unit and a first-stage second gate driving unit are connected to different start trigger signal ends; Control ends of the first node reset module and the compensation module are respectively connected to output ends of different-stage first gate driving units; control ends of the fourth node reset module and the data writing module are respectively connected to output ends of different-stage second gate driving units.

11. The display panel of claim 7, wherein, In the second display area, control ends of the data writing module and the compensation module in the pixel driving circuit are both connected to a first control signal end, and control ends of the first node reset module and the fourth node reset module are both connected to a second control signal end.

12. The display panel of claim 11, wherein, Further comprising a plurality of gate driving units corresponding to the first display area and the second display area, the plurality of gate driving units are cascaded; The first control signal end and the second control signal end are respectively connected to output ends of different-stage gate driving units.

13. The display panel of claim 7, wherein, The pixel driving circuit further comprises a light-emitting control module, and the display panel further comprises a plurality of first light-emitting control units corresponding to pixel driving circuits in the first display area and a plurality of second light-emitting control units corresponding to pixel driving circuits in the second display area, wherein the plurality of first light-emitting control units are cascaded, the plurality of second light-emitting control units are cascaded, a first-stage first light-emitting control unit and a first-stage second light-emitting control unit are connected to different start trigger signal ends.

14. A display device comprising: The display panel comprises any one of claims 1 to 13. The display panel comprises any one of claims 1 to 13.

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