Interconnection circuit structure

Abstract

The present application provides an interconnection circuit structure for a deep trench capacitor, wherein the deep trench capacitor includes a capacitor trench group, including: a front-layer interconnection wire, including: a first front-layer interconnection wire, located above and to the side of the capacitor trench group and extending in the same direction as the capacitor trench group; a plurality of second front-layer interconnection wires, located on the capacitor trench group and arranged at intervals in the extending direction of the capacitor trench group, the second front-layer interconnection wires spanning the capacitor trench group and connected to the first front-layer interconnection wire at one end; a rear-layer interconnection wire, located on the second front-layer interconnection wire and part of the first front-layer interconnection wire; a plurality of through-wires, arranged between the front-layer interconnection wire and the rear-layer interconnection wire, forming a circuitous interconnection circuit structure. The interconnection circuit structure of the technical solution of the present application can improve the performance of the deep trench capacitor at high frequencies and improve the high-frequency adaptability of the deep trench capacitor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an interconnection circuit structure. Background Art

[0002] In digital circuits, the high-frequency signals output by devices easily generate electromagnetic waves, which cause electromagnetic noise. The signal and electromagnetic noise are coupled, causing the signal voltage transmitted on the signal line to be distorted. In order to suppress this interference, decoupling capacitors are inserted into the circuit.

[0003] In existing deep trench capacitors (DTCs) integrated on interposers, the interconnects between the capacitor trench groups often use straight wiring. The magnetic flux generated by current induction easily causes self-inductance in the interconnects, increasing the equivalent series inductance (ESL) of the capacitor trench groups. Furthermore, for high-frequency signals, the impedance of the capacitor changes with frequency. Higher-frequency signals are more likely to be grounded through the capacitor, causing the effective capacitance to decrease with increasing frequency.

[0004] Therefore, in order to improve the performance of the device at high frequencies in response to high-frequency signal interference, it is necessary to improve the interconnection circuit of the DTC to enhance the high-frequency adaptability of the deep trench capacitor. Summary of the Invention

[0005] The technical problem solved by the technical solution of the present application is to provide an interconnection circuit that can improve the performance of deep trench capacitors at high frequencies and enhance the high-frequency adaptability of deep trench capacitors.

[0006] To solve the above technical problems, the technical solution of the present application provides an interconnection circuit structure for a deep trench capacitor, wherein the deep trench capacitor includes a capacitor trench group, including: a front-layer interconnection wire, including: a first front-layer interconnection wire, located above and to the side of the capacitor trench group and extending in the same direction as the capacitor trench group; a plurality of second front-layer interconnection wires, located on the capacitor trench group and arranged at intervals in the extension direction of the capacitor trench group, the second front-layer interconnection wires spanning the capacitor trench group and connected to the first front-layer interconnection wire at one end; a rear-layer interconnection wire, located on the second front-layer interconnection wire and a portion of the first front-layer interconnection wire; and a plurality of through-wires, arranged between the front-layer interconnection wire and the rear-layer interconnection wire, to form a circuitous interconnection circuit structure.

[0007] In an embodiment of the present application, the interconnection circuit structure includes a plurality of rear-layer interconnection wires arranged at intervals along the extension direction of the capacitor groove group, each rear-layer interconnection wire includes a first rear-layer interconnection wire located on the first front-layer interconnection wire and a second rear-layer interconnection wire located on the second front-layer interconnection wire.

[0008] In the embodiment of the present application, part of the through-wires are located between the second front-layer interconnection wire and the second rear-layer interconnection wire, and part of the through-wires are located between the first front-layer interconnection wire and the first rear-layer interconnection wire.

[0009] In the embodiment of the present application, the rear-layer interconnection wire is L-shaped, and the through wire is located at one end or both ends of the L-shape.

[0010] In an embodiment of the present application, the front-layer interconnection wire further includes a U-shaped or straight-line third front-layer interconnection wire, and adjacent capacitor trench groups are connected via the third front-layer interconnection wire.

[0011] In the embodiment of the present application, the U-shaped third front-layer interconnection wire further includes a third rear-layer interconnection wire, and the third front-layer interconnection wire and the third rear-layer interconnection wire are connected via through-wires located at both ends of the U-shape.

[0012] In the embodiment of the present application, some of the third front-layer interconnection wires cross the capacitor trench group and are arranged alternately with the second front-layer interconnection wires.

[0013] In the embodiment of the present application, an inter-conductor dielectric layer is further provided between the front-layer interconnection conductor and the rear-layer interconnection conductor, and the through-conductor is located in the inter-conductor dielectric layer.

[0014] In an embodiment of the present application, the capacitor trench group and the front-layer interconnection wire further include an interlayer dielectric layer, a first wire layer and a front-layer inter-wire dielectric layer in sequence, and the first wire layer and the front-layer interconnection wire are connected through the front-layer through-wire in the front-layer inter-wire dielectric layer.

[0015] In an embodiment of the present application, when the operating frequency is greater than 1 GHz, the capacitance of the deep trench capacitor is greater than 20 picofarads and the equivalent inductance is less than 10 picohenry.

[0016] The technical solution of the present application forms a circuitous interconnection circuit structure by arranging a front-layer interconnection wire and a rear-layer interconnection wire above the capacitor groove group, wherein the front-layer interconnection wire includes a first front-layer interconnection wire and multiple second front-layer interconnection wires, and the rear-layer interconnection wire is located on the second front-layer interconnection wire and a portion of the first front-layer interconnection wire. By designing the position of the through-wire between the front-layer interconnection wire and the rear-layer interconnection wire, a circuitous interconnection circuit structure is formed. The circuitous interconnection circuit structure can eliminate self-inductance and reduce the equivalent inductance value.

[0017] Each rear-layer interconnection wire includes a first rear-layer interconnection wire located on the first front-layer interconnection wire and a second rear-layer interconnection wire located on the second front-layer interconnection wire, part of the through-wires are located between the second front-layer interconnection wire and the second rear-layer interconnection wire, and part of the through-wires are located between the first front-layer interconnection wire and the first rear-layer interconnection wire, so as to form a circuitous interconnection circuit structure.

[0018] Furthermore, the rear-layer interconnection wire is L-shaped, and the through wire is located at one or both ends of the L-shape, so that the direction of signal transmission in the rear-layer interconnection wire is opposite to the direction of signal transmission in the front-layer interconnection wire below the rear-layer interconnection wire, forming a circuitous interconnection circuit structure and avoiding the generation of self-induction.

[0019] The front-layer interconnection conductor further includes a U-shaped or straight third front-layer interconnection conductor, and adjacent capacitor trench groups are connected via the third front-layer interconnection conductor. The U-shaped third front-layer interconnection conductor further includes a third rear-layer interconnection conductor, and the third front-layer interconnection conductor and the third rear-layer interconnection conductor are connected via through conductors located at both ends of the U-shape, so that the transmission directions of signals in adjacent lines between adjacent capacitor trench groups are opposite, thereby avoiding self-inductance between adjacent capacitor trench groups.

[0020] A plurality of rear-layer interconnection wires are arranged at intervals along the extension direction of the capacitor groove group, which can weaken the self-inductance phenomenon and reduce ESL. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0022] Figure 1 A schematic diagram of the structure of an interconnection circuit;

[0023] Figure 2 for Figure 1 The cross-sectional view at the position of the AA dotted box;

[0024] Figure 3 for Figure 1 The cross-sectional view at the position of the dotted box BB in the middle;

[0025] Figure 4 A schematic diagram of an interconnection circuit structure (showing only the front-layer interconnection wires) according to an embodiment of the present application;

[0026] Figure 5 A schematic diagram of an interconnection circuit structure according to an embodiment of the present application;

[0027] Figure 6 for Figure 5 Cross-sectional view at the AA position;

[0028] Figure 7 for Figure 5 Cross-sectional view of the middle BB position;

[0029] Figure 8 This is a schematic diagram of another interconnection circuit structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0031] refer to Figure 1 An interconnect circuit for a deep trench capacitor includes a capacitor trench group 11A and a capacitor trench group 11B. Each capacitor trench group includes five capacitor trenches 11, and the capacitor trenches 11 are located in a semiconductor substrate 10. An interconnect circuit is arranged on the capacitor trench group 11A and the capacitor trench group 11B, and the interconnect circuit uses straight wiring. The interconnect circuit mainly includes two structures, one of which is shown in FIG. Figure 2 An interlayer dielectric layer 12 is formed on the surface of the capacitor trench 11 and the semiconductor substrate 10. A front metal layer 13, an intermetallic interlayer dielectric layer 14, a first conductor layer 15, an intermetallic interlayer dielectric layer 16, and a second conductor layer 17 are sequentially formed on the surface of the interlayer dielectric layer 12. A through conductor 18 is formed in the intermetallic interlayer dielectric layer 16, and the through conductor 18 connects the first conductor layer 15 and the second conductor layer 17. Figure 3, shows a second interconnection circuit, wherein an interlayer dielectric layer 12, a front metal layer 13, an intermetallic interlayer dielectric layer 14 and a first conductor layer 15 are sequentially formed on the surface of the semiconductor substrate 10, and a through conductor 19 is formed in the intermetallic interlayer dielectric layer 14, and the through conductor 19 connects the first conductor layer 15 and the front metal layer 13.

[0032] The two interconnect circuit structures described above span capacitor trench group 11A and capacitor trench group 11B and are arranged parallel to each other. Although this minimizes the wiring length, the magnetic flux generated by current induction easily causes self-inductance in the interconnect circuit, increasing the equivalent series inductance (ESL) of the capacitor unit. In addition, due to the impedance z = 1 / jωC, where ω = 2πf, f is the frequency of the high-frequency signal and C is the capacitance of the capacitor, the higher the frequency, the easier it is to connect to ground through the capacitor. The capacitor C, combined with the self-inductance effect caused by the straight wiring, causes the effective capacitance to decrease with increasing frequency, resulting in poor performance of the above interconnect circuit at high frequencies.

[0033] Based on this, the technical solution of the present application designs the lines of the interconnected wires and the positions of the through-wires to form a circuitous interconnected circuit structure. The circuitous interconnected circuit structure can eliminate self-inductance, thereby achieving a decoupling effect, so that high capacity and low ESL can still be achieved when working at high frequencies.

[0034] The technical solution of this application is described in detail below with reference to the embodiments and drawings.

[0035] refer to Figure 4 The interconnection circuit structure of the embodiment of the present application is used for a deep trench capacitor. The deep trench capacitor includes a capacitor trench group 110. The capacitor trench group 110 includes a plurality of capacitor trenches 111 distributed in parallel or substantially in parallel. The embodiment of the present application is described using 5 parallel distributed capacitor trenches 111 as an example.

[0036] The capacitor trench 111 is located in the semiconductor substrate 100. The capacitor trench 111 may be filled with dielectric and electrode layers commonly found in the art, which will not be further described herein. Therefore, the terms "on the capacitor trench 111," "on the capacitor trench group 110," and "above the capacitor trench group" that appear below essentially refer to the dielectric and electrode layers filled in the capacitor trench 111 or above the dielectric and electrode layers.

[0037] The interconnection circuit structure includes a front-layer interconnection conductor 120, which includes a first front-layer interconnection conductor 121 and a plurality of second front-layer interconnection conductors 122. The first front-layer interconnection conductor 121 is located above and to the side of the capacitor trench group 110, that is, the first front-layer interconnection conductor 121 is located above the semiconductor substrate 100 on the side of the capacitor trench group 110. The first front-layer interconnection conductor 121 extends in the same direction as the capacitor trench group 110. In some embodiments, the first front-layer interconnection conductor layer 121 is parallel or substantially parallel to the capacitor trench 110. The first front-layer interconnection conductor layer 120 is an indispensable part of forming a continuous and circuitous interconnection circuit structure.

[0038] The semiconductor substrate 100 (together with the capacitor trench group 110) and the first front-layer interconnection wire 121 further include an interlayer dielectric layer ILD, a first wire layer M0 and a front-layer inter-wire dielectric layer IMD1 in sequence. Figure 4 and Figure 5 The front inter-conductor dielectric layer IMD1 further includes a through conductor, which is used to connect the first conductor layer M0 and the front interconnect conductor 120. Similarly, the inter-layer dielectric layer ILD also has a through conductor to connect the first conductor layer M0 and the capacitor trench group. It should be noted that the through conductors in the front inter-conductor dielectric layer IMD1 and the inter-layer dielectric layer ILD do not participate in forming a circuitous interconnection circuit structure and are therefore not shown.

[0039] The second front layer interconnect wires 122 are located on the capacitor groove group 110 and are spaced apart in the extension direction of the capacitor groove group 110. The second front layer interconnect wires 122 span the capacitor groove group 110 and are connected to the first front layer interconnect wires 121 at one end. Adjacent second front layer interconnect wires 122 are parallel or substantially parallel to each other, and the extension direction of the second front layer interconnect wires 122 is perpendicular or substantially perpendicular to the extension direction of the capacitor groove group 110. In other words, the extension direction of the second front layer interconnect wires 122 is perpendicular or substantially perpendicular to the extension direction of the first front layer interconnect wires 121. In some embodiments, the front layer interconnect wires 120 are comb-shaped. The distance between adjacent second front layer interconnect wires 122 is designed according to actual conditions, for example, considering the self-inductance effect and device size. Since there are other line conductors (such as the third front-layer interconnection conductor 123 mentioned later) between adjacent second front-layer interconnection conductors 122, the self-inductance generated between adjacent second front-layer interconnection conductors 122 can be weakened. Therefore, the distance between the second front-layer interconnection conductors 122 can be designed to be very small, which is conducive to the miniaturization of the device.

[0040] refer to Figure 5 The interconnection circuit structure further includes a rear-layer interconnection conductor 130, which is located on the second front-layer interconnection conductor 122 and a portion of the first front-layer interconnection conductor 121. Specifically, there are multiple rear-layer interconnection conductors 130, which are spaced apart along the extension direction of the capacitor trench group 110. Each rear-layer interconnection conductor 130 includes a first rear-layer interconnection conductor 131 located on the first front-layer interconnection conductor 121 and a second rear-layer interconnection conductor 132 located on the second front-layer interconnection conductor 122. The second rear-layer interconnection conductor 132 completely covers the second front-layer interconnection conductor 122 and overlaps with each other, while the first rear-layer interconnection conductor 131 does not completely cover the first front-layer interconnection conductor 121. A portion of the first front-layer interconnection conductor 121 is exposed between adjacent first rear-layer interconnection conductors 131, which lays the foundation for forming a continuous and circuitous interconnection circuit structure. In some embodiments, the first rear-layer interconnection conductor 131 and the second rear-layer interconnection conductor 132 form an L-shape, that is, the rear-layer interconnection conductor 130 can be L-shaped.

[0041] refer to Figure 6 and Figure 7 ,in Figure 6 for Figure 5 The cross-sectional view at the AA position in the middle, Figure 7 for Figure 5 Cross-sectional view at position BB. An inter-conductor dielectric layer IMD2 is further included between the front-layer interconnection conductor 120 and the rear-layer interconnection conductor 130. That is, an inter-conductor dielectric layer IMD2 is included between the first front-layer interconnection conductor 121 and the first rear-layer interconnection conductor 131, and between the second front-layer interconnection conductor 122 and the second rear-layer interconnection conductor 132. The rear-layer interconnection conductor 130 completely covers the inter-conductor dielectric layer IMD2, and the rear-layer interconnection conductor 130 and the inter-conductor dielectric layer IMD2 have the same shape and size.

[0042] Continue to refer Figure 5 , a plurality of through-conductors 140 are arranged between the front-layer interconnection conductors 120 and the back-layer interconnection conductors 130. It should be understood that Figure 5 In fact, the through wire 140 will be blocked by the back-layer interconnect wire 130 from the perspective of Figure 5 The schematic diagram shows the through-conductor 140 only for a better understanding of the position of the through-conductor 140. By designing the lines of the front-layer interconnection wire 120 and the back-layer interconnection wire 130 and the position of the through-conductor 140, a circuitous interconnection circuit structure can be formed. The signal transmission directions in the circuitous lines are opposite, so the decoupling effect can be achieved, which can significantly reduce ESL. Figures 5 to 7, the through-wire 140 can be mainly divided into two parts, wherein one part of the through-wire 140 is located between the first front-layer interconnection wire 121 and the first rear-layer interconnection wire 131, and the other part of the through-wire 140 is located between the second front-layer interconnection wire 122 and the second rear-layer interconnection wire 132. In some embodiments, the rear-layer interconnection wire 130 is L-shaped, and the through-wire 140 is located at one or both ends of the L-shape. In the embodiment of the present application, the rear-layer interconnection wire 130 has a through-wire 140 at only one end, and the other end is a signal receiving end (the received signal is, for example, a current signal), and the signal input end of the rear-layer interconnection wire 130 is one end of the first rear-layer interconnection wire 131, while the remaining rear-layer interconnection wires 130 on the capacitor groove group have through-wires 140 at both ends to form a circuitous interconnection circuit structure.

[0043] Reference Figure 5 The upper end of the L-shaped rear interconnection wire 130 on the far right is the signal input end, and the signal input end is one end of the first rear interconnection wire 131. The input signal I enters the second rear interconnection wire 132 through the first rear interconnection wire 131. The direction of signal transmission is shown by the arrow in the figure. Figure 7 The signal I is transmitted to the end of the second rear layer interconnection wire 132 (corresponding to Figure 7 When the second rear-layer interconnection wire 132 is at the right end thereof, since the end of the second rear-layer interconnection wire 132 has a through-wire 140, the signal I enters the second front-layer interconnection wire 122 located below the second rear-layer interconnection wire 132 through the through-wire 140. The signal I is then transmitted along the second front-layer interconnection wire 122 to the first front-layer interconnection wire 121. In an actual formation process, the second front-layer interconnection wire 122 and the first front-layer interconnection wire 121 can be formed in the same etching process. Figure 7 In order to distinguish the positions of the second front-layer interconnection conductor 122 and the first front-layer interconnection conductor 121, a boundary line is shown between them. Similarly, a boundary line is shown between the second rear-layer interconnection conductor 132 and the first rear-layer interconnection conductor 131. The signal I propagates in opposite directions in the second rear-layer interconnection conductor 132 and the second front-layer interconnection conductor 122, completing a circuitous route. This circuitous route can eliminate self-inductance issues.

[0044] Combine Figure 5 and Figure 6Next, because both ends of the middle L-shaped rear-layer interconnection conductor 130 have through-conductors 140, the signal I, after traveling along the second front-layer interconnection conductor 122 to the first front-layer interconnection conductor 121, enters the middle first rear-layer interconnection conductor 131 through the through-conductors 140. The signal I then travels along the middle first rear-layer interconnection conductor 131 to the second rear-layer interconnection conductor 132. After reaching the end of the second rear-layer interconnection conductor 132, the signal I passes through the through-conductors 140 to the second front-layer interconnection conductor 122 below it. The direction of signal I propagation in the second front-layer interconnection conductor 122 is opposite to that in the second rear-layer interconnection conductor 132, completing a second detour. Using the same method as the second detour, the signal I makes a third detour at the leftmost L-shaped rear-layer interconnection conductor 130, finally passing through the first front-layer interconnection conductor 121 to the adjacent interconnection circuit structure.

[0045] The above describes the case where there is only one capacitor trench group 110 . The following describes the interconnection circuit structure when there are multiple capacitor trench groups. The number of capacitor trench groups is determined according to the required capacitance and is not limited here.

[0046] refer to Figure 8 , shows an interconnect circuit structure with four capacitor trench groups. The front-layer interconnect wire layer 120 also includes a U-shaped or straight third front-layer interconnect wire 123. The function of the third front-layer interconnect wire 123 is mainly to connect adjacent capacitor trench groups 110. Part of the third front-layer interconnect wire 123 spans the capacitor trench group 110 and is arranged alternately with the second front-layer interconnect wire 130. This part of the third front-layer interconnect wire 123 is connected to the first wire layer through the front-layer through-wire 141 in the front-layer inter-wire dielectric layer.

[0047] In the embodiment of the present application, the two groups of capacitor trench groups 110 located in the upper half are connected by a U-shaped third front layer interconnection wire 123, and the U-shaped third front layer interconnection wire 123 also includes a third rear layer interconnection wire 133. The third rear layer interconnection wire 133 is also U-shaped. The two ends of the U-shaped third front layer interconnection wire 123 are connected to the two ends of the U-shaped third rear layer interconnection wire 133 through a through wire.

[0048] The above details the circuitous transmission method of the signal I above the upper right capacitor trench group 110. The following describes how the signal I is transmitted from the upper right interconnection circuit structure to the upper left interconnection circuit structure. The signal I passes through the through wire from the left end of the first front layer interconnection wire 121 to one end of the U-shaped third rear layer interconnection wire 133, and then passes along the third rear layer interconnection wire 133 (as shown in FIG. Figure 8The direction of the signal I is opposite when the two sides of the U-shape are transmitted, completing the circuitous process between the capacitor groove groups, so that the self-induction phenomenon caused by the same signal direction will not occur between adjacent capacitor groove groups. Then, the third front layer interconnection wire below the third rear layer interconnection wire 133 is entered by the through-wire, and the transmission direction of the signal I in the third front layer interconnection wire is opposite to the transmission direction in the third rear layer interconnection wire, completing another circuitous process. Next, the signal I enters the L-shaped rear layer interconnection wire in the middle of the upper left side, and is then transferred to the front layer interconnection wire of the lower floor by the through-wire from the middle L-shaped rear layer interconnection wire. The following transmission process can refer to the foregoing content and will not be repeated here.

[0049] Continue to refer Figure 8 , although the direction of the signal I when it is transmitted in the second front layer interconnection conductor 132 is the same (such as Figure 6 The arrows in the middle all point upward), but adjacent second front layer interconnection wires 132 are arranged at intervals to reduce ESL.

[0050] By adopting the interconnection circuit structure of the embodiment of the present application, the capacitance of the deep trench capacitor can still be greater than 20 picofarads when the operating frequency is greater than 1 gigahertz, and the equivalent inductance value is reduced to less than 10 picohenry, which has better adaptability at high frequencies.

[0051] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0052] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0053] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" indicates the absence of intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0054] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0055] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. An interconnect circuit structure for a deep trench capacitor, wherein the deep trench capacitor comprises a capacitor trench group, characterized in that: include: Front-layer interconnect wires, including: a first front-layer interconnection wire, located above and on the side of the capacitor trench group and extending in the same direction as the capacitor trench group; a plurality of second front-layer interconnect wires, located on the capacitor trench group and spaced apart in an extension direction of the capacitor trench group, the second front-layer interconnect wires spanning the capacitor trench group and having one end connected to the first front-layer interconnect wire; a rear-layer interconnection wire located on the second front-layer interconnection wire and a portion of the first front-layer interconnection wire; A plurality of through-conductors are arranged between the front-layer interconnection conductors and the rear-layer interconnection conductors, so that the direction of signal transmission in the rear-layer interconnection conductors is opposite to that in the front-layer interconnection conductors, forming a circuitous interconnection circuit structure.

2. The interconnection circuit structure according to claim 1, wherein: It comprises a plurality of rear-layer interconnection wires spaced apart along the extension direction of the capacitor groove group, each rear-layer interconnection wire comprising a first rear-layer interconnection wire located on the first front-layer interconnection wire and a second rear-layer interconnection wire located on the second front-layer interconnection wire.

3. The interconnection circuit structure according to claim 2, wherein: Part of the through-conducting wires is located between the second front-layer interconnection wire and the second rear-layer interconnection wire, and part of the through-conducting wires is located between the first front-layer interconnection wire and the first rear-layer interconnection wire.

4. The interconnection circuit structure according to claim 3, wherein: The rear-layer interconnection wire is L-shaped, and the through wire is located at one end or both ends of the L-shape.

5. The interconnection circuit structure according to claim 1, wherein: The front layer interconnection wires further include a U-shaped or straight third front layer interconnection wire, and adjacent capacitor trench groups are connected via the third front layer interconnection wires.

6. The interconnection circuit structure according to claim 5, wherein: The U-shaped third front layer interconnection wire also includes a third rear layer interconnection wire. The third front layer interconnection wire and the third rear layer interconnection wire are connected via through-wires located at both ends of the U-shape.

7. The interconnection circuit structure according to claim 5, wherein: Part of the third front-layer interconnection wires crosses the capacitor trench group and is arranged alternately with the second front-layer interconnection wires.

8. The interconnection circuit structure according to claim 1, wherein: An inter-conductor dielectric layer is further provided between the front-layer interconnection conductor and the rear-layer interconnection conductor, and the through-conductor is located in the inter-conductor dielectric layer.

9. The interconnection circuit structure according to claim 1, wherein: An interlayer dielectric layer, a first conductor layer, and a front-layer interconductor dielectric layer are sequentially included between the capacitor trench group and the front-layer interconnect conductor. The first conductor layer and the front-layer interconnect conductor are connected through a front-layer through-conductor in the front-layer interconductor dielectric layer.

10. The interconnection circuit structure according to claim 1, wherein: When the operating frequency is greater than 1 gigahertz, the capacitance of the deep trench capacitor is greater than 20 picofarads and the equivalent inductance is less than 10 picohenry.

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