Device for electrostatic discharge protection and method of manufacturing the same

Abstract

The present application provides a device for electrostatic discharge protection and a manufacturing method thereof, the device comprising: a first input / output pad electrically connected to an input / output pin, the first input / output pad containing an input / output protection circuit disposed between a power line and a ground line, the input / output protection circuit configured to discharge an electrostatic discharge current at the input / output pin; a second input / output pad, the second input / output pad being a blank pad electrically connected to a radio frequency input / output terminal of an internal radio frequency circuit and an input / output pin respectively, configured to receive a signal from the input / output pin and transmit to the internal radio frequency circuit. With the above device, the parasitic capacitance load can be minimized while electrostatically protecting the radio frequency circuit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit design, and particularly relates to a device for electrostatic discharge protection and a manufacturing method thereof. BACKGROUND

[0002] This section is intended to provide background information to facilitate a better understanding of embodiments of the present application as set forth in the claim. The description herein does not constitute admission of prior art.

[0003] As electronic components become smaller and smaller, many integrated circuits are vulnerable to electrostatic discharge (ESD). Generally, an ESD current is a current that is generated instantaneously between two charged objects due to contact, short circuit or dielectric breakdown. ESD events can occur during the manufacturing process of electronic devices, for example, machine or human operation can cause ESD charging or discharging, which can permanently damage internal circuits.

[0004] ESD protection circuits can be used to protect circuits from ESD events to prevent electronic devices from malfunctioning or breakdown. However, most ESD protection circuits usually introduce a lot of parasitic capacitance. This parasitic capacitance can substantially reduce the performance of radio frequency (RF) circuits.

[0005] Therefore, how to implement ESD protection for sensitive RF circuits while minimizing parasitic capacitance load has become a problem to be solved. SUMMARY

[0006] In view of the problems existing in the prior art, a device for electrostatic discharge protection and a manufacturing method thereof are provided to minimize parasitic capacitance in the circuit while protecting RF circuits from static electricity.

[0007] The present application provides the following solutions.

[0008] In a first aspect of the present application, a device for electrostatic discharge protection is provided, comprising: a first input / output pad electrically connected to an input / output pin, the first input / output pad containing an input / output protection circuit disposed between a power line and a ground line, the input / output protection circuit being configured to discharge electrostatic discharge current at the input / output pin; and a second input / output pad, the second input / output pad being an empty pad electrically connected to a radio frequency input / output terminal of an internal radio frequency circuit and the input / output pin respectively, and being configured to receive a signal from the input / output pin and transmit to the internal radio frequency circuit.

[0009] In an embodiment, the apparatus further comprises: a power supply pad and a ground pad; wherein the power supply pad is electrically connected to the power supply pin and the input of the internal radio frequency circuit, and the power supply pad is provided with a power supply protection circuit; and / or the ground pad is electrically connected to the ground pin and the output of the internal radio frequency circuit, and the ground pad is provided with a ground protection circuit.

[0010] In an embodiment, during the package bonding process of the apparatus, the second input / output pad is bonded to the input / output pin after the first input / output pad is bonded to the input / output pin.

[0011] In an embodiment, the input / output protection circuit comprises: a first diode, the anode of which is electrically connected to the input / output pin, and the cathode of which is electrically connected to the power supply line, configured to provide a first dissipation path for electrostatic discharge current at the input / output pin; and a second diode, the cathode of which is electrically connected to the input / output pin, and the anode of which is electrically connected to the ground line, configured to provide a second dissipation path for electrostatic discharge current at the input / output pin, wherein the second dissipation path and the first dissipation path are opposite.

[0012] In an embodiment, the power supply protection circuit and the ground protection circuit each comprise: a clamping diode, the anode of which is connected to the ground line, and the cathode of which is connected to the power supply line; and a clamping circuit, the clamping circuit comprising: an RC series circuit connected to the power supply line and the ground line; an inverter circuit connected to the RC series circuit, the power supply line and the ground line; and an N-type discharge transistor connected to the inverter circuit, the power supply line and the ground line.

[0013] In an embodiment, the first input / output pad and the second input / output pad are respectively bonded to the input / output pin by a bonding wire to achieve electrical connection.

[0014] In an embodiment, the input / output protection circuit is arranged below the first input / output pad; the power supply protection circuit is arranged below the power supply pad, and the ground protection circuit is arranged below the ground pad.

[0015] In a second aspect, a method for manufacturing an apparatus for electrostatic discharge protection is provided, comprising: providing the apparatus according to any one of the first aspect, wherein during the package bonding process of the apparatus, the input / output pin is bonded to the second input / output pad after the first input / output pad is bonded to the input / output pin.

[0016] The above at least one technical solution adopted by the embodiment of the present application can achieve the following beneficial effects: in the embodiment, the empty pad is arranged between the input / output pin and the internal radio frequency circuit for signal transmission, and the input / output pin is additionally electrically connected to another pad containing the ESD protection circuit, so that the parasitic capacitance load of the radio frequency circuit is significantly reduced while the radio frequency circuit is protected by ESD.

[0017] It should be understood that the above description is only a summary of the technical solutions of the present application, so as to enable a clearer understanding of the technical means of the present application, so that the content of the specification can be implemented. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described by way of example. BRIEF DESCRIPTION OF DRAWINGS

[0018] By reading the detailed description of the exemplary embodiments below, those of ordinary skill in the art will understand the advantages and benefits described herein and other advantages and benefits. The drawings are for the purpose of illustrating exemplary embodiments only and are not considered limiting of the present application. Moreover, the same reference numbers are used throughout the drawings to represent the same components. In the drawings:

[0019] Figure 1 Structure diagram of a device for electrostatic discharge (ESD) protection according to an embodiment of the present application;

[0020] Figure 2 Schematic diagram of a power supply protection circuit / ground protection circuit according to an embodiment of the present application.

[0021] In the drawings, the same or corresponding reference numbers represent the same or corresponding parts. DETAILED DESCRIPTION

[0022] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0023] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0024] In the description of the present application, it is also necessary to explain that, unless otherwise explicitly specified and limited, the terms "set", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. In addition, the term "coupling" herein includes any direct and indirect electrical connection means. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0025] In addition, it should be noted that the embodiments and features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0026] The following will be described in detail Figure 1 The device for electrostatic discharge (ESD) protection of the present application is described in detail.

[0027] As Figure 1 shown, a device for electrostatic discharge (ESD) protection is provided, applied to an integrated circuit chip, the integrated circuit chip comprising an internal radio frequency circuit, and a plurality of pads are arranged around the internal radio frequency circuit. Wherein, the device for electrostatic discharge (ESD) protection of the present application specifically comprises:

[0028] A first input / output pad 110 is electrically connected to an input / output pin (I / O pin) 21, and the first input / output pad 110 comprises an input / output protection circuit 111 arranged between a power supply line VDD and a ground line VSS, wherein the input / output protection circuit 111 is an electrostatic discharge (ESD) protection circuit configured to discharge electrostatic discharge current generated at the input / output pin 21.

[0029] A second input / output pad 120 is an empty pad as a conductive element, one end of which is electrically connected to the input / output pin 21, and the other end is electrically connected to a radio frequency input / output end of the internal radio frequency circuit 20, and is configured to receive an input signal from the input / output pin 21 and transmit to the internal radio frequency circuit 20.

[0030] The term "empty pad" used herein generally refers to an input / output pad that does not contain any protection circuit.

[0031] Referring to Figure 1 , the working principle of the electrostatic discharge protection of the present application is as follows:

[0032] In normal state, the ESD protection elements (e.g. diodes) in the input / output protection circuit 111 are in off state, signals are transmitted from the input / output pin 21 to the RF I / O of the internal RF circuit 20 via the second input / output pad 120 for normal operation.

[0033] When an electrostatic discharge (ESD) event occurs at the input / output pin 21, an electrostatic pulse is generated from the input / output pin 21, and the ESD current is transmitted to the power line VDD and the ground line VSS via the first diode 31 or the second diode 32 in the input / output protection circuit 111, respectively, to discharge the ESD current and protect the internal RF circuit 20 from the ESD event, preventing the electronic device from malfunctioning or breakdown.

[0034] It can be understood that most ESD protection circuits usually introduce a lot of parasitic capacitance, which will substantially reduce the performance of the internal RF circuit. Therefore, the internal RF circuit 20 needs to trade off between ESD protection performance and circuit performance. Assuming that the parasitic capacitance of the diode in the input / output protection circuit 111 is Cdio in the prior art, the ESD ground impedance presented to the internal RF circuit 20 is: Z = (-1) / (2π*Cdio). However, in the case of the present embodiment, the ESD ground impedance presented to the RF circuit is: Z = (-1) / (2π*Cdio) + 2π*Lbond, where Lbond is the parasitic inductance. In essence, the parasitic capacitance load of the RF circuit is greatly reduced.

[0035] In an embodiment, the device for electrostatic discharge (ESD) protection of the present application further comprises a power pad 130 and a ground pad 140.

[0036] The power pad 130 is connected to the power pin 22 and the input end of the internal RF circuit 20, and the power line VDD is connected to the power pad 130 to provide a power voltage. In order to avoid damage to the internal RF circuit 20 caused by a possible electrostatic discharge (ESD) event at the power pin 22, the power pad 130 is also provided with a power protection circuit 131 for discharging the electrostatic discharge current generated at the power pin 22.

[0037] The ground pad 140 is connected to the ground pin 23 and the output end of the internal RF circuit 20, and the ground line VSS is connected to the ground pad 140 to provide a ground voltage. In order to avoid damage to the internal RF circuit 20 caused by a possible electrostatic discharge (ESD) event at the ground pin 23, the ground pad 140 is also provided with a ground protection circuit 141 for discharging the electrostatic discharge current generated at the ground pin 23.

[0038] InFigure 1 In the case shown, it can be understood that, when an ESD is applied to any pin of the chip, a large voltage will be coupled to the power line VDD, and the above-mentioned power protection circuit 131 or ground protection circuit 141 is used to discharge the electrostatic discharge (ESD) current generated at any pin, for example, when a positive electrostatic pulse is generated from the input / output pin 21, the positive electrostatic pulse will turn on the first diode 31 in the input / output protection circuit 111, and the voltage of the power line VDD will be pulled up through the turned-on first diode 31 unit, so as to discharge the ESD current through the power pad 130 and the ground pad 140.

[0039] In an embodiment, during the packaging and bonding process of the device, the second input / output pad 120 is bonded with the input / output pin 21 after the first input / output pad 110 is bonded with the input / output pin 21. It should be understood that the electrostatic discharge (ESD) event is also extremely likely to occur during the manufacturing and packaging process of the above-mentioned device. In the present embodiment, since the first input / output pad 110 carrying the input / output protection circuit 111 is connected first, the input / output pin 21 can always "see" a circuit (such as a diode) for electrostatic discharge (ESD) protection, so that even if an electrostatic discharge (ESD) event occurs during the manufacturing and packaging process, the electrostatic discharge (ESD) current can be discharged through the input / output protection circuit 111 (such as through the diode), so that the internal radio frequency circuit 20 can be protected during the manufacturing process.

[0040] On the contrary, if the input / output pin 21 is first bonded with the second input / output pad 120, it is possible that an electrostatic discharge (ESD) event occurs at the moment of bonding, and the internal radio frequency circuit 20 is burned out.

[0041] In an embodiment, the input / output protection circuit 111 comprises a first diode 31 and a second diode 32.

[0042] The anode of the first diode 31 is coupled with the input / output pin through the first input / output pad 110, and the cathode is electrically connected to the power line VDD. The first diode 31 is configured to provide a first consumption path for the electrostatic discharge current at the input / output pin 21, and is particularly configured to provide a discharge path for a positive electrostatic pulse occurring at the input / output pin 21. In Figure 1 In the case shown, the first consumption path is grounded from the first diode 31 through the power protection circuit 131 in the power pad 130.

[0043] The negative electrode of the second diode 32 is electrically connected to the input / output pin, i.e. coupled with the positive electrode of the first diode 31, and the positive electrode of the second diode 32 is electrically connected to the ground line VSS, which is configured to provide a second consumption path for the electrostatic discharge current at the input / output pin 21, in particular, to provide a discharge path for the negative electrostatic pulse occurring at the input / output pin 21.

[0044] In the embodiment, the ESD protection circuit composed of diodes is adopted as the input / output protection circuit 111 to avoid introducing excessive parasitic capacitance, and to transfer the positive high voltage applied to the input / output pin 21 to the power protection circuit 131 in the power pad 130 and the negative high voltage to the ground protection circuit 141 in the ground pad 140.

[0045] In another embodiment, the input / output protection circuit 111 can also include two or more diodes, which are not specifically limited in the present application.

[0046] Figure 2 The schematic diagram of the power protection circuit 131 / ground protection circuit 141 according to an embodiment of the present application is shown in the following Figure 2 The power protection circuit 131 and the ground protection circuit 141 are described in detail.

[0047] In an embodiment, the power protection circuit 131 and the ground protection circuit 141 each include a clamping diode 41 and a clamping circuit 42.

[0048] The positive electrode of the clamping diode 41 is connected to the ground line VSS, and the negative electrode is connected to the power line VDD. When a high voltage generated from ESD is applied to the ground line VSS, the clamping diode 41 is turned on, and the high voltage leaks to the power line VDD.

[0049] The clamp circuit 42 comprises: an RC series circuit connected to the power supply line VDD and the ground line VSS, wherein the RC series circuit comprises a resistance element R connected in series between the power supply line VDD and the ground line VSS, and a capacitor C as a capacitive load; an inverter circuit connected to the RC series circuit, the power supply line VDD and the ground line VSS, wherein the inverter circuit is a complementary metal oxide semiconductor (CMOS) inverter formed by complementarily arranging a P-type transistor P1 and an N-type transistor N1. That is, the inverter circuit connects the gate of the P-type transistor P1 and the gate of the N-type transistor N1, and sets the connection point as an input node IN; connects the drain of the P-type transistor P1 and the drain of the N-type transistor N1, and sets the connection point as an output node OUT. The connection point of the resistance element R and the capacitor C of the RC series circuit is connected to the input node IN; and an N-type discharge transistor N2 connected to the inverter circuit, the power supply line VDD and the ground line VSS, wherein the gate of the N-type discharge transistor N2 is connected to the output node OUT of the inverter circuit, the drain is connected to the power supply line VDD, and the source is connected to the ground line VSS, for providing a low-resistance discharge channel between the power supply and the ground when an ESD impact is sensed, and discharging the static charge in time.

[0050] In Figure 1 and Figure 2 In the example shown, when the circuit is in the normal power-on process, since the rise time of the VDD voltage is much greater than the time constant of the RC series circuit. At this time, the capacitor C can be charged in time by the power supply line VDD, and the input node IN presents a high level. After the coupling of the inverter circuit, the output node OUT is in a low level state, thereby strictly turning off the N-type discharge transistor N2. When the power supply line VDD is impacted by ESD, it can be understood that when any pin of the chip is impacted by ESD, a large voltage will be coupled to the power supply line VDD. Since the rise time of the ESD voltage is greater than the time constant of the RC series circuit, the rise speed of the power supply line VDD voltage is much greater than that of the input node IN, and the capacitor C cannot be charged in time, at this time the input node IN is in a low level. After the action of the inverter circuit, the output node OUT is pulled up to a high level by the P-type transistor P1, thereby turning on the N-type discharge transistor N2. In the on state, the N-type discharge transistor N2 provides a low-resistance discharge channel, and the ESD current can be effectively discharged. On the other hand, at this time the voltage between VDD / VSS is clamped at a relatively low potential, avoiding damage to the internal radio frequency circuit in the overvoltage state.

[0051] In another embodiment, the clamp diode and the clamp circuit can also have other structures, for example, comprising two or more clamp diodes, for example, the clamp circuit comprises two or more inverter circuits, which are not specifically limited in the present application.

[0052] Therefore, in the power protection circuit 131 and the ground protection circuit 141 thus configured, if an ESD event is applied to the power pin 22 or the ground pin 23, the power protection circuit 131 or the ground protection circuit 141 will be triggered by the above-mentioned specific voltage to operate in a manner of eliminating the potential difference between the power line VDD and the ground line VSS, thus protecting the internal radio frequency circuit 20.

[0053] In an embodiment, the first input / output pad 110 and the second input / output pad 120 are respectively bonded to the input / output pin 21 by a bonding wire to achieve electrical connection. The bonding wire is made of gold or copper.

[0054] In an embodiment, the input / output protection circuit 111 is arranged below the first input / output pad 110; the power protection circuit 131 is arranged below the power pad 130, and the ground protection circuit is arranged below the ground pad 140. It can be understood that arranging the protection circuit below the pad is more compact than arranging the pad and the protection circuit in the same plane.

[0055] The present application also provides a manufacturing method of the device for electrostatic discharge protection, specifically comprising:

[0056] The device according to any one of the above-mentioned embodiments is provided, wherein during the packaging bonding process of the device, the input / output pin 21 is bonded to the second input / output pad 120 after the first input / output pad 110 is bonded to the input / output pin 21.

[0057] It should be understood that the manufacturing and packaging process of the above-mentioned device is also extremely prone to electrostatic discharge (ESD) events. In the present embodiment, since the first input / output pad 110 carrying the input / output protection circuit 111 is connected first, the input / output pin 21 can always "see" a circuit (such as a diode) for electrostatic discharge (ESD) protection, so that even if an electrostatic discharge (ESD) event occurs during the manufacturing and packaging process, the electrostatic discharge (ESD) current can be discharged through the input / output protection circuit 111 (such as through the diode), thus protecting the internal radio frequency circuit 20 during the manufacturing process.

[0058] On the contrary, if the input / output pin 21 is first bonded to the second input / output pad 120, it is possible that an electrostatic discharge (ESD) event occurs at the moment of bonding, which in turn burns out the internal radio frequency circuit 20.

[0059] Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A device for electrostatic discharge protection, characterized in that, include: A first input / output pad (110) is electrically connected to an input / output pin (21). The first input / output pad (110) includes an input / output protection circuit (111) disposed between a power line (VDD) and a ground line (VSS). The input / output protection circuit (111) is configured to discharge electrostatic discharge current at the input / output pin (21). The second input / output pad (120) is an empty pad electrically connected to the input / output pin (21) and the radio frequency input / output terminal of the internal radio frequency circuit (20), respectively, and is configured to receive signals from the input / output pin (21) and transmit them to the internal radio frequency circuit (20); the empty pad refers to an input / output pad that does not contain any protection circuitry. The first input / output pad (110) and the second input / output pad (120) are respectively bonded to the input / output pin (21) to achieve electrical connection.

2. The apparatus according to claim 1, characterized in that, Also includes: Power pad (130) and ground pad (140); wherein, The power pad (130) is electrically connected to the power pin (22) and the input terminal of the internal radio frequency circuit (20), and the power pad (130) is provided with a power protection circuit (131); and / or, The grounding pad (140) is electrically connected to the grounding pin (23) and the output terminal of the internal radio frequency circuit (20), and the grounding pad (140) is provided with a ground protection circuit (141).

3. The apparatus according to claim 1, characterized in that, During the packaging bonding process of the device, after the first input / output pad (110) is bonded to the input / output pin (21), the second input / output pad (120) is bonded to the input / output pin (21).

4. The apparatus according to claim 2, characterized in that, The input / output protection circuit (111) includes: A first diode (31), the positive terminal of which is electrically connected to the input / output pin (21) and the negative terminal of which is electrically connected to the power supply line (VDD), is configured to provide a first dissipation path for the electrostatic discharge current at the input / output pin (21); and, A second diode (32), the negative terminal of which is electrically connected to the input / output pin (21) and the positive terminal connected to ground (VSS), is configured to provide a second dissipation path for another type of electrostatic discharge current at the input / output pin (21).

5. The apparatus according to claim 2, characterized in that, The power protection circuit (131) and the ground protection circuit (141) respectively include: A clamping diode (41), the positive terminal of which is connected to the ground line (VSS) and the negative terminal of which is connected to the power line (VDD); and, Clamping circuit (42) includes: an RC series circuit connected to the power line (VDD) and the ground line (VSS); an inverter circuit connected to the RC series circuit, the power line (VDD) and the ground line (VSS); and an N-type discharge transistor (N2) connected to the inverter circuit, the power line (VDD) and the ground line (VSS).

6. The apparatus according to claim 1 or 2, characterized in that, The first input / output pad (110) and the second input / output pad (120) are respectively bonded to the input / output pin (21) by bonding wires to achieve electrical connection.

7. The apparatus according to claim 2, characterized in that, The input / output protection circuit (111) is arranged below the first input / output pad (110); The power protection circuit (131) is arranged below the power pad (130), and the ground protection circuit (141) is arranged below the ground pad (140).

8. A method for manufacturing an apparatus for electrostatic discharge protection, characterized in that, include: Provide an apparatus as claimed in any one of claims 1-7, wherein, During the packaging process of the device, after the first input / output pad (110) is bonded to the input / output pin (21), the input / output pin (21) is bonded to the second input / output pad (120).

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