Light emitting element, light emitting component, display device, and method for manufacturing display device

Abstract

A light emitting element includes a first type semiconductor pattern, a second type semiconductor pattern, a light emitting pattern, a first electrode, a second electrode, and a protective layer. The second type semiconductor pattern overlaps the first type semiconductor pattern and is located on a first side of the first type semiconductor pattern. The light emitting pattern is located between the first type semiconductor pattern and the second type semiconductor pattern. The first electrode is located on a second side of the first type semiconductor pattern, the second side being opposite the first side, and the first electrode connects the first type semiconductor pattern. The second electrode is located on the same side of the second type semiconductor pattern as the first type semiconductor pattern and connects the second type semiconductor pattern. The protective layer is located on an opposite side of the second type semiconductor pattern from the first type semiconductor pattern, and a difference between a refractive index of the protective layer and a refractive index of the second type semiconductor pattern is less than 1.8. Further, a light emitting module including the light emitting element, a display device including the light emitting element, and a manufacturing method of the display device are also proposed.

Description

TECHNICAL FIELD

[0001] The present application relates to a light emitting element, a light emitting component comprising the same, a display device, and a manufacturing method of the display device. BACKGROUND

[0002] Micro-LEDs are suitable for constructing pixel structures of micro-LED display devices due to their low power consumption, high brightness, high resolution, and high color saturation. Since the size of micro-LEDs is extremely small, the current method for manufacturing micro-LED display devices is to use a mass transfer technique, i.e., to use a micro-electromechanical array technique to pick and place a large number of micro-LED dies on a driving backplane with pixel circuits.

[0003] In order to be able to perform mass transfer, the light emitting element must be in a suspended state. Currently, the main tether used to suspend the light emitting element is silicon oxide (SiOx), which has a relatively low fracture strength. However, the tether is also formed on the surface of the light emitting element. Since the refractive index of silicon oxide is relatively low compared to the semiconductor layer of the light emitting element, the light emitted by the light emitting element is prone to total reflection, resulting in a decrease in the light extraction efficiency (LEE) of the light emitting element. SUMMARY

[0004] The present application provides a light emitting element with improved light extraction efficiency.

[0005] The present application provides a light emitting component with improved light extraction efficiency.

[0006] The present application provides a display device with improved light extraction efficiency.

[0007] The present application provides a manufacturing method of a display device, which can provide a display device with improved light extraction efficiency.

[0008] One embodiment of the present application provides a light emitting element, comprising: a first type semiconductor pattern; a second type semiconductor pattern, overlapping the first type semiconductor pattern and located on a first side of the first type semiconductor pattern; a light emitting pattern, located between the first type semiconductor pattern and the second type semiconductor pattern; a first electrode, located on a second side of the first type semiconductor pattern, the second side being opposite to the first side, and the first electrode being connected to the first type semiconductor pattern; a second electrode, located on the same side of the second type semiconductor pattern as the first type semiconductor pattern, and connected to the second type semiconductor pattern; and a protective layer, located on the opposite side of the second type semiconductor pattern to the first type semiconductor pattern, and the refractive index difference between the protective layer and the second type semiconductor pattern being less than 1.8.

[0009] In one embodiment of the present application, the refractive index of the protective layer is greater than 1.46.

[0010] In one embodiment of the present application, the protective layer comprises silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, hafnium dioxide, zirconium dioxide, diamond-like carbon or amorphous carbon.

[0011] In one embodiment of the present application, the second type semiconductor pattern comprises a P-type semiconductor material.

[0012] In one embodiment of the present application, the thickness of the second type semiconductor pattern is between 1 μm and 3 μm.

[0013] In one embodiment of the present application, the thickness of the first type semiconductor pattern is between 0.1 μm and 1 μm.

[0014] One embodiment of the present application provides a light emitting assembly, comprising: a carrier plate; a plurality of support members located on the carrier plate; and the light emitting element as described above, suspended between the plurality of support members by a tether.

[0015] In one embodiment of the present application, the tether extends to the sidewalls of the second type semiconductor pattern, the light emitting pattern and the first type semiconductor pattern, and is connected to the support members.

[0016] In one embodiment of the present application, the tether further extends to the opposite side of the first type semiconductor pattern and the second type semiconductor pattern to the protective layer, and the first electrode and the second electrode are connected to the first type semiconductor pattern and the second type semiconductor pattern, respectively, through a first via in the tether.

[0017] In one embodiment of the present application, the material of the tether is different from the material of the protective layer.

[0018] In one embodiment of the present application, the refractive index of the protective layer is greater than the refractive index of the tether.

[0019] In one embodiment of the present application, the tethering member includes silicon oxide.

[0020] In one embodiment of the present application, the light emitting component further includes a support layer between the support member, the light emitting element, and the carrier plate.

[0021] In one embodiment of the present application, the display device includes a circuit substrate, and the light emitting element is on the circuit substrate and electrically connected to the circuit substrate.

[0022] In one embodiment of the present application, the circuit substrate further includes a first contact pad electrically connected to the first electrode and a second contact pad electrically connected to the second electrode.

[0023] In one embodiment of the present application, the circuit substrate further includes a switching element electrically connected to the first contact pad or the second contact pad.

[0024] In one embodiment of the present application, a method for manufacturing a display device includes providing a growth substrate, forming a multi-layer semiconductor layer on the growth substrate, forming a first sacrificial layer on the multi-layer semiconductor layer, forming an intermediate substrate on the first sacrificial layer, removing the growth substrate, patterning the multi-layer semiconductor layer to form a semiconductor stack, forming a tethering member on the semiconductor stack and the intermediate substrate, the tethering member having a plurality of first through holes exposing the semiconductor stack, forming a first electrode and a second electrode in the plurality of first through holes, respectively, forming a plurality of support members on the tethering member, the support members not overlapping the semiconductor stack, forming a carrier plate on the plurality of support members and the semiconductor stack, removing the intermediate substrate, removing part of the first sacrificial layer to expose the semiconductor stack, and forming a protective layer on the semiconductor stack.

[0025] In one embodiment of the present application, forming the first sacrificial layer on the multi-layer semiconductor layer includes roughening a surface of the multi-layer semiconductor layer, and forming the first sacrificial layer on the roughened surface of the multi-layer semiconductor layer.

[0026] In one embodiment of the present application, forming the intermediate substrate on the first sacrificial layer includes forming a bonding layer on the first sacrificial layer, and forming the intermediate substrate on the bonding layer.

[0027] In one embodiment of the present application, forming the plurality of support members on the tethering member includes forming a second sacrificial layer on the semiconductor stack and the tethering member, the second sacrificial layer having a plurality of second through holes not overlapping the semiconductor stack and exposing the tethering member, and forming the support members in the plurality of second through holes.

[0028] In order to make the features and advantages of the present application more apparent, specific embodiments will be described below with reference to the accompanying drawings, and the following detailed description is given to enable those skilled in the art to carry out the present application without undue effort. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figures 1 to 11 is a partial sectional schematic view of a step flow of a manufacturing method of a display device 10 according to an embodiment of the present application.

[0030] In the drawings:

[0031] 10: display device

[0032] 10A: light emitting component

[0033] 110: circuit substrate

[0034] 112: back plate

[0035] 114: drive circuit layer

[0036] 120: light emitting element

[0037] BL: bonding layer

[0038] CP: protective layer

[0039] CS: carrier substrate

[0040] E1: first electrode

[0041] E2: second electrode

[0042] EL: light emitting layer

[0043] EP: light emitting pattern

[0044] F1, Fs: surface

[0045] GS: growth substrate

[0046] I1: buffer layer

[0047] I2: gate insulating layer

[0048] I3: interlayer insulating layer

[0049] I4: insulating layer

[0050] IS: intermediate substrate

[0051] PC: support

[0052] PD1, PD2: pad

[0053] PL: support layer

[0054] PR: patterned photoresist layer

[0055] RS: surface

[0056] S1: first side

[0057] S2: second side

[0058] SF1: first sacrificial layer

[0059] SF2: second sacrificial layer

[0060] SL1: first type semiconductor layer

[0061] SL2: second type semiconductor layer

[0062] SP1: first type semiconductor pattern

[0063] SP2: second type semiconductor pattern

[0064] SS: semiconductor stack

[0065] T: switching element

[0066] TC: semiconductor layer

[0067] TD: drain

[0068] TG: gate

[0069] TR: tie

[0070] TS: source

[0071] t1, t2: thickness

[0072] V11, V12: first via

[0073] V2: second via

[0074] VA1, VA2, VA3: via

[0075] VL1, VL2: power line

[0076] W1, W2, We: sidewall DETAILED DESCRIPTION

[0077] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity. Like reference numerals can be used to denote like elements throughout the specification and drawings. It should be understood that when a layer, film, region, or substrate is referred to as being "on" or "connected to" another layer, film, region, or substrate, it can be directly on or connected to the other layer, film, region, or substrate or intervening layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" can mean physically and / or electrically connected. Also, "electrically connected" or "coupled" can be two elements exist other elements.

[0078] It should be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element,”“component,”“region,”“layer” or“section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms, including“at least one,” unless the content clearly indicates otherwise. As used herein, the term“and / or” includes any and all combinations of one or more of the associated listed items. It will be understood by those within the art that, in some aspects of this disclosure, terms such as“including,”“comprising,”“consisting of” and the like are to be construed in an inclusive fashion, i.e., there is no exclusion of additional elements or steps.

[0080] In addition, relative terms such as“lower” or“bottom” and“upper” or“top” can be used herein to describe one element’s or another’s relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the“lower” side of other elements would then be oriented on the“upper” sides of the other elements. The exemplary term“lower” can therefore

[0081] “about,”“approximately,” or“substantially” as used herein include the stated value and average values falling within an acceptable range of deviation determined by one of ordinary skill in the art to be within the scope of the particular value as the limit of precision. For example,“about” can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, “about,”“approximately,” or“substantially” as used herein can select a more acceptable range of deviation or standard deviation for optical properties, etching properties, or other properties, as can not apply one standard deviation to all properties.

[0082] The exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected to occur. Thus, embodiments described herein are not to be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can often have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

[0083] Figures 1 to 11 FIG. 1 is a partial cross-sectional schematic view of a step flow of a method of fabricating a display device 10 according to an embodiment of the present disclosure. Please refer to FIG. 1. Figure 1 In the step flow of the method of fabricating the display device 10, a growth substrate GS is provided. The growth substrate GS can be a sapphire (Sapphire) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, an indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or other suitable substrate for epitaxial process, but not limited thereto.

[0084] Next, in some embodiments, a release layer (not shown) can be formed on the surface of the growth substrate GS as needed. The release layer can facilitate the removal of the growth substrate GS later, and also facilitate the epitaxial process later. The material of the release layer can be aluminum nitride (AIN), for example.

[0085] Next, a blanket multi-layer semiconductor layer is formed on the growth substrate GS and the release layer (if any). For example, a first type semiconductor layer SL1 can be formed on the growth substrate GS and the release layer (if any), then a light emitting layer EL is formed on the first type semiconductor layer SL1, and then a second type semiconductor layer SL2 is formed on the light emitting layer EL. The first type semiconductor layer SL1 and the second type semiconductor layer SL2 can include a group II-VI material (e.g., zinc selenide (ZnSe)) or a group III-V material (e.g., gallium nitride (GaN), gallium phosphide (GaP), aluminum nitride (AIN), indium nitride (InN), indium gallium nitride (InGaN), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), or aluminum indium gallium phosphide (AlInGaP)). For example, in the present embodiment, the first type semiconductor layer SL1 is, for example, an N-type doped semiconductor layer, and the material of the N-type doped semiconductor layer is, for example, N-type aluminum indium gallium phosphide (AlInGaP), and the second type semiconductor layer SL2 includes, for example, a P-type doped semiconductor material, and the P-type doped semiconductor material is, for example, P-type gallium phosphide (GaP), but the present application is not limited thereto. In the present embodiment, the structure of the light emitting layer EL is, for example, a multiple quantum well structure (MQW) including a plurality of layers of indium gallium phosphide (InGaP) and a plurality of layers of gallium phosphide (GaP) alternately stacked, and by designing the proportion of indium or gallium in the light emitting layer EL, the light emitting wavelength range of the light emitting layer EL can be adjusted, but the present application is not limited thereto.

[0086] Next, in some embodiments, the surface RS of the second type semiconductor layer SL2 can be surface treated as needed, for example, the surface RS of the second type semiconductor layer SL2 can be roughened to facilitate the subsequent adhesion of the film layer.

[0087] Next, please refer to Figure 2 , a first sacrificial layer SF1 is formed on the surface of the second type semiconductor layer SL2, and then an adhesive layer BL can be formed on the first sacrificial layer SF1 as needed, and then an intermediate substrate IS is formed on the adhesive layer BL and the first sacrificial layer SF1. In the present embodiment, the intermediate substrate IS can be attached to the adhesive layer BL, but the present application is not limited thereto.

[0088] The material of the first sacrificial layer SF1 can be a material that has etching selectivity with respect to silicon oxide (SiOx). For example, the first sacrificial layer SF1 can include metal, diamond-like carbon (DLC), or chemical-mechanical polishing resistant material, but the present application is not limited thereto. In some embodiments, the material of the adhesive layer BL can be silicon oxide (SiOx), but the present application is not limited thereto.

[0089] Next, please refer to Figure 3The growth substrate GS is removed, thereby exposing the first-type semiconductor layer SL1. The growth substrate GS can be removed by, for example, a heat treatment or a laser lift off process, but is not limited thereto.

[0090] Next, referring to FIG. 6, the first-type semiconductor layer SL1, the light-emitting layer EL, and the second-type semiconductor layer SL2 are patterned to form a first-type semiconductor pattern SP1, a light-emitting pattern EP, and a second-type semiconductor pattern SP2, which can constitute a semiconductor stack SS. In this embodiment, the first-type semiconductor pattern SP1 and the light-emitting pattern EP can partially overlap the second-type semiconductor pattern SP2, and expose a portion of the second-type semiconductor pattern SP2. Figure 4

[0091] Next, a tie layer TR is formed on the surface Fs of the first sacrificial layer SF1, the sidewall W2 of the second-type semiconductor pattern SP2, the sidewall We of the light-emitting pattern EP, the sidewall W1 of the first-type semiconductor pattern SP1, and the surface F1 of the first-type semiconductor pattern SP1, and the tie layer TR has first vias V11, V12 that respectively expose the first-type semiconductor pattern SP1 and the second-type semiconductor pattern SP2. In this way, the tie layer TR and the second-type semiconductor pattern SP2 can both adhere to the surface Fs of the first sacrificial layer SF1, so that the tie layer TR and the second-type semiconductor pattern SP2 face the surface Fs of the first sacrificial layer SF1 can be flush. Next, a first electrode E1 and a second electrode E2 are respectively formed in the first vias V11, V12.

[0092] In this embodiment, the tie layer TR is made of, for example, silicon oxide (SiOx), but is not limited thereto. The first electrode E1 and the second electrode E2 can be made of a metal with good conductivity, such as aluminum (Al), titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), chromium (Cr), or an alloy thereof, or a combination or stack of the above metals and / or alloys. For example, the first electrode E1 or the second electrode E2 can include a metal stack such as Ti / Au, Ti / Al / Ti / Au, or Cr / Al / Ti / Pt / Au.

[0093] Next, referring to FIG. 6, the first-type semiconductor layer SL1, the light-emitting layer EL, and the second-type semiconductor layer SL2 are patterned to form a first-type semiconductor pattern SP1, a light-emitting pattern EP, and a second-type semiconductor pattern SP2, which can constitute a semiconductor stack SS. In this embodiment, the first-type semiconductor pattern SP1 and the light-emitting pattern EP can partially overlap the second-type semiconductor pattern SP2, and expose a portion of the second-type semiconductor pattern SP2. Figure 5 ​In some embodiments, a second sacrificial layer SF2 can also be formed on the semiconductor stack SS, the first electrode E1, the second electrode E2, and the tether TR, and the second sacrificial layer SF2 can be formed with a plurality of second vias V2, each of which does not overlap the semiconductor stack SS in the orthographic projection of the interposer IS, and the second vias V2 can expose portions of the tether TR that are attached to the first sacrificial layer SF1. The second sacrificial layer SF2 can comprise an organic material, but is not limited thereto. In some embodiments, the second vias V2 can have an inverted trapezoidal shape with a wider top and a narrower bottom, but are not limited thereto.

[0094] Next, please refer to Figure 6 A support PC can be formed in each of the second vias V2. Since the second vias V2 can expose the tether TR, and the second vias V2 do not overlap the semiconductor stack SS, the support PC can be located on and connected to the tether TR, and the support PC does not overlap the semiconductor stack SS. In some embodiments, a support layer PL can also be formed on the support PC and the second sacrificial layer SF2, and the support layer PL can be in the same film layer as the support PC, in other words, the support layer PL can be integrally formed with the support PC, but is not limited thereto. In this way, it can be ensured that the support PC and the second sacrificial layer SF2 have a flat upper surface. In some embodiments, the support PC and / or the support layer PL can comprise a material with a certain rigidity, such as a metal. In some embodiments, the support PC and / or the support layer PL can also have a multi-layer structure.

[0095] Next, a carrier substrate CS can be formed on the support layer PL, the support PC, the second sacrificial layer SF2, the first electrode E1, the second electrode E2, and the semiconductor stack SS. For example, the carrier substrate CS can be attached to the surface of the support layer PL. Next, please refer to Figure 7 The interposer IS and the adhesive layer BL can be removed after the formation of the carrier substrate CS, for example, by laser ablation, heat treatment, and / or etching.

[0096] Next, please refer to Figure 8 The first sacrificial layer SF1 can be removed in portions to expose the semiconductor stack SS. For example, in the present embodiment, a patterned photoresist layer PR can be formed by a thin film deposition process and a lithography process, and then an etching process can be used to remove portions of the first sacrificial layer SF1 that are not shielded by the patterned photoresist layer PR, thereby exposing the second-type semiconductor pattern SP2 of the semiconductor stack SS.

[0097] Next, please refer to Figure 9A protective layer CP is formed on the semiconductor stack SS. For example, in this embodiment, the protective layer CP can be deposited using the patterned photoresist layer PR as a shield, such that the protective layer CP is formed on the surface of the second semiconductor pattern SP2 of the semiconductor stack SS. In some embodiments, the protective layer CP can also extend onto the surface of the tie TR. The material of the protective layer CP can include, but is not limited to, silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al203), titanium oxide (TiOx), hafnium dioxide (Hf02), zirconium dioxide (Zr02), diamond-like carbon (DLC), or amorphous carbon.

[0098] At this point, the light emitting element 120 is formed on the carrier substrate CS, and can include: the first semiconductor pattern SP1; the second semiconductor pattern SP2, which overlaps the first semiconductor pattern SP1 and is located on the first side S1 of the first semiconductor pattern; the light emitting pattern EP, which is located between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, wherein the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the light emitting pattern EP form the semiconductor stack SS; the first electrode E1, which is located on the second side S2 of the first semiconductor pattern SP1 opposite the first side S1 and is connected to the first semiconductor pattern SP1; the second electrode E2, which is located on the same side of the second semiconductor pattern SP2 as the first semiconductor pattern SP1 and is connected to the second semiconductor pattern SP2; and the protective layer CP, which is located on the side of the second semiconductor pattern SP2 opposite the first semiconductor pattern SP1, and the refractive index difference between the protective layer CP and the second semiconductor pattern SP2 is less than 1.8.

[0099] In some embodiments, the thickness t1 of the first semiconductor pattern SP1 can be between 0.1 μm and 1 μm, and the thickness t2 of the second semiconductor pattern SP2 can be between 1 μm and 3 μm. By adjusting the thickness t1 of the first semiconductor pattern SP1 and the thickness t2 of the second semiconductor pattern SP2 to be within the above ranges, constructive interference of the light waves emitted by the light emitting element 120 can be achieved, thereby improving the light extraction efficiency (LEE) of the light emitting element 120. In addition, by making the refractive index difference between the protective layer CP and the second semiconductor pattern SP2 less than 1.8, the proportion of light emitted by the light emitting element 120 that is totally reflected can be reduced, thereby improving the light extraction efficiency (LEE) of the light emitting element 120.

[0100] In the embodiment, the first electrode E1 and the second electrode E2 of the light emitting element 120 are located on the same side of the semiconductor stack SS, and the light emitting element 120 can be a flip chip light emitting diode. In some embodiments, the second type semiconductor pattern SP2 of the semiconductor stack SS of the light emitting element 120 can be located on the light emitting surface, and the second type semiconductor pattern SP2 can include a P-type semiconductor material. In some embodiments, the light emitting element 120 can be a red light emitting diode with high efficiency.

[0101] Next, referring to Figure 10 After the protective layer CP is formed, the patterned photoresist layer PR can also be removed to expose the first sacrificial layer SF1. Then, the first sacrificial layer SF1 can also be removed to expose the tether TR. Then, after the protective layer CP is formed and the patterned photoresist layer PR and the first sacrificial layer SF1 are removed, the second sacrificial layer SF2 can also be removed. For example, the second sacrificial layer SF2 can be removed by exposure and development. At this point, the light emitting assembly 10A according to an embodiment of the present application is completed, and the light emitting assembly 10A can include a carrier substrate CS, a plurality of support pieces PC located on the carrier substrate CS, a light emitting element 120 suspended between the support pieces PC by the tether TR, and a support layer PL located between the plurality of support pieces PC and the light emitting element 120 and the carrier substrate CS. By making the refractive index difference between the protective layer CP of the light emitting element 120 and the second type semiconductor pattern SP2 of the light emitting assembly 10A less than 1.8, the proportion of light emitted by the light emitting element 120 that is totally reflected can be reduced, thereby improving the light extraction efficiency of the light emitting assembly 10A.

[0102] Next, referring to Figure 4 and Figure 10 In some embodiments, the tether TR extends on the sidewall W1 of the first type semiconductor pattern SP1, the sidewall We of the light emitting pattern EP, the sidewall W2 of the second type semiconductor pattern SP2, and the support piece PC, and the tether TR connects the support pieces PC so that the light emitting element 120 can be suspended between the support pieces PC. In addition, the tether TR can also extend on the side opposite to the protective layer CP of the first type semiconductor pattern SP1 and the second type semiconductor pattern SP2, and the first electrode E1 and the second electrode E2 are connected to the first type semiconductor pattern SP1 and the second type semiconductor pattern SP2, respectively, through the first via V11, V12 in the tether TR.

[0103] In some embodiments, the material of the tie element TR and the material of the protective layer CP may be different, and the refractive index of the protective layer CP may be greater than the refractive index of the tie element TR. In some embodiments, the tie element TR may include silicon oxide to facilitate mass transfer processes. In some embodiments, the refractive index of the protective layer CP may be greater than the refractive index of silicon oxide; for example, the refractive index of the protective layer CP may be greater than about 1.46. In some embodiments, the protective layer CP may include silicon oxynitride (SiON) with a refractive index of about 1.6.

[0104] In some embodiments, the protective layer CP may include HfO2 with a refractive index between about 1.85 and 2.1.

[0105] In some embodiments, the protective layer CP may include ZrO2 with a refractive index between about 1.9 and 2.15.

[0106] In some embodiments, the protective layer CP may comprise diamond-like carbon with a refractive index of about 2.4. In some embodiments, the protective layer CP may comprise amorphous carbon with a refractive index between about 1.5 and 3.1.

[0107] Next, please refer to Figure 11 After removing the second sacrificial layer SF2, a circuit board 110 can be further provided, wherein the circuit board 110 may include pads PD1 and PD2 located on its surface. Then, a mass transfer process can be performed, that is, transferring... Figure 10 After the light-emitting element 120 in the light-emitting component 10A is removed, it is transferred to the circuit board 110. For example, the first electrode E1 of the light-emitting element 120 is placed on the pad PD1, and the second electrode E2 of the light-emitting element 120 is placed on the pad PD2, such that the first electrode E1 is located between the semiconductor stack SS and the pad PD1 of the circuit board 110, and the second electrode E2 is located between the semiconductor stack SS and the pad PD2 of the circuit board 110. Afterwards, the first electrode E1 and the second electrode E2 of the light-emitting element 120 can be electrically connected to the pads PD1 and PD2 respectively by, for example, heat treatment. Thus, the display device 10 according to an embodiment of the present invention is completed, and the display device 10 may include: a circuit board 110; and a light-emitting element 120, located on the circuit board 110 and electrically connected to the circuit board 110. Since the refractive index difference between the protective layer CP of the light-emitting element 120 of the display device 10 and the second type semiconductor pattern SP2 is less than 1.8, the light emitted by the light-emitting element 120 is less likely to undergo total internal reflection, thus improving the light extraction efficiency of the display device 10.

[0108] For example, the circuit substrate 110 can include a base plate 112 and a drive circuit layer 114. The base plate 112 of the circuit substrate 110 can be a transparent substrate, an opaque substrate, a flexible substrate, or an inflexible substrate, and can be made of a quartz substrate, a glass substrate, a polymer substrate, or other suitable material. The drive circuit layer 114 can include elements or lines required by the display device 10, such as driving elements, switching elements, storage capacitors, power supply lines, driving signal lines, timing signal lines, current compensation lines, detection signal lines, and the like. The drive circuit layer 114 can be formed on the base plate 112 by using thin film deposition processes, photolithography processes, and etching processes. The drive circuit layer 114 can include at least one insulating layer and at least one conductive layer, and can include more insulating layers and conductive layers as needed.

[0109] In some embodiments, the drive circuit layer 114 of the circuit substrate 110 can further include an array of switching elements, where the array of switching elements includes a plurality of switching elements T arranged in an array, and the switching elements T can be electrically connected to the light emitting elements 120. In detail, the drive circuit layer 114 can include, for example, the switching elements T, power supply lines VL1, VL2, contact pads PD1, PD2, a buffer layer I1, a gate insulating layer I2, an interlayer insulating layer I3, and an insulating layer I4. The switching element T is composed of a semiconductor layer TC, a gate TG, a source TS, and a drain TD. An area of the semiconductor layer TC overlapping the gate TG can be regarded as a channel region of the switching element T. The buffer layer I1 is located between the base plate 112 and the semiconductor layer TC, and is used to prevent impurities in the base plate 112 from moving into the semiconductor layer TC and to enhance adhesion between the semiconductor layer TC and the base plate 112. The gate insulating layer I2 is located between the gate TG and the semiconductor layer TC. The interlayer insulating layer I3 is disposed between the source TS, the drain TD, and the power supply line VL1 and the gate TG and the power supply line VL2. The insulating layer I4 is disposed between the source TS, the drain TD, and the power supply line VL1 and the contact pads PD1, PD2. The contact pads PD1, PD2 can be electrically connected to the power supply line VL1 and the drain TD through vias VA1, VA2 in the insulating layer I4, respectively, and the source TS can be electrically connected to the power supply line VL2 through a via VA3 in the insulating layer I3. When the gate TG receives a signal from, for example, a driving element to turn on the switching element T, a signal received by the source TS from the power supply line VL2 can be transmitted to the second electrode E2 of the light emitting element 120. In some embodiments, the contact pad PD1 can be electrically connected to the switching element T, and the contact pad PD2 can be electrically connected to the power supply line VL1.

[0110] The material of the semiconductor layer TC can include a silicon semiconductor material (e.g., polysilicon, amorphous silicon, etc.), an oxide semiconductor material, an organic semiconductor material, but is not limited thereto. The material of the gate TG, the source TS, the drain TD, the power lines VL1, VL2, and the pads PD1, PD2 can include a metal having good conductivity, such as aluminum, molybdenum, titanium, copper, an alloy of the above metals, or a stack of the above metals and alloys, but is not limited thereto. For example, the pad PD1 can include a stack of a titanium layer, an aluminum layer, and a titanium layer, or a stack of a molybdenum layer, an aluminum layer, and a molybdenum layer, but is not limited thereto.

[0111] The material of the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layer I4 can include a transparent inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a stack of the above materials, but is not limited thereto. In some embodiments, the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layer I4 can also have a single-layer structure or a multi-layer structure, respectively, such as a stack of any two or more of the above insulating materials, which can be combined and varied as needed.

[0112] In some embodiments, the first electrode E1 and the second electrode E2 can also be electrically connected to the pads PD1, PD2, respectively, through a connecting material, such as conductive paste (e.g., silver paste), solder, metal, or other materials. In some embodiments, other conductive materials or conductive paste can also be included between the connecting material and the pads PD1, PD2, the first electrode E1, or the second electrode E2.

[0113] In summary, the light emitting element, the light emitting component, and the display device of the present application can reduce the proportion of light emitted by the light emitting element that is totally reflected by making the difference between the refractive indices of the protective layer and the second-type semiconductor pattern less than about 1.8, thereby improving the light extraction efficiency of the light emitting element, the light emitting component, and the display device.

[0114] Although the present application has been disclosed with reference to the embodiments above, it is not intended to limit the present application, and anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of the present application should be defined by the appended claims.

Claims

1. A light emitting assembly, characterized by The display device comprises a light emitting component, a support layer, and a carrier plate. The light emitting component comprises a carrier plate, a plurality of supports, and a light emitting element suspended between the supports by a tether. The light emitting element further comprises a first type semiconductor pattern, a second type semiconductor pattern overlapping the first type semiconductor pattern and located on a first side of the first type semiconductor pattern, a light emitting pattern between the first type semiconductor pattern and the second type semiconductor pattern, a first electrode on a second side of the first type semiconductor pattern opposite the first side and connected to the first type semiconductor pattern, a second electrode on the same side of the second type semiconductor pattern as the first type semiconductor pattern and connected to the second type semiconductor pattern, and a protective layer on a side of the second type semiconductor pattern opposite the first type semiconductor pattern and having a refractive index difference with the second type semiconductor pattern less than 1.

8. The tether extends from the second type semiconductor pattern, the light emitting pattern, and a sidewall of the first type semiconductor pattern and is connected to the supports. The supports do not overlap the first type semiconductor pattern, the light emitting pattern, and the second type semiconductor pattern. The light emitting component further comprises a support layer between the supports and the light emitting element and the carrier plate and having a gap between the support layer and the light emitting element. The tether further extends from the first type semiconductor pattern and the second type semiconductor pattern on a side opposite the protective layer, and the first electrode and the second electrode are connected to the first type semiconductor pattern and the second type semiconductor pattern, respectively, through first through holes in the tether. The tether has a material different from a material of the protective layer. The tether comprises silicon oxide. The display device comprises a light emitting component as claimed in any one of claims 1 to 4, and the manufacturing method comprises: providing a growth substrate; forming a multi-layer semiconductor layer on the growth substrate; forming a first sacrificial layer on the multi-layer semiconductor layer; forming an intermediate substrate on the first sacrificial layer; 2. The light emitting assembly of claim 1, wherein, removing the growth substrate; 3. The light emitting assembly of claim 1, wherein, patterning the multi-layer semiconductor layer to form a semiconductor stack; 4. The light emitting assembly of claim 1, wherein, forming a tether on the semiconductor stack and the intermediate substrate and having a plurality of first through holes exposing the semiconductor stack; 5. A method for manufacturing a display device, comprising: forming a first electrode and a second electrode in the first through holes, respectively; forming a plurality of supports on the tether and not overlapping the semiconductor stack; forming a carrier plate on the plurality of supports and the semiconductor stack; removing the intermediate substrate; removing part of the first sacrificial layer to expose the semiconductor stack; and forming a protective layer on the semiconductor stack; wherein forming a plurality of supports on the tether comprises: ​ ​ ​ ​ ​ ​ ​ ​ forming a second sacrificial layer on the semiconductor stack and the tether, and the second sacrificial layer has a plurality of second vias that do not overlap the semiconductor stack and expose the tether; and forming the support in the second vias.

6. The method for manufacturing a display device according to claim 5, wherein wherein the forming a first sacrificial layer on the multilayer semiconductor layer comprises: roughening a surface of the multilayer semiconductor layer; and forming the first sacrificial layer on the roughened surface of the multilayer semiconductor layer.

7. The method for manufacturing a display device according to claim 5, wherein wherein the forming an intervening substrate on the first sacrificial layer comprises: forming an adhesion layer on the first sacrificial layer; and forming the intervening substrate on the adhesion layer. wherein the forming an intervening substrate on the first sacrificial layer comprises: forming an adhesion layer on the first sacrificial layer; and forming the intervening substrate on the adhesion layer.

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