Transistor, electrically controlled drum and printer

Abstract

The disclosure provides a transistor, an electrically controlled drum and a printer. In the transistor, an active layer comprises a first heavily doped region, a first high-resistance region, a channel region overlapped with a gate, a second high-resistance region and a second heavily doped region arranged in sequence in a direction from a first source-drain electrode to a second source-drain electrode, the first heavily doped region is in electrical contact with the first source-drain electrode, the second heavily doped region is in electrical contact with the second source-drain electrode, and the first high-resistance region and the second high-resistance region are both not overlapped with a projection of the gate on a substrate. The high-voltage resistance of the transistor is improved, which is helpful to the performance stability of the electrically controlled drum.

Description

Technical Field

[0001] This disclosure pertains to the field of printing technology, specifically relating to a transistor, an electronically controlled drum, and a printer. Background Technology

[0002] This section is intended to provide background or context for the embodiments set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] A traditional laser printer's drum unit is a cylinder coated with a photosensitive material (such as selenium). Regardless of whether the photosensitive material actually contains selenium, it is commonly referred to as a drum unit. When the photosensitive material is exposed to a laser, its electrical resistance changes. The areas of the drum unit exposed to the laser have lower resistance, and the charge accumulated in those areas disappears. The areas of the drum unit not exposed to the laser retain their charge and can attract toner. This creates a toner pattern on the drum surface, which is then transferred to the paper. The laser components in laser printers are relatively expensive. Summary of the Invention

[0004] This disclosure provides a transistor, an electronically controlled drum, and a printer.

[0005] The present disclosure adopts the following technical solution: a transistor, the transistor comprising: a substrate, an active layer disposed on the substrate, a gate insulating layer disposed on the active layer away from the substrate, and a gate disposed on the gate insulating layer away from the substrate, the transistor further comprising: an interlayer insulating layer covering the gate, a first source drain and a second source drain located on the interlayer insulating layer away from the substrate and electrically contacting the active layer through a via;

[0006] The active layer includes a first heavily doped region, a first high-resistivity region, a channel region overlapping the gate, a second high-resistivity region, and a second heavily doped region sequentially disposed along the direction from the first source / drain to the second source / drain. The first heavily doped region is in electrical contact with the first source / drain, and the second heavily doped region is in electrical contact with the second source / drain. The orthographic projections of the first high-resistivity region and the second high-resistivity region on the substrate do not overlap with the orthographic projection of the gate on the substrate.

[0007] In some embodiments, the gate insulating layer and the gate are substantially flush, and the interlayer insulating layer further covers at least the first high-resistivity region and the second high-resistivity region.

[0008] In some embodiments, the first high-resistivity region includes a first intrinsic semiconductor region; the second high-resistivity region includes a second intrinsic semiconductor region.

[0009] In some embodiments, the first high-resistivity region includes a first lightly doped region; the second high-resistivity region includes a second lightly doped region.

[0010] In some embodiments, the first high-resistivity region includes a first lightly doped region and a first intrinsic semiconductor region sequentially disposed along the direction from the first heavily doped region to the channel region; the second high-resistivity region includes a second lightly doped region and a second intrinsic semiconductor region sequentially disposed along the direction from the second heavily doped region to the channel region.

[0011] In some embodiments, the gate includes: a first gate and a second gate disposed at a distance along the direction from the first source / drain to the second source / drain; the region in the active layer opposite to the gap between the first gate and the second gate includes: a third high-resistivity region.

[0012] In some embodiments, the gate insulating layer is vacated at the gap between the first gate and the second gate.

[0013] In some embodiments, the gate further includes a third gate located between the first gate and the second gate and spaced apart from the first gate and the second gate.

[0014] In some embodiments, the driving circuit layer further includes a passivation layer covering the first source drain and the second source drain, a planarization layer located on the side of the passivation layer away from the substrate, and the pixel electrode is electrically connected to one of the first source drain and the second source drain through a via penetrating the planarization layer and the passivation layer.

[0015] The present disclosure adopts the following technical solution: an electronically controlled drum, comprising: a substrate, a driving circuit layer disposed on the substrate, a plurality of pixel electrodes located on the side of the driving circuit layer away from the substrate and electrically connected to the driving circuit layer, and a charge transport layer covering the plurality of pixel electrodes, wherein the plurality of pixel electrodes are disposed at intervals from each other, and the driving circuit layer is used to control the charge distribution of the charge transport layer;

[0016] The driving circuit layer includes: transistors corresponding one-to-one with the pixel electrodes, wherein one of the first source-drain and the second source-drain of the transistors is electrically connected to the corresponding pixel electrode, and at least one of the transistors is the aforementioned transistor.

[0017] In some embodiments, the driving circuit layer further includes a passivation layer covering the first source drain and the second source drain, a planarization layer located on the side of the passivation layer away from the substrate, and the pixel electrode is electrically connected to one of the first source drain and the second source drain through a via penetrating the planarization layer and the passivation layer.

[0018] The present disclosure adopts the following technical solution: a printer, including the aforementioned electronically controlled drum. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of an electrically controlled drum according to an embodiment of the present disclosure.

[0020] Figure 2 This is a schematic diagram of the structure of an electrically controlled drum according to another embodiment of the present disclosure.

[0021] Figure 3 This is a schematic diagram of the structure of an electrically controlled drum according to another embodiment of the present disclosure.

[0022] Figure 4 This is a schematic diagram of the structure of an electrically controlled drum according to another embodiment of the present disclosure.

[0023] Figure 5 This is a schematic diagram of the structure of an electrically controlled drum according to another embodiment of the present disclosure.

[0024] Figure 6 This is a schematic flowchart of a printing method according to an embodiment of the present disclosure.

[0025] The reference numerals in the attached figures are as follows: 1. Substrate; 3. Pixel electrode; 4. Passivation layer; 5. Planarization layer; 6. Charge transport layer; 21. Active layer; 22. Gate insulating layer; 23. Gate; 23a. First gate; 23b. Second gate; 23c. Third gate; 24. Interlayer insulating layer; 25. First source / drain; 26. Second source / drain; 211. First heavily doped region; 212. First intrinsic semiconductor region; 213. Channel region; 214. Second intrinsic semiconductor region; 215. Second heavily doped region; 216. First lightly doped region; 217. Second lightly doped region; 218. Third intrinsic semiconductor region. Detailed Implementation

[0026] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0027] refer to Figures 1 to 5 The present disclosure provides an electrically controlled drum, including: a substrate 1, a driving circuit layer disposed on the substrate 1, a plurality of pixel electrodes 3 located on the side of the driving circuit layer away from the substrate 1 and electrically connected to the driving circuit layer, and a charge transport layer 6 covering the plurality of pixel electrodes 3, wherein the plurality of pixel electrodes 3 are disposed at intervals from each other, and the driving circuit layer is used to control the charge distribution of the charge transport layer 6.

[0028] The charge transport layer 6 can be charged with either positive or negative charges by a charging roller. Then, the driving circuit layer selectively conducts the charge to ground to a portion of the charge transport layer 6. Uncharged areas of the charge transport layer 6 do not attract toner, while charged areas attract toner, thereby transferring the pattern to be printed onto the surface of the charge transport layer 6.

[0029] The manufacturing process of this electronically controlled drum is simple and mature, and the structure of the drive circuit layer can refer to the structure of the back panel of existing flexible display panels.

[0030] The substrate 1 can be rigid or flexible. When the electronically controlled drum is fabricated on a flexible substrate 1, the substrate 1 of the electronically controlled drum can be made into a cylindrical shape.

[0031] The patterns of the charge accumulation region (accumulating positive or negative charge) and the non-charge accumulation region in the charge transport layer 6 are controlled by the drive circuit layer, eliminating the need for a laser source, reducing printer costs, and increasing printer lifespan.

[0032] In some embodiments, the material of the substrate 1 includes polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, or polyaryl compounds.

[0033] In some embodiments, charge transport layer 6 is an electron transport layer. In other embodiments, charge transport layer 6 is a hole transport layer.

[0034] In some embodiments, the driving circuit layer includes multiple parallel gate lines (not shown) and multiple parallel data lines (not shown). The extending direction of the gate lines is perpendicular to the extending direction of the data lines. The driving circuit layer also includes multiple transistors arranged in an array. The pixel electrodes 3 are arranged in an array, and each pixel electrode 3 is connected to a transistor. The gate 23 of the transistor is connected to a gate line, the first source / drain 25 of the transistor is connected to a data line electrode, and the second source / drain 26 of the transistor is connected to the corresponding pixel electrode 3.

[0035] Since the operating voltage of the printed drum is in the range of 600V to 800V, it is necessary to improve the voltage withstand capability of the transistor.

[0036] In view of this, the embodiments of this disclosure configure the active layer and the gate as follows: the active layer includes a first heavily doped region, a first high-resistivity region, a channel region overlapping with the gate, a second high-resistivity region, and a second heavily doped region sequentially disposed along the direction from the first source / drain to the second source / drain. The first heavily doped region is in electrical contact with the first source / drain, and the second heavily doped region is in electrical contact with the second source / drain. The orthogonal projections of the first high-resistivity region and the second high-resistivity region on the substrate do not overlap with the orthogonal projection of the gate on the substrate.

[0037] refer to Figure 1The driving circuit layer includes transistors corresponding to the pixel electrodes 3. The transistors include an active layer 21 disposed on the substrate 1, a gate insulating layer 22 disposed on the side of the active layer 21 away from the substrate, and a gate 23 disposed on the side of the gate insulating layer 22 away from the substrate. The transistors also include an interlayer insulating layer 24 covering the gate 23, a first source drain 25 and a second source drain 26 located on the side of the interlayer insulating layer 24 away from the substrate and electrically contacted with the active layer 21 through a via.

[0038] Specifically, the transistor can be an N-type transistor or a P-type transistor, and this disclosure does not limit it.

[0039] One of the first source / drain 25 and the second source / drain 26 is electrically connected to the corresponding pixel electrode 3; the other is connected, for example, to a data line.

[0040] The active layer 21 includes a first heavily doped region 211, a first intrinsic semiconductor region 212, a channel region 213 overlapping with the gate 23, a second intrinsic semiconductor region 214, and a second heavily doped region 215, which are sequentially disposed along the direction from the first source / drain 25 to the second source / drain 26. The first heavily doped region 211 is in electrical contact with the first source / drain 25, and the second heavily doped region 215 is in electrical contact with the second source / drain 26.

[0041] The channel region 213 can be an intrinsic semiconductor, an N-type doped semiconductor, or a P-type doped semiconductor; this disclosure does not limit it in this regard.

[0042] In some embodiments, the active layer 21 is made of polycrystalline silicon, amorphous silicon, or a transparent semiconductor oxide such as indium zinc oxide (IGZO).

[0043] In the following embodiments, the active layer 21 is made of low-temperature polycrystalline silicon, and the channel regions 213 are all intrinsic low-temperature polycrystalline silicon.

[0044] The first intrinsic semiconductor region 212 and the second intrinsic semiconductor region 214 do not overlap with the gate 23 when projected onto the substrate 1, and both are always in a high-resistivity state, thereby improving the voltage withstand capability of the transistor.

[0045] The following is Figure 1 The flowchart illustrates a method for preparing an electrically controlled drum.

[0046] The first step is to form an active layer 21 on substrate 1. Specifically, a low-temperature polysilicon (LTPS) layer is formed on substrate 1. The LPS layer is then subjected to laser crystallization. Photoresist is coated onto the LPS. The photoresist is exposed and developed. Dry etching is then performed to form the pattern of the active layer 21. The photoresist is then removed.

[0047] The second step is to deposit the gate insulating layer 22. The material of the gate insulating layer 22 is, for example, silicon nitride, silicon oxide, zirconium dioxide, hafnium dioxide, aluminum oxide, etc.

[0048] The third step involves depositing a first metal layer for forming the gate 23 using a sputtering process.

[0049] The fourth step involves patterning the gate insulating layer 22 and the first metal layer using the same photomask. Specifically, photoresist is coated onto the first metal layer. The photoresist is then exposed and developed. The first metal layer and the gate insulating layer 22 are then subjected to dry etching or wet etching. Subsequently, the photoresist is removed.

[0050] The fifth step involves heavily doping a portion of the active layer 21 to form a first heavily doped region 211 and a second heavily doped region 215. Specifically, photoresist is coated, exposed, and developed to expose the areas in the active layer 21 where the first heavily doped region 211 and the second heavily doped region 215 will be formed. The first heavily doped region 211 is separated from the channel region 213 by a first intrinsic semiconductor region 212, and the second heavily doped region 215 is separated from the channel region 213 by a second intrinsic semiconductor region 214. The doping concentration of the first heavily doped region 211 and the second heavily doped region 215 is, for example, 10⁻⁶. 15 cm -2 The first heavily doped region 211 and the second heavily doped region 215 are used to form ohmic contacts with the first source / drain 25 and the second source / drain 26.

[0051] Along the direction from the first source / drain 25 to the second source / drain 26, the dimensions of both the first intrinsic semiconductor region 212 and the second intrinsic semiconductor region 214 are greater than 1µm.

[0052] Step 6: Forming the interlayer insulating layer 24. The interlayer insulating layer 24 is, for example, a monolayer silicon oxide, a monolayer silicon nitride, or a composite layer structure of the two.

[0053] The seventh step involves forming the first source / drain electrode 25 and the second source / drain electrode 26. Specifically, this is achieved by sequentially depositing the second metal layer, coating with photoresist, exposing, developing, wet etching, and removing the photoresist.

[0054] Step 8: Passivation layer 4 and planarization layer 5 are formed sequentially. The material of passivation layer 4 is, for example, silicon nitride. The material of planarization layer 5 is, for example, organic resin. Vias are then formed that extend to the first source / drain 25 or to the second source / drain 26.

[0055] The ninth step is to form the pixel electrodes 3. Specifically, a third metal layer is deposited, followed by photoresist deposition, exposure, development, and etching to obtain multiple pixel electrodes 3 separated from each other. The material of the third metal layer is, for example, an aluminum alloy.

[0056] Step 10: Deposit charge transport layer 6.

[0057] In some embodiments, reference Figure 1 The gate insulating layer 22 and the gate 23 are basically flush, and the interlayer insulating layer 24 also covers at least the first intrinsic semiconductor region 212 and the second intrinsic semiconductor region 214.

[0058] Figure 2 The transistor shown is Figure 1 The differences in the transistors shown include: the active layer 21 includes a first heavily doped region 211, a first lightly doped region 216, a channel region 213 opposite to the gate 23, a second lightly doped region 217, and a second heavily doped region 215 arranged sequentially along the direction from the first source / drain 25 to the second source / drain 26. The first heavily doped region 211 is in electrical contact with the first source / drain 25, and the second heavily doped region 215 is in electrical contact with the second source / drain 26.

[0059] After doping the first heavily doped region 211 and the second heavily doped region 215, the photoresist is removed, followed by an ion implantation process. The ion concentrations of the first lightly doped region 216 and the second lightly doped region 217 are 10. 12 cm -2 Up to 10 13 cm -2 Within the range.

[0060] The first lightly doped region 216 and the second lightly doped region 217 do not overlap with the gate 23 when projected onto the substrate 1. They always exhibit a relatively high resistance state, thereby improving the voltage withstand capability of the transistor.

[0061] Figure 3 The transistor shown is Figure 1 The differences in the transistors shown include: the active layer 21 further includes a first lightly doped region 216 located between the first heavily doped region 211 and the first intrinsic semiconductor region 212 along the direction from the first source / drain 25 to the second source / drain 26, and a second lightly doped region 217 located between the second heavily doped region 215 and the second intrinsic semiconductor region 214.

[0062] Introducing a first lightly doped region 216 as a transition region between the first intrinsic semiconductor region 212 and the first heavily doped region 211, and introducing a second lightly doped region 217 as a transition region between the second intrinsic semiconductor region 214 and the second heavily doped region 215, can make the energy band change within the active layer 21 smoother, which is beneficial for reducing leakage current and improving breakdown resistance.

[0063] All three embodiments above introduce a high-resistivity region between the heavily doped channel region and the gate on the substrate. The high-resistivity region does not overlap with the gate's orthogonal projection on the substrate.

[0064] refer to Figure 4In some embodiments, the driving circuit layer includes transistors corresponding to the pixel electrodes 3. Each transistor includes an active layer 21 disposed on the substrate 1, a gate insulating layer 22 disposed on the side of the active layer 21 away from the substrate, and a first gate 23a and a second gate 23b disposed on the side of the gate insulating layer 22 away from the substrate. The first gate 23a and the second gate 23b are substantially flush with the boundary of the gate insulating layer 22. The transistor also includes an interlayer insulating layer 24 that at least covers the first gate 23a and the second gate 23b, and a first source drain 25 and a second source drain 26 located on the side of the interlayer insulating layer 24 away from the substrate and electrically contacting the active layer 21 through a via.

[0065] One of the first source / drain electrode 25 and the second source / drain electrode 26 is electrically connected to the corresponding pixel electrode 3.

[0066] The active layer 21 includes a first heavily doped region 211, a first lightly doped region 216, a first channel region 213 opposite to the first gate 23a, a third intrinsic semiconductor region 218, a second channel region 213 opposite to the second gate 23b, a second lightly doped region 217, and a second heavily doped region 215, which are sequentially arranged along the direction from the first source / drain 25 to the second source / drain 26. The first heavily doped region 211 is in electrical contact with the first source / drain 25 through a via penetrating the interlayer insulating layer 24, and the second heavily doped region 215 is in electrical contact with the second source / drain 26 through a via penetrating the interlayer insulating layer 24. The orthographic projections of the first lightly doped region 216, the third intrinsic semiconductor region 218, and the second lightly doped region 217 onto the substrate 1 do not overlap with the orthographic projections of the first gate 23a and the second gate 23b onto the substrate 1.

[0067] The third intrinsic semiconductor region 218 is a high-resistivity region. In other embodiments, the intrinsic semiconductor is low-resistivity and needs to be made into a high-resistivity state through a doping process.

[0068] In this embodiment, both the first channel region 213 and the second channel region 213 are intrinsic semiconductors. In other embodiments, the first channel region 213 and the second channel region 213 are N-type doped or P-type doped.

[0069] The voltage signals received by the first gate 23a and the second gate 23b are the same.

[0070] The first gate 23a and the second gate 23b can respectively adjust the carrier concentration of the first channel region 213 and the second channel region 213, thereby controlling the voltage distribution in the active layer 21, which is beneficial to enhancing the voltage resistance of the first gate 23a and the second gate 23b.

[0071] Figure 5 The illustrated embodiments and Figure 4The differences in the illustrated embodiment include: the transistor further includes a third gate 23c located between the first gate 23a and the second gate 23b and spaced apart from the first gate 23a and the second gate 23b; the gate insulating layer 22 further includes a section located between the third gate 23c and the active layer 21 and substantially flush with the third gate 23c.

[0072] The third gate 23c can receive the voltage that turns off the transistor, thus ensuring that the region in the active layer 21 opposite to the third gate 23c is always in a high-resistivity state. This region can absorb a larger voltage drop, which helps to improve the transistor's high-voltage withstand capability.

[0073] In some embodiments, the size of the third gate 23c is less than 2 μm along the direction from the first source / drain 25 to the second source / drain 26. If this size is too large, the transistor will be difficult to turn on.

[0074] In some embodiments, the driving circuit layer further includes a passivation layer 4 covering the first source drain 25 and the second source drain 26, a planarization layer 5 located on the side of the passivation layer 4 away from the substrate 1, and the pixel electrode 3 is electrically connected to one of the first source drain 25 and the second source drain 26 through a via penetrating the planarization layer 5 and the passivation layer 4.

[0075] Based on the same inventive concept, embodiments of this disclosure also provide an electrically controlled drum, including the aforementioned electrically controlled drum.

[0076] refer to Figure 6 The embodiments of this disclosure also provide a printing method for the aforementioned electronically controlled drum, comprising:

[0077] Step 101: Charge the pixel electrode 3 to a preset high-level voltage or a preset low-level voltage;

[0078] Step 102: Make the charge transport layer 6 carry charge;

[0079] Step 103: Connect at least a portion of the pixel electrode 3 to ground to discharge the charge in at least a portion of the charge transport layer 6, and then allow the charge retention region in the charge transport layer 6 to adsorb toner.

[0080] by Figure 1 The following explanation uses the electrically controlled drum as an example. Figure 1 The transistor shown is an N-type transistor.

[0081] In step 101, the voltage difference between the gate 23 and the first source-drain 25 is set to -5V, and the voltage difference between the second source-drain 26 and the first source-drain 25 is set to 600V to 800V. The transistor is in the off state.

[0082] In step 102, the charging roller causes the charge transport layer 6 to be filled with positive charge.

[0083] In step 103, the voltage difference between the gate 23 and the first source / drain 25 is set to 10V to turn on the transistor. Positive charges are then directed to ground in a localized region of the charge transport layer 6 corresponding to the pixel electrode 3 to which the transistor is connected.

[0084] In some embodiments, the charge transport layer 6 carries a charge via a charging roller.

[0085] Based on the same inventive concept, embodiments of this disclosure also provide a transistor, the transistor comprising: a substrate, an active layer disposed on the substrate, a gate insulating layer disposed on the active layer away from the substrate, and a gate disposed on the gate insulating layer away from the substrate; the transistor further comprising: an interlayer insulating layer covering the gate, a first source drain and a second source drain located on the interlayer insulating layer away from the substrate and electrically contacting the active layer through a via;

[0086] The active layer includes a first heavily doped region, a first high-resistivity region, a channel region overlapping the gate, a second high-resistivity region, and a second heavily doped region sequentially disposed along the direction from the first source / drain to the second source / drain. The first heavily doped region is in electrical contact with the first source / drain, and the second heavily doped region is in electrical contact with the second source / drain. The orthographic projections of the first high-resistivity region and the second high-resistivity region on the substrate do not overlap with the orthographic projection of the gate on the substrate.

[0087] The transistor's voltage withstand capability has been improved, making it suitable for use in electrically controlled drums or other devices. The detailed structure of the transistor can be found in the foregoing embodiments and will not be repeated here.

[0088] The various embodiments in this disclosure are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0089] The scope of protection of this disclosure is not limited to the embodiments described above. Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its scope and spirit. If such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, then the intent of this disclosure also includes such modifications and variations.

Claims

1. A transistor, characterized in that, The transistor includes: a substrate, an active layer disposed on the substrate, a gate insulating layer disposed on the active layer away from the substrate, and a gate disposed on the gate insulating layer away from the substrate. The transistor further includes: an interlayer insulating layer covering the gate, a first source drain and a second source drain located on the interlayer insulating layer away from the substrate and electrically contacted with the active layer through a via. The active layer includes a first heavily doped region, a first high-resistivity region, a channel region overlapping the gate, a second high-resistivity region, and a second heavily doped region sequentially disposed along the direction from the first source / drain to the second source / drain. The first heavily doped region is in electrical contact with the first source / drain, and the second heavily doped region is in electrical contact with the second source / drain. The orthographic projections of the first high-resistivity region and the second high-resistivity region on the substrate do not overlap with the orthographic projection of the gate on the substrate. The first high-resistivity region includes a first lightly doped region and a first intrinsic semiconductor region sequentially arranged along the direction from the first heavily doped region to the channel region; the second high-resistivity region includes a second lightly doped region and a second intrinsic semiconductor region sequentially arranged along the direction from the second heavily doped region to the channel region.

2. The transistor according to claim 1, characterized in that, The gate insulating layer and the gate are substantially flush, and the interlayer insulating layer also covers at least the first high-resistivity region and the second high-resistivity region.

3. The transistor according to claim 1, characterized in that, The first high-resistivity region includes a first intrinsic semiconductor region; the second high-resistivity region includes a second intrinsic semiconductor region.

4. The transistor according to claim 1, characterized in that, The first high-resistivity region includes a first lightly doped region; the second high-resistivity region includes a second lightly doped region.

5. The transistor according to claim 1, characterized in that, The gate includes: a first gate and a second gate spaced apart along the direction from the first source / drain to the second source / drain; the region in the active layer opposite to the gap between the first gate and the second gate includes: a third high-resistivity region.

6. The transistor according to claim 5, characterized in that, The gate insulating layer is vacated at the gap between the first gate and the second gate.

7. The transistor according to claim 5, characterized in that, The gate further includes a third gate located between the first gate and the second gate and spaced apart from the first gate and the second gate.

8. An electrically controlled drum, characterized in that, include: A substrate, a driving circuit layer disposed on the substrate, a plurality of pixel electrodes located on the side of the driving circuit layer away from the substrate and electrically connected to the driving circuit layer, and a charge transport layer covering the plurality of pixel electrodes, wherein the plurality of pixel electrodes are spaced apart from each other, and the driving circuit layer is used to control the charge distribution of the charge transport layer; The driving circuit layer includes: transistors corresponding one-to-one with the pixel electrodes, wherein one of the first source-drain and the second source-drain of the transistors is electrically connected to the corresponding pixel electrode, wherein at least one of the transistors is a transistor according to any one of claims 1 to 7.

9. The electrically controlled drum according to claim 8, characterized in that, The driving circuit layer further includes a passivation layer covering the first source drain and the second source drain, and a planarization layer located on the side of the passivation layer away from the substrate. The pixel electrode is electrically connected to one of the first source drain and the second source drain through a via penetrating the planarization layer and the passivation layer.

10. A printer, characterized in that, Includes the electrically controlled drum according to claim 8 or 9.

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