A shield gate trench device and a manufacturing method thereof

Abstract

The present application provides a shield gate trench device and a manufacturing method thereof, relating to the field of semiconductor technology. First, an epitaxial wafer is provided, wherein the epitaxial wafer includes trenches. Then, a field plate oxide layer is grown based on the trenches. Next, the trenches are filled with polycrystalline until the filled polycrystalline is higher than the mesa of the epitaxial wafer. After that, the polycrystalline is planarized and then a part of the polycrystalline and the field plate oxide layer inside the trenches are etched to form a first polycrystalline layer in the trenches. Then, a buffer oxide layer is grown along the inner wall of the trenches, and a High K material layer is deposited on the surface of the buffer oxide layer. Then, polycrystalline filling is performed based on the surface of the High K material layer. Next, the polycrystalline in the trenches is etched, and the polycrystalline on the surface of the High K material layer is retained. Finally, the polycrystalline on the surface of the High K material layer is oxidized, and polycrystalline is deposited along the trenches to form a second polycrystalline layer. The present application has the advantages of small device stress and low capacitance effect.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a shielded gate trench device and a manufacturing method thereof. Background Art

[0002] SGT (Shielded Gate Transistor) MOSFETs are mainly used in medium-voltage and low-voltage fields. The device structure includes trenches, and polysilicon is deposited on both the bottom and the top of the trenches and isolated by a field plate oxide layer.

[0003] As an important index for evaluating shielded gate trench devices, the capacitance effect and stress of the field plate oxide layer are both very important. However, in the prior art, problems such as obvious capacitance effect and large stress generally exist. Summary of the Invention

[0004] The purpose of the present application is to provide a shielded gate trench device and a manufacturing method thereof to solve the problems such as obvious capacitance effect and large stress existing in shielded gate trench devices in the prior art.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a manufacturing method of a shielded gate trench device, and the method includes:

[0007] Providing an epitaxial wafer, wherein the epitaxial wafer includes trenches;

[0008] Growing a field plate oxide layer based on the trenches;

[0009] Performing polycrystalline filling on the trenches until the filled polycrystalline is higher than the mesa of the epitaxial wafer;

[0010] Etching a part of the polycrystalline and the field plate oxide layer in the trenches after polycrystalline planarization to form a first polycrystalline layer in the trenches;

[0011] Growing a buffer oxide layer along the inner wall of the trenches;

[0012] Depositing a High K material layer on the surface of the buffer oxide layer;

[0013] Performing polycrystalline filling based on the surface of the High K material layer;

[0014] Etching the polycrystalline in the trenches and retaining the polycrystalline on the surface of the High K material layer;

[0015] Oxidizing the polycrystalline on the surface of the High K material layer and depositing polycrystalline along the trenches to form a second polycrystalline layer.

[0016] Optionally, after the step of polycrystalline oxidation on the surface of the High K material layer, the method further includes:

[0017] Removing the High K material layer on the mesa of the epitaxial layer and the sidewalls of the trench, and retaining the High K material layer on the surface of the first polycrystalline layer;

[0018] Removing the buffer oxide layer on the sidewalls of the outer trench and the mesa of the epitaxial wafer and then growing a gate oxide layer;

[0019] Depositing polycrystalline based on the trench to form a second polycrystalline layer in the trench.

[0020] Optionally, the step of etching the polycrystalline in the trench and retaining the polycrystalline on the surface of the High K material layer includes:

[0021] Etching the polycrystalline in the trench and retaining 500 - 3000 angstroms of polycrystalline on the surface of the High K material layer.

[0022] Optionally, the step of depositing a High K material layer along the surface of the buffer oxide layer includes:

[0023] Depositing at least one material layer of silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and titanium oxide along the surface of the buffer oxide layer.

[0024] Optionally, the step of growing a buffer oxide layer along the inner wall of the trench includes:

[0025] Growing a 50 - 2000 angstrom buffer oxide layer along the inner wall of the trench.

[0026] Optionally, the step of providing an epitaxial wafer includes:

[0027] Providing a substrate;

[0028] Growing an epitaxial layer based on the surface of the substrate;

[0029] Fabricating a trench based on the epitaxial layer.

[0030] Optionally, the step of etching a part of the polycrystalline and the field plate oxide layer in the trench after polycrystalline planarization includes:

[0031] Removing the polycrystalline above the mesa of the epitaxial wafer to make the polycrystalline in the trench flush with the mesa of the epitaxial wafer;

[0032] Removing a part of the polycrystalline in the trench to leave a first polycrystalline layer in the trench;

[0033] Removing the field plate oxide layer on the mesa of the epitaxial wafer and part of the sidewalls of the trench, and retaining the field plate oxide layer connected to the first polycrystalline layer.

[0034] On the other hand, an embodiment of the present application further provides a shielded gate trench device, and the device includes:

[0035] An epitaxial wafer provided with trenches;

[0036] A first polycrystalline layer and a second polycrystalline layer located in the trenches, wherein the first polycrystalline layer is located below the second polycrystalline layer, and the first polycrystalline layer and the second polycrystalline layer are isolated by a buffer oxide layer, a High K material layer, and a polycrystalline oxide layer;

[0037] A first oxide layer located between the first polycrystalline layer and the epitaxial wafer;

[0038] A second oxide layer located between the second polycrystalline layer and the epitaxial wafer.

[0039] Optionally, the second oxide layer is a buffer oxide layer, and the device further includes a High K material layer located between the second polycrystalline layer and the buffer oxide layer; or

[0040] The second oxide layer is a gate oxide layer.

[0041] Optionally, the thickness of the polycrystalline oxide layer is 500 - 3000 angstroms.

[0042] Compared with the prior art, the present application has the following beneficial effects:

[0043] An embodiment of the present application provides a shielded gate trench device and a manufacturing method thereof. First, an epitaxial wafer is provided, where the epitaxial wafer includes trenches, then a field plate oxide layer is grown based on the trenches, and then the trenches are filled with polycrystals until the filled polycrystals are higher than the mesa of the epitaxial wafer. Then, after the polycrystals are planarized, a part of the polycrystals and the field plate oxide layer in the trenches are etched to form a first polycrystalline layer in the trenches. Then, a buffer oxide layer is grown along the inner wall of the trenches, a High K material layer is deposited on the surface of the buffer oxide layer, and then polycrystalline filling is performed based on the surface of the High K material layer. Then, the polycrystals in the trenches are etched, and the polycrystals on the surface of the High K material layer are retained. Finally, the polycrystals on the surface of the High K material layer are oxidized, and polycrystals are deposited along the trenches to form a second polycrystalline layer. On the one hand, since the present application uses a High K material layer to isolate the first polycrystalline layer and the second polycrystalline layer, it has a high breakdown field strength, can increase the device breakdown voltage, and at the same time, using the High K material layer can make the stress of the device small. On the other hand, using a multi-layer oxidation process can increase the spacing between the first polycrystalline layer and the second polycrystalline layer, effectively reduce the capacitance between the polycrystals, and improve the electrical performance of the device.

[0044] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specific embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. Description of the Drawings

[0045] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0046] Figure 1 It is a schematic cross-sectional view corresponding to silicon trench etching in the prior art.

[0047] Figure 2 It is a schematic cross-sectional view corresponding to the growth of the buffer oxide layer in the prior art.

[0048] Figure 3 It is a schematic cross-sectional view corresponding to SiN deposition in the prior art.

[0049] Figure 4 It is a schematic cross-sectional view corresponding to the deposition of the field plate oxide layer in the prior art.

[0050] Figure 5 It is a schematic cross-sectional view corresponding to polycrystalline filling in the prior art.

[0051] Figure 6 It is a schematic cross-sectional view corresponding to polycrystalline planarization in the prior art.

[0052] Figure 7 It is a schematic cross-sectional view corresponding to polycrystalline etching in the prior art.

[0053] Figure 8 It is a schematic cross-sectional view corresponding to the corrosion of the field plate oxide layer in the prior art.

[0054] Figure 9 It is a schematic cross-sectional view corresponding to polycrystalline oxidation in the prior art.

[0055] Figure 10 It is a schematic cross-sectional view corresponding to SiN corrosion in the prior art.

[0056] Figure 11 It is a schematic cross-sectional view corresponding to the corrosion of the buffer oxide layer in the prior art.

[0057] Figure 12 It is a schematic cross-sectional view corresponding to the growth of the gate oxide layer in the prior art.

[0058] Figure 13 It is a schematic cross-sectional view corresponding to polycrystalline filling in the prior art.

[0059] Figure 14 It is a schematic cross-sectional view corresponding to the growth of the field plate oxide layer in the prior art.

[0060] Figure 15 It is a schematic cross-sectional view corresponding to polycrystalline filling in the prior art.

[0061] Figure 16 It is a schematic cross-sectional view corresponding to polycrystalline planarization in the prior art.

[0062] Figure 17 It is a schematic cross-sectional view corresponding to polycrystalline etching in the prior art.

[0063] Figure 18 It is a schematic cross-sectional view corresponding to field plate oxide layer corrosion in the prior art.

[0064] Figure 19 It is a schematic cross-sectional view corresponding to gate oxide layer growth in the prior art.

[0065] Figure 20 It is a schematic cross-sectional view corresponding to polycrystalline filling in the prior art.

[0066] Figure 21 It is an exemplary flowchart of the method for manufacturing a shielded gate trench device provided by an embodiment of the present application.

[0067] Figure 22 It is a schematic cross-sectional view corresponding to S101 provided by an embodiment of the present application.

[0068] Figure 23 It is a schematic cross-sectional view corresponding to S102 provided by an embodiment of the present application.

[0069] Figure 24 It is a schematic cross-sectional view corresponding to S103 provided by an embodiment of the present application.

[0070] Figure 25 It is a schematic cross-sectional view corresponding to S1041 provided by an embodiment of the present application.

[0071] Figure 26 It is a schematic cross-sectional view corresponding to S1042 provided by an embodiment of the present application.

[0072] Figure 27 It is a schematic cross-sectional view corresponding to S1043 provided by an embodiment of the present application.

[0073] Figure 28 It is a schematic cross-sectional view corresponding to S105 provided by an embodiment of the present application.

[0074] Figure 29 It is a schematic cross-sectional view corresponding to S106 provided by an embodiment of the present application.

[0075] Figure 30 It is a schematic cross-sectional view corresponding to S107 provided by an embodiment of the present application.

[0076] Figure 31 This is a schematic cross-sectional view corresponding to S108 provided by an embodiment of the present application.

[0077] Figure 32 This is a schematic cross-sectional view corresponding to the polycrystalline oxidation on the surface of the High K material layer provided by an embodiment of the present application.

[0078] Figure 33 This is a schematic cross-sectional view corresponding to the deposition of polycrystals provided by an embodiment of the present application.

[0079] Figure 34 This is a schematic cross-sectional view corresponding to S110 provided by an embodiment of the present application.

[0080] Figure 35 This is a schematic cross-sectional view corresponding to the removal of the buffer oxide layer provided by an embodiment of the present application.

[0081] Figure 36 This is a schematic cross-sectional view corresponding to the growth of the gate oxide layer provided by an embodiment of the present application.

[0082] Figure 37 This is a schematic cross-sectional view corresponding to S112 provided by an embodiment of the present application. Detailed implementation manners

[0083] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Components of the embodiments of the present application generally described and illustrated in the drawings herein can be arranged and designed in a variety of different configurations.

[0084] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but is merely representative of selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0085] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, terms such as "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0086] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0087] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0088] As described in the background art, in the current preparation process of the shield gate trench device, the field plate oxide layer generally has obvious capacitance effect, large stress and other problems.

[0089] In the prior art, in the preparation process of the shield gate trench device, it generally includes the ONO method and the left-right structure SGT method. Among them, the ONO method process is generally as follows:

[0090] 1. Silicon trench etching. Generally, a patterned mask layer is used for etching. The etched image is as Figure 1 shown.

[0091] 2. Buffer oxide layer growth. Generally, the buffer oxide layer is grown by sampling the surface of the oxide trench and the mesa of the epitaxial wafer. The structure is as Figure 2 shown.

[0092] 3. SiN deposition. Among them, a thin layer of SiN is deposited along the surface of the trench and the mesa of the epitaxial wafer. The structure is as Figure 3 shown.

[0093] 4. Field plate oxide layer deposition. The field plate oxide layer generally uses SiO 2 . And the buffer oxide layer, the SiN layer and the field plate oxide layer form the ONO structure. The structure is as Figure 4 shown.

[0094] 5. Polycrystalline filling. The polycrystalline referred to in this application means polysilicon. The trench is filled with polycrystalline. In order to ensure that the trench is filled with polycrystalline, the height of the filled polycrystalline needs to be higher than the mesa of the epitaxial wafer. The structure is as Figure 5 shown.

[0095] 6. Polycrystalline planarization. The polycrystalline on the surface layer of the epitaxial wafer is removed to make the height of the polycrystalline flush with the surface of the epitaxial wafer. The structure is as Figure 6 shown.

[0096] 7. Polycrystalline etching. Part of the polycrystalline in the trench is etched. The structure is as Figure 7 shown.

[0097] 8. Field plate oxide layer corrosion. The redundant field plate oxide layer is removed, including removing part of the field plate oxide layer in the trench and the field plate oxide layer on the mesa of the epitaxial wafer. The structure is as Figure 8as shown

[0098] 9. Polycrystalline oxidation. Oxidize the polycrystalline surface layer deposited in the trench to form an oxide layer for isolation. The structure is as Figure 9 shown

[0099] 10. SiN etching. Remove the excess SiN layer, and a wet etching process can be used. The structure is as Figure 10 shown

[0100] 11. Buffer oxide layer etching. Remove the excess buffer oxide layer, and a wet etching process can also be used to expose the epitaxial wafer. The structure is as Figure 11 shown

[0101] 12. Gate oxide layer growth. Grow the gate oxide layer at the position where the ONO structure is removed. The structure is as Figure 12 shown

[0102] 13. Polycrystalline filling. Deposit polycrystalline along the trench, and the polycrystalline in the upper and lower parts of the trench is isolated by the oxide layer formed by polycrystalline oxidation. The structure is as Figure 13 shown

[0103] The subsequent processes are common, for example, defining the active area, depositing metal electrodes, etc., which will not be elaborated here.

[0104] For the shielded gate trench device fabricated through the ONO structure, SiN can effectively isolate the oxidation reaction, protect the trench sidewalls and the epitaxial substrate, oxidize the unprotected polycrystalline, obtain an oxide layer with sufficient thickness, thereby increasing the spacing between the two layers of polycrystalline and reducing the capacitance effect.

[0105] However, the SiN layer in the ONO structure will be retained at the bottom of the trench, with high stress and prone to forming defects leading to leakage. Moreover, both the SiN layer and the field plate are for CVD operation, and the film quality is not as good as that of the grown oxide layer, which may have defects and reduce the breakdown voltage.

[0106] The process of the SGT method with the left - right structure is generally as follows:

[0107] 1. Silicon - silicon trench etching. The structure is as Figure 1 shown

[0108] 2. Field plate oxide layer growth. The structure is as Figure 14 shown

[0109] 3. Polycrystalline filling. The structure is as Figure 15 shown

[0110] 4. Polycrystalline planarization. The structure is as Figure 16 shown

[0111] 5. Polycrystalline etching. The structure is as Figure 17 shown

[0112] 6. Field plate oxide layer etching. The structure is as Figure 18 shown.

[0113] 7. Gate oxide layer growth. The structure is as Figure 19 shown.

[0114] 8. Polycrystalline filling. The structure is as Figure 20 shown. The subsequent processes are conventional processes.

[0115] Among them, the left - right structure SGT method shortens the process flow. The two - layer polycrystalline has a large area and a small spacing, and the capacitance effect is obvious.

[0116] Therefore, no matter the ONO method or the left - right structure SGT method is adopted in the prior art, there are problems of large stress or obvious capacitance effect.

[0117] In view of this, the present application provides a method for manufacturing a shielded gate trench device. By setting a High K material layer and a multi - layer oxide layer between the first polycrystalline layer and the second polycrystalline layer in the trench, the device stress is reduced, and the capacitance between the first polycrystalline layer and the second polycrystalline layer is decreased.

[0118] The following is an exemplary description of the method for manufacturing a shielded gate trench device provided by the present application:

[0119] As an optional implementation manner, please refer to Figure 21 , the method for manufacturing a shielded gate trench device includes:

[0120] S101. Provide an epitaxial wafer, where the epitaxial wafer includes trenches.

[0121] S102. Grow a field plate oxide layer based on the trenches.

[0122] S103. Perform polycrystalline filling on the trenches until the filled polycrystalline is higher than the mesa of the epitaxial wafer.

[0123] S104. After polycrystalline planarization, etch part of the polycrystalline and the field plate oxide layer in the trenches to form a first polycrystalline layer in the trenches.

[0124] S105. Grow a buffer oxide layer along the inner wall of the trenches.

[0125] S106. Deposit a High K material layer along the surface of the buffer oxide layer.

[0126] S107. Perform polycrystalline filling based on the surface of the High K material layer.

[0127] S108. Etch the polycrystalline in the trenches and retain the polycrystalline on the surface of the High K material layer.

[0128] S109, oxidize the polycrystal on the surface of the High K material layer and deposit polycrystal along the trench to form a second polycrystalline layer.

[0129] As an implementation, S101 may include:

[0130] S1011, provide a substrate.

[0131] S1012, grow an epitaxial layer based on the surface of the substrate.

[0132] S1013, fabricate a trench based on the epitaxial layer.

[0133] That is, the epitaxial wafer provided in this application includes a substrate and an epitaxial layer. Among them, the type of the substrate may not be limited. For example, a silicon substrate, a sapphire substrate, a silicon carbide substrate, etc. may be used. The epitaxial layer may use homoepitaxy or heteroepitaxy. Optionally, this application uses silicon epitaxy and fabricates a trench on the epitaxial layer. The structure is as Figure 22 shown. It should be noted that the epitaxial wafer is still shown in the drawings.

[0134] In one implementation, the trench can be fabricated by means of a mask. First, coat photoresist on the surface layer of the epitaxial wafer, pattern the photoresist, and then remove the photoresist.

[0135] It should be noted that only one trench is taken as an example in the drawings. However, it can be understood that in actual applications, the number of trenches may be more. For example, the number of epitaxial wafers can be 50, 60, etc., which is not limited here.

[0136] When fabricating the trench, please refer to Figure 23 , a field plate oxide layer can be grown along the surface layer of the epitaxial wafer. Among them, since the material of the epitaxial layer is silicon, the surface layer of the epitaxial layer can be oxidized to form SiO 2 as the field plate oxide layer. Since the field plate oxide layer is a grown oxide layer, it has high quality and good voltage resistance.

[0137] Continue to refer to Figure 24 , source region polycrystal filling can be carried out along the trench. Among them, since the depth of the trench is relatively deep, in order to ensure that the polycrystal fills the entire trench, it is necessary to ensure that the filled polycrystal is higher than the mesa of the epitaxial wafer.

[0138] Optionally, S104 includes:

[0139] S1041, remove the polycrystal higher than the mesa of the epitaxial wafer to make the polycrystal in the trench flush with the mesa of the epitaxial wafer.

[0140] S1042, remove part of the polycrystal in the trench to leave a first polycrystalline layer in the trench.

[0141] S1043, remove the field plate oxide layer on the mesa of the epitaxial wafer and on the sidewalls of some trenches, and retain the field plate oxide layer connected to the first polycrystalline layer.

[0142] Please refer to Figure 25 , when performing polycrystalline planarization, processes such as chemical mechanical polishing (CMP) can be used for planarization to make the polycrystalline in the trench flush with the mesa of the epitaxial wafer.

[0143] And, please refer to Figure 26 , continue to etch some of the polycrystalline in the trench, and use the remaining polycrystalline as the first polycrystalline layer, where the thickness of the first polycrystalline layer is about half of the trench depth.

[0144] After that, remove the field plate oxide layer on the mesa of the epitaxial wafer and on the sidewalls of some trenches, and retain the field plate oxide layer connected to the first polycrystalline layer, as Figure 27 shown.

[0145] After that, in order to facilitate the subsequent deposition of the High K material layer, a buffer oxide layer needs to be grown along the inner wall of the trench. Among them, the buffer oxide layer is also formed by the process of oxidizing the epitaxial layer, but the thickness of the buffer oxide layer is relatively thin, and its thickness is generally 50 - 2000 angstroms, as Figure 28 shown. When fabricating the buffer oxide layer, a buffer oxide layer will also be formed by oxidizing the surface of the first polycrystalline layer.

[0146] After fabricating the buffer oxide layer, the High K material layer can be continuously deposited. Since the buffer oxide layer has been fabricated in advance, the deposition effect of the High K material layer is better, and the structure after deposition is as Figure 29 shown.

[0147] It should be noted that the High K material refers to a high dielectric constant material. For example, the High K material layer provided in this application can be at least one of silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and titanium oxide material layers.

[0148] And, setting the High K material layer as the horizontal isolation of the device, it can not only effectively isolate the two layers of polycrystalline, but also has a high breakdown field strength, which can increase the device withstand voltage, the stress of the device is small, and the device performance is improved.

[0149] Please refer to Figure 30 , continue to fill the polycrystalline. The purpose of filling the polycrystalline is to retain the underlying polycrystalline, increase the thickness of the two layers of polycrystalline in the trench, and reduce the capacitance effect.

[0150] Then etch the polycrystalline in the trench and retain the polycrystalline on the surface of the High K material layer. The structure is as Figure 31 shown. Among them, the retained polycrystalline thin layer is generally relatively thin and will not affect the device performance, generally 500 - 3000 angstroms.

[0151] After that, the polycrystals on the surface of the High-K material layer are oxidized, and the polycrystals are oxidized into silicon dioxide to form a dielectric layer, such as Figure 32 , where the oxide layer is the dielectric layer. Then, polycrystals are deposited along the trenches to form a second polycrystalline layer, such as Figure 33 shown. Among them, the second polycrystalline layer shown in the figure is the structure after planarization treatment. As shown in the figure, the first polycrystalline layer and the second polycrystalline layer are isolated by a buffer oxide layer, a High-K material layer, and a dielectric layer. The thickness of the multi-layer structure is relatively thick. According to the capacitance calculation formula:

[0152] C = εS / d

[0153] where ε represents the dielectric constant, s represents the facing area between the first polycrystalline layer and the second polycrystalline layer, and d represents the distance between the second polycrystalline layer and the second polycrystalline layer. Therefore, due to the large spacing between the first polycrystalline layer and the second polycrystalline layer, the capacitance is smaller, improving the device performance.

[0154] Figure 33 In the device structure shown, the High-K material layer includes the structure between the first polycrystalline layer and the second polycrystalline layer, and also includes the structure on the sidewall of the second polycrystalline layer. As another implementation, the method further includes:

[0155] S110, removing the High-K material layer on the epitaxial layer mesa and the trench sidewall, and retaining the High-K material layer on the surface of the first polycrystalline layer.

[0156] S111, removing the buffer oxide layer on the outer trench sidewall and the epitaxial wafer mesa and then growing a gate oxide layer.

[0157] S112, depositing polycrystals based on the trenches to form a second polycrystalline layer in the trenches.

[0158] such as Figure 34 shown, after depositing the High-K material layer and fabricating the oxide layer, the excess High-K material layer can be removed, and only the High-K material layer on the surface of the first polycrystalline layer is retained.

[0159] such as Figure 35 , continue to remove the buffer oxide layer on the trench sidewall and the epitaxial wafer mesa.

[0160] In addition, as Figure 36 shown, continue to grow the gate oxide layer. Finally, perform polycrystalline filling to form a second polycrystalline layer, and the structure is as Figure 37 shown.

[0161] Based on the above implementation, as Figure 33 shown, the embodiment of the present application further provides a shield gate trench device, and the device includes:

[0162] An epitaxial wafer with grooves, a first polycrystalline layer and a second polycrystalline layer located in the grooves, wherein the first polycrystalline layer is located below the second polycrystalline layer, and the first polycrystalline layer and the second polycrystalline layer are isolated by a buffer oxide layer, a High K material layer and a polycrystalline oxide layer; a first oxide layer located between the first polycrystalline layer and the epitaxial wafer; a second oxide layer located between the second polycrystalline layer and the epitaxial wafer.

[0163] Wherein, the thickness of the polycrystalline oxide layer is 500 - 3000 angstroms, and the first oxide layer is the grown field plate oxide layer, which will not be elaborated here. As an implementation, the second oxide layer is a buffer oxide layer, and the device further includes a High K material layer located between the second polycrystalline layer and the buffer oxide layer, as Figure 33 described. As another implementation, as Figure 37 shown, the second oxide layer is a gate oxide layer, and the buffer oxide layer is only located between the first polycrystalline layer and the second polycrystalline layer and is used for isolation.

[0164] On the one hand, the present application uses High K materials, which have a high breakdown field strength, can increase the device breakdown voltage, and the device stress is small. On the other hand, a multi-layer structure is used for the isolation between the first polycrystalline layer and the second polycrystalline layer, so the capacitance between polycrystals can be effectively reduced, and the electrical performance of the product can be improved.

[0165] In summary, the embodiments of the present application provide a shielded gate trench device and its manufacturing method. First, an epitaxial wafer is provided, wherein the epitaxial wafer includes grooves, then a field plate oxide layer is grown based on the grooves, and then the grooves are filled with polycrystals until the filled polycrystals are higher than the mesa of the epitaxial wafer. After the polycrystals are planarized, part of the polycrystals and the field plate oxide layer in the grooves are etched to form a first polycrystalline layer in the grooves. Then, a buffer oxide layer is grown along the inner wall of the grooves, a High K material layer is deposited on the surface of the buffer oxide layer, then polycrystals are filled based on the surface of the High K material layer, and then the polycrystals in the grooves are etched, and the polycrystals on the surface of the High K material layer are retained. Finally, the polycrystals on the surface of the High K material layer are oxidized, and polycrystals are deposited along the grooves to form a second polycrystalline layer. On the one hand, since the present application uses a High K material layer to realize the isolation between the first polycrystalline layer and the second polycrystalline layer, it has a high breakdown field strength, can increase the device breakdown voltage, and at the same time, using the High K material layer can make the device stress small. On the other hand, using a multi-layer oxidation process can increase the distance between the first polycrystalline layer and the second polycrystalline layer, effectively reduce the capacitance between polycrystals, and improve the electrical performance of the device.

[0166] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0167] For those skilled in the art, it is obvious that the present application is not limited to the details of the above-described exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed within the present application. Any reference signs in the claims should not be construed as limiting the claims concerned.

Claims

1. A method for fabricating a shielded gate trench device, characterized in that, the method includes: providing an epitaxial wafer, wherein the epitaxial wafer includes trenches; growing a field plate oxide layer based on the trenches; performing polycrystalline filling on the trenches until the filled polycrystalline is higher than the mesa of the epitaxial wafer; etching a part of the polycrystalline and the field plate oxide layer in the trenches after polycrystalline planarization to form a first polycrystalline layer in the trenches; growing a buffer oxide layer along the inner wall of the trenches; depositing a High K material layer along the surface of the buffer oxide layer; performing polycrystalline filling based on the surface of the High K material layer; etching the polycrystalline in the trenches and retaining the polycrystalline on the surface of the High K material layer; oxidizing the polycrystalline on the surface of the High K material layer and depositing polycrystalline along the trenches to form a second polycrystalline layer.

2. The method for fabricating a shielded gate trench device according to claim 1, characterized in that, after the step of oxidizing the polycrystalline on the surface of the High K material layer, the method further includes: removing the High K material layer on the mesa of the epitaxial layer and the sidewalls of the trenches, and retaining the High K material layer on the surface of the first polycrystalline layer; removing the buffer oxide layer on the sidewalls of the outer trenches and the mesa of the epitaxial wafer and then growing a gate oxide layer; depositing polycrystalline based on the trenches to form a second polycrystalline layer in the trenches.

3. The method for fabricating a shielded gate trench device according to claim 1, characterized in that, the step of etching the polycrystalline in the trenches and retaining the polycrystalline on the surface of the High K material layer includes: etching the polycrystalline in the trenches and retaining 500 - 3000 angstroms of polycrystalline on the surface of the High K material layer.

4. The method for fabricating a shielded gate trench device according to claim 1, characterized in that, the step of depositing a High K material layer along the surface of the buffer oxide layer includes: depositing at least one material layer of silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and titanium oxide along the surface of the buffer oxide layer.

5. The method for fabricating a shielded gate trench device according to claim 1, characterized in that, the step of growing a buffer oxide layer along the inner wall of the trenches includes: growing a buffer oxide layer with a thickness of 50 - 2000 angstroms along the inner wall of the trenches.

6. The method for fabricating a shielded gate trench device according to claim 1, characterized in that, the step of providing an epitaxial wafer includes: providing a substrate; growing an epitaxial layer based on the surface of the substrate; fabricating trenches based on the epitaxial layer.

7. The method for fabricating a shielded gate trench device according to claim 1, characterized in that, the step of etching a part of the polycrystalline and the field plate oxide layer in the trenches after polycrystalline planarization includes: removing the polycrystalline higher than the mesa of the epitaxial wafer to make the polycrystalline in the trenches flush with the mesa of the epitaxial wafer; removing a part of the polycrystalline in the trenches to leave a first polycrystalline layer in the trenches; removing the field plate oxide layer on the mesa of the epitaxial wafer and part of the sidewalls of the trenches, and retaining the field plate oxide layer connected to the first polycrystalline layer.

8. A shielded gate trench device, characterized in that, the shielded gate trench device is fabricated by the method according to any one of claims 1 to 7, and the device includes: An epitaxial wafer provided with grooves; A first polycrystalline layer and a second polycrystalline layer located in the grooves, wherein the first polycrystalline layer is located below the second polycrystalline layer, and the first polycrystalline layer and the second polycrystalline layer are isolated by a buffer oxide layer, a High K material layer, and a polycrystalline oxide layer; A first oxide layer located between the first polycrystalline layer and the epitaxial wafer; A second oxide layer located between the second polycrystalline layer and the epitaxial wafer.

9. The shield gate trench device according to claim 8, characterized in that the thickness of the polycrystalline oxide layer is 500 - 3000 angstroms.

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