An undervoltage lockout circuit

Abstract

The present invention discloses an undervoltage lockout circuit, including a resistor R2 and a Zener diode D3. One end of the resistor R2 is connected to a high-voltage power supply VDD, one end of the resistor R1, the drain of a switch NM1, and the drain of a switch NM2. The other end of the resistor R2 is connected to the cathode of the Zener diode D3, the gate of the switch NM1, and the gate of the switch NM2. The other end of the resistor R1 is connected to the cathode of the Zener diode D1. The source of the switch NM1 is connected to one end of the resistor R5. The source of the switch NM2 is connected to one end of the resistor R6. The other end of the resistor R6 is connected to an undervoltage lockout signal VDDON_N, the drain of the switch NM10, and the gate of the switch NM4. The undervoltage lockout circuit of the present invention is simple to implement and has few process limitations.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an undervoltage lockout circuit. Background Art

[0002] The function of the undervoltage lockout (UVLO) circuit is to monitor the chip's power supply voltage in real time to ensure that the chip will not be activated before the power supply voltage reaches the startup voltage. Only when the power supply voltage reaches the startup voltage can the chip start working; when the power supply voltage is lower than the undervoltage lockout voltage, the power supply is directly cut off to prevent the chip from being damaged due to the power supply voltage being too low. Usually, a certain amount of hysteresis is set between the startup voltage and the undervoltage lockout voltage of the undervoltage lockout circuit to ensure that the chip can enter the startup state normally and work stably, while ensuring that fluctuations in the power supply voltage will not cause abnormal operation of the chip. For example, when an electronic device is working, if it carries a large load, the device will pull the chip's power supply voltage down to below the startup voltage at the moment of startup. In order to avoid the situation where the device shuts down as soon as it is turned on, it is necessary to use an undervoltage lockout circuit to monitor and lock the chip's power supply voltage in real time to improve the stability and reliability of the device's operation. Therefore, the undervoltage lockout circuit is an indispensable part of the power management chip.

[0003] A common implementation of the undervoltage lockout circuit is as follows Figure 1 shown. Figure 1 In the circuit, VDD is the power supply, VDDON_N is the undervoltage lockout signal, and VDDON_N outputs the inverted signal VDDON_P through the high-voltage inverter inv1. The voltage regulator diode D1 is connected to the V GS The voltage is clamped to prevent excessive VDD voltage from breaking down the PM1 gate. Switching tube PM1, Zener diodes D1, D2, D3, and D4, and resistors R2, R4, and R6 form the VDD voltage sampling circuit. Vc is the sampling voltage, which controls the on and off state of switching tube NM1, thereby controlling the undervoltage lockout signal. Zener diode D7 clamps the sampling voltage Vc to prevent excessive Vc from breaking down the NM1 gate.

[0004] The working principle of the UVLO circuit of this scheme is as follows: VDD gradually increases from 0V. When VDD is less than the reverse breakdown voltage of the two Zener diodes 2V, DZ When (V DZ is the reverse breakdown voltage of a Zener diode), the UVLO circuit does not start working. DZ When the resistor R1 and the Zener diodes D5 and D6 form a branch that starts to conduct, the undervoltage lockout signal VDDON_N is clamped by D5 and D6, and VDDON_N=VDD=2V DZ, the inverter inv1 output signal VDDON_P is low. Since VDD does not reach the reverse breakdown voltage of the three Zener diodes at this time, the branch consisting of resistors R2, R4, R6 and Zener diodes D2, D3 and D4 is not conducting, and Vc is pulled down to ground by resistor R6. At this time, the switch tube NM1 is in the off state, and the branch consisting of Zener diode D1, resistor R3 and NM1 cannot conduct. Therefore, Va=VDDON_N=2V DZ , then the V of PM1 tube GS The voltage is 0V and the PM1 tube is in the off state.

[0005] The VDD voltage continues to rise. When VDD rises to the point where the V GS The voltage reaches the PM1 tube turn-on threshold voltage V TH_PM1 When PM1 is turned on, Vb is pulled up by PM1 to the PM1 drain potential V D_PM1 (V D_PM1 =VDD-V DS_PM1 ), the branch composed of PM1 tube, Zener diode D4 and resistors R4 and R6 is turned on, and the sampling voltage Vc begins to increase with the increase of VDD voltage.

[0006] When VDD rises to the threshold voltage V that makes Vc reach the NM1 tube, TH_NM1 When the NM1 tube is turned on, VDDON_N is pulled down to ground, and the output signal VDDON_P of the inverter inv1 is flipped to a high level, controlling the internal circuit to start working. The VDD voltage at this time is called the startup voltage VDD_ON. Including after VDD reaches the turn-on voltage, VDDON_N is pulled down to ground, and the voltage regulator diode D1 is connected to the V GS The voltage is clamped, then the V GS The voltage is always kept at the reverse breakdown voltage V of a Zener diode. DZ , so the PM1 tube remains open.

[0007] When the VDD voltage starts to drop from above VDD_ON, Vc decreases accordingly until Vc < V TH_NM1 When the NM1 tube is turned off, VDDON_N is pulled up to VDD again, and the inverter inv1 output signal VDDON_P is flipped to a low level again, outputting an undervoltage lockout signal to control the internal circuit to stop working. Therefore, the VDD voltage at this time is called the undervoltage lockout voltage VDD_OFF.

[0008] Another common undervoltage lockout circuit structure is Figure 2 shown. Figure 2The UVLO circuit shown in the figure consists of a VDD_ON voltage detection circuit, a VDD_OFF voltage detection circuit, and an undervoltage lockout signal output branch. The VDD_ON voltage detection circuit includes high-voltage PMOS transistors PM1 and PM2, high-voltage NMOS transistors NM1 and NM2, a Zener diode D1, resistors R1, R2, R3, R6, R7, R8, R9, R12, R13, R14, R15, switches NM4, NM6, NM8, NMOS transistors NM9, NM10, NM11, and capacitor C1. NMOS transistors NM9, NM10, and NM11 are connected in series as diodes to clamp the Vh signal. The VDD_OFF voltage detection circuit includes a high-voltage PMOS transistor PM3, resistors R4, R10, R16, capacitor C2, and a UVLO comparator circuit. The undervoltage lockout signal output branch includes switches NM3, NM12, NM13, and resistor R11.

[0009] The working principle of this circuit is as follows: When the VDD voltage gradually increases from 0V to the reverse breakdown voltage V DZ When the branch composed of resistor R5 and voltage stabilizing diode D2 is turned on, Vf is clamped by D2, and Vf=V DZ At this time, NM2 is turned on, and the signal Vd is pulled up to the source potential V of NM2 by the resistor R7. S_NM2 (V S_NM2 =V DZ -V GS_NM2 ), control switches NM6 and NM8 to turn on. NM6 pulls signal Vg to ground, shorting resistors R12 and R15. NM8 pulls Vj to ground, and Vk is also pulled to ground. Switch NM12 is turned off, and NM13 is also off, pulling VDDON_N to a high level.

[0010] When VDD rises to VDD=V DZ +V DS_NM1 (V DS_NM1 =NM1 conduction voltage drop), the VDD_ON voltage detection circuit is turned on. When the VDD voltage continues to rise until the sampling voltage Vh reaches the turn-on threshold voltage V of the switch tube NM4 TH_NM4 When NM4 is turned on, Vd is pulled down to ground. At this time, the switch tubes NM6 and NM8 are turned off, and Vj is pulled up to Vh by the resistor R13, and Vk is also pulled up to Vh, that is, Vk=Vj=Vh=V TH_NM4, controlling switch NM12 to turn on, pulling VDDON_N down to ground, and the internal circuitry begins operating. After the circuit starts, PM3 turns on, and the VDD_OFF voltage detection circuit turns on. At this point, the VDD voltage is high, and the sampled voltage Vm is greater than the internal reference voltage Vref. Therefore, the UVLO comparator outputs signal VDDOFF_N at a high level, turning on switch NM5 and NM13.

[0011] When the VDD voltage gradually decreases from VDD_ON, the sampling voltage Vm decreases accordingly. When VDD decreases to the point where Vm is less than Vref, the comparator output signal VDDOFF_N turns to a low level, and the switches NM5 and NM13 are turned off. At the same time, the sampling voltage Vh also decreases as VDD decreases. When Vh is less than V TH_NM4 When Vd is pulled up again, the switch tube NM4 is turned off, and the switch tubes NM6 and NM8 are turned on. The NM8 tube pulls Vj down to the ground, that is, Vk is pulled down to the ground, and the control switch tube NM12 is turned off. At this time, VDDON_N is pulled up to a high level again, and the control circuit stops working.

[0012] The disadvantages of the UVLO circuit in solution 1 above are as follows:

[0013] (1) This solution must use thick gate oxide BCD technology, which has great limitations in process selection. Before the high-voltage power supply VDD reaches the start-up voltage VDD_ON, the V of the NMOS tube in the high-voltage inverter inv1 is GS The voltage is the power supply VDD, so the V GS There is a high voltage requirement; after VDD reaches VDD_ON, the VDDON_N signal is pulled down to the ground. At this time, the PMOS tube in the high-voltage inverter inv1 is subjected to V GS The voltage is the high voltage power supply VDD, which requires the V GS The withstand voltage must reach the chip's limit operating voltage, so the circuit must be designed using thick gate oxide BCD technology to ensure that the device V GS The voltage resistance meets the design requirements. Thick gate oxide process is easier to implement on the process of 0.18um or above (the process line width is greater than 0.18um), and high V is easier to produce on the process of 0.18um and below. GS It is difficult to manufacture voltage-resistant devices, and only a few wafer fabrication plants can produce them. Therefore, this circuit has great limitations in process selection.

[0014] (2) This solution uses a large number of Zener diodes, which takes up a large area of ​​the circuit layout and has a high chip manufacturing cost. In this circuit, the voltage on the cathodes of Zener diodes D1 and D2 is the high voltage power supply VDD, and the cathode of D4 also needs to withstand high voltage (VDD-V DS_PM1), to prevent the PN junction between the isolation ring and the substrate of the Zener diode from being broken down due to excessive VDD voltage, a high-voltage Zener diode is required for the design. Generally, the higher the junction withstand voltage of the Zener diode, the larger the layout area. Therefore, the layout area of ​​the high-voltage Zener diode is much larger than that of the low-voltage Zener diode. In this solution, a total of four high-voltage Zener diodes and three low-voltage Zener diodes are required. The large number of Zener diodes will significantly increase the circuit area and greatly increase the chip manufacturing cost.

[0015] The disadvantages of the UVLO circuit in solution 2 above are as follows:

[0016] (1) The implementation of the UVLO function of this solution is complex and some functions are redundant. This solution designs a VDD_ON voltage detection circuit and a VDD_OFF voltage detection circuit respectively. When VDD = VDD_ON, NM4 in the VDD_ON voltage detection circuit turns on and pulls Vd down to ground. The signal Vk controls NM12 to turn on and pulls VDDON_N down to ground. After the VDD_OFF voltage detection circuit works, it pulls down Vd and VDDON_N again. This part of the function is redundant. In addition, when VDD = VDD_OFF, the output signal of the VDD_OFF voltage detection circuit controls NM13 to turn off. At the same time, it is necessary to ensure that the Vk signal in the VDD_ON voltage detection circuit can control NM12 to turn off so that VDDON_N can flip to a high level again and the control circuit stops working. This part of the function is redundant, making the implementation of the undervoltage lockout function more complicated.

[0017] (2) This solution requires the use of a large number of large-value resistors for current limiting. The large-value resistors occupy a large layout area and are not suitable for process technologies above 0.18um (the process line width is greater than 0.18um). The VDD_ON voltage detection circuit in this solution adopts a resistor divider structure. During the circuit startup process, a large-value resistor is required to limit the current. At the same time, R5 also needs to be designed as a large-value resistor to limit the current of its branch. The number of large-value resistors used in this solution is large, which greatly increases the circuit layout area. Under the same resistance value requirement, the larger the process line width, the larger the size of the manufactured resistor device. If this solution is designed using a process technology above 0.18um, the layout area occupied by the resistor device will increase significantly, which increases the chip manufacturing cost. Therefore, this circuit is not suitable for process technologies above 0.18um. Summary of the Invention

[0018] Therefore, it is necessary to provide an undervoltage lockout circuit to solve the problems of the existing undervoltage lockout circuit having a complex structure and occupying a large circuit layout area.

[0019] To achieve the above-mentioned objectives, the present invention provides an undervoltage lockout circuit, comprising a resistor R2, a Zener diode D3, a Zener diode D2, and a switch tube NM3, wherein one end of the resistor R2 is connected to a high-voltage power supply VDD, one end of the resistor R1, the drain of the switch tube NM1, and the drain of the switch tube NM2, the other end of the resistor R2 is connected to the cathode of the Zener diode D3, the gate of the switch tube NM1, and the gate of the switch tube NM2, the other end of the resistor R1 is connected to the cathode of the Zener diode D1, the source of the switch tube NM1 is connected to one end of the resistor R5, the source of the switch tube NM2 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the undervoltage lockout signal VDDON_N, the drain of the switch tube NM10, and the gate of the switch tube NM4, and the drain of the switch tube NM4 is connected to the Zener diode D1 through the resistor R4 and the Zener diode D2. The anode of the Zener diode D2 is connected to the anode of the Zener diode D1; the source of the switching tube NM4 is connected to one end of the resistor R8 and the gate of the switching tube NM5, the drain of the switching tube NM5 is connected to the other end of the resistor R5 and the gate of the switching tube NM6, the drain of the switching tube NM6 is connected to the other end of the resistor R8 and the gate of the switching tube NM10, the source of the switching tube NM6, the source of the switching tube NM5, the source of the switching tube NM10 and the anode of the Zener diode D3 are connected to the ground terminal GND; the source of the switching tube NM3 is connected to the source of the switching tube NM4 and one end of the resistor R7, the drain of the switching tube NM3 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the anode of the Zener diode D1, the other end of the resistor R7 is connected to the ground terminal GND, and the gate of the switching tube NM3 is connected to the low-voltage power supply VCCA.

[0020] Furthermore, the reverse breakdown voltage of the Zener diode D2 is the same as the reverse breakdown voltage of the Zener diode D1 and the reverse breakdown voltage of the Zener diode D3.

[0021] Furthermore, a clamping device is included, one end of the clamping device is connected to the gate of the switch tube NM5, and the other end of the clamping device is connected to the ground terminal GND.

[0022] Furthermore, the clamping device includes more than two NMOS tubes, the gate of the switch tube NM5 is connected to the drain and gate of the first NMOS tube, the source of the first NMOS tube of two adjacent NMOS tubes is connected to the gate and drain of the next NMOS tube, and the source of the last NMOS tube is connected to the ground terminal GND.

[0023] Furthermore, the clamping device includes an NMOS transistor NM7, an NMOS transistor NM8, and an NMOS transistor NM9, the drain of the NMOS transistor NM7 and the gate of the NMOS transistor NM7 are connected to the gate of the NMOS transistor NM5, the source of the NMOS transistor NM7 is connected to the drain of the NMOS transistor NM8 and the gate of the NMOS transistor NM8, the source of the NMOS transistor NM8 is connected to the drain of the NMOS transistor NM9 and the gate of the NMOS transistor NM9, and the source of the NMOS transistor NM9 is connected to the ground terminal GND.

[0024] Furthermore, the NMOS transistors of the clamping device have the same turn-on threshold voltage.

[0025] Furthermore, a resistor R9 is included, and the other end of the resistor R8 is connected to the gate of the switch tube NM10 through the resistor R9.

[0026] Furthermore, a capacitor C1 is included, one end of the capacitor C1 is connected to the gate of the switch tube NM10, and the other end of the capacitor C1 is connected to the ground terminal GND.

[0027] Furthermore, the switch tube NM5 and the switch tube NM10 have the same turn-on threshold voltage.

[0028] Furthermore, the switch tube NM1 or the switch tube NM2 is an NMOS tube.

[0029] Different from the existing technology, the above technical solution has the following advantages:

[0030] 1. The undervoltage lockout circuit of the present invention is simple to implement. This undervoltage lockout circuit uses a Zener diode and a resistor to form a VDD voltage detection circuit. The sampled voltage Vc is used to control the on and off of the switch NM5, thereby controlling the output of the undervoltage lockout signal, thereby achieving the purpose of real-time monitoring of the VDD voltage. The VDD_ON voltage detection function is implemented by controlling the switch NM4, and the VDD_OFF voltage detection function is further switched by using NM3. This eliminates the need for separately designed internal reference voltages and comparator circuits, resulting in a simple circuit structure.

[0031] 2. The undervoltage lockout circuit of the present invention has minimal process limitations and good versatility. All MOS devices in the circuit do not require high VGS withstand voltages, eliminating the need for thick-gate-oxide BCD processes. Thin-gate-oxide BCD processes can meet design requirements, reducing process limitations during circuit design.

[0032] 3. The undervoltage lockout circuit of the present invention has a small layout area, saving chip manufacturing costs. The circuit only requires three voltage-stabilizing diodes, occupying a small circuit layout area. Furthermore, the circuit uses two voltage-stabilizing diodes to implement the VDD_ON voltage detection function, eliminating the need for large-value resistors for current limiting during startup. This significantly reduces the use of large-value resistors, further reducing the circuit layout area, and helping to reduce chip manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A circuit structure diagram of an undervoltage lockout circuit according to background technology;

[0034] Figure 2 A circuit structure diagram of another under-voltage lockout circuit in the background art;

[0035] Figure 3 is a circuit structure diagram of an undervoltage lockout circuit according to one embodiment;

[0036] Figure 4 is a circuit structure diagram of an undervoltage lockout circuit structure according to another embodiment;

[0037] Figure 5 FIG. 4 is a circuit diagram of an undervoltage lockout circuit structure according to another embodiment. DETAILED DESCRIPTION

[0038] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0039] See also Figures 3 to 5This embodiment provides an undervoltage lockout circuit, including a resistor R2 and a Zener diode D3, a Zener diode D2 and a switch tube NM3, one end of the resistor R2 is connected to a high-voltage power supply VDD, one end of the resistor R1, the drain of the switch tube NM1, and the drain of the switch tube NM2, the other end of the resistor R2 is connected to the cathode of the Zener diode D3, the gate of the switch tube NM1, and the gate of the switch tube NM2, the other end of the resistor R1 is connected to the cathode of the Zener diode D1, the source of the switch tube NM1 is connected to one end of the resistor R5, the source of the switch tube NM2 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the undervoltage lockout signal VDDON_N, the drain of the switch tube NM10, and the gate of the switch tube NM4, and the drain of the switch tube NM4 is connected to the Zener diode D3 through the resistor R4. The anode of diode D2 and the cathode of Zener diode D2 are connected to the anode of Zener diode D1. The source of switch tube NM4 is connected to one end of resistors R8 and R7, the source of switch tube NM3, and the gate of switch tube NM5. The drain of switch tube NM3 is connected to one end of resistor R3. The other end of resistor R3 is connected to the anode of Zener diode D1. The gate of switch tube NM3 is connected to the low-voltage power supply VCCA. The drain of switch tube NM5 is connected to the other end of resistor R5 and the gate of switch tube NM6. The drain of switch tube NM6 is connected to the other end of resistor R8 and the gate of switch tube NM10. The other end of resistor R7, the source of switch tube NM6, the source of switch tube NM5, the source of switch tube NM10, and the anode of Zener diode D3 are connected to ground terminal GND.

[0040] The high-voltage power supply VDD is an external power supply that provides power to the internal operating circuit. The "high voltage" in the high-voltage power supply VDD does not refer to the voltage being high voltage, but rather serves to distinguish it from the low-voltage power supply VCCA mentioned below. Generally, the low-voltage power supply VCCA is generated by a regulator circuit within the internal operating circuit, which converts the voltage of the high-voltage power supply VDD into the low-voltage power supply VCCA. Since the voltage of VDD is generally higher than that of VCCA, the two power supplies are distinguished by high and low voltage. The undervoltage lockout signal VDDON_N is used to control whether the internal operating circuit begins operation. When the undervoltage lockout signal VDDON_N is pulled down to ground, the internal operating circuit begins operation. In the circuit of the present invention, signal Vc is a sampling voltage that controls the on and off of switch NM5. Signal Vf generated by the VDD detection circuit controls the on and off of switch NM10, thereby controlling the output of the undervoltage lockout signal VDDON_N. The on and off of the switch tubes NM1 and NM2 are controlled by the signal Vb, and the voltage stabilizing diode D3 clamps Vb, thereby ensuring that the V GS The voltage is within its withstand voltage range. Resistors R2, R5 and R6 are current limiting resistors.

[0041] The working principle of the undervoltage lockout circuit of the present invention is as follows:

[0042] When the high voltage power supply VDD is less than the reverse breakdown voltage of a Zener diode V DZ， When the reverse breakdown voltage of the voltage-stabilizing diodes D1, D2 and D3 in the circuit of the present invention is the same, each branch in the circuit cannot be turned on, and the circuit cannot start working at this time; when the high-voltage power supply VDD rises to V DZ When the resistor R2 and the voltage stabilizing diode D3 form a branch that starts to conduct, the signal Vb is clamped by D3, and Vb = V DZ , then Vb controls the switch tubes NM1 and NM2 to turn on, and the switch tubes NM1 and NM2 pull up Vd and VDDON_N through resistors R5 and R6 respectively, thereby controlling the switch tubes NM4 and NM6 to turn on; when VDD continues to rise to the reverse breakdown voltage of the two Zener diodes 2V DZ When VDD_ON is reached, the voltage detection circuit composed of the Zener diodes D1, D2, resistors R1, R4, R8 and the switches NM4, NM6 starts to work, and the sampling voltage Vc starts to increase with the increase of VDD voltage. When VDD increases to the point where Vc reaches the turn-on threshold voltage V TH_NM5 When NM5 is turned on, the signal Vd is pulled down to the ground, so the switch NM6 controlled by the signal Vd is turned off, and the Ve voltage is pulled up to Vc by the resistor R8. At the same time, the signal Vf is also pulled up to Vc. At this time, Vf=Ve=Vc=V TH_NM5 Generally, the switch tube NM5 and the switch tube NM10 can be set to the same type of switch tube, that is, the switch tube NM5 and the switch tube NM10 have the same turn-on threshold voltage. At this time, Vf also reaches the turn-on threshold voltage V of the switch tube NM10. TH_NM10 , NM10 tube is turned on, and the undervoltage lockout signal VDDON_N is pulled down to ground, controlling the internal working circuit to start working. Therefore, the VDD voltage at this time is called the start-up voltage VDD_ON. At this time, the circuit realizes the VDD_ON voltage detection function.

[0043] Then in Figure 3 In the embodiment, the startup voltage VDD_ON is expressed as follows:

[0044]

[0045] Where V TH_NM5 is the turn-on threshold voltage of the switch tube NM5, V D1is the reverse breakdown voltage of the Zener diode D1. The undervoltage lockout circuit of the above embodiment is simple to implement, eliminating the need for separate internal reference voltage and comparator circuit design. This reduces the circuit layout area and reduces chip manufacturing costs. Furthermore, the process selection limitations are minimal, resulting in excellent versatility. All switching devices in the circuit of the present invention do not require a high VGS withstand voltage, eliminating the need for a thick-gate-oxide BCD process. A thin-gate-oxide BCD process can meet the design requirements, reducing the process selection limitations during circuit design.

[0046] The VDD_OFF voltage detection function operates as follows: When the high-voltage power supply VDD rises to the startup voltage VDD_ON, the undervoltage lockout signal VDDON_N is pulled down to ground, controlling the internal working circuit to start operating. At this time, the internal regulator circuit starts to operate, outputting the low-voltage power supply VCCA to a high level, turning on the switch NM3 and turning off the switch NM4 under the control of VDDON_N. At this time, the circuit switches to the VDD_OFF voltage detection circuit.

[0047] When the VDD voltage drops and is lower than VDD_ON and further drops gradually, the sampling voltage Vc decreases accordingly. When VDD drops to a level that makes Vc lower than the threshold voltage V of the switch NM5, TH_NM5 When , NM5 turns off, and Vd is pulled up again by resistor R5. At this time, switch NM6 turns on, pulling Ve down to ground, and Vf = 0V. Therefore, switch NM10 controlled by Vf turns off, and the undervoltage lockout signal VDDON_N is pulled up to a high level again, controlling the internal circuit to stop working. The VDD voltage at this time is called the shutdown voltage VDD_OFF. The expression of the undervoltage lockout voltage VDD_OFF is as follows:

[0048]

[0049] Among them, V DZ This is the reverse breakdown voltage of Zener diode D1. The undervoltage lockout circuit of the present invention implements the VDD_OFF voltage detection function through switch NM3. This allows switching between the VDD_ON and VDD_OFF voltage detection functions to be achieved through the control of switches NM3 and NM4, eliminating the need for separate internal reference voltage and comparator circuits, resulting in a simple circuit structure.

[0050] In order to avoid the gate voltage of the switch tube NM5 being too high, Figure 4As shown, the undervoltage lockout circuit of the present invention further includes a clamping device, one end of which is connected to the gate of the switch tube NM5, and the other end of which is connected to the ground terminal GND. In this way, the gate voltage of the switch tube NM5 is clamped by the clamping device, and the clamping voltage is lower than the internal low-voltage power supply voltage. The gate voltages of the switch tubes NM1 and NM2 of the present invention are clamped by the voltage regulator diode D3, and the gate voltages of the switch tubes NM3 and NM4 are at most the internal low-voltage power supply voltage. Therefore, all MOS devices in the circuit of the present invention have no V GS High voltage resistance requirements do not require the use of thick gate oxide BCD process for design.

[0051] In some embodiments, the clamping device can be implemented using a Zener diode. Figure 5 As shown, the clamping device is composed of NMOS tubes connected in the form of diodes. The clamping device of this embodiment includes more than two NMOS tubes. The gate of the switch tube NM5 is connected to the drain and gate of the first NMOS tube. The source of the first NMOS tube of the two adjacent NMOS tubes is connected to the gate and drain of the next NMOS tube. The source of the last NMOS tube is connected to the ground terminal GND. By clamping the NMOS tube, the gate voltage of the switch tube NM5 can be clamped so that the switch tube NM5 has no V GS High voltage withstand requirements. As a specific embodiment, the clamping device can include three NMOS transistors, including NMOS transistors NM7, NMOS transistor NM8, and NMOS transistor NM9. The drain and gate of NMOS transistor NM7 are connected to the gate of NMOS transistor NM5. The source of NMOS transistor NM7 is connected to the drain and gate of NMOS transistor NM8. The source of NMOS transistor NM8 is connected to the drain and gate of NMOS transistor NM9. The source of NMOS transistor NM9 is connected to ground GND. By connecting NMOS transistors NM7, NMOS transistors NM8, and NMOS transistors NM9 in series and in a diode configuration, Vc is clamped to prevent excessive Vc voltage from breaking down the gate of NM5.

[0052] The circuit of the present invention also includes an RC filter circuit consisting of a resistor R9 and a capacitor C1, which filters the signal Vf. One end of the resistor R9 is connected to the other end of the resistor R8, the other end of the resistor R9 is connected to one end of the capacitor C1 and the gate of the switch tube NM10, and the other end of the capacitor C1 is connected to the ground terminal GND.

[0053] In all the above embodiments, the switch tube NM1 or the switch tube NM2 is preferably an NMOS tube, and other switch tubes can also be implemented by using NMOS tubes.

[0054] The undervoltage lockout circuit of the present invention has the following advantages over the prior art:

[0055] 1. The undervoltage lockout circuit of the present invention is simple to implement. This UVLO circuit uses a Zener diode and a resistor to form a VDD voltage detection circuit. The sampled voltage Vc is used to control the on and off of the switch NM5, thereby controlling the output of the undervoltage lockout signal, thereby achieving the purpose of real-time monitoring of the VDD voltage. The VDD_ON and VDD_OFF voltage detection functions can be switched by controlling the switches NM3 and NM4, eliminating the need for separate internal reference voltage and comparator circuit design, resulting in a simple circuit structure.

[0056] 2. The undervoltage lockout circuit of the present invention has little limitation in process selection and good versatility. All MOS devices in the circuit of the present invention have no V GS For high voltage resistance requirements, there is no need to use thick gate oxide BCD process for design. The thin gate oxide BCD process can meet the design requirements, reducing the limitations of process selection during circuit design.

[0057] 3. The undervoltage lockout circuit of the present invention has a small layout area, saving chip manufacturing costs. The circuit only requires three voltage-stabilizing diodes, occupying a small circuit layout area. Furthermore, the circuit uses two voltage-stabilizing diodes to implement the VDD_ON voltage detection function, eliminating the need for large-value resistors for current limiting during startup. This significantly reduces the use of large-value resistors, further reducing the circuit layout area, and helping to reduce chip manufacturing costs.

[0058] It should be noted that although the above embodiments have been described herein, this does not limit the scope of patent protection of the present invention. Therefore, based on the innovative concept of the present invention, changes and modifications to the embodiments described herein, or equivalent structural or equivalent process transformations made using the contents of the present invention's specification and drawings, and direct or indirect application of the above technical solutions to other related technical fields, are all included in the scope of patent protection of the present invention.

Claims

1. An undervoltage lockout circuit, characterized in that: The circuit includes a resistor R2, a Zener diode D3, a Zener diode D2 and a switch tube NM3, one end of the resistor R2 is connected to the high-voltage power supply VDD, one end of the resistor R1, the drain of the switch tube NM1 and the drain of the switch tube NM2, the other end of the resistor R2 is connected to the cathode of the Zener diode D3, the gate of the switch tube NM1 and the gate of the switch tube NM2, the other end of the resistor R1 is connected to the cathode of the Zener diode D1, the source of the switch tube NM1 is connected to one end of the resistor R5, the source of the switch tube NM2 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the undervoltage lockout signal VDDON_N, the drain of the switch tube NM10 and the gate of the switch tube NM4, the drain of the switch tube NM4 is connected to the anode of the Zener diode D1 through the resistor R4 and the Zener diode D2, and the cathode of the Zener diode D2 is connected to the anode of the Zener diode D1. The anode of Zener diode D2 is connected to the drain of switch NM4 through resistor R4; the source of switch NM4 is connected to one end of resistor R8 and the gate of switch NM5; the drain of switch NM5 is connected to the other end of resistor R5 and the gate of switch NM6; the drain of switch NM6 is connected to the other end of resistor R8 and the gate of switch NM10; the source of switch NM6, the source of switch NM5, the source of switch NM10, the anode of Zener diode D3, and ground GND are connected; the source of switch NM3 is connected to the source of switch NM4 and one end of resistor R7; the drain of switch NM3 is connected to one end of resistor R3; the other end of resistor R3 is connected to the anode of Zener diode D1; the other end of resistor R7 is connected to ground GND; and the gate of switch NM3 is connected to the low-voltage power supply VCCA; It also includes a resistor R9, and the other end of the resistor R8 is connected to the gate of the switch tube NM10 through the resistor R9; The switch transistor NM5 and the switch transistor NM10 have the same turn-on threshold voltage.

2. The undervoltage lockout circuit according to claim 1, wherein: The reverse breakdown voltage of the Zener diode D2 is the same as the reverse breakdown voltage of the Zener diode D1 and the reverse breakdown voltage of the Zener diode D3.

3. The undervoltage lockout circuit according to claim 1, wherein: A clamping device is also included, one end of which is connected to the gate of the switch tube NM5, and the other end of which is connected to the ground terminal GND.

4. The undervoltage lockout circuit according to claim 3, wherein: The clamping device includes more than two NMOS tubes, the gate of the switch tube NM5 is connected to the drain and gate of the first NMOS tube, the source of the first NMOS tube of two adjacent NMOS tubes is connected to the gate and drain of the next NMOS tube, and the source of the last NMOS tube is connected to the ground terminal GND.

5. The undervoltage lockout circuit according to claim 4, wherein: The clamping device includes an NMOS transistor NM7, an NMOS transistor NM8, and an NMOS transistor NM9. The drain of the NMOS transistor NM7 and the gate of the NMOS transistor NM7 are connected to the gate of the NMOS transistor NM5. The source of the NMOS transistor NM7 is connected to the drain of the NMOS transistor NM8 and the gate of the NMOS transistor NM8. The source of the NMOS transistor NM8 is connected to the drain of the NMOS transistor NM9 and the gate of the NMOS transistor NM9. The source of the NMOS transistor NM9 is connected to the ground terminal GND.

6. The undervoltage lockout circuit according to claim 4, wherein: The NMOS tubes of the clamping device have the same turn-on threshold voltage.

7. The undervoltage lockout circuit according to claim 1, wherein: The system further includes a capacitor C1 , one end of which is connected to the gate of the switch tube NM10 , and the other end of which is connected to the ground terminal GND.

8. The undervoltage lockout circuit according to claim 1, wherein: The switch tube NM1 or the switch tube NM2 is an NMOS tube.

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