Systems and methods for deep learning based primary transform architecture

Abstract

Apparatuses, systems, and techniques for transforming input data to train a neural network. In at least one embodiment, one or more data transformations are identified in a sequence of data transformations and combined into one or more master data transformations for execution by one or more parallel processing units in order to prepare data for training an untrained neural network.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 16 / 719,883, filed on December 18, 2019, entitled “MASTER TRANSFORM ARCHITECTURE FOR DEEP LEARNING,” which is hereby incorporated by reference in its entirety and for all purposes. Technical Field

[0003] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, according to various new techniques described herein, at least one embodiment relates to a processor or computing system for transforming input data to train a neural network and perform inference using the neural network. Background Art

[0004] Training a neural network so that it can be used for inference typically requires large amounts of data. This data is often provided in various formats or requires modification before being used to train the neural network. Preparing data for training and inference by transforming it back and forth is a critical part of training a neural network to perform deep learning inference. While transforming input data to prepare it for training a neural network is often necessary, it can also be expensive due to technical limitations (e.g., memory requirements) and format-based restrictions. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A system for training and inference using a neural network according to at least one embodiment is shown;

[0006] Figure 2 A system for training and inference using a neural network accelerated by one or more parallel processing units (PPUs) is shown in accordance with at least one embodiment.

[0007] Figure 3 shows an example sequence of transformations to prepare data for training and inference using a neural network in accordance with at least one embodiment;

[0008] Figure 4 shows the percentage of time each example transform processes data for training and inference using a neural network according to at least one embodiment;

[0009] Figure 5An example sequence of transformations is shown for preparing data for training and inference using a neural network, wherein a subset of the example transformations are performed by one or more graphics processing units (GPUs) and the remaining example transformations are performed by one or more central processing units (CPUs), in accordance with at least one embodiment.

[0010] Figure 6 An example sequence of transformations for preparing data for training and inference using a neural network is shown, wherein a subset of the example transformations have been combined into a main transformation that is performed by one or more GPUs, with the remaining example transformations individually performed by one or more CPUs, in accordance with at least one embodiment;

[0011] Figure 7 A system for determining one or more primary transforms based on a sequence of transforms to be executed on one or more parallel processing units (PPUs), such as a graphics processing unit (GPU), is shown, each primary transform comprising two or more data transforms, in accordance with at least one embodiment;

[0012] Figure 8 A process for determining one or more primary transforms, each comprising two or more data transforms, based on a sequence of transforms to be executed on one or more parallel processing units (PPUs), such as a graphics processing unit (GPU), according to at least one embodiment is shown;

[0013] Figure 9A Inference and / or training logic according to at least one embodiment is shown;

[0014] Figure 9B Inference and / or training logic according to at least one embodiment is shown;

[0015] Figure 10 illustrates the training and deployment of a neural network according to at least one embodiment;

[0016] Figure 11 An example data center system is shown in accordance with at least one embodiment;

[0017] Figure 12A An example of an autonomous vehicle according to at least one embodiment is shown;

[0018] Figure 12B According to at least one embodiment, Figure 12A Examples of camera positions and fields of view for autonomous vehicles;

[0019] Figure 12C According to at least one embodiment Figure 12A A block diagram of an example system architecture for an autonomous vehicle;

[0020] Figure 12Dis a diagram illustrating a method for one or more cloud-based servers and Figure 12A A diagram of a system for communicating between autonomous vehicles;

[0021] Figure 13 is a block diagram illustrating a computer system according to at least one embodiment;

[0022] Figure 14 is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 15 A computer system according to at least one embodiment is shown;

[0024] Figure 16 A computer system according to at least one embodiment is shown;

[0025] Figure 17A A computer system according to at least one embodiment is shown;

[0026] Figure 17B A computer system according to at least one embodiment is shown;

[0027] Figure 17C A computer system according to at least one embodiment is shown;

[0028] Figure 17D A computer system according to at least one embodiment is shown;

[0029] Figure 17E and Figure 17F illustrates a shared programming model in accordance with at least one embodiment;

[0030] Figure 18 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0031] Figure 19A and Figure 19B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0032] Figure 20A and Figure 20B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0033] Figure 21 A computer system according to at least one embodiment is shown;

[0034] Figure 22A A parallel processor according to at least one embodiment is shown;

[0035] Figure 22Bshows a partition unit according to at least one embodiment;

[0036] Figure 22C illustrates a processing cluster according to at least one embodiment;

[0037] Figure 22D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0038] Figure 23 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0039] Figure 24 A graphics processor according to at least one embodiment is shown;

[0040] Figure 25 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0041] Figure 26 A deep learning application processor according to at least one embodiment is shown;

[0042] Figure 27 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0043] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0044] Figure 29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0045] Figure 30 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0046] Figure 31 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0047] Figure 32 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0048] Figure 33A and Figure 33B Thread execution logic is shown that includes an array of processing elements of a graphics processor core, in accordance with at least one embodiment.

[0049] Figure 34 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0050] Figure 35illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0051] Figure 36 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment; and

[0052] Figure 37 A streaming multiprocessor in accordance with at least one embodiment is shown. DETAILED DESCRIPTION

[0053] Figure 1 A system for training and inference using one or more neural networks 110, 112 is shown, according to at least one embodiment. In at least one embodiment, a training framework 108 is used to train an untrained neural network 110 to perform operations such as classification. In at least one embodiment, the training framework 108 is a set of software modules with instructions that, when executed, perform operations to train the neural network 110, including performing calculations and backpropagating or updating weight values ​​to nodes in the neural network 110. In at least one embodiment, the untrained neural network 110 is a feedforward neural network. In at least one embodiment, the untrained neural network 110 is a radial basis function neural network. In at least one embodiment, the untrained neural network 110 is a recurrent neural network. In at least one embodiment, the untrained neural network 110 is a convolutional neural network. In at least one embodiment, the untrained neural network 110 is a modular neural network. In at least one embodiment, the untrained neural network 110 is any other type of neural network suitable for training to perform inference and other deep learning operations.

[0054] In at least one embodiment, the training framework 108 trains an untrained neural network 110 comprising trainable logic to determine logit values. In at least one embodiment, the logit values ​​are raw predicted values. In at least one embodiment, the logit values ​​can be any numeric, Boolean, or other value. In at least one embodiment, the training framework 108 trains the untrained neural network 110, such as those described herein, to perform operations such as classification. In at least one embodiment, the training framework 108 trains the untrained neural network 110 based on training data 102. In at least one embodiment, the training data 102 comprises images. In at least one embodiment, the training data 102 comprises text. In at least one embodiment, the training data 102 comprises raw data. In at least one embodiment, the training data 102 is any other type of data suitable for training the untrained neural network 110 using the training framework 108. In at least one embodiment, the training data 102 is supervised training data. In at least one embodiment, the training data 102 is unsupervised training data. In at least one embodiment, the training data 102 is a mixture of supervised and unsupervised training data. In at least one embodiment, training data 102 is any other type of supervised or unsupervised data suitable for training untrained neural network 110 .

[0055] In at least one embodiment, training data 102 must be prepared and / or transformed 106 for use by training framework 108 to train untrained neural network 110 as described herein. In at least one embodiment, training data 102 is unformatted. In at least one embodiment, training data 102 includes a variable format that is not suitable for training untrained neural network 110. In at least one embodiment, data preparation and transformation 106 prepares the data for use in training untrained neural network 110. In at least one embodiment, for example, data preparation and transformation 106 applies one or more transformations or computations to training data 102 to place it in a format suitable for training untrained neural network 110 via training framework 108. In at least one embodiment, one or more transformations or computations applied by data preparation and transformation 106 are unordered. In at least one embodiment, one or more transformations or computations applied by data preparation and transformation 106 must be specifically ordered. In at least one embodiment, one or more transformations or computations applied by data preparation and transformation 106 are reordered to optimize the transformation of training data 102.

[0056] In at least one embodiment, a training framework 108 trains an untrained neural network 110 using training data 102 that has been prepared and transformed 106 to facilitate neural network training. In at least one embodiment, the training framework 108 produces a trained neural network 112. In at least one embodiment, the trained neural network 112 determines one or more results 114 based on the new data 104 through deep learning inference or other inference. In at least one embodiment, the new data 104 is prepared and transformed 106 using the techniques described herein to perform deep learning inference or other inference using the trained neural network 112.

[0057] Figure 2 A system for training and inference using a neural network with acceleration 216 through one or more parallel processing units (PPUs) 218 ​​is shown in accordance with at least one embodiment. In at least one embodiment, a training framework 208 as described herein is used to train an untrained neural network 210 to perform one or more operations, such as classification, as described herein. In at least one embodiment, the training framework 208 uses training data 202 to train the untrained neural network 210, as further described herein, to perform operations based on information learned from the training data 202.

[0058] In at least one embodiment, before training framework 208 can train untrained neural network 210, input training data 202 is prepared and transformed 206 to ensure that input training data 202 is in a format usable by training framework 208 for training untrained neural network 210. In at least one embodiment, one or more transformations are applied 206 to prepare training data 202 for use by training framework 208 to train untrained neural network 210. In at least one embodiment, applying 206 transformations may not be necessary to prepare training data 202 for use by training framework 208 to train untrained neural network 210. In at least one embodiment, one or more transformations used in data preparation and transformation 206 apply calculations and other mathematical operations to training data 202, as further described herein. In at least one embodiment, one or more transformations used in data preparation and transformation 206 apply other non-mathematical operations to training data 202, as further described herein.

[0059] In at least one embodiment, one or more transformations for data preparation and transformation 206 are accelerated by one or more PPUs 218, including graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more PPUs 218, such as GPUs, implement 216 all of the transformations described herein for performing data preparation and transformation 206. In at least one embodiment, one or more PPUs 218, such as GPUs, implement 216 a portion of the transformations described herein for performing data preparation and transformation 206. In at least one embodiment, one or more PPUs 218, such as GPUs, implement 216 a portion of the training framework 208 for training an untrained neural network 210 as described herein. In at least one embodiment, one or more PPUs 218, such as GPUs, work in conjunction with one or more central processing units (CPUs) to apply one or more transformations, as described herein, to prepare and transform 206 training data 202 for use by the training framework 208 in training an untrained neural network 210 as described herein.

[0060] Figure 3 A sequence of example transformations 308, 310, 312, 314, 316, 318, 320 is shown to prepare input data 302 for training and inference using a neural network, according to at least one embodiment. In at least one embodiment, input data 302, as described above, is prepared and transformed 304 to create transformed data 306 suitable for training an untrained neural network via a training framework, as described herein. In at least one embodiment, data preparation and transformation 304 is a collection of transformations 308, 310, 312, 314, 316, 318, 320 to prepare input data 302 for use by a training framework to train an untrained neural network. In at least one embodiment, data preparation and transformation 304 is a collection of transformations 308, 310, 312, 314, 316, 318, 320 to prepare input data 302 for inference using a trained neural network.

[0061] In at least one embodiment, example transformations 308, 310, 312, 314, 316, 318, 320 illustrate a sequence of data transformations to be applied to input data 302 to generate transformed data 306 suitable for training an untrained neural network. In at least one embodiment, the sequence of data transformations 308, 310, 312, 314, 316, 318, 320 has a specific order. In at least one embodiment, the sequence of data transformations 308, 310, 312, 314, 316, 318, 320 is unordered.

[0062] In at least one embodiment, example transforms include data transforms for medical imaging. In at least one embodiment, example transforms include data transforms capable of processing 2-, 3-, and 4-dimensional medical data, including raw and reconstructed data volumes. In at least one embodiment, example transforms include general transforms as well as those specific to a modality, such as an imaging modality and associated data type. In at least one embodiment, example transforms include data transforms that are not specific to the application space. In at least one embodiment, example transforms include transforms that load specific values ​​associated with input data 308. In at least one embodiment, example transforms include transforms that transform 3D values ​​into a 4D array 310. In at least one embodiment, example transforms include transforms that adjust intensity values ​​312 on input data 302, such as an image. In at least one embodiment, example transforms include transforms that extract rectangular subvolumes 314 from input data 302, such as an image. In at least one embodiment, example transforms include transforms that randomly flip 316 input data 302, such as an image, horizontally or vertically. In at least one embodiment, example transforms include transforms that randomly rotate points in the X, Y plane 318 of input data 302 (e.g., an image). In at least one embodiment, an example transformation includes a transformation that scales the input data 302 intensity oscillations 320 .

[0063] In at least one embodiment, the data input and output dimensions between each data transformation in the data transformation sequence 308, 310, 312, 314, 316, 318, 320 are variable. In at least one embodiment, the data input and output dimensions between each data transformation in the data transformation sequence 308, 310, 312, 314, 316, 318, 320 are fixed. In at least one embodiment, each data transformation in the data transformation sequence 308, 310, 312, 314, 316, 318, 320 has variable memory and computation time requirements.

[0064] Figure 4 The percentage of time that each example transformation processes data used in training an untrained neural network and in inference using a trained neural network, according to at least one embodiment, is shown. In at least one embodiment, data transformations such as the example transformations 402, 404, 406, 408, 410, 412, 414 described herein have varying memory and compute time requirements when executed by a central processing unit (CPU) or a parallel processing unit (PPU), such as a graphics processing unit (GPU). In at least one embodiment, some transformations have high memory or compute time requirements 402, 408, 410, 414. In at least one embodiment, some transformations have low memory or compute time requirements 404, 406, 412.

[0065] In at least one embodiment, data transformations 402, 408, 410, 414 with high memory or compute time requirements can be accelerated by implementation on a PPU (such as a GPU). In at least one embodiment, data transformations accelerated by implementation on a PPU (such as a GPU) are limited by memory requirements. In at least one embodiment, data transformations are selected for implementation on a PPU (such as a GPU) based on whether their memory requirements exceed the available memory on one or more PPUs, including a GPU. In at least one embodiment, one or more data transformations are selected for implementation on a PPU, including a GPU, based on their total memory requirements and other considerations described below, to be performed in conjunction with other transformations performed by one or more CPUs.

[0066] Figure 5 An example sequence of transformations for preparing data for training a neural network and performing inference using the trained neural network is shown, wherein a subset of the example transformations 512, 516, 522 are performed by a graphics processing unit (GPU) and the remaining example transformations are performed by a central processing unit (CPU), according to at least one embodiment. In at least one embodiment, input data 502 is prepared and transformed 504 using a series of transformations, partially implemented on the CPU and partially implemented on one or more parallel processing units (PPUs), such as GPUs, to create transformed data 506 for use by a training framework to train an untrained neural network. In at least one embodiment, one or more transformations 512, 516, 522 are implemented for acceleration by one or more PPUs (e.g., one or more GPUs).

[0067] In at least one embodiment, the transformation is selected for implementation on one or more PPUs (e.g., one or more GPUs) based on computational time and memory requirements. In at least one embodiment, the transformation must have memory requirements that can be satisfied by the available memory of the one or more PPUs (including one or more GPUs). In at least one embodiment, additional considerations, as described below, determine whether to implement the transformation on one or more PPUs (e.g., one or more GPUs).

[0068] In at least one embodiment, some data transformations must be performed sequentially, where the output from one input matches the dimensions of the input of the next transformation in the transformation sequence. In at least one embodiment, an example transformation that transforms 3D data points into a 4D array 508 includes data output having dimensions supported by a subsequent transformation 512. In at least one embodiment, because the subsequent transformation 512 is implemented for acceleration by one or more PPUs (including GPUs), data is copied from memory associated with the one or more CPUs implementing the previous transformation 508 to memory associated with the one or more PPUs (including GPUs) implementing the subsequent transformation 512. In at least one embodiment, once the accelerated data transformation 512 completes its operation, the data is copied back to memory associated with the one or more CPUs 510.

[0069] In at least one embodiment, if a subsequent transformation 516 after copying the data to memory associated with the one or more CPUs is accelerated or executed by one or more PPUs (e.g., GPUs), an additional copy of the results 510 from the previous data transformation 512 to memory associated with the one or more PPUs (such as GPUs) must be performed in order to execute the subsequent accelerated transformation 516. In at least one embodiment, the results from the subsequent accelerated transformation 516 are then copied back 514 to memory associated with the one or more CPUs for use by the additional data transformation in the sequence of data transformations.

[0070] In at least one embodiment, after one or more CPUs have executed a series of data transformations, additional individual data transformations 522 can be accelerated by one or more PPUs (e.g., GPUs). In at least one embodiment, at any point in the data transformation sequence where subsequent individual transformations 522 are executed or accelerated by one or more PPUs (e.g., GPUs), the data must be copied from the memory storing the results of the previous sequence transformations 518 to memory associated with one or more PPUs (e.g., GPUs) for use by the additional individual accelerated transformations 522. In at least one embodiment, after the additional individual accelerated transformations 522 have completed processing, the results are then copied 520 from the memory associated with one or more PPUs (including GPUs) to memory associated with one or more CPUs. In at least one embodiment, once the sequence of transformations, whether ordered or unordered, is complete, the transformed data 506 is ready to be used by the training framework to train an untrained neural network.

[0071] Figure 6An example sequence of transformations for preparing data for training a neural network and performing inference using the trained neural network is shown, according to at least one embodiment, wherein a subset of the example transformations have been combined into a main transformation 610 performed by one or more parallel processing units (PPUs), such as one or more graphics processing units (GPUs), with the remaining example transformations being individually performed by one or more central processing units (CPUs). In at least one embodiment, input data 602 is prepared and transformed 604 using a series of data transformations, partially implemented on one or more CPUs and partially implemented on one or more PPUs (e.g., one or more GPUs), to create transformed data 606 for use by a training framework to train an untrained neural network. In at least one embodiment, one or more transformations are combined into a main transformation 610, which includes transformations that, when combined, meet specific requirements, as described herein, so as to be processed serially by one or more PPUs (including GPUs) without transferring execution back to one or more CPUs and without copying intermediate data from memory associated with one or more PPUs (e.g., GPUs) to memory associated with one or more CPUs. In at least one embodiment, transforms 616 implemented for acceleration or processing by one or more PPUs (including one or more GPUs) but not included in main transform 610 are individually processed by one or more PPUs (eg, one or more GPUs).

[0072] In at least one embodiment, multiple transforms in a transform sequence that meet memory and data requirements are aggregated into a master transform 610 for acceleration or processing by one or more PPUs (e.g., one or more GPUs). In at least one embodiment, the transforms to be aggregated into the master transform 610 must have aggregated memory requirements that meet the constraints imposed by one or more PPUs (e.g., GPUs). In at least one embodiment, the master transform 610 that aggregates the transforms must not require more memory than is available on one or more PPUs (e.g., GPUs).

[0073] In at least one embodiment, the transforms to be aggregated into the main transform 610 must have compatible data inputs and outputs. In at least one embodiment, data inputs and outputs are compatible if they have dimensions and types that allow one transform to be performed after another without further modifying the data dimensions or data types. For example, in at least one embodiment, a data transform that outputs an NxN matrix cannot provide its output to a subsequent data transform that requires a KxK input without additional data processing, such as padding or trimming. In at least one embodiment, a data transform that only outputs a KxK output will match a subsequent data transform that requires a KxK data input.

[0074] In at least one embodiment, the main transformation 610 includes two or more data transformations from a data transformation sequence that includes compatible data inputs and outputs. In at least one embodiment, the main transformation 610 includes two or more data transformations that collectively have memory requirements that can be satisfied by one or more PPUs (such as GPUs). In at least one embodiment, the data outputs of each data transformation in the data transformation sequence executed on one or more CPUs are transferred 608 from memory associated with one or more CPUs to memory associated with one or more PPUs (e.g., one or more GPUs), and the data outputs are used as inputs to the main transformation 610. In at least one embodiment, the main transformation 610 performs two or more aggregated data transformation operations using one or more PPUs (e.g., one or more GPUs). In at least one embodiment, the data outputs from the main transformation 610 are transferred 612 from memory associated with one or more PPUs (e.g., one or more GPUs) to memory associated with one or more CPUs. In at least one embodiment, the data outputs 612 from the main transformation 610 are then used by the remaining data transformations in the data transformation sequence.

[0075] In at least one embodiment, additional individual data transformations 616 not included in the main transformation 610 can also be accelerated by one or more PPUs (e.g., one or more GPUs). In at least one embodiment, at any point in the data transformation sequence, when subsequent individual transformations 616 not included in the main transformation 610 are executed or accelerated by one or more PPUs (e.g., one or more GPUs), data must be copied or transferred 614 from the memory storing the results of the previous transformation sequence to memory associated with one or more PPUs (e.g., one or more GPUs) for use by the additional individual accelerated transformations 616. In at least one embodiment, after the additional individual accelerated transformations 616 have completed processing, the results are then copied 618 from the memory associated with the one or more PPUs (e.g., one or more GPUs) to memory associated with one or more CPUs. In at least one embodiment, once the ordered or unordered transformation sequence including one or more main transformations 610 is completed, the transformed data 606 is ready to be used by the training framework to train an untrained neural network.

[0076] Figure 7A system is shown for determining one or more primary transforms, each comprising two or more data transforms, based on a sequence of transforms to be executed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment. In at least one embodiment, a system configuration 702 is known, indicating the computational and memory resources on the system implementing the one or more primary transforms, as described above. In at least one embodiment, the system configuration 702 and input data 704, as described above, are used by a component, such as a system analyzer 708, to determine the computational and resource availability of the system implementing the one or more primary transforms to prepare data for training one or more untrained neural networks.

[0077] In at least one embodiment, input data 704, as described above and further herein, is used by an input transformation designer 710. In at least one embodiment, input transformation designer 710 is a set of software modules that contain instructions that, when executed, perform operations to determine information regarding data transformations. In at least one embodiment, input transformation designer 710 determines the total computational and memory requirements to transform input data 704 for training an untrained neural network, as described herein. In at least one embodiment, input transformation designer 710 determines a predefined sequence of data transformations for transforming input data 704 for training an untrained neural network.

[0078] In at least one embodiment, the transformation controller 712 controls the determination of one or more primary transformations, given a profile of available compute and memory resources and the transformations 706 to be applied, such as those determined by the system analyzer 708 and the input transformation designer 710. In at least one embodiment, the transformation controller 712 includes a transformation analyzer 714 or other component or method to determine the computational requirements of each transformation implementation or kernel for specific input data 704. In at least one embodiment, the transformation controller 712 uses the transformation analyzer 714 or other component or method to determine internal PPU (or GPU) memory requirements when processing the transformations. In at least one embodiment, the transformation controller 712 utilizes the transformation analyzer 714 or other component or method to determine the input and output data dimensions of each transformation in the sequence of transformations to be applied, such as those determined by the input transformation designer 710.

[0079] In at least one embodiment, the resource monitoring engine 716 monitors available memory used during the transformation analysis 714 on specific input data 704. In at least one embodiment, the resource monitoring engine 716 imposes limits on transformation resource usage in order to determine the impact of the limits on computation and memory performance of the transformation analysis 714. In at least one embodiment, the resource monitoring engine 716 provides other resource usage information that is used by the transformation controller to determine individual resource consumption profiles and sequences of data transformations when applied to specific input data 704.

[0080] In at least one embodiment, the master transformation framework 718 utilizes information from the system analyzer 708, the input transformation designer 710, and the transformation controller 712 to determine an optimal transformation configuration or an optimal transformation sequence for a given set of transformations, system resource availability, and input data. In at least one embodiment, the master transformation designer 720 combines two or more transformations in the transformation sequence determined by the master transformation framework 718 into one or more master transformations. In at least one embodiment, two or more master transformations are created if multiple groups of two or more transformations in the transformation sequence determined by the master transformation framework 718 are independently combined. In at least one embodiment, a user explicitly allocates additional memory on one or more parallel processing units and specifies two or more data transformations with mismatched input and output dimensions. In at least one embodiment, combining two or more data transformations with mismatched input and output dimensions can optimize PPU resource utilization and efficient use of PPU memory registers when the transformations cannot match based on input and output dimensions.

[0081] In at least one embodiment, the master transform designer 720 creates an updated implementation or kernel for one or more master transforms, each master transform comprising two or more data transforms that are processed or executed by one or more PPUs (e.g., one or more GPUs). In at least one embodiment, the master transform designer 720 provides an implementation of an efficient memory allocation mechanism for using a single GPU to execute multiple transforms that are operated in parallel through multi-threaded CPU calls. In at least one embodiment, the master transform designer 720 merges two or more transforms into a single master transform. In at least one embodiment, the master transform designer 720 merges one or more groups of two or more transforms into multiple master transforms based on input and output data compatibility and memory and computational time requirements in the transform sequence, as described above. In at least one embodiment, the master transform designer 720 outputs an updated before-after transform sequence 722 that comprises one or more master transforms for training an untrained neural network, as described herein.

[0082] Figure 8A process for determining one or more primary transforms, each comprising two or more data transforms from a transform sequence to be executed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), is shown in accordance with at least one embodiment. In at least one embodiment, the process for determining a pre-transform sequence and a post-transform sequence comprising one or more primary transforms begins 802 by determining a system configuration 804, including available processing and memory resources on a system implementing the data transforms for training an untrained neural network, as described above. In at least one embodiment, the available data transforms are configured 806, as described above, to determine a sequence of data transforms to be applied to input data in preparation for training the untrained neural network.

[0083] In at least one embodiment, a transformation controller, as described above, configures the input data in a set of data transformations to determine the computational time and memory resource requirements for each transformation, as well as the transformation data input and output dimensions, as described above. In at least one embodiment, the transformations in the transformation sequence are optimized 810 based on the techniques and information described above. Once the transformation sequence has been optimized, in at least one embodiment, one or more master transformations are designed 812 from the optimized transformation sequence, and an optimized software implementation or kernel is generated, as described above. In at least one embodiment, after the master transformation designer 812 generates one or more master transformations, each master transformation comprising two or more data transformations, an optimized before and after transformation sequence comprising the one or more master transformations is output 814, and the process for generating the optimized transformation sequence comprising the one or more master transformations is completed 816.

[0084] Reasoning and training logic

[0085] Figure 9A Inference and / or training logic 915 is shown for performing inference and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Provides details regarding the inference and / or training logic 915.

[0086] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 901 stores input / output data during training and / or inference using aspects of one or more embodiments and / or weight parameters during forward propagation of weight parameters for each layer of a neural network trained or used in conjunction with one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0087] In at least one embodiment, any portion of code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 901 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 901 is internal or external to a processor, for example, or composed of DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage space on or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0088] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, code and / or data storage 905 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 905 stores weight parameters and / or input / output data for each layer of the neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 905 is internal or external to the processor, for example, whether it is composed of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in inference and / or training of the neural network, or some combination of these factors.

[0089] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially identical storage structures and partially different storage structures. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0090] In at least one embodiment, inference and / or training logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 920, which are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, activations are performed in response to executing instructions or other code, linear algebra and / or matrix-based mathematics performed by ALU 910 to generate activations stored in activation storage 920, wherein weight values ​​stored in code and / or data storage 905 and / or in code and / or data storage 901 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 905 or code and / or data storage 901 or other on-chip or off-chip storage.

[0091] In at least one embodiment, one or more ALUs 910 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, one or more ALUs 910 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, data store 901, code and / or data store 905, and activation store 920 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be on different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation store 920 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0092] In at least one embodiment, activation storage 920 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 920 may be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, activation storage 920 may be selected to be internal or external to the processor, for example, or to comprise DRAM, SRAM, flash memory, or other storage types, depending on the storage available on or off chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors. In at least one embodiment, Figure 9A The inference and / or training logic 915 shown in FIG can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9A The illustrated inference and / or training logic 915 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0093] Figure 9B Inference and / or training logic 915 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 915 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B The inference and / or training logic 915 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9BThe inference and / or training logic 915 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 9B In at least one embodiment shown in FIG, code and / or data storage 901 and code and / or data storage 905 are each associated with dedicated computing resources, such as computing hardware 902 and computing hardware 906, respectively. In at least one embodiment, computing hardware 902 and computing hardware 906 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 901 and code and / or data storage 905, respectively, with the results of the functions being stored in activation storage 920.

[0094] In at least one embodiment, each of the code and / or data stores 901 and 905 and the corresponding computing hardware 902 and 906 corresponds to a different layer of a neural network, such that activations from one "storage / compute pair 901 / 902" of code and / or data store 901 and computing hardware 902 are provided as input to the next "storage / compute pair 905 / 906" of code and / or data store 905 and computing hardware 906, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 901 / 902 and 905 / 906 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 915 after or in parallel with the storage / compute pairs 901 / 902 and 905 / 906.

[0095] Neural network training and deployment

[0096] Figure 10The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights can be randomly selected or pre-trained using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0097] In at least one embodiment, untrained neural network 1006 is trained using supervised learning, where training dataset 1002 includes inputs paired with expected outputs for the inputs, or where training dataset 1002 includes inputs with known outputs and neural network 1006 is a manually layered output. In at least one embodiment, untrained neural network 1006 is trained in a supervised manner, processing inputs from training dataset 1002 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 1006. In at least one embodiment, training framework 1004 adjusts the weights that control untrained neural network 1006. In at least one embodiment, training framework 1004 includes tools for monitoring the degree to which untrained neural network 1006 converges to a model (e.g., trained neural network 1008) suitable for generating correct answers (e.g., results 1014) based on known input data (e.g., new dataset 1012). In at least one embodiment, the training framework 1004 iteratively trains the untrained neural network 1006 while adjusting the weights to improve the output of the untrained neural network 1006 using a loss function and an adjustment algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0098] In at least one embodiment, untrained neural network 1006 is trained using unsupervised learning, wherein untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1002 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 1006 can learn groupings within training dataset 1002 and can determine how individual inputs relate to untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1008 capable of performing operations useful for reducing the dimensionality of new dataset 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 1012 that deviate from the normal pattern of new dataset 1012.

[0099] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, for example, through a transfer learning technique. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to new datasets 1012 without forgetting the knowledge infused into the network during initial training.

[0100] Data Center

[0101] Figure 11 An example data center 1100 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0102] In at least one embodiment, Figure 11As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, group computing resources 1114, and node computing resources ("node CRs") 1116(1)-1116(N), where "N" represents any whole positive integer. In at least one embodiment, the node CRs 1116(1)-1116(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1116(1)-1116(N) may be a server having one or more of the above-mentioned computing resources.

[0103] In at least one embodiment, the grouped computing resources 1114 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 1114 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0104] In at least one embodiment, resource coordinator 1112 may configure or otherwise control one or more nodes CR 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may comprise a software design infrastructure ("SDI") management entity for data center 1100. In at least one embodiment, resource coordinator may comprise hardware, software, or some combination thereof.

[0105] In at least one embodiment, Figure 11As shown, the framework layer 1120 includes a job scheduler 1132, a configuration manager 1134, a resource manager 1136, and a distributed file system 1138. In at least one embodiment, the framework layer 1120 may include a framework that supports the software 1132 of the software layer 1130 and / or one or more applications 1142 of the application layer 1140. In at least one embodiment, the software 1132 or the application 1142 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 1138 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1132 may include a Spark driver to facilitate scheduling workloads supported by the various layers of the data center 1100. In at least one embodiment, the configuration manager 1134 may be capable of configuring the various layers, such as the software layer 1130 and the framework layer 1120 including Spark and a distributed file system 1138 for supporting large-scale data processing. In at least one embodiment, the resource manager 1136 may be capable of managing the cluster or group computing resources mapped to or allocated to support the distributed file system 1138 and the job scheduler 1132. In at least one embodiment, the cluster or group computing resources may include the group computing resources 1114 on the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1136 may coordinate with the resource coordinator 1112 to manage these mapped or allocated computing resources.

[0106] In at least one embodiment, the software 1132 included in the software layer 1130 may include software used by at least a portion of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1138 of the framework layer 1120. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0107] In at least one embodiment, the one or more applications 1142 included in the application layer 1140 may include one or more types of applications used by at least a portion of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1138 of the framework layer 1120. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0108] In at least one embodiment, any of configuration manager 1134, resource manager 1136, and resource coordinator 1112 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1100 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0109] In at least one embodiment, data center 1100 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using the resources described above with respect to data center 1100.

[0110] In at least one embodiment, a data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0111] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9BProvides details about the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be configured in the system Figure 11 for use in inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0112] In at least one embodiment, the reasoning and / or training logic 2 may be used in the system Figure 11 In the present invention, the present invention can perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0113] autonomous vehicles

[0114] Figure 12A An example of an autonomous vehicle 1200 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 1200 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0115] Automated driving vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") and the Society of Automotive Engineers ("SAE") under the U.S. Department of Transportation, "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of this standard). In one or more embodiments, the vehicle 1200 may be capable of functioning according to one or more of the levels 1 to 5 of automated driving. For example, in at least one embodiment, the vehicle 1200 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0116] In at least one embodiment, the vehicle 1200 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1200 may include, but is not limited to, a propulsion system 1250, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1250 may be connected to a drive train of the vehicle 1200, which may include, but is not limited to, a transmission, to enable propulsion of the vehicle 1200. In at least one embodiment, the propulsion system 1250 may be controlled in response to receiving a signal from a throttle / accelerator 1252.

[0117] In at least one embodiment, when propulsion system 1250 is operating (e.g., when the vehicle is traveling), a steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, steering system 1254 may receive signals from steering actuator 1256. A steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1246 may be used to operate the vehicle brakes in response to signals received from brake actuator 1248 and / or brake sensors.

[0118] In at least one embodiment, the controller 1236 may include, but is not limited to, one or more system-on-chips ("SoCs") ( Figure 12A1200 ). The controller 1236 may include a graphics processing unit (GPU) (not shown) and / or a graphics processing unit (GPU) to provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 1200. For example, in at least one embodiment, the controller 1236 may send signals to operate vehicle brakes via a brake actuator 1248, to operate a steering system 1254 via one or more steering actuators 1256, and to operate a propulsion system 1250 via one or more throttles / accelerators 1252. The controller 1236 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist a driver in driving the vehicle 1200. In at least one embodiment, the one or more controllers 1236 may include a first controller 1236 for autonomous driving functionality, a second controller 1236 for functional safety functionality, a third controller 1236 for artificial intelligence functionality (e.g., computer vision), a fourth controller 1236 for infotainment functionality, a fifth controller 1236 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1236 may handle two or more of the above functions, two or more controllers 1236 may handle a single function, and / or any combination thereof.

[0119] In at least one embodiment, the one or more controllers 1236 provide signals for controlling one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1258 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more inertial measurement unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360 degree cameras), long range cameras (e.g., infrared cameras), and / or a combination of these. Figure 12A Not shown), mid-range camera ( Figure 12A), one or more speed sensors 1244 (e.g., for measuring the speed of the vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more brake sensors (e.g., as part of a brake sensor system 1246), and / or other sensor types are received.

[0120] In at least one embodiment, one or more controllers 1236 may receive input (e.g., represented by input data) from a dashboard 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1234, an audible annunciator, a speaker, and / or other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 12A ), location data (e.g., the location of the vehicle 1200, such as on a map), directions, the locations of other vehicles (e.g., occupancy barriers), information about objects and the states of objects sensed by the one or more controllers 1236, etc. For example, in at least one embodiment, the HMI display 1234 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0121] In at least one embodiment, the vehicle 1200 further includes a network interface 1224 that can communicate over one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, the network interface 1224 may be capable of communicating via Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. In at least one embodiment, the one or more wireless antennas 1226 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., LoRaWAN, SigFox, etc.) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0122] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Provides details about the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be configured in the system Figure 12A for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0123] In at least one embodiment, the reasoning and / or training logic 2 may be used in the system Figure 12A In the present invention, the present invention can perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0124] Figure 12B According to at least one embodiment, Figure 12A An example of camera locations and fields of view for an autonomous vehicle 1200 is shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on the vehicle 1200.

[0125] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1200. The camera may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera having an RCCC, RCCB, and / or RBGC filter array, may be used in an effort to improve photosensitivity.

[0126] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0127] In at least one embodiment, one or more of the cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to cut out stray light and reflections from within the vehicle (e.g., reflections of the dashboard reflecting in the windshield mirror) that might interfere with the camera's ability to capture image data. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated within four pillars at each corner of the cabin.

[0128] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 1200 can be used for surround vision, as well as to help identify the forward path and obstacles with the assistance of one or more controllers 1236 and / or control SoCs, thereby providing information that is critical for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition).

[0129] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the road, or bicycles). Although Figure 12BOnly one wide-angle camera 1270 is shown in FIG. 1 , however, in other embodiments, any number (including zero) of wide-angle cameras 1270 may be present on the vehicle 1200 . In at least one embodiment, any number of remote cameras 1298 (e.g., a remote stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the remote cameras 1298 may also be used for object detection and classification, as well as basic object tracking.

[0130] In at least one embodiment, any number of stereo cameras 1268 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1268 may include an integrated control unit including a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1200's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera samples (one on each side) and an image processing chip that may measure the distance from the vehicle 1200 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 may be used in addition to those described herein.

[0131] In at least one embodiment, a camera having a field of view of a portion of the environment including the sides of the vehicle 1200 (e.g., a side view camera) can be used for surround viewing to provide information for creating and updating the occupancy grid and generating side collision warnings. For example, in at least one embodiment, the surround camera 1274 (e.g., Figure 12B Four surround cameras 1274 (shown) can be positioned on the vehicle 1200. The one or more surround cameras 1274 can include, but are not limited to, any number and combination of wide-angle cameras 1270, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fisheye cameras can be located on the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0132] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1200 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0133] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B , details regarding the reasoning and / or training logic 915 are provided herein. In at least one embodiment, the reasoning and / or training logic 915 may be Figure 12B for use in a system for performing inference or prediction operations based at least in part on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein.

[0134] In at least one embodiment, the reasoning and / or training logic 2 may be used in the system Figure 12B In the present invention, the present invention can perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0135] Figure 12C According to at least one embodiment, Figure 12A A block diagram of an example system architecture for an autonomous vehicle 1200 is provided. In at least one embodiment, Figure 12C Each of one or more components, one or more features, and one or more systems of vehicle 1200 is shown as being connected via bus 1202. In at least one embodiment, bus 1202 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 1200 that facilitates control of various features and functions of vehicle 1200, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 1202 may be configured with dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1202 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1202 may be an ASIL B compliant CAN bus.

[0136] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or in addition to CAN. In at least one embodiment, any number of buses 1202 may be present, including, but not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1202 may be used to perform different functions and / or for redundancy. For example, a first bus 1202 may be used for collision avoidance, and a second bus 1202 may be used for actuation control. In at least one embodiment, each bus 1202 may communicate with any component of the vehicle 1200, and two or more buses 1202 may communicate with the same component. In at least one embodiment, each of any number of system-on-chips ("SoCs") 1204, each of one or more controllers 1236, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 1200) and may be connected to a common bus, such as a CAN bus.

[0137] In at least one embodiment, the vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to Figure 12A Those described. Controller 1236 can be used for a variety of functions. In at least one embodiment, controller 1236 can be coupled to any of the various other components and systems of vehicle 1200 and can be used to control vehicle 1200, artificial intelligence of vehicle 1200, infotainment of vehicle 1200, and / or similar functions.

[0138] In at least one embodiment, the vehicle 1200 may include any number of SoCs 1204. Each of the SoCs 1204 may include, but is not limited to, a central processing unit ("CPU(s)") 1206, a graphics processing unit ("GPU(s")) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data stores 1216, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1204 may be used to control the vehicle 1200 in various platforms and systems. For example, in at least one embodiment, the one or more SoCs 1204 may be combined in a system (e.g., a system of the vehicle 1200) with a high-definition ("HD") map 1222 that may be downloaded from one or more servers (e.g., a system of the vehicle 1200) via a network interface 1224. Figure 12C) to obtain map refreshes and / or updates.

[0139] In at least one embodiment, one or more CPUs 1206 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1206 may be active at any given time.

[0140] In at least one embodiment, one or more CPUs 1206 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently powered; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0141] In at least one embodiment, one or more GPUs 1208 may include an integrated GPU (or "iGPU" herein). In at least one embodiment, one or more GPUs 1208 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may utilize an enhanced tensor instruction set in at least one embodiment. In one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may utilize a computing application programming interface (API). In at least one embodiment, one or more GPUs 1208 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0142] In at least one embodiment, one or more GPUs 1208 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1208 can be fabricated on fin field-effect transistors (“FinFETs”). In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level-0 (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point datapaths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0143] In at least one embodiment, one or more GPUs 1208 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0144] In at least one embodiment, the one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow the one or more GPUs 1208 to directly access the one or more CPUs 1206 page tables. In at least one embodiment, when the one or more GPUs 1208 memory management units ("MMUs") experience a miss, an address translation request may be sent to the one or more CPUs 1206. In response, in at least one embodiment, the one or more CPUs 1206 may look up the virtual-to-physical mapping of the address in its page table and transmit the translation back to the one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1206 and the one or more GPUs 1208, thereby simplifying programming the one or more GPUs 1208 and porting applications to the one or more GPUs 1208.

[0145] In at least one embodiment, one or more GPUs 1208 may include any number of access counters that can track the frequency with which one or more GPUs 1208 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0146] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a level 3 ("L3") cache available to one or more CPUs 1206 and one or more GPUs 1208 (e.g., connected to both CPUs 1206 and GPUs 1208). In at least one embodiment, one or more caches 1212 may include a write-back cache that can track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB or more, depending on the embodiment, although smaller cache sizes may be used.

[0147] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks of one or more GPUs 1208 (e.g., freeing up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0148] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). One or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and reasoning. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone 1296; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0149] In at least one embodiment, a DLA can perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1208. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1208 and / or other one or more accelerators 1214.

[0150] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator ("PVA"), which may be referred to herein alternatively as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1238, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. One or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0151] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0152] In at least one embodiment, the DMA can enable components of one or more PVAs to access system memory independently of one or more CPUs 1206. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more addressing dimensions, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0153] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0154] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0155] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, which includes, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0156] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0157] In at least one embodiment, one or more SoCs 1204 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0158] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to the algorithmic domain that requires predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small data sets, that require predictable runtimes with low latency and low power. In at least one embodiment, an autonomous vehicle, such as vehicle 1200, the PVA is designed to run classic computer vision algorithms because they are efficient at object detection and integer math operations.

[0159] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0160] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0161] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. For example, in at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In an embodiment using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1266 associated with vehicle 1200 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1264 or one or more RADAR sensors 1260), etc.

[0162] In at least one embodiment, one or more SoCs 1204 may include one or more data stores 1216 (e.g., memory). In at least one embodiment, one or more data stores 1216 may be on-chip memory of one or more SoCs 1204 that may store neural networks to be executed on one or more GPUs 1208 and / or DLAs. In at least one embodiment, one or more data stores 1216 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1212 may include an L2 or L3 cache.

[0163] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). Processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, one or more SoCs 1204 thermal and temperature sensor management, and / or one or more SoCs 1204 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1204 may use the ring oscillator to detect the temperature of one or more CPUs 1206, one or more GPUs 1208, and / or one or more accelerators 1214. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1204 into a lower power consumption state and / or place the vehicle 1200 into a driver's safe parking pattern (e.g., bringing the vehicle 1200 to a safe stop).

[0164] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine can be an audio subsystem that can provide full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0165] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0166] In at least one embodiment, one or more processors 1210 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0167] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce the final video, thereby generating the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1204, the neural network being configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, but are otherwise disabled.

[0168] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image.

[0169] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, without requiring one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1208 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0170] In at least one embodiment, one or more SoCs 1204 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more SoCs 1204 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0171] In at least one embodiment, the one or more SoCs 1204 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders ("codecs"), power management, and / or other devices. The one or more SoCs 1204 may be used to process data from cameras (e.g., via Gigabit multimedia serial links and Ethernet connections), sensors (e.g., one or more LIDAR sensors 1264, one or more RADAR sensors 1260, etc., which may be connected via Ethernet), data from the bus 1202 (e.g., vehicle 1200 speed, steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., via Ethernet or CAN bus connections), etc. In at least one embodiment, the one or more SoCs 1204 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to offload the one or more CPUs 1206 from routine data management tasks.

[0172] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data storage devices 1216, can provide a fast and efficient platform for Level 3-5 autonomous driving vehicles.

[0173] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., the C programming language) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0174] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and allow the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1220) may include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the symbols and pass this semantic understanding to a path planning module running on the CPU Complex.

[0175] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: flashing lights indicate icy conditions" along with lights can be interpreted by multiple neural networks independently or collectively. In at least one embodiment, the sign itself can be identified as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1208.

[0176] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1200. In at least one embodiment, an always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0177] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use the CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approaching speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1262 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0178] In at least one embodiment, the vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1218 may include an X86 processor, for example, and the one or more CPUs 1218 may be used to perform any of a variety of functions, including, for example, arbitrating potential inconsistent results between ADAS sensors and the one or more SoCs 1204, and / or monitoring the status and health of one or more controllers 1236 and / or an information system on a chip ("information SoC") 1230.

[0179] In at least one embodiment, the vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, the one or more GPUs 1220 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input (e.g., sensor data) from sensors of the vehicle 1200.

[0180] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas 1226 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., a passenger's client device) via the cloud (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1200 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. The vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1200). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1200.

[0181] In at least one embodiment, the network interface 1224 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, the network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0182] In at least one embodiment, the vehicle 1200 may further include one or more data stores 1228, which may include, but are not limited to, off-chip (e.g., one or more SoCs 1204) storage. In at least one embodiment, the one or more data stores 1228 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0183] In at least one embodiment, the vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or assisted-GPS sensors) to assist with mapping, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example, but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0184] In at least one embodiment, the vehicle 1200 may further include one or more RADAR sensors 1260. One or more RADAR sensors 1260 may be used by the vehicle 1200 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. One or more RADAR sensors 1260 may use CAN and / or bus 1202 (e.g., to transmit data generated by one or more RADAR sensors 1260) for control and access to object tracking data, and in some examples may access Ethernet to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1260 are pulse Doppler RADAR sensors.

[0185] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 meters). In at least one embodiment, one or more RADAR sensors 1260 can help distinguish between static and moving objects and can be used by the ADAS system 1238 for emergency brake assistance and forward collision warning. The one or more sensors 1260 included in the long-range RADAR system may include, but are not limited to, a monostatic multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the central four antennas, can create a focused beam pattern designed to record the surroundings of the vehicle 1200 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may provide an expanded field of view, allowing for quick detection of vehicles entering or exiting the vehicle's 1200 lane.

[0186] In at least one embodiment, as an example, a medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor blind spots behind and near the vehicle. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1238 for blind spot detection and / or lane change assistance.

[0187] In at least one embodiment, the vehicle 1200 may further include one or more ultrasonic sensors 1262. One or more ultrasonic sensors 1262, which may be positioned on the front, rear, and / or sides of the vehicle 1200, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1262 may operate at a functional safety level of ASIL B.

[0188] In at least one embodiment, the vehicle 1200 can include one or more LIDAR sensors 1264. The one or more LIDAR sensors 1264 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1264 can be functional safety level ASIL B. In at least one embodiment, the vehicle 1200 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1264 that can use Ethernet (e.g., provide data to a Gigabit Ethernet switch).

[0189] In at least one embodiment, one or more LIDAR sensors 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1264 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support 100 Mbps Ethernet connectivity. In at least one embodiment, one or more non-obtrusive LIDAR sensors 1264 may be used. In such an embodiment, one or more LIDAR sensors 1264 may be implemented as small devices that can be embedded in the front, rear, sides, and / or corners of the vehicle 1200. In at least one embodiment, one or more LIDAR sensors 1264 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 1264 may be configured for a horizontal field of view between 45 and 135 degrees.

[0190] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1200 to the object. In at least one embodiment, flash LIDAR can allow for the generation of a highly accurate and distortion-free image of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0191] In at least one embodiment, the vehicle 1200 may also include one or more IMU sensors 1266. In at least one embodiment, the one or more IMU sensors 1266 may be located at the center of the rear axle of the vehicle 1200. In at least one embodiment, the one or more IMU sensors 1266 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1266 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1266 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0192] In at least one embodiment, one or more IMU sensors 1266 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 1266 can enable vehicle 1200 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 can be combined in a single integrated unit.

[0193] In at least one embodiment, the vehicle 1200 can include one or more microphones 1296 positioned within and / or around the vehicle 1200. In at least one embodiment, the one or more microphones 1296 can be used for emergency vehicle detection and identification, among other things.

[0194] In at least one embodiment, the vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long range cameras 1298, one or more mid range cameras 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1200. In at least one embodiment, the type of camera used depends on the vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1200. In at least one embodiment, the number of cameras may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. The cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet. In at least one embodiment, the present disclosure previously referred to herein may provide a plurality of cameras. Figure 12A and Figure 12B Each camera can be described in more detail.

[0195] In at least one embodiment, vehicle 1200 may further include one or more vibration sensors 1242. One or more vibration sensors 1242 may measure vibration of a component (e.g., an axle) of vehicle 1200. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0196] In at least one embodiment, the vehicle 1200 may include an ADAS system 1238. The ADAS system 1238 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1238 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0197] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to vehicles immediately adjacent to the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1200 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0198] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 1224 and / or one or more wireless antennas 1226. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1200 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 1200, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0199] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0200] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking on impending collisions.

[0201] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1200 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure by activating a turn signal. In at least one embodiment, the LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, a LKA system is a variation of the LDW system. If the vehicle 1200 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 1200.

[0202] In at least one embodiment, the BSW system detects and warns the driver of vehicles in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0203] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the rear camera range while the vehicle 1200 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0204] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1200 itself decides whether to follow the results of the primary or secondary computer (e.g., the first or second controller 1236 of the controller 1236). For example, in at least one embodiment, the ADAS system 1238 can be a backup and / or auxiliary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 can be provided to a supervisory MCU. In at least one embodiment, if the outputs of the primary and secondary computers conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0205] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary computer and the secondary computer indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0206] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine, based at least in part on outputs from the primary and secondary computers, conditions under which the secondary computer provides a false alarm. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1204.

[0207] In at least one embodiment, the ADAS system 1238 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and a different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0208] In at least one embodiment, the output of the ADAS system 1238 can be input into the primary computer's perception module and / or the primary computer's dynamic driving task module. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception module can use this information when identifying the object. In at least one embodiment, as described herein, the secondary computer can have its own neural network that has been trained to reduce the risk of false positives.

[0209] In at least one embodiment, the vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system 1230 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle. For example, the infotainment SoC 1230 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 1234, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0210] In at least one embodiment, the infotainment SoC 1230 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 can communicate with other devices, systems, and / or components of the vehicle 1200 via a bus 1202 (e.g., a CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1230 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of the main controller 1236 (e.g., the vehicle's 1200 main computer and / or backup computer). In at least one embodiment, the infotainment SoC 1230 can cause the vehicle 1200 to enter a driver-to-safety stop mode, as described herein.

[0211] In at least one embodiment, the vehicle 1200 may further include an instrument panel 1232 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). The instrument panel 1232 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument panel 1232 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the instrument panel 1232. In at least one embodiment, the instrument panel 1232 may be included as part of the infotainment SoC 1230, or vice versa.

[0212] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Provides details about the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be configured in the system Figure 12C for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0213] In at least one embodiment, the reasoning and / or training logic 2 may be used in the system Figure 12C In the present invention, the present invention can perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0214] Figure 12D In accordance with at least one embodiment, a cloud-based server and Figure 12A 12. A diagram of a system 1276 for communicating between autonomous vehicles 1200 is provided. In at least one embodiment, system 1276 may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. One or more servers 1278 may include, but is not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(H) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with high-speed connections, such as, but not limited to, NVLink interfaces 1288 developed by NVIDIA and / or PCIe connections 1286. In at least one embodiment, the GPUs 1284 are connected via NVLink and / or NVSwitch SoC, and the GPUs 1284 and PCIe switches 1282 are connected via a PCIe interconnect. In at least one embodiment, although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1278 may include, but is not limited to, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0215] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 1278 may transmit an updated neural network 1292 and / or map information 1294, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 1290. In at least one embodiment, updates to the map information 1294 may include, but not limited to, updates to the HD map 1222, such as information regarding construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1292, updated neural network 1292, and / or map information 1294 may be generated by new training and / or experience represented by data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 1278 and / or other servers).

[0216] In at least one embodiment, one or more servers 1278 can be used to train a machine learning model (e.g., a neural network) based at least in part on training data. The training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1290, and / or the machine learning model can be used by one or more servers 1278 to remotely monitor the vehicle.

[0217] In at least one embodiment, one or more servers 1278 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1278 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 can include the deep learning infrastructure of a data center using CPU power.

[0218] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1200, such as an image sequence and / or objects located within that image sequence by the vehicle 1200 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1200, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1200 is malfunctioning, the one or more servers 1278 may send a signal to the vehicle 1200 instructing the vehicle's 1200 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0219] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, hardware structure 915 is used to execute one or more embodiments. Figure 9A and / or Figure 9B Provides details about the hardware structure 915.

[0220] Computer system

[0221] Figure 13 1300, which may include an execution unit to execute instructions. In at least one embodiment, the computer system 1300 may include, but is not limited to, components such as a processor 1302, whose execution unit includes logic to execute algorithms for processing data in accordance with the present disclosure, such as the embodiments described herein. In at least one embodiment, the computer system 1300 may include, but is not limited to, a processor such as a processor 1302, whose execution unit includes logic to execute algorithms for processing data. In at least one embodiment, the computer system 1300 may include a processor such as the Intel® processor 1302 available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1300 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0222] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0223] In at least one embodiment, computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 13 is a single-processor desktop or server system, but in another embodiment, system 13 may be a multi-processor system. In at least one embodiment, processor 1302 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 may be coupled to a processor bus 1310, which may transmit data signals between processor 1302 and other components in computer system 1300.

[0224] In at least one embodiment, processor 1302 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1302. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1306 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0225] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating point operations, is also located in the processor 1302. The processor 1302 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of the general-purpose processor 1302, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1302. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0226] In at least one embodiment, execution unit 1308 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. Memory 1320 may store instructions 1319 and / or data 1321 represented by data signals that may be executed by processor 1302.

[0227] In at least one embodiment, the system logic chip can be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1316, and the processor 1302 can communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 can provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 can initiate data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O 1322. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to the memory 1320 via a high-bandwidth memory path 1318 , and the graphics / video card 1312 may be coupled to the MCH 1316 via an Accelerated Graphics Port (“AGP”) interconnect 1314 .

[0228] In at least one embodiment, computer system 1300 may use system I / O 1322, which is a proprietary hub interface bus, to couple MCH 1316 to I / O controller hub ("ICH") 1330. In at least one embodiment, ICH 1330 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub ("FlashBIOS") 1328, a wireless transceiver 1326, a data store 1324, a legacy I / O controller 1323 including a user input and keyboard interface, a serial expansion port 1327 (e.g., a universal serial bus (USB)), and a network controller 1334. The data store 1324 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0229] In at least one embodiment, Figure 13 A system is shown that includes interconnected hardware devices or "chips," while in other embodiments, Figure 13An exemplary system-on-chip (SoC) may be shown. In at least one embodiment, the devices shown in FIG. cc may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1300 are interconnected using a Compute Express Link (CXL) interconnect.

[0230] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A 9B provide details about the reasoning and / or training logic 915. In at least one embodiment, the reasoning and / or training logic 915 can be used in the system Figure 13 for performing inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0231] In at least one embodiment, the reasoning and / or training logic 2 may be used in the system Figure 13 In the present invention, the present invention can perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0232] Figure 14 1 is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0233] In at least one embodiment, system 1400 may include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (versions 1, 2, 3), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 14 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 14 An exemplary system-on-chip (SoC) may be shown. In at least one embodiment, Figure 14The devices shown in FIG can be interconnected with a dedicated interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, a Compute Express Link (CXL) interconnect is used to interconnect the Figure 14 One or more components of .

[0234] In at least one embodiment, Figure 14 It may include a display 1424, a touch screen 1425, a touchpad 1430, a near field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, a fast chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, a BIOS / firmware / flash (“BIOS, FW flash”) 1422, a DSP 1460, a drive 1420 “SSD or HDD” (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera), or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0235] In at least one embodiment, other components may be communicatively coupled to processor 1410 via the components discussed above. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1446, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1464, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1464 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450 and the Bluetooth unit 1452 and WWAN unit 1456 may be implemented in a next generation form factor ("NGFF").

[0236] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A 9B provides details about the reasoning and / or training logic 915. In at least one embodiment, the reasoning and / or training logic 915 may be Figure 14 The invention provides a system for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network usage described herein.

[0237] In at least one embodiment, the reasoning and / or training logic 2 may be used in the system Figure 14 In the present invention, the present invention can perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0238] Figure 15 Illustrated is a computer system 1500 in accordance with at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0239] In at least one embodiment, computer system 1500 includes, but is not limited to, at least one central processing unit ("CPU") 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1500 includes, but is not limited to, main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1504, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1522 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems having computer system 1500.

[0240] In at least one embodiment, computer system 1500 includes, but is not limited to, input device 1508, parallel processing system 1512, and display device 1506, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device 1508, such as a keyboard, mouse, touchpad, microphone, or more. In at least one embodiment, each of the aforementioned modules may be located on a single semiconductor platform to form a processing system.

[0241] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A 9B provide details about the reasoning and / or training logic 915. In at least one embodiment, the reasoning and / or training logic 915 can be used in the system Figure 15 for performing inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0242] In at least one embodiment, the reasoning and / or training logic 2 may be used in the system Figure 15 In the present invention, the present invention can perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0243] Figure 16 A computer system 1600 is shown in accordance with at least one embodiment. In at least one embodiment, computer system 1600 includes, but is not limited to, a computer 1610 and a USB stick 1620. In at least one embodiment, computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1610 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0244] In at least one embodiment, the USB stick 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing core 1630 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1630 comprises an application specific integrated circuit ("ASIC") optimized to perform any amount and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1630 is a tensor processing unit ("TPC") optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1630 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0245] In at least one embodiment, USB interface 1640 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1650 can include any amount and type of logic that enables processing unit 1630 to interface with a device (e.g., computer 1610) via USB connector 1640.

[0246] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 can be used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0247] In at least one embodiment, the reasoning and / or training logic 2 may be used in the system Figure 16 In the present invention, the present invention can perform inference and prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0248] Figure 17AAn exemplary architecture is shown in which multiple GPUs 1710-1713 are communicatively coupled to multiple multi-core processors 1705-1706 via high-speed links 1740-1743 (e.g., buses / point-to-point interconnects, etc.). In one embodiment, the high-speed links 1740-1743 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0249] Furthermore, in one embodiment, two or more GPUs 1710-1713 are interconnected via high-speed links 1729-1730, which may be implemented using the same or different protocols / links as used for high-speed links 1740-1743. Similarly, two or more multi-core processors 1705-1706 may be connected via high-speed link 1728, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocol / links may be used (e.g., via a common interconnect fabric). Figure 17A All communications between the various system components shown in .

[0250] In at least one embodiment, each multi-core processor 1705-1706 is communicatively coupled to processor memory 1701-1702 via memory interconnects 1726-1727, respectively, and each GPU 1710-1713 is communicatively coupled to GPU memory 1720-1723 via GPU memory interconnects 1750-1753, respectively. Memory interconnects 1726-1727 and 1750-1753 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1701-1702 and GPU memory 1720-1723 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 1701-1702 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0251] As described herein, although the various processors 1705-1706 and GPUs 1710-1713 may be physically coupled to specific memories 1701-1702, 1720-1723, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across the various physical memories. For example, the processor memories 1701-1702 may each contain 64GB of system memory address space, and the GPU memories 1720-1723 may each contain 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0252] Figure 17B 17. Additional details are shown for the interconnection between the multi-core processor 1707 and the graphics acceleration module 1746 according to an exemplary embodiment. The graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to the processor 1707 via a high-speed link 1740. Alternatively, the graphics acceleration module 1746 may be integrated on the same package or chip as the processor 1707.

[0253] In at least one embodiment, the illustrated processor 1707 includes a plurality of cores 1760A-1760D, each having a translation lookaside buffer 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components, not shown, for executing instructions and processing data. The caches 1762A-1762D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1756 may be included in the caches 1762A-1762D and shared by each group of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1707 and the graphics acceleration module 1746 are connected to the system memory 1714, which may include Figure 17A Processor memory 1701-1702 in.

[0254] Coherence is maintained for data and instructions stored in the various caches 1762A-1762D, 1756, and system memory 1714 via inter-core communication over a coherence bus 1764. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1764 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is executed over the coherence bus 1764 to snoop cache accesses.

[0255] In one embodiment, proxy circuitry 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, thereby allowing graphics acceleration module 1746 to participate in a cache coherence protocol as a peer of cores 1760A-1760D. Specifically, interface 1735 provides connectivity to proxy circuitry 1725 via high-speed link 1740 (e.g., PCIe bus, NVLink, etc.), and interface 1737 connects graphics acceleration module 1746 to link 1740.

[0256] In one implementation, the accelerator integrated circuit 1736 represents the multiple graphics processing engines 1731, 1732, N of the graphics acceleration module and provides cache management, memory access, context management, and interrupt management services. The graphics processing engines 1731, 1732, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1731, 1732, N may comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731-1732, N, or the graphics processing engines 1731-1732, N may be individual GPUs integrated into a common package, line card, or chip.

[0257] In one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1714. The MMU 1739 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1738 stores commands and data for efficient access by graphics processing engines 1731-1732, N. In at least one embodiment, data stored in cache 1738 and graphics memory 1733-1734, M is kept consistent with core caches 1762A-1762D, 1756, and system memory 1714. As previously described, this task may be accomplished via proxy circuitry 1725 acting on behalf of cache 1738 and graphics memory 1731-1732, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1762A-1762D, 1756 to cache 1738 and receiving updates from cache 1738).

[0258] A set of registers 1745 stores context data for threads executed by graphics processing engines 1731-1732, N, and context management circuitry 1748 manages thread contexts. For example, context management circuitry 1748 can perform save and restore operations to save and restore the context of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1748 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to context. In one embodiment, interrupt management circuitry 1747 receives and processes interrupts received from system devices.

[0259] In one implementation, the MMU 1739 converts virtual / effective addresses from the graphics processing engine 1731 into real / physical addresses in the system memory 1714. One embodiment of the accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. The graphics accelerator module 1746 can be dedicated to a single application executing on the processor 1707, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1731-1732, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0260] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge to the system for the graphics acceleration module 1746 and provides address translation and system memory caching services. In addition, the accelerator integrated circuit 1736 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1731-1732.

[0261] Because the hardware resources of graphics processing engines 1731-1732, N are explicitly mapped into the real address space seen by host processor 1707, any host processor can directly address these resources using effective address values. In one embodiment, one function of accelerator integrated circuit 1736 is to physically separate graphics processing engines 1731-1732, N so that they appear as independent units to the system.

[0262] In at least one embodiment, one or more graphics memories 1733-1734, M are respectively coupled to each graphics processing engine 1731-1732, N. Graphics memories 1733-1734, M store instructions and data, which are processed by each graphics processing engine 1731-1732, N. Graphics memories 1733-1734, M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0263] In one embodiment, to reduce data traffic on link 1740, a biasing technique is used to ensure that the data stored in graphics memory 1733-1734, M is the data most frequently used by graphics processing engines 1731-1732, N, and preferably not used (at least not frequently) by cores 1760A-1760D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 1731-1732, N) in the core's cache 1762A-1762D, 1756 core, and system memory 1714.

[0264] Figure 17C Another exemplary embodiment is shown in which an accelerator integrated circuit 1736 is integrated into the processor 1707. In this embodiment, the graphics processing engines 1731-1732, N communicate directly with the accelerator integrated circuit 1736 via the interface 1737 and the interface 1735 (which may also utilize any form of bus or interface protocol) through a high-speed link 1740. The accelerator integrated circuit 1736 can perform operations related to Figure 17B The operations described above are identical to those described above. However, due to its close proximity to the coherence bus 1764 and caches 1762A-1762D, 1756, higher throughput is possible. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1736 and a programming model controlled by the graphics acceleration module 1746.

[0265] In at least one embodiment, graphics processing engines 1731-1732, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1731-1732, N, thereby providing virtualization within a VM / partition.

[0266] In at least one embodiment, graphics processing engines 1731-1732,N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1731-1732,N to allow each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1731-1732,N. In at least one embodiment, the operating system can virtualize graphics processing engines 1731-1732,N to provide access to each process or application.

[0267] In at least one embodiment, the graphics acceleration module 1746 or individual graphics processing engines 1731-1732,N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1731-1732,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0268] Figure 17D An exemplary accelerator integrated slice 1790 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 1736. An application is an effective address space 1782 in system memory 1714 that stores process elements 1783. In one embodiment, process elements 1783 are stored in response to a GPU call 1781 from an application 1780 executing on processor 1707. Process elements 1783 contain the process state of the corresponding application 1780. A work descriptor (WD) 1784 contained in process element 1783 may be a single job requested by the application, or may contain a pointer to a job queue. In at least one embodiment, WD 1784 is a pointer to a job request queue in the application's address space 1782.

[0269] The graphics acceleration module 1746 and / or the individual graphics processing engines 1731-1732, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment can be included.

[0270] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns a graphics acceleration module 1746 or an individual graphics processing engine 1731. Because the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0271] In operation, the WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1746. Data from the WD 1784 can be stored in registers 1745 and used by the MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page roaming circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. The interrupt management circuitry 1747 can process interrupt events 1792 received from the graphics acceleration module 1746. When executing graphics operations, the effective addresses 1793 generated by the graphics processing engines 1731-1732, N are converted into real addresses by the MMU 1739.

[0272] In one embodiment, the same set of registers 1745 is replicated for each graphics processing engine 1731-1732, N, and / or graphics acceleration module 1746, and the registers 1745 can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1790. Example registers that can be initialized by the hypervisor are shown in Table 1.

[0273] Table 1 – Registers initialized by the hypervisor

[0274]

[0275] Example registers that may be initialized by the operating system are shown in Table 2.

[0276] Table 2 – Registers initialized by the operating system

[0277]

[0278] In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731-1732, N. It contains all the information needed for the graphics processing engine 1731-1732, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0279] Figure 17E 1796 virtualizes the graphics acceleration module engine for the operating system 1795.

[0280] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1746. There are two programming models where the graphics acceleration module 1746 is shared by multiple processes and partitions, time-sliced ​​sharing and graphics-directed sharing.

[0281] In this model, the hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. For the graphics acceleration module 1746 to support virtualization through the hypervisor 1796, the graphics acceleration module 1746 must adhere to the following conditions: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1746 must provide a context save and restore mechanism. 2) The graphics acceleration module 1746 guarantees that application job requests are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1746 provides the ability to preempt job processing. 3) When operating in a directed shared programming model, fairness must be ensured between graphics acceleration module 1746 processes.

[0282] In at least one embodiment, an application 1780 is required to make an operating system 1795 system call using a graphics acceleration module 1746 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1746 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1746 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics acceleration module 1746. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of an application setting the AMR. If the implementation of the accelerator integrated circuit 1736 and graphics acceleration module 1746 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 1796 can optionally apply the current privilege mask overwrite register (AMOR) value before placing the AMR into the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the effective address of an area in the application's address space 1782 for the graphics acceleration module 1746 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be fixed system memory.

[0283] Upon receiving the system call, the operating system 1795 may verify that the application 1780 has been registered and granted permission to use the graphics acceleration module 1746. The operating system 1795 then calls the hypervisor 1796 using the information shown in Table 3.

[0284] Table 3 – OS to Hypervisor call parameters

[0285]

[0286] Upon receiving the hypervisor call, the hypervisor 1796 verifies that the operating system 1795 has registered and been granted permission to use the graphics acceleration module 1746. The hypervisor 1796 then places the process element 1783 into a linked list of process elements of the corresponding graphics acceleration module 1746 type. The process element may include the information shown in Table 4.

[0287] Table 4 – Process element information

[0288]

[0289] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1790 registers 1745 .

[0290] like Figure 17F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 1701-1702 and GPU memories 1720-1723. In this implementation, operations executed on GPUs 1710-1713 utilize the same virtual / effective memory address space to access processor memories 1701-1702, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701, a second portion is allocated to second processor memory 1702, a third portion is allocated to GPU memory 1720, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1701-1702 and GPU memories 1720-1723, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0291] In one embodiment, bias / coherency management circuitry 1794A-1794E within one or more MMUs 1739A-1739E ensures cache coherency between the caches of one or more host processors (e.g., 1705) and GPUs 1710-1713 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 17F Multiple instances of bias / coherence management circuits 1794A- 1794E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1705 and / or within an accelerator integrated circuit 1736 .

[0292] One embodiment allows GPU-attached memory 1720-1723 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memory 1720-1723 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows host processor 1705 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memory 1720-1723 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1710-1713. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0293] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1720-1723, with or without a bias cache in GPUs 1710-1713 (e.g., to cache frequently / recently used entries in the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0294] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU-attached memory 1720-1723 is accessed, resulting in the following operations. First, local requests from GPUs 1710-1713 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1720-1723. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 1705 (e.g., via the high-speed link discussed above). In one embodiment, requests from processor 1705 to find the requested page in the host processor bias complete a request similar to a normal memory read. Alternatively, requests directed to GPU biased pages can be forwarded to GPUs 1710-1713. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism.

[0295] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1705 bias to GPU bias, but not for the reverse migration.

[0296] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1705. To access these pages, processor 1705 may request access from GPU 1710, which may or may not immediately grant access. Therefore, to reduce communication between processor 1705 and GPU 1710, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1705, and vice versa.

[0297] One or more hardware structures 915 are used to implement one or more embodiments. Figure 9A and / or Figure 9B Details regarding one or more of the hardware structures 915 are provided.

[0298] Figure 18An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0299] Figure 18 is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic, including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and a sup.2S / I.sup.2C controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industry Processor Interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870 .

[0300] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in integrated circuit 1800 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0301] In at least one embodiment, inference and / or training logic 2 may be used in integrated circuit 1800 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0302] Figures 19A-19BAn exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0303] Figures 19A-19B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 19A An exemplary graphics processor 1910 of a system-on-chip integrated circuit is shown, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Figure 19B An additional exemplary graphics processor 1940 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 19A The graphics processor 1910 is a low power graphics processor core. In at least one embodiment, Figure 19B The graphics processor 1940 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1910, 1940 can be Figure 18 A variant of the graphics processor 1810.

[0304] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D through 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, such that the vertex processor 1905 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 1905 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1915A-1915N use the primitives and vertex data generated by the vertex processor 1905 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1915A-1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0305] In at least one embodiment, graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, one or more caches 1925A-1925B, and one or more circuit interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide a mapping of virtual to physical addresses for graphics processor 1910, including for vertex processor 1905 and / or fragment processors 1915A-1915N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B may synchronize with other MMUs within the system, including with other MMUs. Figure 18 One or more MMUs associated with one or more application processors 1805, graphics processor 1815, and / or video processor 1820 enable each processor 1805-1820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable graphics processor 1910 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0306] In at least one embodiment, graphics processor 1940 includes one or more MMUs 1920A-1920B, caches 1925A-1925B, and Figure 19A 1930A-1930B of the graphics processor 1910. In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F through 1955N-1 and 1955N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A-1955N and a tiling unit 1958 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0307] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Provides details about the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be implemented in an integrated circuit. Figure 19A and / or Figure 19B for performing inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function or architecture, or a neural network use case described herein.

[0308] In at least one embodiment, inference and / or training logic 2 may be used in integrated circuits 19A and / or 19B for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0309] Figures 20A-20B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 20A Shows that can be included in Figure 18 Graphics core 2000 within graphics processor 1810, and in at least one embodiment, may be such as Figure 19B Unified shader cores 1955A-1955N are shown. Figure 20B A highly parallel, general-purpose graphics processing unit 2030 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0310] In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and cache / shared memory 2020, which are common to execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 may include multiple slices 2001A-2001N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 2000. Slices 2001A-2001N may include support logic including local instruction caches 2004A-2004N, thread schedulers 2006A-2006N, thread dispatchers 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, slices 2001A-2001N may include a set of additional function units (AFUs 2012A-2012N), floating point units (FPUs 2014A-2014N), integer arithmetic logic units (ALUs 2016A-2016N), address calculation units (ACUs 2013A-2013N), double-precision floating point units (DPFPUs 2015A-2015N), and matrix processing units (MPUs 2017A-2017N).

[0311] In at least one embodiment, the FPU 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2015A-2015N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2017A-2017N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2012A-2012N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0312] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9BDetails are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in graphics core 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0313] In at least one embodiment, inference and / or training logic 2 may be used in graphics core 2000 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0314] Figure 20B A general purpose processing unit (GPGPU) 2030 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 2030 can be directly linked to other instances of GPGPU 2030 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2030 includes a host interface 2032 to enable connection to a host processor. In at least one embodiment, host interface 2032 is a PCI Express interface. In at least one embodiment, host interface 2032 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 to assign execution threads associated with those commands to a group of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, cache memory 2038 may serve as a higher level of cache for cache memory within compute clusters 2036A-2036H.

[0315] In at least one embodiment, GPGPU 2030 includes memory 2044A-2044B coupled to compute clusters 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, memory 2044A-2044B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0316] In at least one embodiment, computing clusters 2036A-2036H each include a set of graphics cores, e.g. Figure 20A The graphics core 2000 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning calculations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 2036A-2036H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0317] In at least one embodiment, multiple instances of GPGPU 2030 can be configured to function as a compute cluster. In at least one embodiment, the communication used by compute clusters 2036A-2036H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate via host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to a GPU link 2040, enabling direct connections to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 reside in separate data processing systems and communicate via a network device accessible through host interface 2032. In at least one embodiment, GPU link 2040 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 2032 .

[0318] In at least one embodiment, the GPGPU 2030 can be configured to train a neural network. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment, where the GPGPU 2030 is used for inference, the GPGPU can include fewer compute clusters 2036A-2036H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2044A-2044B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0319] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in GPGPU 2030 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0320] In at least one embodiment, inference and / or training logic 2 may be used in GPGPU 2030 for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0321] Figure 21 A block diagram of a computer system 2100 is shown, according to at least one embodiment. In at least one embodiment, computer system 2100 includes a processing subsystem 2101 having one or more processors 2102 and system memory 2104 communicating via an interconnect path that may include a memory hub 2105. In at least one embodiment, memory hub 2105 may be a separate component within a chipset component or may be integrated within one or more processors 2102. In at least one embodiment, memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In one embodiment, I / O subsystem 2111 includes an I / O hub 2107, which enables computer system 2100 to receive input from one or more input devices 2108. In at least one embodiment, I / O hub 2107 may enable a display controller, which may be included in one or more processors 2102, to provide output to one or more display devices 2110A. In at least one embodiment, the one or more display devices 2110A coupled to the I / O hub 2107 may include local, internal, or embedded display devices.

[0322] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to the memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 can be any of a number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2112 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 2112 form a graphics processing subsystem that can output pixels to one of one or more display devices 2110A coupled via the I / O hub 2107. In at least one embodiment, the one or more parallel processors 2112 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 2110B.

[0323] In at least one embodiment, a system storage unit 2114 can be connected to the I / O hub 2107 to provide a storage mechanism for the computer system 2100. In at least one embodiment, an I / O switch 2116 can be used to provide an interface mechanism to enable connections between the I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2120. In at least one embodiment, the network adapter 2118 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0324] In at least one embodiment, the computer system 2100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2107. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 21 Communication paths for various components in a SoC, such as NV-Link high-speed interconnect or interconnect protocol.

[0325] In at least one embodiment, one or more parallel processors 2112 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2112 include circuits optimized for general-purpose processing. In at least one embodiment, the components of the computer system 2100 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2112, memory hub 2105, processor 2102, and I / O hub 2107 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computer system 2100 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computer system.

[0326] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Provides details about the reasoning and / or training logic 915. In at least one embodiment, the reasoning and / or training logic 915 may be Figure 21 for use in system 2100 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0327] In at least one embodiment, inference and / or training logic 2 may be used in system diagram 2100 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0328] processor

[0329] Figure 22A 2200 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2200 is shown as a processor according to an exemplary embodiment. Figure 21 A variation of the one or more parallel processors 2112 is shown.

[0330] In at least one embodiment, parallel processor 2200 includes parallel processing unit 2202. In at least one embodiment, parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of parallel processing unit 2202. In at least one embodiment, I / O unit 2204 can be directly connected to other devices. In at least one embodiment, I / O unit 2204 connects to other devices using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between memory hub 2105 and I / O unit 2204 forms communication link 2113. In at least one embodiment, I / O unit 2204 is connected to a host interface 2206 and a memory crossbar switch 2216, where host interface 2206 receives commands for performing processing operations and memory crossbar switch 2216 receives commands for performing memory operations.

[0331] In at least one embodiment, when host interface 2206 receives command buffers via I / O unit 2204, host interface 2206 can direct work operations to execute those commands to front end 2208. In at least one embodiment, front end 2208 is coupled to scheduler 2210, which is configured to distribute commands or other work items to processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing cluster array 2212 is properly configured and in a valid state before distributing tasks to processing cluster arrays 2212. In at least one embodiment, scheduler 2210 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2212. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2212 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2212 by scheduler 2210 logic within a microcontroller that includes scheduler 2210 .

[0332] In at least one embodiment, processing cluster array 2212 may include up to "N" processing clusters (e.g., cluster 2214A, cluster 2214B, through cluster 2214N). In at least one embodiment, each cluster 2214A-2214N of processing cluster array 2212 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2210 may allocate work to clusters 2214A-2214N of processing cluster array 2212 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling may be handled dynamically by scheduler 2210 or may be assisted in part by compiler logic during the compilation of program logic configured to be executed by processing cluster array 2212. In at least one embodiment, different clusters 2214A-2214N of processing cluster array 2212 may be assigned to process different types of programs or to perform different types of computations.

[0333] In at least one embodiment, processing cluster array 2212 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2212 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2212 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0334] In at least one embodiment, processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 2202 may transfer data from system memory via I / O units 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) during processing and then written back to system memory.

[0335] In at least one embodiment, when parallel processing unit 2202 is used to perform graphics processing, scheduler 2210 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2214A-2214N of processing cluster array 2212. In at least one embodiment, portions of processing cluster array 2212 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2214A-2214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2214A-2214N for further processing.

[0336] In at least one embodiment, the processing cluster array 2212 can receive processing tasks to be executed via the scheduler 2210, which receives commands defining the processing tasks from the front end 2208. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2210 can be configured to obtain an index corresponding to a task, or can receive the index from the front end 2208. In at least one embodiment, the front end 2208 can be configured to ensure that the processing cluster array 2212 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0337] In at least one embodiment, each of the one or more instances of parallel processing unit 2202 can be coupled to parallel processor memory 2222. In at least one embodiment, parallel processor memory 2222 can be accessed via memory crossbar 2216, which can receive memory requests from processing cluster array 2212 and I / O unit 2204. In at least one embodiment, memory crossbar 2216 can access parallel processor memory 2222 via memory interface 2218. In at least one embodiment, memory interface 2218 can include multiple partition units (e.g., partition unit 2220A, partition unit 2220B, through partition unit 2220N), which can each be coupled to a portion of parallel processor memory 2222 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2220A-2220N are configured to be equal to the number of memory cells, such that the first partition unit 2220A has a corresponding first memory cell 2224A, the second partition unit 2220B has a corresponding memory cell 2224B, and the Nth partition unit 2220N has a corresponding Nth memory cell 2224N. In at least one embodiment, the number of partition units 2220A-2220N may not be equal to the number of memory devices.

[0338] In at least one embodiment, memory units 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2224A-2224N, allowing partition units 2220A-2220N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2222. In at least one embodiment, local instances of parallel processor memory 2222 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0339] In at least one embodiment, any of the clusters 2214A-2214N in the processing cluster array 2212 can process data to be written to any memory unit 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar 2216 can be configured to transmit the output of each cluster 2214A-2214N to any partition unit 2220A-2220N or another cluster 2214A-2214N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with a memory interface 2218 via the memory crossbar 2216 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2216 has connections to memory interface 2218 for communicating with I / O unit 2204, as well as connections to local instances of parallel processor memory 2222, thereby enabling processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory that is not local to parallel processing unit 2202. In at least one embodiment, memory crossbar switch 2216 can use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0340] In at least one embodiment, multiple instances of parallel processing unit 2202 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2202 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2202 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2202 or parallel processor 2200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0341] Figure 22B is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, the partition unit 2220 is Figure 22A220N。In at least one embodiment, the partition unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and an ROP 2226 (raster operation unit). The L2 cache 2221 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2216 and the ROP 2226. In at least one embodiment, the L2 cache 2221 outputs read misses and urgent write-back requests to the frame buffer interface 2225 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2225 for processing. In at least one embodiment, the frame buffer interface 2225 communicates with memory units in the parallel processor memory (such as Figure 22A interacts with one of the memory units 2224A-2224N (e.g., within parallel processor memory 2222).

[0342] In at least one embodiment, ROP 2226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2226 then outputs the processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2226 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 2226 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0343] In at least one embodiment, ROP 2226 is included within each processing cluster (e.g., clusters 2214A-2214N of FIG. 22 ), rather than within partition unit 2220. In at least one embodiment, read and write requests for pixel data are transferred through memory crossbar 2216 rather than pixel fragment data transfers. In at least one embodiment, processed graphics data may be displayed on a display device such as a Figure 21 2100), routed by the processor 2102 for further processing, or by Figure 22A One of the processing entities within parallel processor 2200 is routed for further processing.

[0344] Figure 22C22 is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 2214A-2214N of Figure 22. In at least one embodiment, the processing cluster 2214 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines in each processing cluster.

[0345] In at least one embodiment, the operation of the processing cluster 2214 can be controlled by a pipeline manager 2232 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2232 receives instructions from the scheduler 2210 of FIG. 22 and manages the execution of these instructions by the graphics multiprocessor 2234 and / or the texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 2214. In at least one embodiment, one or more instances of the graphics multiprocessor 2234 can be included within the processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 can process data, and the data crossbar 2240 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2232 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2240.

[0346] In at least one embodiment, each graphics multiprocessor 2234 within a processing cluster 2214 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0347] In at least one embodiment, instructions transmitted to the processing cluster 2214 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2234. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop by the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2234, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2234.

[0348] In at least one embodiment, the graphics multiprocessor 2234 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2234 can abandon the internal cache and use cache memory within the processing cluster 2214 (e.g., L1 cache 2248). In at least one embodiment, each graphics multiprocessor 2234 can also access a partition unit (e.g., Figure 22A L2 cache within partition units 2220A-2220N) of the graphics multiprocessor 2234 is shared across all processing clusters 2214 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2202 can be used as global memory. In at least one embodiment, processing cluster 2214 includes multiple instances of graphics multiprocessor 2234, which can share common instructions and data, which can be stored in L1 cache 2248.

[0349] In at least one embodiment, each processing cluster 2214 may include a memory management unit ("MMU") 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2245 may reside within the memory interface 2218 of FIG. 22 . In at least one embodiment, the MMU 2245 includes a set of page table entries (PTEs) that map virtual addresses to physical addresses of tiles (more on tiling below) and, optionally, to cache line indices. In at least one embodiment, the MMU 2245 may include a translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 2234 or L1 cache or within the processing cluster 2214. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0350] In at least one embodiment, the processing clusters 2214 can be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations, including determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2234, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2234 outputs processed tasks to a data crossbar 2240 to provide the processed tasks to another processing cluster 2214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2216. In at least one embodiment, a preROP 2242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 2220A-2220N of FIG. 22 ). In at least one embodiment, the PreROP 2242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0351] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9BDetails are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 can be used in graphics processing cluster 2214 to perform inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0352] In at least one embodiment, inference and / or training logic 2 may be used in graphics processing cluster 2214 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0353] Figure 22D A graphics multiprocessor 2234 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2234 is coupled to a pipeline manager 2232 of a processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 has an execution pipeline that includes, but is not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more general purpose graphics processing unit (GPGPU) cores 2262, and one or more load / store units 2266. The GPGPU cores 2262 and the load / store units 2266 are coupled to a cache memory 2272 and a shared memory 2270 via a memory and cache interconnect 2268.

[0354] In at least one embodiment, the instruction cache 2252 receives a stream of instructions to be executed from the pipeline manager 2232. In at least one embodiment, the instructions are cached in the instruction cache 2252 and dispatched for execution by the instruction unit 2254. In one embodiment, the instruction unit 2254 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2262. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2266.

[0355] In at least one embodiment, register file 2258 provides a set of registers for the functional units of graphics multiprocessor 2234. In at least one embodiment, register file 2258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2262, load / store unit 2266) connected to graphics multiprocessor 2234. In at least one embodiment, register file 2258 is divided between each functional unit such that a dedicated portion of register file 2258 is allocated to each functional unit. In at least one embodiment, register file 2258 is divided between the different warps being executed by graphics multiprocessor 2234.

[0356] In at least one embodiment, the GPGPU cores 2262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2234. The GPGPU cores 2262 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2262 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2234 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0357] In at least one embodiment, the GPGPU core 2262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0358] In at least one embodiment, the memory and cache interconnect 2268 is an interconnect network that connects each functional unit of the graphics multiprocessor 2234 to the register file 2258 and the shared memory 2270. In at least one embodiment, the memory and cache interconnect 2268 is a crossbar interconnect that allows the load / store unit 2266 to perform load and store operations between the shared memory 2270 and the register file 2258. In at least one embodiment, the register file 2258 can operate at the same frequency as the GPGPU core 2262, resulting in very low latency for data transfers between the GPGPU core 2262 and the register file 2258. In at least one embodiment, the shared memory 2270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2234. In at least one embodiment, the cache memory 2272 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2236. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2272, threads executing on GPGPU core 2262 may programmatically store data in shared memory.

[0359] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0360] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A 9B provide details regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in graphics multiprocessor 2234 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network usage scenarios described herein.

[0361] In at least one embodiment, inference and / or training logic 2 may be used in the graphics multiprocessor 2234 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0362] Figure 23 A multi-GPU computing system 2300 is shown in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 2300 may include a processor 2302 coupled to a plurality of general purpose graphics processing units (GPGPUs) 2306A-D via a host interface switch 2304. In at least one embodiment, host interface switch 2304 is a PCI Express switch device that couples processor 2302 to a PCI Express bus, over which processor 2302 can communicate with GPGPUs 2306A-D. GPGPUs 2306A-D may be interconnected via a set of high-speed, point-to-point GPU-to-GPU links 2316. In at least one embodiment, GPU-to-GPU links 2316 connect to each of GPGPUs 2306A-D via dedicated GPU links. In at least one embodiment, P2P GPU links 2316 enable direct communication between each of GPGPUs 2306A-D without requiring communication over host interface bus 2304 to which processor 2302 is connected. In at least one embodiment, host interface bus 2304 remains available for system memory access or communication with other instances of multi-GPU computing system 2300, for example, via one or more network devices, through GPU-to-GPU traffic directed to P2P GPU link 2316. While in at least one embodiment, GPGPUs 2306A-D are connected to processor 2302 via host interface switch 2304, in at least one embodiment, processor 2302 includes direct support for P2P GPU link 2316 and can connect directly to GPGPUs 2306A-D.

[0363] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A 9B provide details regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in multi-GPU computing system 2300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0364] In at least one embodiment, inference and / or training logic 2 may be used in a multi-GPU computing system 2300 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0365] Figure 24 FIG2 is a block diagram of a graphics processor 2400 according to at least one embodiment. In at least one embodiment, graphics processor 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, ring interconnect 2402 couples graphics processor 2400 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2400 is one of many processors integrated within a multi-core processing system.

[0366] In at least one embodiment, the graphics processor 2400 receives batches of commands via a ring interconnect 2402. In at least one embodiment, the incoming commands are interpreted by a command streamer 2403 in a pipeline front end 2404. In at least one embodiment, the graphics processor 2400 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2403 provides commands to a geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, the command streamer 2403 provides commands to a video front end 2434 coupled to a media engine 2437. In at least one embodiment, the media engine 2437 includes a video quality engine (VQE) 2430 for video and image post-processing and a multi-format encoding / decoding (MFX) 2433 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each generate execution threads for thread execution resources provided by at least one graphics core 2480A.

[0367] In at least one embodiment, the graphics processor 2400 includes scalable thread execution resources featuring modular cores 2480A-2480N (sometimes referred to as core slices), each of which has multiple sub-cores 2450A-2450N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2400 can have any number of graphics cores 2480A-2480N. In at least one embodiment, the graphics processor 2400 includes a graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, the graphics processor 2400 is a low-power processor having a single sub-core (e.g., 2450A). In at least one embodiment, the graphics processor 2400 includes multiple graphics cores 2480A-2480N, each of which includes a set of first sub-cores 2450A-2450N and a set of second sub-cores 2460A-2460N. In at least one embodiment, each of the first sub-cores 2450A-2450N includes at least a first set of execution units 2452A-2452N and media / texture samplers 2454A-2454N. In at least one embodiment, each of the second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each of the sub-cores 2450A-2450N, 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0368] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in graphics processor 2400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network usage scenarios described herein.

[0369] In at least one embodiment, inference and / or training logic 2 may be used in graphics processor 2400 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0370] Figure 25is a block diagram illustrating the microarchitecture of a processor 2500 that may include logic circuitry for executing instructions according to at least one embodiment. In at least one embodiment, the processor 2500 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2510 may include registers for storing packed data, such as the 64-bit wide MMX registers in microprocessors enabled with MMX technology, such as those of Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2510 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0371] In at least one embodiment, the processor 2500 includes an in-order front end ("front end") 2501 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2501 may include several units. In at least one embodiment, an instruction prefetcher 2526 retrieves instructions from memory and provides the instructions to an instruction decoder 2528, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2528 decodes the received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") that the machine can execute. In at least one embodiment, the instruction decoder 2528 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2530 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2534 for execution. In at least one embodiment, when trace cache 2530 encounters a complex instruction, microcode ROM 2532 provides the microinstructions necessary to complete the operation.

[0372] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2528 may access the microcode ROM 2532 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2528. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2532. In at least one embodiment, the trace cache 2530 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2532 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2532 completes the micro-op sequencing for the instruction, the front end 2501 of the machine may resume fetching micro-ops from the trace cache 2530.

[0373] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2503 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2503 includes, but is not limited to, an allocator / register renamer 2540, a memory microinstruction queue 2542, an integer / floating-point microinstruction queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow / general floating-point scheduler ("slow / general FP scheduler") 2504, and a simple floating-point scheduler ("simple FP scheduler") 2506. In at least one embodiment, the fast scheduler 2502, the slow / general floating-point scheduler 2504, and the simple floating-point scheduler 2506 are also collectively referred to as "microinstruction schedulers 2502, 2504, 2506." The allocator / register renamer 2540 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2540 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2540 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2542 for memory operations and an integer / floating point microinstruction queue 2544 for non-memory operations, preceding the memory scheduler 2546 and the microinstruction schedulers 2502, 2504, 2506. In at least one embodiment, the microinstruction schedulers 2502, 2504, 2506 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2502 of at least one embodiment can schedule on every half master clock cycle, while the slow / general floating point scheduler 2504 and the simple floating point scheduler 2506 can schedule once every master processor clock cycle. In at least one embodiment, microinstruction schedulers 2502, 2504, 2506 arbitrate on dispatch ports to schedule microinstructions for execution.

[0374] In at least one embodiment, execution block 2511 includes, but is not limited to, integer register file / branch network 2508, floating point register file / branch network ("FP register file / branch network") 2510, address generation units ("AGUs") 2512 and 2514, fast arithmetic logic units ("fast ALUs") 2516 and 2518, slow arithmetic logic unit ("slow ALU") 2520, floating point ALU ("FP") 2522, and floating point move unit ("FP move") 2524. In at least one embodiment, integer register file / branch network 2508 and floating point register file / bypass network 2510 are also referred to herein as "register files 2508, 2510." In at least one embodiment, AGUs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating-point ALU 2522, and floating-point move unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524." In at least one embodiment, execution block 2511 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0375] In at least one embodiment, register files 2508 and 2510 may be arranged between microinstruction schedulers 2502, 2504, and 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, integer register file / branch network 2508 performs integer operations. In at least one embodiment, floating-point register file / branch network 2510 performs floating-point operations. In at least one embodiment, each of register files 2508 and 2510 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2508 and 2510 may communicate data with each other. In at least one embodiment, integer register file / branch network 2508 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2510 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0376] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524 can execute instructions. In at least one embodiment, register files 2508 and 2510 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2500 can include, but is not limited to, any number of execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524, and combinations thereof. In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2522 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2516 and 2518. In at least one embodiment, fast ALUs 2516 and 2518 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2520, as slow ALU 2520 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUs 2512 and 2514. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2522 and floating point shift unit 2524 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2522 and floating point shift unit 2524 can operate on 128-bit wide packed data operands that can be used in conjunction with SIMD and multimedia instructions.

[0377] In at least one embodiment, the microinstruction schedulers 2502, 2504, and 2506 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2500, processor 2500 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0378] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0379] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the execution block 2511 and other memories or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in the execution block 2511. Additionally, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution block 2511 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0380] In at least one embodiment, part or all of the inference and / or training logic 2 may be incorporated into the EXE block 2511 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in the EXE block 2511. Additionally, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the EXE block 2511 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0381] Figure 26 A deep learning application processor 2600 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2600 uses instructions that, if executed by the deep learning application processor 2600, cause the deep learning application processor 2600 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2600 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2600 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor 2600 includes, but is not limited to, processing clusters 2610(1)-2610(12), inter-chip links (“ICLs”) 2620(1)-2620(12), inter-chip controllers (“ICCs”) 2630(1)-2630(2), second generation high bandwidth memory (“HBM2”) 2640(1)-2640(4), memory controllers (“Mem Ctrlr”) 2642(1)-2642(4), high bandwidth memory physical layer (“HBM PHY”) 2644(1)-2644(4), a management controller central processing unit (“management controller CPU”) 2650, serial peripheral interface, inter-integrated circuit, and general purpose input / output blocks (“SPI, I2C, GPIO”) 2660, a peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 2670, and a sixteen-lane peripheral component interconnect express port (“PCI Express”). x 16”)2680.

[0382] In at least one embodiment, the processing cluster 2610 can perform deep learning operations, including inference or prediction operations based on weight parameters calculated by one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2610 can include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2600 can include any number and type of processing clusters 2600. In at least one embodiment, the inter-chip link 2620 is bidirectional. In at least one embodiment, the inter-chip link 2620 and the inter-chip controller 2630 enable multiple deep learning application processors 2600 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2600 can include any number (including zero) and type of ICLs 2620 and ICCs 2630.

[0383] In at least one embodiment, HBM22640 provides a total of 32GB of memory. HBM22640(i) is associated with both a memory controller 2642(i) and an HBM PHY 2644(i). In at least one embodiment, any number of HBM22640 can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2642 and HBM PHYs 2644. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 2660, DMA 2670, and / or PCIe 2680 can be replaced with any number and type of blocks to implement any number and type of communication standards in any technically feasible manner.

[0384] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Provides details regarding inference and / or training logic 915. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2600. In at least one embodiment, the deep learning application processor 2600 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2600. In at least one embodiment, the processor 2600 can be used to perform one or more of the neural network use cases described herein.

[0385] Figure 27is a block diagram of a neuromorphic processor 2700 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2700 can receive one or more inputs from a source external to the neuromorphic processor 2700. In at least one embodiment, these inputs can be transmitted to one or more neurons 2702 within the neuromorphic processor 2700. In at least one embodiment, the neurons 2702 and their components can be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2700 can include, but is not limited to, thousands of instances of neurons 2702, although any suitable number of neurons 2702 can be used. In at least one embodiment, each instance of a neuron 2702 can include a neuron input 2704 and a neuron output 2706. In at least one embodiment, a neuron 2702 can generate an output that can be transmitted to the inputs of other instances of the neuron 2702. In at least one embodiment, the neuron input 2704 and the neuron output 2706 can be interconnected via a synapse 2708.

[0386] In at least one embodiment, the neurons 2702 and synapses 2708 can be interconnected so that the neuromorphic processor 2700 operates to process or analyze information received by the neuromorphic processor 2700. In at least one embodiment, the neuron 2702 can send an output pulse (or "trigger" or "spike") when the input received through the neuron input 2704 exceeds a threshold. In at least one embodiment, the neuron 2702 can sum or integrate the signal received at the neuron input 2704. For example, in at least one embodiment, the neuron 2702 can be implemented as a leaky integrate-and-trigger neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2702 can generate an output (or "trigger") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-and-trigger neuron can sum the signal received at the neuron input 2704 into a membrane potential and can apply an application attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may trigger if multiple input signals are received at neuron input 2704 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2702 may be implemented using circuitry or logic that receives input, integrates the input into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2702 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2706 when the result of applying the transfer function to neuron input 2704 exceeds a threshold. In at least one embodiment, once neuron 2702 triggers, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2702 may resume normal operation after a suitable period of time (or recovery period).

[0387] In at least one embodiment, neurons 2702 can be interconnected via synapses 2708. In at least one embodiment, synapses 2708 can be operable to transmit a signal from the output of a first neuron 2702 to the input of a second neuron 2702. In at least one embodiment, a neuron 2702 can transmit information across more than one instance of synapse 2708. In at least one embodiment, one or more instances of a neuron output 2706 can be connected to an instance of a neuron input 2704 in the same neuron 2702 via an instance of synapse 2708. In at least one embodiment, an instance of a neuron 2702 that generates an output to be transmitted across an instance of synapse 2708 can be referred to as a "presynaptic neuron" relative to that instance of synapse 2708. In at least one embodiment, an instance of a neuron 2702 that receives an input transmitted across an instance of synapse 2708 can be referred to as a "postsynaptic neuron" relative to an instance of synapse 2708. In at least one embodiment, with respect to the various instances of synapses 2708, because an instance of neuron 2702 can receive input from one or more instances of synapses 2708 and can also transmit output through one or more instances of synapses 2708, a single instance of neuron 2702 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0388] In at least one embodiment, neurons 2702 may be organized into one or more layers. Each instance of a neuron 2702 may have a neuron output 2706 that may fan out to one or more neuron inputs 2704 via one or more synapses 2708. In at least one embodiment, the neuron output 2706 of a neuron 2702 in a first layer 2710 may be connected to the neuron input 2704 of a neuron 2702 in a second layer 2712. In at least one embodiment, layers 2710 may be referred to as "feed-forward layers." In at least one embodiment, each instance of a neuron 2702 in an instance of the first layer 2710 may fan out to each instance of a neuron 2702 in the second layer 2712. In at least one embodiment, the first layer 2710 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 2702 in each instance of the second layer 2712 may fan out to fewer than all instances of a neuron 2702 in the third layer 2714. In at least one embodiment, the second layer 2712 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, neurons 2702 in a second layer 2712 can fan out to neurons 2702 in multiple other layers, including fanning out to neurons 2702 in the (same) second layer 2712. In at least one embodiment, the second layer 2712 can be referred to as a "recurrent layer." The neuromorphic processor 2700 can include, but is not limited to, any suitable combination of recurrent layers and feed-forward layers, including, but not limited to, sparsely connected feed-forward layers and fully connected feed-forward layers.

[0389] In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, a reconfigurable interconnect fabric or a dedicated hardwired interconnect to connect synapses 2708 to neurons 2702. In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2702 as needed based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2708 may be connected to neurons 2702 using an interconnect fabric such as a network on a chip or through dedicated connections. In at least one embodiment, the synaptic interconnect and its components may be implemented using circuitry or logic.

[0390] Figure 2828. A processing system according to at least one embodiment is shown. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2802 or processor cores 2807. In at least one embodiment, system 2800 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0391] In at least one embodiment, the system 2800 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the system 2800 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2800 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2800 is a television or set-top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.

[0392] In at least one embodiment, one or more processors 2802 each include one or more processor cores 2807 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2807 is configured to process a specific instruction set 2809. In at least one embodiment, the instruction set 2809 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, the processor cores 2807 can each process a different instruction set 2809, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 2807 can also include other processing devices, such as a digital signal processor (DSP).

[0393] In at least one embodiment, the processor 2802 includes a cache memory 2804. In at least one embodiment, the processor 2802 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2802. In at least one embodiment, the processor 2802 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared among the processor cores 2807 using known cache coherence techniques. In at least one embodiment, the processor 2802 further includes a register file 2806. The processor can include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2806 can include general purpose registers or other registers.

[0394] In at least one embodiment, one or more processors 2802 are coupled to one or more interface buses 2810 to transmit communication signals, such as address, data, or control signals, between the processors 2802 and other components in the system 2800. In at least one embodiment, the interface bus 2810 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2810 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2802 includes an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, the memory controller 2816 facilitates communication between memory devices and other components of the processing system 2800, while the platform controller hub (PCH) 2830 provides connections to input / output (I / O) devices via a local I / O bus.

[0395] In at least one embodiment, memory device 2820 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other suitable memory device for use as processor memory. In at least one embodiment, memory device 2820 may be used as system memory for processing system 2800 to store data 2822 and instructions 2821 for use when one or more processors 2802 execute applications or processes. In at least one embodiment, memory controller 2816 is also coupled to an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 in processor 2802 to perform graphics and media operations. In at least one embodiment, display device 2811 may be connected to processor 2802. In at least one embodiment, display device 2811 may include one or more internal display devices, such as in a mobile electronic device or laptop, or an external display device connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2811 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0396] In at least one embodiment, the platform controller hub 2830 enables peripheral devices to connect to the storage device 2820 and the processor 2802 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, a touch sensor 2825, and a data storage device 2824 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2824 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2825 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2826 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2828 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, a network controller 2834 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2810. In at least one embodiment, an audio controller 2846 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2800 includes an optional legacy I / O controller 2840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, the platform controller hub 2830 can also be connected to one or more universal serial bus (USB) controllers 2842 that connect input devices such as a keyboard and mouse 2843 combination, a camera 2844, or other USB input devices.

[0397] In at least one embodiment, instances of the memory controller 2816 and the platform controller hub 2830 may be integrated into a discrete external graphics processor, such as the external graphics processor 2812. In at least one embodiment, the platform controller hub 2830 and / or the memory controller 2816 may be external to one or more processors 2802. For example, in at least one embodiment, the system 2800 may include an external memory controller 2816 and a platform controller hub 2830, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2802.

[0398] Reasoning and / or training logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9BDetail is provided regarding the inference and / or training logic 915. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the graphics processor 2800. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more ALUs embodied in the 3D pipeline 2812. Additionally, in at least one embodiment, the inference and / or training operations described herein may utilize a number of inference and / or training operations other than the 3D pipeline 2812. Figure 9A or Figure 9B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2800 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0399] In at least one embodiment, some or all of the inference and / or training logic 2 may be incorporated into the graphics processor 2800. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more of the ALUs included in the 3D pipeline 2812. Furthermore, in at least one embodiment, the inference and / or training operations described herein may utilize the same Figure 1 and Figure 2 In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2800 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0400] Figure 29 is a block diagram of a processor 2900 having one or more processor cores 2902A-2902N, an integrated memory controller 2914, and an integrated graphics processor 2908, in accordance with at least one embodiment. In at least one embodiment, the processor 2900 may include additional cores, up to and including the additional core 2902N represented by the dashed box. In at least one embodiment, each processor core 2902A-2902N includes one or more internal cache units 2904A-2904N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2906.

[0401] In at least one embodiment, the internal cache units 2904A-2904N and the shared cache unit 2906 represent a cache memory hierarchy within the processor 2900. In at least one embodiment, the cache memory units 2904A-2904N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is categorized as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2906 and 2904A-2904N.

[0402] In at least one embodiment, the processor 2900 may also include a set of one or more bus controller units 2916 and a system agent core 2910. In at least one embodiment, the one or more bus controller units 2916 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2910 provides management functions for various processor components. In at least one embodiment, the system agent core 2910 includes one or more integrated memory controllers 2914 to manage access to various external memory devices (not shown).

[0403] In at least one embodiment, one or more processor cores 2902A-2902N include support for simultaneous multithreading. In at least one embodiment, system agent core 2910 includes components for coordinating and operating cores 2902A-2902N during multithreaded processing. In at least one embodiment, system agent core 2910 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 2902A-2902N and graphics processor 2908.

[0404] In at least one embodiment, the processor 2900 also includes a graphics processor 2908 for performing graphics processing operations. In at least one embodiment, the graphics processor 2908 is coupled to a shared cache unit 2906 and a system agent core 2910 including one or more integrated memory controllers 2914. In at least one embodiment, the system agent core 2910 also includes a display controller 2911 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2911 may also be a separate module coupled to the graphics processor 2908 via at least one interconnect, or may be integrated within the graphics processor 2908.

[0405] In at least one embodiment, a ring-based interconnect 2912 is used to couple the internal components of the processor 2900. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2908 is coupled to the ring interconnect 2912 via I / O links 2913.

[0406] In at least one embodiment, I / O link 2913 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2918 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2902A-2902N and the graphics processor 2908 uses the embedded memory module 2918 as a shared last-level cache.

[0407] In at least one embodiment, the processor cores 2902A-2902N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2902A-2902N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 2902A-2902N execute a common instruction set, while one or more other processor cores 2902A-2902N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2902A-2902N are heterogeneous in terms of microarchitecture, wherein one or mo...

Claims

1. A processor, comprising: One or more circuits for selecting and combining two or more data transformations from a series of data transformations into a main transformation that is executed by one or more parallel processing units, wherein the series of data transformations are partially implemented on one or more central processing units and partially implemented on one or more parallel processing units, and wherein the two or more data transformations are combined based at least in part on input and output data sizes, memory requirements, and memory availability of the one or more parallel processing units, the two or more data transformations having compatible data inputs and outputs and whose aggregate memory requirements conform to constraints imposed by the one or more parallel processing units. 2 . The processor of claim 1 , wherein the combination of the two or more data transformations is based at least in part on a profile of resource requirements of each of the two or more data transformations.

3. The processor of claim 1 , wherein the combination of the two or more data transformations results in a sequence of instructions that implement operations on data to train one or more neural networks.

4. The processor of claim 3, wherein the sequence of instructions implementing the operation is to be executed by one or more parallel processing units. 5 . The processor of claim 1 , wherein the two or more data transformations are combined based at least in part on a computational time requirement of each of the two or more data transformations. 6 . The processor of claim 1 , wherein the two or more data transformations are combined based at least in part on available memory resources of a computing system.

7. The processor of claim 1, wherein the two or more data transformations are a front transformation and a back transformation and prepare 3-dimensional image data for training a neural network.

8. A system comprising: One or more processors to select and combine two or more data transformations from a series of data transformations into a main transformation that is executed by one or more parallel processing units, wherein the series of data transformations are partially implemented on one or more central processing units and partially implemented on one or more parallel processing units, and wherein the two or more data transformations are combined based at least in part on input and output data sizes, memory requirements, and memory availability of the one or more parallel processing units, the two or more data transformations having compatible data inputs and outputs and whose aggregate memory requirements conform to constraints imposed by the one or more parallel processing units. 9 . The system of claim 8 , wherein the combination of the two or more data transformations is based at least in part on resource requirements of each of the two or more data transformations.

10. The system of claim 8, wherein the combination of the two or more data transforms performs a sequence of operations on three-dimensional (3D) image data.

11. The system of claim 10, wherein the combination of the two or more data transformations is accelerated by one or more parallel processing units.

12. The system of claim 8, wherein the two or more data transformations are combined to reduce a time requirement to apply the series of data transformations.

13. The system of claim 8, wherein the individual data transformations are combined based on available memory resources of a computing system implementing the one or more neural networks.

14. The system of claim 13, wherein the one or more neural networks are trained using data transformed by a combination of the two or more data transformations.

15. The system of claim 8, wherein the two or more data transforms are a front transform and a back transform.

16. The system of claim 8, wherein the two or more data transformations prepare three-dimensional 3D image data for training one or more neural networks.

17. The system of claim 8, wherein: performing a combination of the two or more data transformations; Perform another set of data transformations, and The another set of data transformations consists of individual data transformations from the series of data transformations that are not selected into the combination of the two or more data transformations.

18. A machine-readable medium having stored thereon a set of instructions that, if executed by one or more processors, cause the one or more processors to at least: Two or more data transformations are selected from a series of data transformations and combined into a main transformation that is executed by one or more parallel processing units, wherein the series of data transformations are partially implemented on one or more central processing units and partially implemented on one or more parallel processing units, and wherein the two or more data transformations are combined based at least in part on input and output data sizes, memory requirements, and memory availability of the one or more parallel processing units, the two or more data transformations having compatible data inputs and outputs and whose aggregate memory requirements conform to constraints imposed by the one or more parallel processing units.

19. The machine-readable medium of claim 18, wherein the instructions, when executed, further cause the one or more processors to combine two or more data transformations based at least in part on a profile of resource requirements of each of the two or more data transformations.

20. The machine-readable medium of claim 18, wherein the instructions, when executed, further cause the one or more processors to perform a sequence of data transformation operations on data used to train one or more neural networks, wherein the sequence of data transformation operations is specified by a combination of the two or more data transformations.

21. The machine-readable medium of claim 20, wherein the sequence of data transformation operations is accelerated by one or more graphics processing units.

22. The machine-readable medium of claim 18, wherein the two or more data transformations are combined to reduce computational time required to perform each of the two or more data transformations.

23. The machine-readable medium of claim 18, wherein the two or more data transformations are a front transformation and a back transformation and prepare three-dimensional (3D) image data for training a neural network.

24. A method comprising: selecting two or more data transformations from a series of data transformations, wherein a portion of the series of data transformations is implemented on one or more central processing units and a portion of the series of data transformations is implemented on one or more parallel processing units; The two or more data transformations are combined into a main transformation that is executed by one or more parallel processing units, wherein the two or more data transformations are combined based at least in part on input and output data sizes, memory requirements, and memory availability of the one or more parallel processing units, the two or more data transformations having compatible data inputs and outputs and whose aggregate memory requirements conform to constraints imposed by the one or more parallel processing units.

25. The method of claim 24, wherein the combination of the two or more data transformations is based at least in part on resource requirements of each of the two or more data transformations.

26. The method of claim 24, wherein the combination of the two or more data transforms performs a sequence of operations on three-dimensional (3D) image data.

27. The method of claim 24, wherein the combination of the two or more data transformations is performed and another set of data transformations is performed, and the another set of data transformations is composed of individual data transformations from the series of data transformations that were not selected into the combination of the two or more data transformations.

28. The method of claim 24, wherein the two or more data transformations are selected based on a computational time requirement of each of the respective data transformations.

29. The method of claim 24, wherein the two or more data transformations are selected based on available memory resources of a computing system implementing one or more neural networks.

30. The method of claim 29, wherein the one or more neural networks are trained using data transformed by a combination of the two or more data transformations.

31. The method of claim 29, wherein the one or more neural networks are used to perform inference on data transformed by a combination of the two or more data transformations.

32. The method of claim 24, further comprising preparing three-dimensional (3D) image data for training one or more neural networks using the two or more data transformations.

33. The method of claim 24, wherein the two or more data transformations are performed on a batch of input data.

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