Method, non-transitory computer readable medium, and system for image compression

Abstract

A method includes selecting a target block of pixels to compress from an image; selecting an adjoining column of the target block; selecting an adjoining row of the target block; generating two or more basis values based on at least one of a portion of pixels of the adjoining column and a portion of pixels of the adjoining row; computing a gradient based on the two or more basis values; and assigning at least one predictor for the target block using the computed gradient.

Description

TECHNICAL FIELD

[0001] Embodiments relate to compressing and decompressing images. BACKGROUND

[0002] Image compression / decompression traditionally segments an image into blocks of pixels. During encoding (compression), pixels of previously compressed blocks can be reused as context to predict pixels of a current block. During decoding (decompression), pixels of previously decompressed blocks can be reused as context to predict pixels of a current block. A predictor is an algorithm that takes these contextual samples (typically bordering the block to be compressed / decompressed on its left and top side) as input and output starting values for computing, in the block, prediction values used during compression and / or during decompression, which can be later completed by more encoding information and / or filtered to obtain final reconstructed samples. SUMMARY

[0003] In general aspects, an apparatus, system, non-transitory computer-readable medium (having stored thereon computer-executable program code capable of being executed on a computer system) and / or method can perform a process in a method comprising selecting a target block of pixels to compress from an image, selecting an adjoining column of the target block, selecting an adjoining row of the target block, generating two or more basis values based on at least one of a portion of pixels of the adjoining column and a portion of pixels of the adjoining row, computing a gradient based on the two or more basis values, and assigning at least one predictor for the target block using the computed gradient.

[0004] Implementations can include one or more of the following features. For example, the method can further include generating a residual based on the target block and the predictor. The selecting of the adjoining column can include selecting processed pixels, the selecting of the adjoining row can include selecting processed pixels, the adjoining column can be one of a left column or a right column, and the adjoining row can be one of an above row or a below row. The two or more basis values can be associated with basis pixels located at two or more corner portions of the target block. The two or more basis values can be associated with basis pixels located at two or more corner portions of the target block, and the generating of the two or more basis values can include computing an average of two or more processed pixels.

[0005] For example, the two or more base values can be four base values associated with base pixels located at each corner of the target block, three of the four base values can be computed based on an average of at least one of a portion from pixels of an adjoining column and a portion from pixels of an adjoining row, and a fourth of the four base values can be interpolated based on the three computed base values. The computing of the gradient can include using a gradient algorithm to generate pixel values for each cell in the column x row matrix using a gradual transition between colors of the two or more base values. The computing of the gradient can include bilinear interpolation using the gradient algorithm. The assigning a predictor for the target block can include mapping pixels associated with the gradient to pixels in the target block, and assigning color values associated with the gradient as prediction values for the target block based on the mapping of the pixels. BRIEF DESCRIPTION OF DRAWINGS

[0006] Example embodiments will become more fully understood from the detailed description and the accompanying drawings, in which like elements are represented by like reference numerals, which are given by way of illustration only, and thus, are not limiting of example embodiments, and in which:

[0007] FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D FIGURE illustrates a process for computing prediction values in prediction of NxN pixel blocks, according to an example implementation.

[0008] FIGS. 2A-2K FIGURE illustrates some patterns for processing pixels, pixel blocks, and / or pixel macroblocks.

[0009] FIG. 3A FIGURE illustrates an encoder system, according to at least one example embodiment.

[0010] FIG. 3B FIGURE illustrates a decoder system, according to at least one example embodiment.

[0011] FIG. 4A FIGURE illustrates a flow diagram of an encoder system, according to at least one example embodiment.

[0012] FIG. 4B FIGURE illustrates a flow diagram of a decoder system, according to at least one example embodiment.

[0013] FIG. 5 FIGURE illustrates a block diagram of an intra-predictor, according to at least one example embodiment.

[0014] FIG. 6 FIGURE illustrates a block diagram of a method for assigning predictor values, according to at least one example embodiment.

[0015] FIG. 7FIGS. 1-3 illustrate example computer devices and mobile computer devices, according to at least one example embodiment.

[0016] It should be noted that these drawings have not necessarily been drawn to scale and that the embodiments have been illustrated with reference to block diagrams and flowcharts where appropriate to aid in the description of the example embodiments. It should be noted that the relationships provided by these illustrative examples are not limiting. For example, elements can have different relationships or be implemented in a different order or arrangement. It should be noted that features of one example embodiment can be incorporated into another example embodiment. Also, it should be noted that the example embodiments can be implemented in a variety of environments and applications. DETAILED DESCRIPTION

[0017] When generating pixels during decompression, using a bordering block (e.g., to the left and / or above) as a predictor algorithm for computing a context sample for a prediction value during compression and / or decompression can cause block edge artifacts. Block edge artifacts can cause visible edges between blocks after reconstructing an image. Reducing or eliminating these block edge artifacts can require using a post-reconstruction (e.g., filtering) process during decompression. Example embodiments can include using a prediction algorithm that includes a gradient predictor. The use of a gradient predictor can reduce or eliminate block edge artifacts without requiring a post-reconstruction (e.g., filtering) process (to reduce or eliminate block edge artifacts).

[0018] FIG. 1A 、 FIG. 1B and FIG. 1C FIG. 5 illustrates a progression for computing a prediction value in a prediction of an NxN block of pixels, according to an example embodiment. FIG. 1D FIG. 6 illustrates a resulting NxN block having a prediction value for each block.

[0019] Compressing (or decompressing) a block or macroblock can include using an intra prediction process. Intra prediction can exploit spatial redundancy of pixels (e.g., spatially close pixels) in delta coding. A gradient predictor can be used to determine (or compute) a block prediction value (e.g., a predicted pixel value, an extrapolated pixel value, a representative pixel value, and / or the like) for use in delta coding. In other words, a prediction value (or prediction) can be a predicted value (e.g., a pixel value) used in computing a residual when using an image compression scheme that uses delta coding. For example, residual = actual (pixel value) - predicted (pixel value). Further, a prediction can be a predicted value used in computing a reconstructed pixel when using an image decompression scheme that uses delta coding. For example, reconstructed pixel = residual + prediction.

[0020] As FIGS. 1A-1DAs shown, the NxN block is an 8x8 block shown as target block 105 (shown in white (no shading)) as pixels. However, other block sizes (e.g., 4x4, 16x16, etc.) or column x row (4x4, 4x6, 4x8, 8x12, 10x12, 8x16 and / or the like) are within the scope of this disclosure. FIG. 1A As shown, the pixel 110 being processed (in column C, shaded in gray) can be a previously compressed or decompressed pixel to the left of the target block 105. Similarly, the pixel 115 being processed (in row R, shaded in gray) can be a previously compressed or decompressed pixel located above the target block 105. A pixel is shared between processed pixels 110 and 115 (shown in the upper left corner). Previously compressed or decompressed pixels are not shown to the right or below the target block 105 because (if such pixels exist) they are pixels still awaiting compression or decompression.

[0021] like FIG. 1B As shown, processed pixels 120 (a portion of processed pixel 110 in column C and a portion of processed pixel 115 in row R), 125 (which includes a portion of processed pixel 110 in column C), and 130 (which includes a portion of processed pixel 115 in row R) can be portions of processed pixels 110 and 115. Processed pixels 120, 125, and 130 are illustrated as having coarse boundaries within processed pixels 110 and / or 115. Processed pixels 120, 125, and 130 can be selected as the pixels to be used as the basis for forming the gradient algorithm when calculating pixel values. FIG. 1B As shown, it is possible to select three (3) pixels at each corner of an NxN block (thus generating a total of five (5) pixels in the top left corner). However, the selection of other numbers of pixels (e.g., one (1), two (2), four (4), five (5), etc.) is within the scope of this disclosure.

[0022] Now for reference FIG. 1B and FIG. 1C Base pixels 135, 140, and 150 can be the pixels used to form the basis of a gradient algorithm. The gradient algorithm can be used to determine (e.g., compute) the predicted (e.g., pixel value) of the target block 105. It can be based on processed pixels 120 (shown in...). FIG. 1B (in the middle) to determine the base pixel 135 (shown in) FIG. 1C The base value (in the middle). Generating base values ​​(e.g., two or more base values) can include calculating the average of two or more processed pixels. For example, it is possible to calculate the average of the pixel values ​​of processed pixel 120 and assign the resulting value to base pixel 135. It is possible to base the values ​​of processed pixel 125 (shown in the middle).FIG. 1B The base value of base pixel 140 (shown in FIG. 1C The base value of base pixel 140 (shown in FIG. 1B The base value of base pixel 145 (shown in FIG. 1C The base value of base pixel 145 (shown in FIG. 1C Base pixel 135 (shown in FIG. 1A Base pixel 140 can be located at the opposite end of column C within processed pixel 110 as base pixel 135. Base pixel 145 can be located at the opposite end of row R within processed pixel 115 as base pixel 135. In other words, base pixels 135, 140, 145 can be located at the corners of target block 105, but are not included in target block 105 (shown in FIG. 1A

[0023] Base pixel 150 (shown in FIG. 1C Base pixel 150 (shown in

[0024] Reference is now made to FIG. 1D ​The prediction block 155 (of pixels corresponding to the target block 105) is illustrated as having a prediction (e.g., representing pixel values). In other words, as described above, the pixels of the prediction block 155 have assigned values (e.g., representing pixel values) for use in an image compression / decompression scheme using incremental coding. The prediction can be calculated based on a gradient algorithm. The gradient algorithm can use base values selected from at least one of the base pixels 135, 140, 145, and 150. The gradient algorithm can be bilinear interpolation. For example, the gradient algorithm can have a start value (e.g., color) and a stop value (e.g., color). The gradient algorithm can have a direction. For example, the gradient algorithm can be from left to right, right to left, top to bottom, bottom to top, corner to corner, and / or the like. The gradient algorithm can be a combination of color and direction. For example, the gradient algorithm can be from left to right in a first pass and top to bottom in a second pass. The prediction (e.g., pixel values) can be assigned to the prediction block 155 using the gradient algorithm.

[0025] In some implementations, one of a plurality of paradigms for processing pixels, pixel blocks, and / or pixel macroblocks can be selected (e.g., as an encoder option). The processed pixels, pixel blocks, and / or pixel macroblocks include pixels that can be selected for use in a prediction process. In other words, as the processing (e.g., encoding or compression) of pixels, pixel blocks, and / or pixel macroblocks proceeds based on the selected paradigm, the pixels that have been processed (e.g., encoded or compressed) by the paradigm (shown as grayed out) become available for use in future prediction processes. In addition, the unprocessed pixels, pixel blocks, and / or pixel macroblocks (shown in white (unshaded)) do not include pixels that can be selected for use in a prediction process (e.g., because those pixels have not yet been encoded or compressed).

[0026] The paradigm can determine a starting orientation (e.g., a location of a pixel or block) and an order and / or direction for processing the pixels, pixel blocks, and / or pixel macroblocks. For example, the paradigm can start in a corner (e.g., top left, top right, bottom left, or bottom right) and can have a processing traversal flow direction that includes horizontal, vertical, diagonal, and / or the like. The processing traversal flow direction can include left (e.g., horizontal left), right (e.g., horizontal right), up (e.g., horizontal up), down (e.g., horizontal down), a combination (e.g., diagonal down left), and / or the like.

[0027] The paradigm for processing the pixels, pixel blocks, and / or pixel macroblocks determines an order in which the pixels are processed (e.g., encoded or compressed), which results in which column (e.g., column C in FIG. 1A and FIG. 1B and which row (e.g., row R in FIG. 1A and FIG. 1BThe processed pixels (shown as gray shading) include the pixels that have been processed (e.g., encoded or compressed) and can be selected for use in the prediction process. The unprocessed pixels (shown in white (no shading)) can not be selected for use in the prediction process. FIG. 1A and FIG. 1B The results of the selection of the paradigm can be illustrated, which results in the left column (column C) and the upper row (row R) that includes the pixels that have been processed (e.g., encoded or compressed) based on the paradigm and can be selected for use in the prediction process.

[0028] FIGS. 2A-2K Some paradigms for processing pixels, blocks of pixels, and / or macroblocks of pixels are illustrated. FIGS. 2A-2K Eleven (11) paradigms for processing pixels, blocks of pixels, and / or macroblocks of pixels are illustrated. However, other paradigms are within the scope of the present disclosure. In FIGS. 2A-2K In the paradigm, the processed pixels, blocks, or macroblocks are in the column C (gray shading) and the row R (gray shading), while the target pixels, blocks, or macroblocks are shown as a 4x4 block in white (no shading).

[0029] FIG. 2A A vertical processing flow is illustrated that starts in the upper left corner and has a processing direction that moves top-down and left-to-right. FIG. 2B A horizontal right processing flow direction is illustrated that moves top-down and left-to-right. FIG. 2C A horizontal down processing flow is illustrated that starts in the upper left corner and has a processing direction that moves left-to-right. FIG. 2D A diagonal right-up and left-down (zigzag) processing flow direction is illustrated that moves left-to-right. FIG. 2E Another diagonal right-up and left-down (zigzag) processing flow is illustrated that starts in the upper left corner and has a processing direction that moves left-to-right. In FIGS. 2A-2E In the paradigm, the processed pixels, blocks, or macroblocks are in the column C (gray shading) and the row R (gray shading), while the target pixels, blocks, or macroblocks are shown as a 4x4 block in white (no shading). FIGS. 1A-1D The prediction can include using the top and left neighbors as context. Thus, computing the prediction value in the prediction of the target block is as described above with respect to

[0030] FIG. 2F A vertical processing flow is illustrated that starts in the lower left corner and has a processing direction that moves bottom-up and left-to-right. FIG. 2GThe diagonal right-up processing flow is illustrated starting in the lower left corner and having a processing direction that moves from left to right and up. In FIG. 2F and FIG. 2G In the diagonal right-up processing flow, the processed pixels that become available for use in the future prediction process are in the right column C (gray shading) and the upper row R (gray shading). Thus, the processed block, which includes the pixels that can be used in the prediction process, is the right and top neighbor, however the unprocessed pixels (shown in white (no shading)) can not be selected for use in the prediction process. Thus, the prediction can include using the right and top neighbor as context. In this example implementation, computing the prediction value in the prediction of the target block can use gradient predictor computation techniques similar to those described above in FIGS. 1A-1D However, the base value can be determined based on the processed pixels in the right and top neighbor opposite the top and left neighbor described in FIGS. 1A-1D

[0031] FIG. 2H The vertical right-up processing flow is illustrated starting in the upper right corner and having a processing direction that moves from top to bottom and from right to left. In FIG. 2H In the vertical right-up processing flow, the processed pixels that become available for use in the future prediction process are in the right column C (gray shading) and the upper row R (gray shading). Thus, the processed block, which includes the pixels that can be used in the prediction process, is the top and right neighbor, however the unprocessed pixels (shown in white (no shading)) can not be selected for use in the prediction process. Thus, the prediction can include using the top and right neighbor as context. In this example implementation, computing the prediction value in the prediction of the target block can use gradient predictor computation techniques similar to those described above in FIGS. 1A-1D However, the base value can be determined based on the processed pixels in the top and right neighbor opposite the top and left neighbor described in FIGS. 1A-1D

[0032] FIG. 2I The diagonal right-down processing flow is illustrated starting in the lower right corner and having a processing direction that moves from right to left and down. FIG. 2J The horizontal right-up processing flow is illustrated starting in the lower right corner and having a processing direction that moves from right to left. FIG. 2K The diagonal right-down and left-up (zigzag) processing flow is illustrated starting in the lower right corner and having a processing direction that moves from right to left and up and down. In FIGS. 2I-2K ​​In this example, the processing flow results in processed (e.g., encoded or compressed) pixels located in the right column C (gray shading) and the lower row R (gray shading) becoming available for use in future prediction processes, however, unprocessed pixels (shown in white (no shading)) can not be selected for use in prediction processes. Thus, the processed blocks are the bottom and right neighbors. Accordingly, the prediction can include using the bottom and right neighbors as context. In this example implementation, calculating a prediction value in the prediction of the target block can use a gradient predictor calculation technique similar to that described above in FIGS. 1A-1D FIGS. 1A-1D The base value can be determined based on the processed pixels in the bottom and right neighbors opposite the top and left neighbors described above in FIGS. 1A-1D

[0033] FIGS. 2A-2K The example shown illustrates a processing flow that results in one (1) row and one (1) column having processed blocks and / or processed pixels. However, other processing flows can be within the scope of the present disclosure. For example, processing flows that include horizontal, vertical, diagonal, and / or the like combinations of directions are possible. These processing flows can result in two (2) columns and / or two (2) rows having processed blocks and / or processed pixels. For example, combinations of processed blocks and / or processed pixels of left and / or right columns with top and / or bottom rows are possible. In example implementations, the processing flow can result in a left-top-right combination of processed blocks and / or processed pixels.

[0034] In FIG. 3A example, the encoder system 300 can be or include at least one computing device and should be understood to represent virtually any computing device configured to perform the techniques described herein. Accordingly, the encoder system 300 can be understood to include various components that can be utilized to implement the techniques described herein or different or future versions thereof. As an example, the encoder system 300 is illustrated as including at least one processor 305 and at least one memory 310 (e.g., a non-transitory computer-readable storage medium).

[0035] FIG. 3A An encoder system is illustrated in accordance with at least one example embodiment. As FIG. 3A shown, the encoder system 300 includes at least one processor 305, at least one memory 310, a controller 320, and an encoder 325. The at least one processor 305, the at least one memory 310, the controller 320, and the encoder 325 are communicatively coupled via a bus 315.

[0036] The at least one processor 305 can be utilized to execute instructions stored on the at least one memory 310. As such, the at least one processor 305 can enable various features and functionality described herein or additional or alternative features and functionality. The at least one processor 305 and the at least one memory 310 can be utilized for various other purposes. For example, the at least one memory 310 can represent various types of memory and examples of related hardware and software that can be utilized to implement any of the modules described herein.

[0037] The at least one memory 310 can be configured to store data and / or information associated with the encoder system 300. The at least one memory 310 can be a shared resource. For example, the encoder system 300 can be an element of a larger system (e.g., a server, a personal computer, a mobile device, and / or the like). As such, the at least one memory 310 can be configured to store data and / or information associated with other elements within the larger system (e.g., image / video services, web browsing, or wired / wireless communication).

[0038] The controller 320 can be configured to generate and communicate various control signals to various blocks in the encoder system 300. The controller 320 can be configured to generate control signals to implement the techniques described herein. According to example embodiments, the controller 320 can be configured to control the encoder 325 to encode images, sequences of images, video frames, sequences of video frames, and / or the like. For example, the controller 320 can generate a control signal corresponding to an intra-coding mode.

[0039] The encoder 325 can be configured to receive input images 5 (and / or a video stream) and output compressed (e.g., encoded) bits 10. The encoder 325 can convert the video input into discrete video frames (e.g., as images). The input images 5 can be compressed (e.g., encoded) as compressed image bits. The encoder 325 can further convert each image (or discrete video frame) into a matrix of blocks or macroblocks (hereinafter referred to as blocks). For example, an image can be converted into a 32x32, 32x16, 16x16, 16x8, 8x8, 4x8, 4x4, or 2x2 matrix of blocks each having many pixels. Although eight (8) example matrices are recited, example embodiments are not so limited.

[0040] The compressed bits 10 can represent an output of the encoder system 300. For example, the compressed bits 10 can represent encoded images (or video frames). For example, the compressed bits 10 can be stored in a memory (e.g., the at least one memory 310). For example, the compressed bits 10 can be ready for transmission to a receiving device (not shown). For example, the compressed bits 10 can be sent to a system transceiver (not shown) for transmission to a receiving device.

[0041] At least one processor 305 may be configured to execute computer instructions associated with controller 320 and / or encoder 325. At least one processor 305 may be a shared resource. For example, encoder system 300 may be an element of a larger system (e.g., a mobile device, server, and / or the like). Therefore, at least one processor 305 may be configured to execute computer instructions associated with other elements within the larger system (e.g., image / video services, web browsing, or wired / wireless communication).

[0042] FIG. 3B The diagram illustrates a decoder system according to at least one example embodiment. For example... FIG. 3B As shown, the decoder system 350 includes at least one processor 355, at least one memory 360, a controller 370, and a decoder 375. The at least one processor 355, at least one memory 360, the controller 370, and the decoder 375 are communicatively coupled via a bus 365.

[0043] exist FIG. 3B In the examples, decoder system 350 can be at least one computing device and should be understood to represent, in effect, any computing device configured to perform the techniques described herein. Therefore, decoder system 350 can be understood to include various components that can be utilized to implement the techniques described herein or different or future versions thereof. For example, decoder system 350 is illustrated to include at least one processor 355 and at least one memory 360 (e.g., a computer-readable storage medium).

[0044] Therefore, at least one processor 355 can be used to execute instructions stored on at least one memory 360. Thus, at least one processor 355 is capable of implementing the various features and functions described herein, or additional or alternative features and functions. At least one processor 355 and at least one memory 360 can be used for various other purposes. For example, at least one memory 360 can be understood to represent various types of memory and examples of associated hardware and software capable of being used to implement any of the modules described herein. According to the example implementation, the encoder system 300 and the decoder system 350 can be included in the same larger system (e.g., a personal computer, a mobile device, etc.).

[0045] At least one memory 360 may be configured to store data and / or information associated with the decoder system 350. At least one memory 360 may be a shared resource. For example, the decoder system 350 may be an element of a larger system (e.g., a personal computer, mobile device, etc.). Therefore, at least one memory 360 may be configured to store data and / or information associated with other elements within the larger system (e.g., web browsing or wireless communication).

[0046] The controller 370 can be configured to generate various control signals and transmit these control signals to various blocks in the decoder system 350. The controller 370 can be configured to generate control signals to implement the video encoding / decoding techniques described herein. According to an example implementation, the controller 370 can be configured to control the decoder 375 to decode video frames.

[0047] Decoder 375 can be configured to receive compressed (e.g., encoded) bits 10 as input and output image 5. The compressed (e.g., encoded) bits 10 can also represent compressed video bits (e.g., video frames). Therefore, decoder 375 can convert discrete video frames of compressed bits 10 into a video stream.

[0048] At least one processor 355 may be configured to execute computer instructions associated with the controller 370 and / or the decoder 375. At least one processor 355 may be a shared resource. For example, the decoder system 350 may be an element of a larger system (e.g., a personal computer, mobile device, etc.). Therefore, at least one processor 355 may be configured to execute computer instructions associated with other elements within the larger system (e.g., web browsing or wireless communication).

[0049] FIG. 4A and FIG. 4B The figures respectively illustrate at least one example embodiment. FIG. 3A The encoder 325 shown and FIG. 3B The flowchart of decoder 375 is shown. Encoder 325 (described above) includes prediction block 410, transform block 415, quantization block 420, entropy coding block 425, inverse quantization block 430, inverse transform block 435, reconstruction block 440, and loop filter block 445. Other structural variations of encoder 325 can be used to encode the input image 5. For example... FIG. 4A As shown, dashed lines represent reconstruction paths between several blocks, while solid lines represent forward paths between several blocks.

[0050] Each of the aforementioned blocks can be stored in the encoder system (e.g., FIG. 3A The software code, which is in the memory (e.g., at least one memory 310) associated with the encoder system 300 shown and executed by at least one processor (e.g., at least one processor 305) associated with the encoder system, is executed. However, alternative implementations are contemplated, such as encoders implemented as dedicated processors. For example, each of the foregoing blocks (individually and / or in combination) can be an application-specific integrated circuit (ASIC). For example, an ASIC can be configured as prediction block 410, transformation block 415, quantization block 420, and / or the like.

[0051] The prediction block 410 can be configured to exploit image and / or video frame coherence (e.g., pixels that have not changed compared to previously coded pixels). The prediction can include two types. For example, the prediction can include intra prediction and inter prediction. Intra prediction involves predicting pixel values in a block of a frame relative to reference samples in neighboring previously coded blocks of the image. In intra prediction, samples are predicted from reconstructed pixels within the same frame for the purpose of reducing the residual amplitudes and / or errors coded by the transform (e.g., entropy encoding block 425) and entropy coding (e.g., entropy encoding block 425) portions of the transform coder. Inter prediction involves predicting pixel values in a block of a frame relative to data of previously coded frames (e.g., I-frames).

[0052] The prediction block 410 can be configured to use multiple prediction modes (intra prediction modes and / or inter prediction modes) in the prediction of the target block. The prediction block 410 can be configured to determine the prediction mode that results in the best compression results (e.g., the fewest number of bits). In example implementations, the prediction using a gradient algorithm can have the best compression results. For example, a portion of an image that has little complexity (e.g., minimal color variation, minimal texture variation, and / or the like) can use a gradient prediction technique to have the desired compression results. A portion of an image that has little complexity can include sky, water, sand, grass, landscape, and / or the like. The compressed bits 10 can include a header that includes an indication of the prediction mode used to compress each pixel and / or block of pixels.

[0053] The transform block 415 can be configured to convert values of pixels from the spatial domain to transform coefficients in the transform domain. The transform coefficients can correspond to a two-dimensional matrix of coefficients that is typically the same size as the original block. In other words, there can be as many transform coefficients as there are pixels in the original block. However, due to the transform, a portion of the transform coefficients can have a value equal to zero.

[0054] The transform block 415 can be configured to transform the residual (from the prediction block 410) into transform coefficients in, for example, the frequency domain. Typically, the transform includes a Karhunen-Loeve transform (KLT), a discrete cosine transform (DCT), a singular value decomposition transform (SVD), and an asymmetric discrete sine transform (ADST).

[0055] Quantization block 420 can be configured to reduce the amount of data in each transform coefficient. Quantization can involve mapping a relatively large range of values ​​to a relatively small range of values, thereby reducing the amount of data required to represent the quantized transform coefficients. Quantization block 420 can convert transform coefficients into discrete quantum values, which are called quantized transform coefficients or quantization levels. For example, quantization block 420 can be configured to add zeros to the data associated with the transform coefficients. For example, an encoding standard can define 128 quantization levels during scalar quantization.

[0056] The quantized transform coefficients are then entropy encoded by entropy-coded block 425. The entropy-coded coefficients, along with the information needed to decode the block—such as the type of prediction used, motion vectors, and quantizer values—are then output as compressed video bits 10. Compressed video bits 10 can be formatted using various techniques such as run-length coding (RLE) and zero-run coding.

[0057] exist FIG. 4A The reconstruction path in the code ensures that both encoder 325 and decoder 375 (see below for details) work together. FIG. 4B (Description) The same prediction mode, predictor, and / or reference frame are used to decode compressed bit 10 (or compressed video frame bits). The reconstruction path performs functions similar to those that occur during the decoding process, which is discussed in more detail below, including inverse quantization of the quantization transform coefficients at inverse quantization block 430 and inverse transform of the inverse quantization transform coefficients at inverse transform block 435 to produce a derivative residual block (derivative residual). At reconstruction block 440, the derivative residual is added to the prediction block predicted at prediction block 410 to create a reconstruction block. Loop filter block 445 can then be applied to the reconstruction block to reduce distortions such as block artifacts.

[0058] The above about FIG. 4A The encoder 325 described includes the blocks shown. However, the example implementation is not limited to this. Additional blocks may be added based on different encoding configurations and / or technologies used. Furthermore, the above regarding... FIG. 4A Each block shown in the encoder 325 described may be an optional block based on the different encoding configurations and / or technologies used.

[0059] FIG. 4B This is a schematic block diagram of decoder 375 configured to decode compressed bit 10 (or compressed video frame bits). Similar to the reconstruction path of encoder 325 discussed earlier, decoder 375 includes entropy decoding block 450, inverse quantization block 455, inverse transform block 460, reconstruction block 465, loop filtering block 470, prediction block 475, and reconstructing block filtering block 480.

[0060] The data elements within the compressed bits 10 can be decoded (using, for example, context adaptive binary arithmetic decoding) by an entropy decoding block 450 to produce a set of quantized transform coefficients. The quantized transform coefficients are dequantized by an inverse quantization block 455, and inverse transformed (using the ADST) by an inverse transform block 460 to produce a derivative residual that can be identical to the derivative residual created by the reconstruction stage in the encoder 325.

[0061] Using the header information decoded from the compressed bits 10 (e.g., including at least one prediction mode used by the encoder), the decoder 375 can use a prediction block 475 to create the same prediction block created in the encoder 325. The prediction block can be added to the derivative residual to create a reconstructed block by a reconstruction block 465. An in-loop filter block 470 can be applied to the reconstructed block to reduce block artifacts. A deblocking filter block 480 can be applied to the reconstructed block to reduce blocking distortion, and the result output as the image 5.

[0062] The decoder 375 described above with respect to FIG. 4B includes the blocks shown. However, example embodiments are not limited thereto. Additional blocks can be added based on different encoding configurations and / or techniques used. Further, each of the blocks shown in the decoder 375 described above with respect to FIG. 4B may be optional blocks based on different encoding configurations and / or techniques used.

[0063] FIG. 5 A block diagram of an intra predictor 505 is illustrated in accordance with at least one example embodiment. As FIG. 5 shown, the intra predictor 505 (module or block) includes a neighbor selector 510 (module or block), a processed pixel selector 515 (module or block), a base pixel calculator 520 (module or block), a gradient calculator 525 (module or block), and a predictor assignor 530 (module or block). In example embodiments, the intra predictor 505 can be included in the prediction block 410, 475 as shown in FIG. 4A and FIG. 4B to implement an intra prediction algorithm that includes a gradient predictor.

[0064] The neighbor selector 510 can be configured to select neighbors of a pixel or pixel block to process. The pixel or pixel block to process (or target block) can be a pixel or pixel block to compress (encode) or decompress (decode). The neighbors can be adjacent pixel columns and / or adjacent pixel rows. A pixel column can be to the left or right of the pixel or pixel block. A pixel column can be directly adjacent (to the left or right) of the pixel or pixel block. A pixel column can be indirectly adjacent (to the left or right by at least one pixel) of the pixel or pixel block. A pixel row can be above or below the pixel or pixel block. A pixel row can be directly adjacent (above or below) of the pixel or pixel block. A pixel row can be indirectly adjacent (above or below by at least one pixel) of the pixel or pixel block.

[0065] In the example implementations described above with respect to FIGS. 1A-1D and FIGS. 2A-2E the selected column is to the left of the target block. Further, the selected row is above the target block. This is sometimes referred to as selecting a block to process as an upper neighbor (or upper row) and a left neighbor (or left column). In the example implementations described above with respect to FIG. 2F and FIG. 2G the selected column is to the left of the target block. Further, the selected row is below the target block. This is sometimes referred to as selecting a block to process as a bottom neighbor (or lower row) and a left neighbor (or left column). In the example implementations described above with respect to FIG. 2H the selected column is to the right of the target block. Further, the selected row is above the target block. This is sometimes referred to as selecting a block to process as an upper neighbor (or upper row) and a right neighbor (or right column). In the example implementations described above with respect to FIGS. 2I-2K the selected column is to the right of the target block. Further, the selected row is below the target block. This is sometimes referred to as selecting a block to process as a bottom neighbor (or lower row) and a right neighbor (or right column). In the example implementations described above with respect to FIGS. 2I-2K the selected column is to the right of the target block. Further, the selected row is below the target block. This is sometimes referred to as selecting a block to process as a bottom and right neighbor.

[0066] The processed pixel selector 515 can be configured to select at least one pixel from the adjacent pixel columns and / or at least one pixel from the adjacent pixel rows. For example, the at least one pixel can be selected from (and include) each end of the adjacent columns. The at least one pixel can be selected from (and include) each end of the adjacent rows. In the example implementations described above with respect to FIGS. 1A-1DIn the example implementations described, three (3) pixels are selected from each end of the adjacent column and three (3) pixels are selected from each end of the adjacent row. However, the example implementations are not limited to selecting three (3) pixels. The number of selected pixels can be based on the number of pixels in the row and / or column. In other words, the selected pixels can be a portion of the pixels in the row and / or column. However, the selected pixels can be all of the pixels in the row and / or column. The number of selected pixels can be a design choice.

[0067] The base pixel calculator 520 can be configured to calculate at least one base value based on at least one pixel selected from the adjacent column of pixels and / or at least one pixel selected from the adjacent row of pixels. In other words, the base pixel calculator 520 can generate two or more base values based on at least one of a portion of the pixels of the adjacent column and a portion of the pixels of the adjacent row. In example implementations, four (4) base values are calculated. For example, three (3) of the four (4) base values can be calculated based on at least one pixel selected from the adjacent column of pixels and / or at least one pixel selected from the adjacent row of pixels and the fourth base value can be interpolated based on the three calculated base values.

[0068] The base pixels can be located at two or more corners of the target block. In example implementations, the base pixels can be positioned adjacent to each corner of the target block. In other words, the base pixels can be located at the corners of the target block, but not included in the target block. A first base pixel (e.g., FIG. 1C The illustrated base pixel 135) can be located at an intersection (e.g., a corner) of the adjacent row of pixels and the adjacent column of pixels. The base value of this base pixel can be calculated as an average of the pixels selected from the adjacent row on the end of the row that intersects the adjacent column and the pixels selected from the adjacent column that intersects the adjacent row.

[0069] A second base pixel (e.g., FIG. 1C The illustrated base pixel 140) can be located within the adjacent row at the opposite end of the adjacent column. The base value of the second base pixel can be calculated as an average of the selected pixels located within the adjacent row at the opposite end of the adjacent column. A third base pixel (e.g., FIG. 1C The illustrated base pixel 145) can be located within the adjacent column at the opposite end of the adjacent row. The base value of the third base pixel can be calculated as an average of the selected pixels located within the adjacent column at the opposite end of the adjacent row. The aforementioned average can be a weighted average. For example, when calculating the base value of a base pixel, the selected pixels closer to the corner associated with the base pixel can be weighted more heavily than the selected pixels further from the corner. Other weighting schemes are within the scope of the present disclosure.

[0070] A fourth base pixel (e.g., FIG. 1CThe first, second, and third base pixels 150) can be located at corners of the target block opposite the intersection of the adjoining column and the adjoining row. A base value of the fourth base pixel can be determined based on the first, second, and third base pixels. For example, an extrapolation of the base values of the first, second, and third base pixels can be calculated, and the resulting value can be assigned to the base value of the fourth base pixel. The extrapolation can be the base value of the second base pixel + the base value of the third base pixel - the base value of the first base pixel. Alternatively, an average of the base values of the first, second, and third base pixels can be calculated, and the resulting value can be assigned to the base value of the fourth base pixel. This average can be a weighted average. For example, the base value of the second base pixel and the base value of the third base pixel can be weighted more heavily than the base value of the first base pixel when calculating the base value of the fourth base pixel. Other weighting schemes are within the scope of the present disclosure.

[0071] The gradient calculator 525 can be configured to use a gradient algorithm to calculate the predictor values to be assigned to the pixels of the target block. In an example implementation, the gradient algorithm can be bilinear interpolation. Bilinear interpolation can generate a value for a cell of a two-dimensional (2D) matrix based on values of some input values. Linear interpolation is done in a first direction (e.g., in a row or horizontal direction), and then linear interpolation is done in a second direction (e.g., in a column or vertical direction). An average of the resulting values for each cell in the matrix (e.g., an average of the resulting values from the pass in the first direction and the pass in the second direction) can be calculated. The average can be a weighted average.

[0072] The gradient algorithm or color gradient algorithm can create an image that includes a gradual transition between two or more colors along a straight line. Further, the gradient algorithm or color gradient algorithm can include a plurality of pixels along the straight line. Thus, the bilinear interpolation of the gradient algorithm or color gradient algorithm can include generating a pixel value for each cell in the matrix using the gradual transition between the two or more colors.

[0073] In an example implementation, the matrix can be based on the target block. For example, the matrix can be a CxR matrix based on the number of pixels in a column of the target block and the number of pixels in a row of the target block. The two or more colors can be base values of four base pixels located at corners of the target block. Thus, the gradient calculator 525 can be configured to use a gradient algorithm having the base values of the four base pixels as color inputs to generate color values for the cells in the CxR matrix. The CxR matrix is based on the target block.

[0074] Gradient calculator 525 can use other (linear and non-linear) gradient algorithms. For example, a slanted gradient algorithm can be used. A slanted gradient can be a degree (e.g., 45 degrees) along a diagonal of a target block. Gradient algorithms can include radial gradients, conic gradients, skew gradients, and / or the like. Implementations can include function calls. For example, a linear gradient function call can be linear gradient (first color, second color, number of cells). Other gradients and other gradient function calls are within the scope of the present disclosure.

[0075] Predictor assigner 530 can be configured to assign prediction values for use during compression of a target block and / or during decompression of a target block. In an example implementation, predictor assigner 530 can be configured to map cells of a CxR matrix to pixels in a target block. Predictor assigner 530 can be further configured to assign color values of the CxR matrix as prediction values of the target block based on the mapping of the cells (e.g., mapped pixels or pixels that are mapped) of the CxR matrix to pixels in the target.

[0076] FIG. 6 A block diagram of a method for assigning predictor values is illustrated in accordance with at least one example embodiment. The steps described with respect to FIG. 3A and FIG. 3B software code stored in memory (e.g., at least one memory 310, 360) associated with an apparatus (e.g., as illustrated in FIGS. 5 and 6) and executed by at least one processor (e.g., at least one processor 305, 355). However, alternative embodiments are contemplated, such as systems embodied as special purpose processors. Although the steps described below are described as being performed by a processor, these steps need not necessarily be performed by the same processor. In other words, at least one processor can perform the steps described below with respect to FIG. 6 the apparatus. FIG. 6

[0077] In accordance with example implementations, intra prediction can include using a prediction algorithm that includes a gradient predictor. Use of a gradient predictor can reduce or eliminate block edge artifacts without requiring a post-reconstruction (e.g., filtering) process (to reduce or eliminate block edge artifacts). The prediction algorithm that includes a gradient predictor can be implemented in an encoder and / or a decoder. For example, the prediction algorithm that includes a gradient predictor can be implemented in an intra prediction process in a prediction block 410, 475 as illustrated in FIGS. 5 and 6. FIG. 4A and FIG. 4B The prediction algorithm that includes a gradient predictor can be implemented in an intra prediction process in a prediction block 410, 475 as illustrated in FIGS. 5 and 6.

[0078] ​In step S605, an adjacent column is selected. For example, the selection of an adjacent column can be based on the pixel or pixel block (or target block) to be processed. The pixel or pixel block (or target block) to be processed can be a pixel or pixel block to be compressed (encoded) or decompressed (decoded). The neighbor can be an adjacent pixel column. The pixel column can be to the left or right of the pixel or pixel block. The pixel column can be directly adjacent to the pixel or pixel block (on the left or right). The pixel column can be indirectly adjacent to the pixel or pixel block (separated by at least one pixel on the left or right).

[0079] In step S610, adjacent rows are selected. For example, the selection of adjacent rows can be based on the pixel or pixel block (or target block) to be processed. The pixel or pixel block (or target block) to be processed can be a pixel or pixel block to be compressed (encoded) or decompressed (decoded). The neighbor can be an adjacent pixel row. The pixel row can be above or below the pixel or pixel block. The pixel row can be directly adjacent to the pixel or pixel block (above or below). The pixel row can be indirectly adjacent to the pixel or pixel block (separated by at least one pixel above or below).

[0080] In step S615, the column pixels to be processed are selected. For example, at least one pixel can be selected from adjacent pixel columns. For example, at least one pixel can be selected from (and include) each end of an adjacent column. (See above regarding...) FIGS. 1A-1D In the example implementation described, the three (3) pixels are selected from (and include) each end of the adjacent column. However, the example implementation is not limited to selecting three (3) pixels.

[0081] In step S620, rows of pixels are selected for processing. For example, at least one pixel can be selected from adjacent rows of pixels. For example, at least one pixel can be selected from (and include) each end of an adjacent row. (See above regarding...) FIGS. 1A-1D In the example implementation described, the three (3) pixels are selected from (and include) each end of the adjacent rows. However, the example implementation is not limited to selecting three (3) pixels.

[0082] In step S625, a base pixel is calculated. For example, the base value can be based on at least one pixel selected from a column of adjacent pixels and / or at least one pixel selected from a row of adjacent pixels. In an example implementation, four (4) base values ​​are calculated. For example, three (3) of the four (4) base values ​​can be calculated based on at least one pixel selected from a column of adjacent pixels and / or at least one pixel selected from a row of adjacent pixels, and a fourth base value can be interpolated based on the three calculated base values.

[0083] In example implementations, the base pixels can be positioned adjacent to each corner of the target block. In other words, the base pixels can be located at the corners of the target block, but not included in the target block. The base values of the four (4) base pixels can be determined based on the proximity of the selected abutting row pixels and the selected abutting column pixels. Determining the base values is described in more detail above.

[0084] The gradient is calculated in step S630. For example, the gradient can be bilinear interpolation (described in more detail above). The bilinear interpolation of the gradient algorithm or color gradient algorithm can include generating a pixel value for each cell in the CxR matrix using a gradual transition between two or more colors. The two or more colors can be the base values of the four base pixels located at the corners of the target block. Thus, the gradient calculation can generate color values for the cells in the CxR matrix using the gradient algorithm with the base values of the four base pixels as color inputs. The CxR matrix is based on the target block.

[0085] The predictor is assigned in step S635. For example, the CxR matrix can be mapped to pixels in the target block. The color values of the CxR matrix can be assigned as prediction values of the target block based on the mapping of the cells of the CxR matrix to the pixels in the target block.

[0086] FIG. 7 An example of a computer device 700 and a mobile computer device 750 which can be used with the techniques described here is shown. The computing device 700 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The computing device 750 is intended to represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smart phones, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to be limiting as to the scope of the implementations described and / or claimed in this document.

[0087] The computing device 700 includes a processor 702, a memory 704, a storage device 706, a high-speed interface 708 connecting to the memory 704 and a high-speed expansion ports 710, and a low speed interface 712 connecting to a low speed bus 714 and the storage device 706. Each of the components 702, 704, 706, 708, 710, and 712 are interconnected using various busses, and can be mounted on a common motherboard or in other manners as appropriate. The processor 702 can process instructions for execution within the computing device 700, including instructions stored in the memory 704 or on the storage device 706 to display graphical information for a GUI on an external input / output device, such as a display 716 coupled to the high-speed interface 708. In other implementations, multiple processors and / or multiple buses can be used, as appropriate, along with multiple memories and types of memory. Also, multiple computing devices 700 can be connected, with each device providing portions of the necessary operations (e.g., as a server bank, a group of blade servers, or a multi-processor system).

[0088] The storage device 706 is capable of providing mass storage for the computing device 700. In one implementation, the storage device 706 can be or contain a computer-readable medium, such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, a flash memory or other similar solid state memory device, or an array of devices, including devices in a storage area network or other configurations. A computer program product can be tangibly embodied in an information carrier. The computer program product can also contain instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer- or machine- readable medium, such as the memory 704, the storage device 706, or memory on processor 702.

[0089] The storage device 706 is capable of providing mass storage for the computing device 700. In one implementation, the storage device 706 can be or contain a computer-readable medium, such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, a flash memory or other similar solid state memory device, or an array of devices, including devices in a storage area network or other configurations. A computer program product can be tangibly embodied in an information carrier. The computer program product can also contain instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer- or machine- readable medium, such as the memory 704, the storage device 706, or memory on processor 702.

[0090] The high-speed controller 708 manages bandwidth-intensive operations for the computing device 700, while the low-speed controller 712 manages lower bandwidth-intensive operations. Such allocation of functions is exemplary only. In one implementation, the high-speed controller 708 is coupled to memory 704, display 716 (e.g., through a graphics processor or accelerator), and to high-speed expansion ports 710, which can accept various expansion cards (not shown). In the implementation, low-speed controller 712 is coupled to storage device 706 and low-speed expansion port 714. The low-speed expansion port, which can include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet) can be coupled to one or more input / output devices, such as a keyboard, a pointing device, a scanner, or a networking device such as a switch or router, e.g., through a network adapter.

[0091] The computing device 700 can be implemented in a number of different forms, as shown in the figure. For example, it can be implemented as a standard server 720, or multiple times in a group of such servers. It can also be implemented as part of a rack server system 724. In addition, it can be implemented in a personal computer such as a laptop computer 722. Alternatively, components from computing device 700 can be combined with other components in a mobile device (not shown), such as device 750. Each of such devices can contain one or more of computing device 700, 750, and an entire system can be made up of multiple computing devices 700, 750 communicating with each other.

[0092] Computing device 750 includes a processor 752, memory 764, an input / output device such as a display 754, a communication interface 766, and a transceiver 768, among other components. The device 750 can also be provided with a storage device, such as a microdrive or other device, to provide additional storage. Each of the components 750, 752, 764, 754, 766, and 768 are interconnected using various buses, and several of the components can be mounted on a common motherboard or in other manners as appropriate.

[0093] The processor 752 can execute instructions within the computing device 750, including instructions stored in the memory 764. The processor can be implemented as a chipset of chips that include separate and multiple analog and digital processors. The processor can provide, e.g., for coordination of the other components of the device 750, such as control of user interfaces, applications run by device 750, and wireless communication by device 750.

[0094] The processor 752 can communicate with a user through a control interface 758 and a display interface 756 coupled to the display 754. The display 754 can be, for example, a TFT LCD (Thin-Film-Transistor Liquid Crystal Display) or an OLED (Organic Light Emitting Diode) display, or other appropriate display technology. The display interface 756 can comprise appropriate circuitry for driving the display 754 to present graphical and other information to a user. The control interface 758 can receive commands from the user and convert them for submission to the processor 752. In addition, an external interface 762 can be provided in communication with processor 752, to enable near area communication of device 750 with other devices. External interface 762 can provide, for example, for wired communication in some implementations, or for wireless communication in other implementations, and multiple interfaces can also be used.

[0095] The memory 764 stores information within the computing device 750. The memory 764 can be implemented as one or more of a computer-readable medium or media, a volatile memory unit or units, or a non-volatile memory unit or units. Expansion memory 774 can also be provided and connected to device 750 through expansion interface 772, which can include, for example, a SIMM (Single In Line Memory Module) card interface. Such expansion memory 774 can provide extra storage space for device 750, or can also store applications or other information for device 750. Specifically, expansion memory 774 can include instructions to carry out or supplement the processes described above, and can include secure information also. Thus, for example, expansion memory 774 can be provided as a security module for device 750, and can be programmed with instructions that permit secure use of device 750. In addition, secure applications can be provided via the SIMM cards, along with additional information, such as placing identifying information on the SIMM card in a non-hackable manner.

[0096] As discussed below, the memory can include, for example, flash memory and / or NVRAM memory. In one implementation, a computer program product is tangibly embodied in an information carrier. The computer program product contains instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer- or machine-readable medium, such as the memory 764, the expansion memory 774, or memory on processor 752 that can be received in one or more of the receiver 768, or external interface 762.

[0097] Device 750 can communicate wirelessly through communication interface 766, which can include digital signal processing circuitry where necessary. Communication interface 766 can provide for communications under various modes or protocols, such as GSM voice calls, SMS, EMS, or MMS messaging, CDMA, TDMA, PDC, WCDMA, CDMA2000, or GPRS, among others. Such communication can occur, for example, through radio-frequency transceiver 768. In addition, short-range communication can occur, such as using a Bluetooth, Wi-Fi, or other such transceiver (not shown). In addition, GPS (Global Positioning System) receiver module 770 can provide additional navigation- and location-related wireless data to device 750, which can be used as appropriate by applications running on device 750.

[0098] Device 750 can also communicate audibly using audio codec 760, which can receive spoken information from a user and convert it to usable digital information. Audio codec 760 can likewise generate audible sounds for a user, such as through a speaker, e.g., in a handset of device 750. Such

[0099] As shown, computing device 750 can be implemented in a number of different forms. For example, it can be implemented as a cellular telephone 780. It can also be implemented as part of a smart phone 782, personal digital assistant, or other similar mobile device.

[0100] In general aspects, a device, system, non-transitory computer-readable medium (having stored thereon computer-executable program code capable of being executed on a computer system) and / or method can perform a process in a method comprising: selecting a target block of pixels to compress from an image, selecting an adjoining column of the target block, selecting an adjoining row of the target block, generating two or more basis values based on at least one of a portion of pixels of the adjoining column and a portion of pixels of the adjoining row, computing a gradient based on the two or more basis values, and assigning at least one predictor for the target block using the computed gradient.

[0101] Implementations can include one or more of the following features. For example, the method can further include generating a residual based on the target block and the predictor. The selection of the adjoining column can include selecting the processed pixels, the selection of the adjoining row can include selecting the processed pixels, the adjoining column can be one of a left column or a right column, and the adjoining row can be one of an above row or a below row. The two or more basis values can be associated with basis pixels located at two or more corner portions of the target block. The two or more basis values can be associated with basis pixels located at two or more corner portions of the target block, and the generating of the two or more basis values can include calculating an average of the two or more processed pixels.

[0102] For example, the two or more basis values can be four basis values associated with basis pixels located at each corner portion of the target block, three of the four basis values can be calculated based on an average of at least one of a portion of pixels from the adjoining column and a portion of pixels from the adjoining row, and a fourth of the four basis values can be interpolated based on the three calculated basis values. The calculating of the gradient can include using a gradient algorithm to generate a pixel value for each cell in the column x row matrix using a gradual transition between colors of the two or more basis values. The calculating of the gradient can include a bilinear interpolation using the gradient algorithm. The assigning of the predictor for the target block can include mapping pixels associated with the gradient to pixels in the target block, and assigning color values associated with the gradient as prediction values for the target block based on the mapping of the pixels.

[0103] While example embodiments can include various modifications and alternative forms, embodiments thereof are shown as examples in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the claims. Like numbers refer to like elements throughout the description of the figures.

[0104] Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device. Various implementations of the systems and techniques described here can be realized as and / or be implemented by a circuit, a module, a block, or a system that can generally be referred to herein as being capable of combining software and hardware aspects. For example, a module can include functions / acts / computer program instructions executed on a processor (e.g., a processor formed on a silicon substrate, a GaAs substrate, etc.) or some other programmable data processing apparatus.

[0105] Some of the above example embodiments are described as processes or methods depicted as flow diagrams. Although the processes are described in a particular sequential order, many of the processes can be performed concurrently, in parallel, or simultaneously. In addition, the order of the operations can be re-arranged. The processes can terminate when their operations are completed, but can also terminate in response to events not described herein. The processes can correspond to methods, functions, procedures, subroutines, etc.

[0106] The methods discussed above, some of which are illustrated by the flow charts, can be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks can be stored in a machine or computer readable medium such as a storage medium. Processors can perform the necessary tasks.

[0107] The particular structural and functional details disclosed herein are merely representative for purposes of describing the example embodiments. Example embodiments, however, can be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

[0108] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the example embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0109] It should be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., between versus directly between, adjacent to versus directly adjacent to, etc.).

[0110] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and / or including, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0111] It should also be noted that in some alternative implementations, the functions / acts described can occur out of the order noted in the figures. For example, two figures shown in succession can in fact be executed concurrently or can sometimes be executed in the reverse order, depending upon the functionality / acts involved.

[0112] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0113] Portions of the above example embodiments and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. An algorithm, as used here, and as it is used to generally, is conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0114] In the illustrative embodiments described above, references to acts, symbolic representations of operations (e.g., in the form of flowcharts) that can be implemented as program modules or functional processes include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types and can be used as an object or component in the creation of other programs and / or functional processes implemented using existing structures of hardware. Such existing hardware can include one or more Central Processing Units (CPU), Digital Signal Processors (DSPs), application-specific-integrated-circuits, field-programmable gate arrays (FPGA) computers or the like.

[0115] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, or as is apparent from the discussion, terms such as processing or computing or calculating or determining or displaying or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0116] Note also that the software implemented aspects of the example embodiments are typically encoded on some form of non-transitory program storage medium or implemented over some type of transmission medium. The program storage medium can be magnetic (e.g., floppy diskette, or a hard disk drive) or optical (e.g., a compact disk read only memory, or CD ROM), and can be read only or random access. Similarly, the transmission medium can be twisted wire pairs, coaxial cable, optical fiber, or some other suitable transmission medium known to the art. The example embodiments are not limited by these aspects of any given implementation.

[0117] Finally, it should be noted that while the appended claims set forth particular combinations and sub-combinations of features described herein, other combinations and sub-combinations can be readily developed by those of ordinary skill in the art to which the present disclosure pertains. The disclosure is not limited to these particular expressed implementations, which are presented as examples only.

Claims

1. A method for image compression, the method comprising: selecting a target block of pixels to be compressed from an image; selecting an adjoining column of the target block; selecting an adjoining row of the target block; generating a first base value based on at least two pixels from a first end of the adjoining column, wherein the first end of the adjoining column is an end of the adjoining column that is distal from the adjoining row; generating a second base value based on at least two pixels from a first end of the adjoining row, wherein the first end of the adjoining row is an end of the adjoining row that is distal from the adjoining column; generating a third base value based on at least two pixels from a second end of the adjoining column and at least two pixels from a second end of the adjoining row; calculating a gradient based on the first base value, the second base value, and the third base value; and assigning at least one predictor for the target block using the calculated gradient. generating a residual based on the target block and the at least one predictor.

2. The method according to claim 1, further comprising:

3. The method of claim 1, wherein, selecting the adjoining column comprises selecting processed pixels, selecting the adjoining row comprises selecting processed pixels, the adjoining column is one of a left column or a right column, and the adjoining row is one of an above row or a below row.

4. The method of claim 1, wherein, generating the third base value comprises calculating an average of the at least two pixels from a second end of the adjoining column and the at least two pixels from a second end of the adjoining row, generating the first base value comprises calculating an average of the at least two pixels from a first end of the adjoining column, and generating the second base value comprises calculating an average of the at least two pixels from a first end of the adjoining row.

5. The method of claim 1, wherein, a fourth base value is interpolated based on the first base value, the second base value, and the third base value. calculating the gradient comprises generating a pixel value for each cell in a column x row matrix using a gradient algorithm using a gradual transition between colors of at least two of the first base value, the second base value, and the third base value.

6. The method of claim 1, wherein, calculating the gradient comprises using bilinear interpolation of a gradient algorithm.

7. The method of claim 1, wherein, assigning the at least one predictor for the target block comprises 8. The method of any one of claims 1 to 7, wherein, mapping pixels associated with the gradient to pixels in the target block, and assigning color values associated with the gradient as prediction values for the target block based on the mapping of the pixels.

9. A non-transitory computer readable medium containing instructions that, when executed, cause a processor of a computer system to perform any of the steps of the method of any of claims 1-8.

10. A computer system for compressing an image, the computer system configured to perform any of the steps of the method of any of claims 1-8.

11. A system for image compression, the system comprising: a memory storing a set of instructions; and a processor configured to execute the set of instructions to cause the system to: receive an image to be compressed; ​ selecting a target block of pixels from the image; selecting an adjoining column of the target block; selecting an adjoining row of the target block; generating a first base value based on at least two pixels from a first end of the adjoining column, wherein the first end of the adjoining column is an end of the adjoining column that is distal from the adjoining row; generating a second base value based on at least two pixels from a first end of the adjoining row, wherein the first end of the adjoining row is an end of the adjoining row that is distal from the adjoining column; generating a third base value based on at least two pixels from a second end of the adjoining column and at least two pixels from a second end of the adjoining row; calculating a gradient based on the first base value, the second base value, and the third base value; and assigning at least one predictor for the target block using the calculated gradient.

12. The system of claim 11, wherein, The instruction set further includes generating a residual based on the target block and the at least one predictor.

13. The system of claim 11, wherein selecting the adjoining column includes selecting processed pixels, selecting the adjoining row includes selecting processed pixels, the adjoining column is one of a left column or a right column, and the adjoining row is one of an above row or a below row.

14. The system of claim 11, wherein, generating the third base value includes calculating an average of the at least two pixels from the second end of the adjoining column and the at least two pixels from the second end of the adjoining row, generating the first base value includes calculating an average of the at least two pixels from the first end of the adjoining column, and generating the second base value includes calculating an average of the at least two pixels from the first end of the adjoining row.

15. The system of claim 11, wherein, a fourth base value is interpolated based on the first base value, the second base value, and the third base value.

16. The system of claim 11, wherein, calculating the gradient includes generating a pixel value for each cell in a column x row matrix using a gradient algorithm using a gradual transition between colors of at least two of the first base value, the second base value, and the third base value.

17. The system of claim 11, wherein, calculating the gradient includes using bilinear interpolation of a gradient algorithm.

18. The system of any one of claims 11 to 17, wherein, assigning the at least one predictor for the target block includes mapping pixels associated with the gradient to pixels in the target block, and assigning color values associated with the gradient as prediction values for the target block based on the mapping of the pixels.

Images