Zero-crossing detection circuit and synchronous buck converter

Abstract

The application provides a zero-crossing detection circuit and a synchronous buck converter. In the zero-crossing detection circuit, when the upper bridge of the synchronous buck converter is turned off and the lower bridge is turned on, the inductor current gradually decreases and reverses, and before the inductor current reverses, the inductor current flows from the source electrode to the drain electrode of the lower bridge, that is, the potential of the source electrode is greater than that of the drain electrode, and after the inductor current reverses, the inductor current flows from the drain electrode to the source electrode of the lower bridge, that is, the potential of the drain electrode is greater than that of the source electrode, so when the potential of the drain electrode of the lower bridge is no longer less than that of the source electrode of the lower bridge, it indicates that the inductor current is equal to zero, and the comparison circuit controls the lower bridge to be turned off when the inductor current is equal to zero, and thus the zero-crossing detection circuit can realize the zero-crossing detection of the inductor current. In addition, since the differential sampling circuit has the function of amplifying the sampling signal, the difference between the two inputs of the comparison circuit is increased, thereby improving the response speed of the comparison circuit, and thus the response speed of the zero-crossing detection circuit provided by the application is improved.

Description

Technical Field

[0001] This invention relates to the field of buck converters, and in particular to a zero-crossing detection circuit and a synchronous buck converter. Background Technology

[0002] like Figure 1 As shown, both the upper bridge HS and the lower bridge LS of the synchronous buck converter are switching transistors. Under normal conditions, the synchronous buck converter operates in PWM mode under heavy load, meaning the inductor L current is continuous; under light load, it operates in power-saving mode, meaning the inductor L current is discontinuous. When the upper bridge HS is off and the lower bridge LS is on, a zero-crossing detection circuit can be used to detect the zero-crossing of the inductor L current. That is, when the inductor L current is detected to be zero, the lower bridge LS is controlled to turn off to prevent the inductor L current from reversing.

[0003] In practical applications, due to factors such as manufacturing process and environment, there is a large time interval between the lower bridge LS turning off and the detection of zero current in inductor L. As a result, the lower bridge LS turns off only after the current in inductor L reverses, which leads to energy loss.

[0004] Therefore, improving the response speed of zero-crossing detection is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] In view of this, the present invention provides a zero-crossing detection circuit and a synchronous buck converter to improve the response speed of zero-crossing detection.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] As can be seen from the above technical solution, the present invention provides a zero-crossing detection circuit. This zero-crossing detection circuit specifically includes a comparator circuit, a bias circuit, and a differential sampling circuit. In this zero-crossing detection circuit, when the upper bridge of the synchronous buck converter is turned off and the lower bridge is turned on, the inductor current gradually decreases and reverses. Before reversing, the inductor current flows from the source to the drain of the lower bridge, meaning the potential of the source of the lower bridge is greater than the potential of the drain. After reversing, the inductor current flows from the drain to the source of the lower bridge, meaning the potential of the drain of the lower bridge is greater than the potential of the source. Therefore, when the drain potential of the lower bridge is no longer less than the source potential of the lower bridge, it indicates that the inductor current is equal to zero. That is, the comparator circuit controls the lower bridge to turn off when the inductor current is equal to zero. Thus, the zero-crossing detection circuit can achieve zero-crossing detection of the inductor current. In addition, since the differential sampling circuit has an amplification effect, the difference between the two inputs of the comparator circuit increases, thereby improving the response speed of the comparator circuit. Therefore, the response speed of the zero-crossing detection circuit provided by the present invention is improved. Attached Figure Description

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only are a part of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without any creative effort.

[0009] Figure 1 Fig. 1 is a structural schematic diagram of a synchronous buck converter in the prior art;

[0010] Figure 2 Fig. 2 is a structural schematic diagram of a zero-crossing detection circuit according to an embodiment of the present application; Figure 3 Fig. 3 is another structural schematic diagram of a zero-crossing detection circuit according to an embodiment of the present application;

[0011] Figure 4 Fig. 4 is a structural schematic diagram of an embodiment of a logic control circuit;

[0012] Figures 5-7 Fig. 5 is a structural schematic diagram of an embodiment of a differential sampling circuit;

[0013] Figure 8 Fig. 6 is another structural schematic diagram of an embodiment of a differential sampling circuit; Figure 9 Fig. 7 is a structural schematic diagram of an embodiment of a bias circuit;

[0014] Figure 10 Fig. 8 is a structural schematic diagram of an embodiment of a comparison circuit;

[0015] Figure 11 Fig. 9 is a structural schematic diagram of a synchronous buck converter according to an embodiment of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the scope of the present application.

[0017] In this application, the terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply these entities or operations to be in any such actual relationship or order. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0018] In order to improve the response speed of zero-crossing detection, the embodiment of the application provides a zero-crossing detection circuit, the specific structure of which is shown in Figure 2 The zero-crossing detection circuit specifically comprises a comparison circuit 10, a bias circuit 20 and a differential sampling circuit 30.

[0019] In the zero-crossing detection circuit, the bias circuit 20 is connected with the differential sampling circuit 30 and the comparison circuit 10 respectively; two input ends of the differential sampling circuit 30 are connected to the drain D and the source S of the lower bridge LS in the synchronous buck converter respectively, two output ends of the differential sampling circuit 30 are connected with two input ends of the comparison circuit 10 respectively; and an output end of the comparison circuit 10 is connected with the gate of the lower bridge LS.

[0020] In operation, the bias circuit 20 provides bias currents to the differential sampling circuit 30 and the comparison circuit 10 respectively; after receiving the bias currents, the differential sampling circuit 30 starts to differentially sample the potential of the drain D and the potential of the source S of the lower bridge LS in the synchronous buck converter, and outputs the sampling results to the comparison circuit 10; after receiving the bias currents, the comparison circuit 10 compares the sampling results received by the two input ends thereof, and controls the lower bridge LS in the synchronous buck converter to be turned off when the potential of the drain D is no longer smaller than the potential of the source S of the lower bridge LS.

[0021] In the zero-crossing detection circuit, when the upper bridge of the synchronous buck converter is turned off and the lower bridge is turned on, the inductor current gradually decreases and reverses, and before the inductor current reverses, the inductor current flows from the source to the drain of the lower bridge, that is, the potential of the source of the lower bridge is greater than the potential of the drain, and after the inductor current reverses, the inductor current flows from the drain to the source of the lower bridge, that is, the potential of the drain of the lower bridge is greater than the potential of the source. Therefore, when the potential of the drain of the lower bridge is no longer less than the potential of the source of the lower bridge, it indicates that the inductor current is equal to zero, that is, the comparison circuit controls the lower bridge to be turned off when the inductor current is equal to zero, and thus the zero-crossing detection circuit can realize the zero-crossing detection of the inductor current. In addition, since the differential sampling circuit has an amplification effect, the difference between the two inputs of the comparison circuit increases, thereby improving the response speed of the comparison circuit, and thus the response speed of the zero-crossing detection circuit provided by the present application is improved.

[0022] Another embodiment of the present application provides another implementation of the zero-crossing detection circuit, and the specific structure is as shown in Figure 3 The implementation further includes a logic control circuit 40 connected to the differential sampling circuit 30, the comparison circuit 10 and the biasing circuit 20.

[0023] In operation, the biasing circuit 20 is enabled by the zero-crossing detection circuit; after the synchronous buck converter is in a light load working condition and the lower bridge LS is turned on, the logic control circuit 40 controls the differential sampling circuit 30 to be enabled and controls the enabled biasing circuit 20 to output biasing currents respectively; after a preset time after the synchronous buck converter is in a light load working condition and the lower bridge LS is turned on, the logic control circuit 40 controls the comparison circuit 10 to be enabled.

[0024] Generally, when the synchronous buck converter is in a light load working condition, that is, when the synchronous buck converter works in the power saving mode, the inductor current can be reduced to zero and reversed, and this generally occurs when the lower bridge LS is turned on. Therefore, the differential sampling circuit 30 is enabled after the synchronous buck converter is in a light load working condition and the lower bridge LS is turned on, and the biasing circuit 20 starts to work after the synchronous buck converter is in a light load working condition and the lower bridge LS is turned on. In this way, the power consumption of the zero-crossing detection circuit can be reduced.

[0025] The preset time is set according to the actual circuit condition, and after the delay preset time, the overall circuit tends to be stable. Therefore, it can be ensured that the comparison circuit 10 works only after the overall circuit is stable, thereby reducing the possibility of misjudgment of the comparison circuit 10 due to the jump of the sampling result.

[0026] Another embodiment of the present application provides Figure 3 a specific implementation of the logic control circuit 40, and the structure is as shown in Figure 4As shown, specifically comprises: a first NMOS NM1, a first PMOS PM1, a first impedance branch 110 (only one resistor is shown in the figure), a capacitor branch 210, two NAND gates and seven NOT gates.

[0027] The specific structure of this embodiment of the logic control circuit 40 is as follows:

[0028] The input end of the first NOT gate N1 receives an LS signal, and the output end of the first NOT gate N1 is connected to the input end of the second NOT gate N2; wherein the LS signal is high when the lower bridge LS is turned on, and is low when the lower bridge LS is turned off.

[0029] One input end of the first NAND gate Y1 is connected to the output end of the second NOT gate N2, and the other input end receives a PSM signal, and the output end of the first NAND gate Y1 is connected to the input end of the third NOT gate N3; wherein the PSM signal is high when the synchronous buck converter is in light load condition, and is low when the synchronous buck converter is in heavy load condition.

[0030] The output end of the third NOT gate N3 is connected to the input end of the fourth NOT gate N4, the output end of the fourth NOT gate N4 is connected to the input end of the fifth NOT gate N5, and the output end of the fifth NOT gate N5 and the output end of the fourth NOT gate N4 are respectively connected to the corresponding control ends of the differential sampling circuit 30 and the bias circuit 20.

[0031] The gate of the first NMOS NM1 is connected to the gate of the first PMOS PM1, and the connection point is connected to the output end of the second NOT gate N2; the source of the first PMOS PM1 receives a power supply voltage VDD, and the source of the first NMOS NM1 is grounded GND.

[0032] The drain of the first NMOS NM1 is connected to the drain of the first PMOS PM1, and the connection point is connected to the input end of the sixth NOT gate N6 through the first impedance branch 110; the capacitor branch 210 is arranged between the input end of the sixth NOT gate N6 and the ground GND.

[0033] One input end of the second NAND gate Y2 is connected to the output end of the sixth NOT gate N6, and the other input end is connected to the output end of the third NOT gate N3, and the output end of the second NAND gate Y2 is connected to the input end of the seventh NOT gate N7; the output end of the seventh NOT gate N7 and the output end of the second NAND gate Y2 are respectively connected to the corresponding control ends of the comparison circuit 10.

[0034] Wherein, the first impedance branch 110 includes at least one resistor, when the number of resistors is greater than 1, each resistor is connected to other resistors in series or parallel; the capacitor branch 210 includes at least one capacitor, when the number of capacitors is greater than 1, each capacitor is connected to other capacitors in series or parallel.

[0035] The working principle of this embodiment of the logic control circuit 40 is shown as follows:

[0036] Figure 4 The branch shown in the dashed box 01 is composed of logic circuits, and its working principle is relatively simple, which will not be described in detail here. Only the correspondence between the potential Samp_h at the output end of the fifth NOT gate N5 and the potential Samp_n at the output end of the fourth NOT gate N4 and the input signal (LS signal and PSM signal) is listed as shown in the following table.

[0037] LS PSM Samp_h Samp_n 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0

[0038] Figure 4 The working principle of the branch shown in the dashed box 02 is as follows: when the LS signal changes from high level to low level, the first PMOS transistor PM1 is turned on, and the power supply voltage VDD charges the capacitor branch 210 through the first impedance branch 110. When the capacitor branch 210 is fully charged, the input end potential of the sixth inverter becomes high level. Since the charging time of the capacitor is short and can be ignored, the input end potential of the sixth inverter immediately becomes high level, and there is no delay.

[0039] At this time, the potential of one input end of the second NAND gate Y2 becomes low level, so the potential of the output end of the second NAND gate Y2 immediately becomes high level regardless of whether the PSM signal is high level or low level, and the potential of the output end of the seventh NOT gate N7 immediately becomes low level.

[0040] When the LS signal is high level, the first NMOS transistor NM1 is turned on, and the charged capacitor branch 210 is discharged slowly through the first NMOS transistor NM1 and the first impedance branch 110. Until the capacitor branch 210 is discharged, the input end potential of the sixth inverter will decrease to low level. Since the discharge time of the capacitor is long and cannot be ignored, the input end potential of the sixth inverter is delayed to low level. The charging time of the capacitor branch 210 is the preset time in the above embodiment, which can be adjusted in actual application.

[0041] At this time, if the PSM is high level, the potential of the other input end of the second NAND gate Y2 is also high level, so the potential of the output end of the second NAND gate Y2 is delayed to low level, and the potential of the output end of the seventh NOT gate N7 is delayed to high level; if the PSM is low level, the potential of the other input end of the second NAND gate Y2 is low level, so the potential of the output end of the second NAND gate Y2 immediately becomes high level, and the potential of the output end of the seventh NOT gate N7 immediately becomes low level, which is not affected by the delay of the input end potential of the sixth inverter to low level.

[0042] Therefore, the correspondence between the potential Cmp_n at the output of the second NAND gate Y2, the potential Cmp_p at the output of the seventh NOT gate N7, and the input signals (LS signal and PSM signal) is shown in the table below.

[0043] LS PSM Cmp_p Cmp_n 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0

[0044] The above is only one specific implementation of the logic control circuit 40. In practical applications, the above implementation is not limited to, but can be determined according to the specific situation. All of them are within the protection scope of this application.

[0045] Another embodiment of this application provides Figure 3 One specific implementation of the differential sampling circuit 30 has the following structure: Figure 5 As shown, it specifically includes: six NMOS transistors, two second impedance branches 120 (only one resistor is shown in the figure as an example), and two third impedance branches 130 (only one resistor is shown in the figure as an example).

[0046] The specific structure of this embodiment of the differential sampling circuit 30 is shown below:

[0047] The gate of the second NMOS transistor NM2 is connected to the gate of the fourth NMOS transistor NM4, and the connection point is connected to the drain of the second NMOS transistor NM2; the gate of the third NMOS transistor NM3 is connected to the gate of the fifth NMOS transistor NM5, and the connection point is connected to the drain of the third NMOS transistor NM3; the drains of the second NMOS transistor NM2 and the drains of the third NMOS transistor NM3 are connected, and the connection point is connected to the bias circuit 20.

[0048] The source of the second NMOS transistor NM2 is connected to the source of the fourth NMOS transistor NM4, and the connection point is connected to the drain of the sixth NMOS transistor NM6. The source of the sixth NMOS transistor NM6 is connected to the drain D of the lower bridge LS through a second impedance branch 120.

[0049] The source of the third NMOS transistor NM3 is connected to the source of the fifth NMOS transistor NM5, and the connection point is connected to the drain of the seventh NMOS transistor NM7. The source of the seventh NMOS transistor NM7 is connected to the source S of the lower bridge LS through another second impedance branch 120.

[0050] The gate of the sixth NMOS transistor NM6 is connected with the gate of the seventh NMOS transistor NM7, and the connection point is connected with the corresponding output terminal of the logic control circuit 40; the drain of the fourth NMOS transistor NM4 receives the power supply voltage VDD through a third impedance branch 130; the drain of the fifth NMOS transistor NM5 receives the power supply voltage VDD through another third impedance branch 130; the drain of the fourth NMOS transistor NM4 and the drain of the fifth NMOS transistor NM5 are respectively connected with the two input terminals of the comparison circuit 10.

[0051] The two second impedance branches 120 have the same impedance value, and the two third impedance branches 130 have the same impedance value; the second NMOS transistor NM2 and the third NMOS transistor NM3 are the same, and the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are the same.

[0052] It should be noted that in actual application, the size ratio of the second NMOS transistor NM2 and the fourth NMOS transistor NM4, and the size ratio of the third NMOS transistor NM3 and the fifth NMOS transistor NM5 can be any value, which is not limited here and can be determined according to the specific situation, and is within the protection scope of the present application.

[0053] Optionally, the second impedance branch 120 and the third impedance branch 130 each include at least one resistor, and when the number of resistors is greater than 1, each resistor is connected with other resistors in series or in parallel.

[0054] It should be noted that in actual application, the resistance value of the second impedance branch 120 connected with the sixth NMOS transistor NM6 can be slightly greater than that of the other second impedance branch 120, so that the delay in the flipping process of the output signal of the comparison circuit 10 and the delay from the flipping of the output signal to the off of the lower bridge LS can be offset.

[0055] The working principle of the embodiment of the differential sampling circuit 30 is as follows:

[0056] After receiving the bias current, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are all turned on; when the synchronous buck converter is in a light load working condition and the lower bridge LS is turned on, the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are turned on, that is, the differential sampling circuit 30 is enabled; at this time, the fourth NMOS transistor NM4, the third impedance branch 130 connected with the fourth NMOS transistor NM4, the sixth NMOS transistor NM6 and the second impedance branch 120 connected with the sixth NMOS transistor NM6 form a path, sample the potential of the drain D of the lower bridge LS, and amplify it as in_p; similarly, the fifth NMOS transistor NM5, the third impedance branch 130 connected with the fifth NMOS transistor NM5, the seventh NMOS transistor NM7 and the second impedance branch 120 connected with the seventh NMOS transistor NM7 form a path, sample the potential of the source S of the lower bridge LS, and amplify it as in_n.

[0057] Another embodiment of the present application provides another embodiment of the differential sampling circuit 30, the specific structure of which is shown in Figure 6 Based on the previous embodiment, the differential sampling circuit 30 further includes an initial state circuit, which includes a fourth impedance branch 140 (only one resistor is shown in the figure as an example), a fifth impedance branch 150 (only two resistors are shown in the figure as an example) and two NMOS transistors.

[0058] In this embodiment, the gate of the eighth NMOS transistor NM8 is connected with the gate of the ninth NMOS transistor NM9, and the connection point is connected with the corresponding output end of the logic control circuit 40; the source of the eighth NMOS transistor NM8 and the source of the ninth NMOS transistor NM9 are both grounded GND; the drain of the eighth NMOS transistor NM8 is connected with the drain of the sixth NMOS transistor NM6 through the fourth impedance branch 140, and the drain of the ninth NMOS transistor NM9 is connected with the source of the seventh NMOS transistor NM7 through the fifth impedance branch 150.

[0059] Among them, the impedance value of the fourth impedance branch 140 is smaller than the impedance value of the fifth impedance branch 150.

[0060] Optionally, the fourth impedance branch 140 and the fifth impedance branch 150 each include at least one resistor, and when the number of resistors is greater than 1, each resistor is connected with other resistors in series or parallel.

[0061] In the working, after receiving the bias current, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are all turned on; when the synchronous buck converter is in the heavy load working condition and / or the lower bridge LS is turned off, the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 are turned on; at this time, the fourth NMOS transistor NM4, the third impedance branch 130 connected with the fourth NMOS transistor NM4, the eighth NMOS transistor NM8 and the fourth impedance branch 140 form a path between the power supply and the ground GND, thereby giving an initial value to in_p; similarly, the fifth NMOS transistor NM5, the third impedance branch 130 connected with the fifth NMOS transistor NM5, the ninth NMOS transistor NM9 and the fifth impedance branch 150 form a path between the power supply and the ground GND, thereby giving an initial value to in_n; as described above, the comparison circuit 10 can be in an initial state.

[0062] Another embodiment of the present application provides another implementation of the differential sampling circuit 30, and the specific structure is as shown in Figure 7 (only shown in Figure 6 the basis of the previous embodiment of the differential sampling circuit 30) which further comprises a clamping circuit; the clamping circuit comprises three NMOS transistors and a sixth impedance branch 160 (only one resistor is shown in the figure as an example).

[0063] The gate of the tenth NMOS transistor NM10, the gate of the eleventh NMOS transistor NM11 and the gate of the twelfth NMOS transistor NM12 are all connected with the drain of the tenth NMOS transistor NM10, and the connection point is connected with the bias circuit 20; the source of the tenth NMOS transistor NM10 is grounded through the sixth impedance branch 160; the source of the eleventh NMOS transistor NM11 is connected with the drain of the fourth NMOS transistor NM4, and the drain of the eleventh NMOS transistor NM11 is connected with the corresponding third impedance branch 130; the source of the twelfth NMOS transistor NM12 is connected with the drain of the fifth NMOS transistor NM5, and the drain of the twelfth NMOS transistor NM12 is connected with the corresponding third impedance branch 130.

[0064] Among them, the sixth impedance branch 160 all includes at least one resistor, when the number of resistors is greater than 1, each resistor is connected with other resistors in series or parallel.

[0065] After receiving the bias current, the tenth NMOS transistor NM10, the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12 are all turned on, and the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12 can make the drain potential of the fourth NMOS transistor NM4 equal to the drain potential of the fifth NMOS transistor NM5, thereby eliminating the system error between the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 and making the sampling result more accurate.

[0066] The above three embodiments only provide three specific implementations of the differential sampling circuit 30. In actual applications, including but not limited to the above-mentioned implementations, no specific limitation is made here, and the specific implementation can be determined according to the specific situation, which is within the protection scope of the present application.

[0067] Another embodiment of the present application provides Figure 3 A specific implementation of the bias circuit 20 has a specific structure as shown in Figure 8 which specifically includes five NMOS tubes and six PMOS tubes.

[0068] The specific structure of this implementation of the bias circuit 20 is as follows:

[0069] The source of the thirteenth NMOS tube NM13 and the source of the fourteenth NMOS tube NM14 are both grounded GND.

[0070] The gate of the thirteenth NMOS tube NM13 and the gate of the fourteenth NMOS tube NM14 are both connected to the drain of the thirteenth NMOS tube NM13; the drain of the fourteenth NMOS tube NM14 is respectively connected to the drain of the third PMOS tube PM3 and the drain of the fourth PMOS tube PM4; the source of the third PMOS tube PM3 receives a power supply voltage VDD, and the source of the third PMOS tube PM3 receives an enable signal EN of the zero-crossing detection circuit.

[0071] The gate of the fourth PMOS tube PM4, the gate of the fifth PMOS tube PM5, and the gate of the sixth PMOS tube PM6 are all connected to the drain of the fourth PMOS tube PM4, and the source of the fourth PMOS tube PM4, the source of the fifth PMOS tube PM5, and the source of the sixth PMOS tube PM6 all receive a power supply voltage VDD; the drain of the fifth PMOS tube PM5 is connected to the differential sampling circuit 30, and the drain of the sixth PMOS tube PM6 is connected to the comparison circuit 10.

[0072] The source of the second PMOS tube PM2 is connected to the first bias current source IBIAS_1, and the drain of the second PMOS tube PM2 is connected to the drain of the thirteenth NMOS tube NM13; the source of the fifteenth NMOS tube NM15 is grounded GND, the gate of the fifteenth NMOS tube NM15 is connected to the gate of the thirteenth NMOS tube NM13, the drain of the fifteenth NMOS tube NM15 is connected to the source of the sixteenth NMOS tube NM16, and the drain of the sixteenth NMOS tube NM16 is connected to the drain of the fourteenth NMOS tube; the gate of the second PMOS tube PM2 and the gate of the sixteenth NMOS tube NM16 are respectively connected to the corresponding output end of the logic control circuit 40.

[0073] Optionally, the current value of the second bias current source IBIAS_2 is greater than or less than the second current source IBIAS_1, which is not specifically limited here and can be determined according to specific conditions, and is within the protection scope of the present application.

[0074] The working principle of this embodiment of the bias circuit 20 is as follows:

[0075] When the zero-crossing detection circuit is not enabled, the third PMOS PM3 is turned on, and the gate potentials of the fourth PMOS PM4, the fifth PMOS PM5, and the sixth PMOS PM6 are pulled up to the power supply voltage VDD, so that the fourth PMOS PM4, the fifth PMOS PM5, and the sixth PMOS PM6 cannot be turned on. Therefore, at this time, the bias circuit 20 is not enabled and cannot provide a bias current.

[0076] When the zero-crossing detection circuit is enabled, the third PMOS PM3 is turned off, and the gate potentials of the fourth PMOS PM4, the fifth PMOS PM5, and the sixth PMOS PM6 are no longer pulled up to the power supply voltage VDD, so that the gate potentials of the fourth PMOS PM4, the fifth PMOS PM5, and the sixth PMOS PM6 are not clamped.

[0077] After the zero-crossing detection circuit is enabled, when the synchronous buck converter is in a light load working condition and the lower bridge LS is turned on, the second PMOS PM2 and the sixteenth NMOS NM16 are both turned on, the first bias current source IBIAS_1 is connected, and the first bias current source IBIAS_1 forms a direct current working point at the gates of the thirteenth NMOS NM13, the fourteenth NMOS NM14, and the fifteenth NMOS NM15, and the voltage of the direct current working point is greater than the turn-on threshold of the thirteenth NMOS NM13, the fourteenth NMOS NM14, and the fifteenth NMOS NM15, that is, the thirteenth NMOS NM13, the fourteenth NMOS NM14, and the fifteenth NMOS NM15 are all turned on. Then, through the thirteenth NMOS NM13, the fourteenth NMOS NM14, the fifteenth NMOS NM15, and the sixteenth NMOS NM16 that are turned on, the gate potentials of the fourth PMOS PM4, the fifth PMOS PM5, and the sixth PMOS PM6 can be pulled down, so that the fourth PMOS PM4, the fifth PMOS PM5, and the sixth PMOS PM6 are all turned on. Therefore, at this time, the bias circuit 20 is enabled and can provide bias currents for the comparison circuit 10 and the differential sampling circuit 30, respectively.

[0078] In addition, in this embodiment, the sixteenth NMOS transistor NM16 and the fifteenth NMOS transistor NM15 make the time required for pulling down the gate potential of the fourth PMOS transistor PM4, the gate potential of the fifth PMOS transistor PM5, and the gate potential of the sixth PMOS transistor PM6 shorter, so that the response speed of the differential sampling circuit 30 and the comparison circuit 10 can be accelerated, and the response speed of the zero-crossing detection circuit is improved.

[0079] The present embodiment also provides Figure 3 Another specific implementation of the biasing circuit 20 is shown in FIG. 6, and the specific structure can be seen from Figure 9 In addition to the above embodiment, the biasing circuit 20 further comprises a seventeenth NMOS transistor NM17.

[0080] In this embodiment, the drain of the seventeenth NMOS transistor NM17 is connected to the second biasing current source IBIAS_2, the source of the seventeenth NMOS transistor NM17 is grounded GND, and the gate of the seventeenth NMOS transistor NM17 receives the non-enable signal UNEN of the zero-crossing detection circuit.

[0081] When the zero-crossing detection circuit is not enabled, the seventeenth NMOS transistor NM17 is turned on, and the second biasing current source IBIAS_2 is connected to the ground GND, so that the second biasing current source IBIAS_2 cannot form a DC operating point on the gate of the thirteenth NMOS transistor NM13 and the gate of the fourteenth NMOS transistor NM14.

[0082] When the zero-crossing detection circuit is enabled, the seventeenth NMOS transistor NM17 is turned off, and the second biasing current source IBIAS_2 is no longer connected to the ground GND, so that the second biasing current source IBIAS_2 forms a DC operating point on the gate of the thirteenth NMOS transistor NM13, the gate of the fourteenth NMOS transistor NM14, and the gate of the fifteenth NMOS transistor NM15. However, the voltage of the DC operating point does not reach the turn-on threshold of the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, and the fifteenth NMOS transistor NM15, so that the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, and the fifteenth NMOS transistor NM15 are all turned off, and the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, and the sixth PMOS transistor PM6 are also turned off, so that the biasing circuit 20 is enabled at this time, but cannot provide a biasing current.

[0083] In this embodiment, before the synchronous buck converter is under light load and the lower bridge LS is turned on, the gates of the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, and the fifteenth NMOS transistor NM15 already have a DC operating point. Therefore, after the synchronous buck converter is under light load and the lower bridge LS is turned on, the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, and the fifteenth NMOS transistor NM15 can turn on faster, that is, shorten the time for the bias circuit 20 to output the bias current, thereby speeding up the response speed of the differential sampling circuit 30 and the comparator circuit 10, and thus improving the response speed of the zero-crossing detection circuit.

[0084] It should be noted that when the current value of the second bias current source IBIAS_2 is less than that of the first bias current source IBIAS_1, the static loss of the bias circuit 20, i.e. the static loss of the zero-crossing detection circuit, is reduced while the response speed of the zero-crossing detection circuit is improved.

[0085] When the differential sampling circuit 30 includes a clamping circuit, another embodiment of this application also provides another specific implementation of the bias circuit 20, the specific structure of which can be found in [reference needed]. Figure 9 ,exist Figure 8 In addition to the above, it also includes: a seventh PMOS transistor PM7, wherein the gate of the seventh PMOS transistor PM7 is connected to the gate of the fourth PMOS transistor PM4, the source of the seventh PMOS transistor PM7 receives the power supply voltage VDD, and the drain of the seventh PMOS transistor PM7 is connected to the clamping circuit to provide the corresponding bias current for the clamping circuit.

[0086] The above two embodiments only provide two implementation methods for the bias circuit 20. In practical applications, the above implementation methods are not limited to, but can be determined according to the specific circumstances. All of them are within the protection scope of this application.

[0087] Another embodiment of this application provides another specific implementation of the comparator circuit 10, the specific structure of which is as follows: Figure 10 As shown, it specifically includes: six NMOS transistors, four PMOS transistors, two inverters, and two seventh impedance branches 170 with the same impedance (only one resistor is shown as an example in the figure).

[0088] The specific structure of this embodiment of the comparator circuit 10 is as follows:

[0089] The gates of the eighth PMOS transistor PM8 and the ninth PMOS transistor PM9 are connected to the two output terminals of the differential sampling circuit 30, respectively; the source of the eighth PMOS transistor PM8 is connected to the source of the ninth PMOS transistor PM9, and the connection point is connected to the bias circuit 20.

[0090] The drain of the eighth PMOS PM8, the drain of the eighteenth NMOS NM18, the gate of the twentieth NMOS NM20 and one end of a seventh impedance branch 170 are connected, the drain of the ninth PMOS PM9, the drain of the nineteenth NMOS NM19, the gate of the twenty-first NMOS NM21 and the other end of the seventh impedance branch 170 are connected, the source of the eighteenth NMOS NM18, the source of the nineteenth NMOS NM19, the source of the twentieth NMOS NM20 and the source of the twenty-first NMOS NM21 are grounded GND.

[0091] The other ends of the two seventh impedance branches 170 are connected, and the connection point is connected with the gate of the eighteenth NMOS NM18 and the gate of the nineteenth NMOS NM19; the source of the twenty-second NMOS NM22 is connected with the drain of the twentieth NMOS NM20, the drain of the twenty-second NMOS NM22 is connected with the drain of the tenth PMOS PM10, and the gate of the twenty-second NMOS NM22 is connected with the corresponding output end of the logic control circuit 40.

[0092] The gate of the tenth PMOS PM10 and the gate of the eleventh PMOS PM11 are connected with the drain of the tenth PMOS PM10, and the source of the tenth PMOS PM10 and the source of the eleventh PMOS PM11 receive the power supply voltage VDD; the drain of the eleventh PMOS PM11 is connected with the drain of the twenty-first NMOS NM21, and the connection point is connected with the output end of the comparison circuit 10 through two inverters in sequence.

[0093] The source of the twenty-third NMOS NM23 is grounded GND, the drain of the twenty-third NMOS NM23 is connected with the drain of the twenty-first NMOS NM21, and the gate of the twenty-third NMOS NM23 is connected with the corresponding output end of the logic control circuit 40.

[0094] The seventh impedance branch 170 includes at least one resistor, and when the number of resistors is greater than 1, each resistor is connected with other resistors in series or parallel.

[0095] The working principle of the embodiment of the comparison circuit 10 is as follows:

[0096] After receiving the bias current, the ninth PMOS PM9 and the tenth PMOS PM10 are turned on; after the preset time after the synchronous buck converter is in the light load working condition and the lower bridge LS is turned on, the twenty-second NMOS NM22 is turned on, the twenty-third NMOS NM23 is turned off, and the comparison circuit 10 enables and compares the two inputs.

[0097] At the beginning, the inductor current of the synchronous buck converter cannot be changed abruptly, and at this time, the potential of the drain D of the lower bridge LS is lower than the potential of the source S of the lower bridge LS, that is, the sampling result of the differential sampling circuit 30 is that the voltage of in_p is less than the voltage of in_n, and at this time, the comparison circuit 10 outputs a low level; then, as the inductor current gradually decreases to zero, the potential of the drain D of the lower bridge LS gradually rises, that is, the voltage of in_p begins to rise, and the voltage of in_n begins to fall, until in_p is greater than in_n, the output of the comparison circuit 10 flips to a high level.

[0098] In this embodiment, the two seventh impedance branches 170 are arranged in such a manner that the gates of the eighteenth NMOS tube NM18 and the nineteenth NMOS tube NM19 become a virtual ground, thereby effectively increasing the gain of the differential pair composed of the ninth PMOS tube PM9 and the tenth PMOS tube PM10 in the comparison circuit 10, and at the same time, the DC operating point is improved, so that the drain current of the twentieth NMOS tube NM20 and the twenty-first NMOS tube NM21 is larger, and the slew rate of the comparison circuit 10 is higher, and the transmission delay is reduced.

[0099] Another embodiment of the present application provides a synchronous buck converter, which has a specific structure as shown in Figure 11 The output end of the zero-crossing detection circuit 400 is connected to the gate of the lower bridge LS in the main circuit 300.

[0100] It should be noted that the specific structure and working principle of the zero-crossing detection circuit 400 are the same as those of the above-mentioned embodiments, and will not be described here again. Please refer to the above-mentioned embodiments.

[0101] The above description of the disclosed embodiments, the features described in each embodiment of the present application can be replaced or combined with each other, so that those skilled in the art can realize or use the present application. The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as the above preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it as an equivalent embodiment without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, all still belong to the protection scope of the technical solution of the present application.

Claims

1. A zero-crossing detection circuit, characterized by, The over-zero detection circuit comprises a differential sampling circuit, a comparison circuit, a biasing circuit and a logic control circuit. The biasing circuit provides biasing currents to the differential sampling circuit and the comparison circuit respectively. Two input terminals of the differential sampling circuit are connected to the drain and the source of the lower bridge of the synchronous step-down converter respectively, and two output terminals of the differential sampling circuit are connected to two input terminals of the comparison circuit respectively. An output terminal of the comparison circuit is connected to the gate of the lower bridge, and is used to control the lower bridge to be turned off when the potential of the drain of the lower bridge is no longer smaller than the potential of the source of the lower bridge. The over-zero detection circuit further comprises a logic control circuit. The logic control circuit is connected to the differential sampling circuit, the comparison circuit and the biasing circuit respectively. The biasing circuit is enabled when the over-zero detection circuit is enabled. The logic control circuit is used to enable the differential sampling circuit, control the enabled biasing circuit to output biasing currents, and enable the comparison circuit after a preset time after the synchronous step-down converter is in a light load working condition and the lower bridge is turned on. The logic control circuit comprises a first NMOS transistor, a first PMOS transistor, a first impedance branch, a capacitor branch, two NAND gates and seven NOT gates.

2. The zero-crossing detection circuit of claim 1, wherein, An input terminal of a first NOT gate receives an LS signal, and an output terminal of the first NOT gate is connected to an input terminal of a second NOT gate. When the LS signal is at a high level, it indicates that the lower bridge is turned on. An input terminal of a first NAND gate is connected to an output terminal of the second NOT gate, and another input terminal of the first NAND gate receives a PSM signal. When the PSM signal is at a high level, it indicates that the synchronous step-down converter is in a light load working condition. An output terminal of the third NOT gate is connected to an input terminal of a fourth NOT gate, and an output terminal of the fourth NOT gate is connected to an input terminal of a fifth NOT gate. The output terminal of the fifth NOT gate and the output terminal of the fourth NOT gate are connected to corresponding control terminals of the differential sampling circuit and corresponding control terminals of the biasing circuit respectively. A gate of the first NMOS transistor is connected to a gate of the first PMOS transistor, and a connection point is connected to the output terminal of the second NOT gate. A source of the first PMOS transistor is connected to a power supply, and a source of the first NMOS transistor is grounded. A drain of the first NMOS transistor is connected to a drain of the first PMOS transistor, and a connection point is connected to an input terminal of a sixth NOT gate through the first impedance branch.

3. The zero-crossing detection circuit of claim 1, wherein, The capacitor branch is arranged between the input terminal of the sixth NOT gate and the ground. An input terminal of a second NAND gate is connected to an output terminal of the sixth NOT gate, and another input terminal of the second NAND gate is connected to an output terminal of the third NOT gate. An output terminal of the seventh NOT gate and an output terminal of the second NAND gate are connected to corresponding control terminals of the comparison circuit respectively. The differential sampling circuit comprises six NMOS transistors, two second impedance branches with the same impedance value, and two third impedance branches with the same impedance value. The second NMOS transistor and the third NMOS transistor are the same, and the fourth NMOS transistor and the fifth NMOS transistor are the same; The gate of the second NMOS transistor is connected with the gate of the fourth NMOS transistor, and a connection point is connected with the drain of the second NMOS transistor; The gate of the third NMOS transistor is connected with the gate of the fifth NMOS transistor, and a connection point is connected with the drain of the third NMOS transistor; The drain of the second NMOS transistor is connected with the drain of the third NMOS transistor, and a connection point is connected with the bias circuit; The source of the second NMOS transistor is connected with the source of the fourth NMOS transistor, and a connection point is connected with the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is connected with the drain of the lower bridge through a second impedance branch; The source of the third NMOS transistor is connected with the source of the fifth NMOS transistor, and a connection point is connected with the drain of the seventh NMOS transistor, and the source of the seventh NMOS transistor is connected with the source of the lower bridge through another second impedance branch; The gate of the sixth NMOS transistor is connected with the gate of the seventh NMOS transistor, and a connection point is connected with the corresponding output end of the logic control circuit, and the sixth NMOS transistor and the seventh NMOS transistor are turned on when the synchronous buck converter is in a light load working condition and the lower bridge is turned on; the drain of the fourth NMOS transistor is connected with the power supply through a third impedance branch; The drain of the fifth NMOS transistor is connected with the power supply through another third impedance branch; The drain of the fourth NMOS transistor and the drain of the fifth NMOS transistor are respectively connected with two input ends of the comparison circuit.

4. The zero-crossing detection circuit of claim 3, wherein, The differential sampling circuit further comprises an initial state circuit; the initial state circuit comprises a fourth impedance branch, a fifth impedance branch and two NMOS transistors; wherein: The gate of the eighth NMOS transistor is connected with the gate of the ninth NMOS transistor, and a connection point is connected with the corresponding output end of the logic control circuit, and the eighth NMOS transistor and the ninth NMOS transistor are turned off when the synchronous buck converter is in a light load working condition and the lower bridge is turned on; The source of the eighth NMOS transistor and the source of the ninth NMOS transistor are both grounded; The drain of the eighth NMOS transistor is connected with the drain of the sixth NMOS transistor through the fourth impedance branch, and the drain of the ninth NMOS transistor is connected with the source of the seventh NMOS transistor through the fifth impedance branch; The impedance value of the fourth impedance branch is smaller than the impedance value of the fifth impedance branch.

5. The zero-crossing detection circuit of claim 3, wherein, The differential sampling circuit further comprises a clamping circuit; the clamping circuit comprises three NMOS transistors and a sixth impedance branch; wherein: The gate of the tenth NMOS transistor, the gate of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor are all connected with the drain of the tenth NMOS transistor, and a connection point is connected with the bias circuit; the source of the tenth NMOS transistor is grounded through the sixth impedance branch; The source of the eleventh NMOS transistor is connected with the drain of the fourth NMOS transistor, and the drain of the eleventh NMOS transistor is connected with the corresponding third impedance branch; The source of the twelfth NMOS transistor is connected with the drain of the fifth NMOS transistor, and the drain of the twelfth NMOS transistor is connected with the corresponding third impedance branch.

6. The zero-crossing detection circuit of claim 1, wherein, The bias circuit comprises four NMOS transistors and six PMOS transistors; wherein: The source of the thirteenth NMOS transistor and the source of the fourteenth NMOS transistor are both grounded; The gate of the thirteenth NMOS transistor and the gate of the fourteenth NMOS transistor are both connected with the drain of the thirteenth NMOS transistor; The drain of the fourteenth NMOS transistor is connected with the drain of the third PMOS transistor and the drain of the fourth PMOS transistor respectively; The source of the third PMOS transistor is connected with the power supply, the source of the third PMOS transistor receives the enable signal of the zero-crossing detection circuit, and the third PMOS transistor is turned off when the zero-crossing detection circuit is enabled; The gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor are all connected with the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor, the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are all connected with the power supply; The drain of the fifth PMOS transistor is connected with the differential sampling circuit, and the drain of the sixth PMOS transistor is connected with the comparison circuit; The source of the second PMOS transistor is connected with the first bias current source, and the drain of the second PMOS transistor is connected with the drain of the thirteenth NMOS transistor; The source of the fifteenth NMOS transistor is grounded, the gate of the fifteenth NMOS transistor is connected with the gate of the thirteenth NMOS transistor, the drain of the fifteenth NMOS transistor is connected with the source of the sixteenth NMOS transistor, and the drain of the sixteenth NMOS transistor is connected with the drain of the fourteenth NMOS transistor; The gate of the second PMOS transistor and the gate of the sixteenth NMOS transistor are respectively connected with the corresponding output end of the logic control circuit, and the second PMOS transistor and the sixteenth NMOS transistor are both turned on when the synchronous buck converter is in a light load working condition and the lower bridge is turned on.

7. The zero-crossing detection circuit of claim 6, wherein, The bias circuit further comprises a seventeenth NMOS transistor; wherein: The drain of the seventeenth NMOS transistor is connected with the second bias current source, and the source of the seventeenth NMOS transistor is grounded; The gate of the seventeenth NMOS transistor receives the non-enable signal of the zero-crossing detection circuit, and the seventeenth NMOS transistor is turned off when the zero-crossing detection circuit is enabled; When the differential sampling circuit comprises a clamping circuit, the bias circuit further comprises a seventh PMOS transistor; wherein: The gate of the seventh PMOS transistor is connected with the gate of the fourth PMOS transistor, the source of the seventh PMOS transistor is connected with the power supply, and the drain of the seventh PMOS transistor is connected with the clamping circuit.

8. The zero-crossing detection circuit of claim 1, wherein, The comparison circuit comprises six NMOS transistors, four PMOS transistors, two inverters and two seventh impedance branches with the same impedance; wherein: The gate of the eighth PMOS transistor and the gate of the ninth PMOS transistor are respectively connected with the two output ends of the differential sampling circuit; The source of the eighth PMOS is connected with the source of the ninth PMOS, and the connection point is connected with the bias circuit; The drain of the eighth PMOS, the drain of the eighteenth NMOS, the gate of the twentieth NMOS and one end of the seventh impedance branch are connected, the drain of the ninth PMOS, the drain of the nineteenth NMOS, the gate of the twenty-first NMOS and the other end of the seventh impedance branch are connected, and the source of the eighteenth NMOS, the source of the nineteenth NMOS, the source of the twentieth NMOS and the source of the twenty-first NMOS are grounded; The other ends of the two seventh impedance branches are connected, and the connection point is connected with the gate of the eighteenth NMOS and the gate of the nineteenth NMOS; The source of the twenty-second NMOS is connected with the drain of the twentieth NMOS, the drain of the twenty-second NMOS is connected with the drain of the tenth PMOS, the gate of the twenty-second NMOS is connected with the corresponding output end of the logic control circuit, and the twenty-second NMOS is turned on after the preset time after the synchronous buck converter is in the light load working condition and the lower bridge is turned on; The gate of the tenth PMOS and the gate of the eleventh PMOS are connected with the drain of the tenth PMOS, and the source of the tenth PMOS and the source of the eleventh PMOS are connected with the power supply; The drain of the eleventh PMOS is connected with the drain of the twenty-first NMOS, and the connection point is connected with the output end of the comparison circuit through two inverters in sequence; The source of the twenty-third NMOS is grounded, the drain of the twenty-third NMOS is connected with the drain of the twenty-first NMOS, the gate of the twenty-third NMOS is connected with the corresponding output end of the logic control circuit, and the twenty-third NMOS is turned off after the preset time after the synchronous buck converter is in the light load working condition and the lower bridge is turned on.

9. A synchronous buck converter, characterized by Comprise: The main circuit and the zero-crossing detection circuit according to any one of claims 1-8; wherein: The output end of the zero-crossing detection circuit is connected with the gate of the lower bridge in the main circuit.

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