Data processing method and apparatus, and electronic device
By using a FIFO storage module in an algorithm that involves collaboration between the CPU and ASIC, the problems of insufficient SRAM scalability and data loss in existing technologies are solved, achieving both flexibility and security in data reading.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING ESWIN COMPUTING TECH CO LTD
- Filing Date
- 2022-05-27
- Publication Date
- 2026-05-19
AI Technical Summary
In the process of algorithm execution in which the CPU and ASIC work together, the existing technology of adding SRAM to achieve data reading has problems such as more interrupts and insufficient scalability, and there is also a risk of data loss.
The system employs a first-in-first-out (FIFO) storage module, which includes at least M+1 storage units. By setting the value of M, the number of frames for reading data is increased, simplifying write operations, avoiding data overwriting, and ensuring data security.
It improves the flexibility and ease of data reading, avoids data loss, and ensures that the CPU can read the latest complete data, especially when the write speed is higher than the read speed.
Smart Images
Figure CN114879912B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more specifically, to a data processing method, apparatus, and electronic device. Background Technology
[0002] In the field of computer technology, the operation of some algorithms often requires the computing module to work in coordination with the central processing unit (CPU). For example, in the digital image processing scenario, some algorithms of image signal processing (ISP) require application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) to work in coordination with the CPU. For example, the 3A algorithm, namely auto focus (AF), auto exposure (AE), and auto white balance (AWB).
[0003] During the execution of the above algorithm, frequent and intensive data transfer between the ASIC and the CPU is required. This is typically a one-way transfer from ASIC to CPU. For example, each frame of an image generates a set of data; based on a typical video frame rate of 60 frames per second, 60 sets of data can be generated per second. The CPU periodically requests the latest data from the ASIC via interrupts or polling through the bus. The request interval may be much longer than the frame rate of the image. However, the CPU does not need to obtain data for every frame; it only needs to obtain the complete data of the latest frame or multiple frames when requesting data. Therefore, it is not necessary to generate an interrupt for the CPU to read data every time a set of data is generated. Thus, how to store the data after the ASIC has completed its calculations to meet the CPU's potential read requests becomes a problem. To solve this problem, related technologies typically involve adding a Static Random-Access Memory (SRAM) or using two SRAMs for ping-pong storage and retrieval. However, adding a single SRAM generates more interrupts and carries the risk of data loss; using two SRAMs results in insufficient scalability and increased logic complexity when more frames of data are needed. Summary of the Invention
[0004] This application provides a data processing method to address the shortcomings of existing technologies where SRAM is added to enable the CPU to read data during the execution of algorithms that cooperate with the CPU.
[0005] Accordingly, embodiments of this application also provide a data processing device, an electronic device, and a storage medium to ensure the implementation and application of the above methods.
[0006] To address the aforementioned problems, this application discloses a data processing method, the method comprising:
[0007] Obtain the first data output by the target calculation module;
[0008] Determine the write address of the first-in-first-out (FIFO) storage module of the electronic device, and write the first data to the storage unit corresponding to the write address;
[0009] The FIFO storage module is a storage module corresponding to the read operation of the central processing unit (CPU). The number of data groups in the read operation is M. The FIFO storage module includes at least M+1 storage units, where M is a positive integer.
[0010] This application also discloses a data processing apparatus, the apparatus comprising:
[0011] The acquisition module is used to acquire the first data output by the target calculation module.
[0012] The write module is used to determine the write address of the first-in-first-out (FIFO) storage module of the electronic device and write the first data to the storage unit corresponding to the write address.
[0013] The FIFO storage module is a storage module corresponding to the read operation of the central processing unit (CPU). The number of data groups in the read operation is M. The FIFO storage module includes at least M+1 storage units, where M is a positive integer.
[0014] This application also discloses an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements one or more of the methods described in this application.
[0015] This application also discloses a computer-readable storage medium storing a computer program that, when executed by a processor, implements one or more of the methods described in this application.
[0016] This application also discloses a computer program product, including a computer program that, when executed by a processor, implements one or more of the methods described in this application.
[0017] The beneficial effects of the technical solutions provided in this application are:
[0018] In this embodiment, the first data output by the target computing module is obtained; the write address of the FIFO storage module of the electronic device is determined, and the first data is written to the storage unit corresponding to the write address; wherein, the FIFO storage module is a storage module corresponding to the CPU's read operation, and the FIFO storage module includes at least M+1 storage units; by setting the value of M, the number of frames for reading data can be easily increased, increasing flexibility; and when writing data, address operations can be ignored, and data can be directly written to the FIFO, making the operation convenient; during the data reading process, unread data will not be overwritten, avoiding data loss and ensuring data security.
[0019] Additional aspects and advantages of the embodiments of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of the application. Attached Figure Description
[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:
[0021] Figure 1 A flowchart illustrating the data processing method provided in the embodiments of this application;
[0022] Figure 2 A schematic diagram of a first example provided for an embodiment of this application;
[0023] Figure 3 This is a schematic diagram of the structure of the data processing apparatus provided in the embodiments of this application;
[0024] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0025] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0026] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this application mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, step, operation, element, component, and / or combinations thereof supported by the art. It should be understood that when we say that an element is “connected” or “coupled” to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element establish a connection relationship through an intermediate element. Furthermore, “connected” or “coupled” as used herein can include wireless connection or wireless coupling. The term “and / or” as used herein indicates at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”
[0027] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0028] See Figure 1 This application provides a data processing method. Optionally, the method is applied to an electronic device, which includes a CPU and a target computing module. The target computing module may be an ASIC, an FPGA, or other modules that perform calculations. For ease of explanation, an ASIC will be used as an example to illustrate the target computing module. However, this does not constitute a limitation on the embodiments of this application.
[0029] like Figure 1 As shown, the method may include the following steps:
[0030] Step 101: Obtain the first data output by the target calculation module.
[0031] The first data is the data output by the ASIC (Target Computing Module) algorithm.
[0032] The algorithms computed by the ASIC can be some of the algorithms of the ISP, such as the algorithms in the aforementioned 3A algorithm; further, taking the AF algorithm as an example, on the ASIC side, in the image processing pipeline, high computational workload and real-time data calculation and statistics are performed on each pixel. The CPU performs complex algorithm calculations based on the statistical results of the ASIC, controls the motor to perform focusing and other operations, thereby completing the entire algorithm process.
[0033] Therefore, the ASIC and CPU require frequent and intensive data transmission, which is a one-way transmission from ASIC to CPU. Each frame of the image generates a set of data. Based on a typical video image frequency of 60 frames per second, 60 sets of data can be generated per second, with an interval of tens of milliseconds between two frames. However, the CPU requests data once every 200 milliseconds (ms). The CPU does not need to obtain the data of every frame, but after the ASIC completes the data calculation, the data storage should ensure that the CPU can read the complete data of the latest frame. However, the relationship between CPU reading time and pipeline is unpredictable, so there may be situations where the CPU is reading while a new frame of data is being calculated and written. In this embodiment, when the ASIC completes the calculation and outputs the first data, it stores it in a preset First-In-First-Out (FIFO) storage module. Specifically, the FIFO storage module is a first-in-first-out dual-port buffer, that is, the first data to enter is the first to be removed. One interface is the input port of the storage module, through which the data output by the ASIC is input to the FIFO storage module; the other interface is the output port of the storage module, through which the CPU reads data.
[0034] Step 102: Determine the write address of the first-in-first-out (FIFO) storage module of the electronic device, and write the first data to the storage unit corresponding to the write address;
[0035] Here, writing the address means writing the data to the address of the storage unit of the FIFO storage module; the FIFO storage module is the storage module corresponding to the read operation of the central processing unit (CPU), and the number of data groups in the read operation is M, that is, the number of data groups read by the CPU in each read operation is M, where M is a positive integer; it can be understood that M is a preset value, and the specific value of M can be modified or adjusted.
[0036] The FIFO storage module includes at least M+1 storage units; that is, the FIFO storage module can include M+1 or more storage units; in this way, it can be ensured that the read address starts at least in the next storage unit after the write address, avoiding read and write data conflicts, until all the required data is read.
[0037] Compared to adding an SRAM, this embodiment of the application can easily increase the number of data reading frames by setting the value of M, thus increasing flexibility. Furthermore, when the ASIC writes data, it can directly write to the FIFO without considering address operations, making the operation convenient. During the data reading process, the read pointer moves according to the CPU's reading order. Regardless of whether writing is in progress, the write pointer will not exceed the read pointer, meaning it will not overwrite unread data, thus avoiding data loss and ensuring data security, especially when the write speed is higher than the read speed.
[0038] As a first example, taking M as 2, the CPU only needs the statistical data of the two most recent frames of images each time it requests data. Therefore, a FIFO storage module with a data group (each storage unit stores a group of data) of 2 and a data group depth (i.e. how many data items make up each group of data) of 2 is instantiated. The FIFO storage module includes M+1 storage units, which means that the space occupied is the group depth * 3.
[0039] Specifically, see Figure 2 There are M+1 storage units, namely storage unit 0, storage unit 1, and storage unit 2. Each storage unit stores a set of data, and each set of data includes 3 data items, with each data item occupying one row. As shown in storage unit 0, it stores data 1, and the three data items of data 1 are stored as data 1_1 row, data 1_2 row, and data 1_3 row, respectively.
[0040] When writing data, the first frame of data (i.e. the first group of data) is placed in storage unit 0 corresponding to address 0, and the second frame of data is placed in storage unit 1 corresponding to address 1. After the second frame is stored, the FIFO's read pointer is at address 0, and the write pointer is at address 2 (where the read pointer and write pointer are separate).
[0041] When the third frame of data arrives, writing begins from address 2.
[0042] After the third frame is written, if the CPU has not read the data, the write pointer jumps to address 0, and the read pointer jumps directly to address 1. At this time, the original first frame data becomes invalid, and the latest data consists of the second and third frames, ensuring that the CPU can read the complete data of the latest frame whenever it comes to read. The single jump distance of the read pointer is the group depth.
[0043] During or after the third frame is written, if the CPU is reading data, the read pointer will start reading from address 0. When the CPU reads, it locks the FIFO using the FIFO's input locking function. After reading is complete, the FIFO is unlocked, and the first and second frames of data (data 1 and data 2) are read. In order to keep the latest two frames of data, the read pointer moves from address 2 back to address 1, and the write pointer moves to address 0.
[0044] The read pointer moves according to the CPU's read order. Regardless of whether writing is in progress, the write pointer will not exceed the read pointer, meaning it will not overwrite unread data, thus avoiding data loss.
[0045] After the reading is complete, the FIFO is unlocked, and the first and second frames of data (data 1 and data 2) are read away.
[0046] In this embodiment, first data output by the target computing module is obtained; the write address of the FIFO storage module of the electronic device is determined, and the first data is written to the storage unit corresponding to the write address; wherein, the FIFO storage module is a storage module corresponding to the CPU's read operation, and the FIFO storage module includes at least M+1 storage units; by setting the value of M, the number of frames for reading data can be easily increased, increasing flexibility; and when writing data, address operations can be ignored, and data can be directly written to the FIFO, making the operation convenient; during the data reading process, unread data will not be overwritten, avoiding data loss and ensuring data security, especially when the write speed is higher than the read speed. This embodiment solves the defects existing in the related technology of implementing CPU data reading by adding SRAM.
[0047] In an optional embodiment, before acquiring the first data output by the target computing module, the method includes:
[0048] Determine the parameter information for the read operation; wherein the parameter information includes at least the number of data groups; wherein the parameter information may also include parameters such as data group depth and data bit width;
[0049] Based on the parameter information, a FIFO storage module corresponding to the read operation is established; wherein, different FIFO storage modules can be established for different read and write operations; optionally, the FIFO storage module can be physical or virtual; in this way, by setting different FIFO storage modules, the number of frames for reading data can be increased or decreased, thereby increasing the flexibility of data transmission.
[0050] In an optional embodiment, the method further includes:
[0051] Receive the read operation from the CPU;
[0052] Determine the first read address corresponding to the read operation; the first read address is the read address corresponding to the execution time of the read operation;
[0053] Data is read from the FIFO storage module according to the first read address.
[0054] Taking the ISP field as an example, the CPU reads the statistical results transmitted by the ASIC through the FIFO storage module, performs algorithm calculations, controls the motor to perform focusing and other operations, thereby completing the entire algorithm process.
[0055] In an optional embodiment, determining the first read address corresponding to the read operation includes:
[0056] Determine the first write address at the current moment; where the current moment is the execution time of the read operation;
[0057] Add a group address to the first write address to obtain the first read address corresponding to the read operation; wherein, when reading data, add a group address to the first write address as the first fetch address; the read address is the next group of the write address, until all the required data is read. This can avoid read and write data conflicts and avoid data loss, ensuring data security, especially when the write speed is higher than the read speed.
[0058] In an optional embodiment, after reading data from the FIFO storage module according to the first read address, the method includes:
[0059] Data write operations of the FIFO storage module are disabled.
[0060] Specifically, when the CPU performs a data read operation, the write operation is blocked. This means locking the input of the FIFO storage module and unlocking it after the read operation is complete. This prevents a situation where the CPU is reading data while a new frame of data is being calculated and written. If this happens, the write operation may overwrite data that the CPU has not yet read. For example, if the write speed is higher than the read speed, data loss may occur, and the CPU will be unable to read the latest frame data.
[0061] Furthermore, in this embodiment of the application, to avoid data overwriting, the method for blocking the data write operation of the FIFO storage module includes:
[0062] If there is a data write operation during execution, the first write address of the data write operation is controlled to not exceed the read address at the current moment.
[0063] When the CPU is reading data, the input is locked. If a write operation is in progress while the input is locked, the write pointer is prevented from exceeding the read pointer. For example, if the write speed is faster than the read speed and the write pointer is about to exceed the read pointer, the write operation is stopped and further write operations are not allowed.
[0064] Furthermore, in this embodiment of the application, the step of controlling the first write address of the data write operation to not exceed the read address at the current moment includes:
[0065] If the first write address of a write operation exceeds the current read address, the data written by that write operation is discarded. When write operations are restricted, the data for that frame is discarded, and after that frame ends, the write pointer returns to the beginning of that frame's address.
[0066] In this embodiment, first data output by the target computing module is obtained; the write address of the FIFO storage module of the electronic device is determined, and the first data is written to the storage unit corresponding to the write address; wherein, the FIFO storage module is a storage module corresponding to the CPU's read operation, and the FIFO storage module includes at least M+1 storage units; by setting the value of M, the number of frames for reading data can be easily increased, increasing flexibility; and when writing data, address operations can be ignored, and data can be directly written to the FIFO, making the operation convenient; during the data reading process, unread data will not be overwritten, avoiding data loss and ensuring data security.
[0067] Based on the same principle as the apparatus provided in the embodiments of this application, the embodiments of this application also provide a data processing apparatus, such as... Figure 3 As shown, the device includes:
[0068] The acquisition module 301 is used to acquire the first data output by the target calculation module.
[0069] The first data is the data output by the ASIC (Target Computing Module) algorithm.
[0070] The algorithms computed by the ASIC can be some of the algorithms of the ISP, such as the algorithms in the aforementioned 3A algorithm; further, taking the AF algorithm as an example, on the ASIC side, in the image processing pipeline, high computational workload and real-time data calculation and statistics are performed on each pixel. The CPU performs complex algorithm calculations based on the statistical results of the ASIC, controls the motor to perform focusing and other operations, thereby completing the entire algorithm process.
[0071] Therefore, the ASIC and CPU require frequent and intensive data transmission, which is a one-way transmission from ASIC to CPU. Each frame of the image generates a set of data. Based on a typical video image frequency of 60 frames per second, 60 sets of data can be generated per second, with an interval of tens of milliseconds between two frames. However, the CPU requests data once every 200 milliseconds (ms). The CPU does not need to obtain the data of every frame, but after the ASIC completes the data calculation, the data storage should ensure that the CPU can read the complete data of the latest frame. However, the relationship between CPU reading time and pipeline is unpredictable, so there may be situations where the CPU is reading while a new frame of data is being calculated and written. In this embodiment, when the ASIC completes the calculation and outputs the first data, it stores it in a preset First-In-First-Out (FIFO) storage module. Specifically, the FIFO storage module is a first-in-first-out dual-port buffer, that is, the first data to enter is the first to be removed. One interface is the input port of the storage module, through which the data output by the ASIC is input to the FIFO storage module; the other interface is the output port of the storage module, through which the CPU reads data.
[0072] The write module 302 is used to determine the write address of the first-in-first-out (FIFO) storage module of the electronic device and write the first data to the storage unit corresponding to the write address.
[0073] The FIFO storage module is a storage module corresponding to the read operation of the central processing unit (CPU). The number of data groups in the read operation is M. The FIFO storage module includes at least M+1 storage units, where M is a positive integer.
[0074] Here, writing the address means writing the data to the address of the storage unit of the FIFO storage module; the FIFO storage module is the storage module corresponding to the read operation of the central processing unit (CPU), and the number of data groups in the read operation is M, that is, the number of data groups read by the CPU in each read operation is M, where M is a positive integer; it can be understood that M is a preset value, and the specific value of M can be modified or adjusted.
[0075] The FIFO storage module includes at least M+1 storage units; that is, the FIFO storage module can include M+1 or more storage units; in this way, it can be ensured that the read address starts at least in the next storage unit after the write address, avoiding read and write data conflicts, until all the required data is read.
[0076] Compared to adding an SRAM, this embodiment of the application can easily increase the number of data reading frames by setting the value of M, thus increasing flexibility. Furthermore, when the ASIC writes data, it can directly write to the FIFO without considering address operations, making the operation convenient. During the data reading process, the read pointer moves according to the CPU's reading order. Regardless of whether writing is in progress, the write pointer will not exceed the read pointer, meaning it will not overwrite unread data, thus avoiding data loss and ensuring data security, especially when the write speed is higher than the read speed.
[0077] As a first example, taking M as 2, the CPU only needs the statistical data of the two most recent frames of images each time it requests data. Therefore, a FIFO storage module with a data group (each storage unit stores a group of data) of 2 and a data group depth (i.e. how many data items make up each group of data) of 2 is instantiated. The FIFO storage module includes M+1 storage units, which means that the space occupied is the group depth * 3.
[0078] Specifically, see Figure 2 There are M+1 storage units, namely storage unit 0, storage unit 1, and storage unit 2. Each storage unit stores a set of data, and each set of data includes 3 data items, with each data item occupying one row. As shown in storage unit 0, it stores data 1, and the three data items of data 1 are stored as data 1_1 row, data 1_2 row, and data 1_3 row, respectively.
[0079] When writing data, the first frame of data (i.e. the first group of data) is placed in storage unit 0 corresponding to address 0, and the second frame of data is placed in storage unit 1 corresponding to address 1. After the second frame is stored, the FIFO's read pointer is at address 0, and the write pointer is at address 2 (where the read pointer and write pointer are separate).
[0080] When the third frame of data arrives, writing begins from address 2.
[0081] After the third frame is written, if the CPU has not read the data, the write pointer jumps to address 0, and the read pointer jumps directly to address 1. At this time, the original first frame data becomes invalid, and the latest data consists of the second and third frames, ensuring that the CPU can read the complete data of the latest frame whenever it comes to read. The single jump distance of the read pointer is the group depth.
[0082] During or after the third frame is written, if the CPU is reading data, the read pointer will start reading from address 0. When the CPU reads, it locks the FIFO using the FIFO's input locking function. After reading is complete, the FIFO is unlocked, and the first and second frames of data (data 1 and data 2) are read. In order to keep the latest two frames of data, the read pointer moves from address 2 back to address 1, and the write pointer moves to address 0.
[0083] The read pointer moves according to the CPU's read order. Regardless of whether writing is in progress, the write pointer will not exceed the read pointer, meaning it will not overwrite unread data, thus avoiding data loss.
[0084] After the reading is complete, the FIFO is unlocked, and the first and second frames of data (data 1 and data 2) are read away.
[0085] Optionally, in this embodiment of the application, the device includes:
[0086] The parameter determination module is used before the acquisition module 301 acquires the first data output by the target calculation module.
[0087] Determine the parameter information for the read operation; wherein the parameter information includes at least the number of data groups;
[0088] A module is established to create the FIFO storage module corresponding to the read operation based on the parameter information.
[0089] Optionally, in embodiments of this application, the apparatus further includes:
[0090] A receiving module is used to receive read operations from the CPU;
[0091] The address determination module is used to determine the first read address corresponding to the read operation;
[0092] The read module is used to read data from the FIFO storage module according to the first read address.
[0093] Optionally, in this embodiment of the application, the address determination module is used for:
[0094] Determine the first write address at the current moment;
[0095] Add a group address to the first write address to obtain the first read address corresponding to the read operation.
[0096] Optionally, in this embodiment of the application, the device includes:
[0097] A shielding module is used to shield the data write operation of the FIFO storage module after the reading module reads data from the FIFO storage module according to the first read address.
[0098] Optionally, in this embodiment of the application, the shielding module includes:
[0099] The control submodule is used to control the first write address of the data write operation to not exceed the read address at the current time if there is a data write operation in the process of execution.
[0100] Optionally, in this embodiment of the application, the control submodule is used for:
[0101] If the first write address of a write operation exceeds the current read address, the data written by the write operation is discarded.
[0102] The data processing device provided in this application embodiment can achieve... Figures 1 to 2 The various processes implemented in the method embodiments are not described in detail here to avoid repetition.
[0103] The data processing apparatus provided in this application includes an acquisition module 301 that acquires first data output by a target computing module; and a writing module 302 that determines the write address of the FIFO storage module of the electronic device and writes the first data to the storage unit corresponding to the write address. The FIFO storage module is a storage module corresponding to the CPU's read operation, and the FIFO storage module includes at least M+1 storage units. By setting the value of M, the number of frames for reading data can be easily increased, increasing flexibility. Furthermore, when writing data, address operations can be ignored, and data can be directly written to the FIFO, making operation convenient. During data reading, unread data will not be overwritten, preventing data loss and ensuring data security.
[0104] The data processing device of this application embodiment can execute the data processing method provided in this application embodiment. The implementation principle is similar. The actions performed by each module and unit in the data processing device in each embodiment of this application are corresponding to the steps in the data processing method in each embodiment of this application. For detailed functional descriptions of each module of the data processing device, please refer to the descriptions in the corresponding data processing methods shown above. They will not be repeated here.
[0105] Based on the same principles as the methods shown in the embodiments of this application, this application also provides an electronic device, which may include, but is not limited to: a processor and a memory; the memory for storing computer programs; and the processor for executing the data processing method shown in any optional embodiment of this application by calling the computer program. Compared with the prior art, the data processing method provided by this application obtains first data output by a target computing module; determines the write address of the FIFO storage module of the electronic device, and writes the first data to the storage unit corresponding to the write address; wherein, the FIFO storage module is a storage module corresponding to the CPU's read operation, and the FIFO storage module includes at least M+1 storage units; by setting the value of M, the number of frames for reading data can be easily increased, increasing flexibility; and when writing data, address operations can be ignored, and data can be directly written to the FIFO, making the operation convenient; during the data reading process, unread data will not be overwritten, avoiding data loss and ensuring data security.
[0106] In an alternative embodiment, an electronic device, such as Figure 4 As shown, Figure 4 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of this application.
[0107] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.
[0108] Bus 4002 may include a pathway for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.
[0109] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.
[0110] The memory 4003 stores computer programs that execute embodiments of this application, and its execution is controlled by the processor 4001. The processor 4001 executes the computer programs stored in the memory 4003 to implement the steps shown in the foregoing method embodiments.
[0111] Among them, electronic devices include, but are not limited to: mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (such as in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 4 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.
[0112] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the steps and corresponding content of the aforementioned method embodiments.
[0113] This application also provides a computer program product, including a computer program that, when executed by a processor, can implement the steps and corresponding content of the aforementioned method embodiments.
[0114] The terms "first," "second," "third," "fourth," "1," "2," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown in the figures or text.
[0115] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.
[0116] The above description is only an optional implementation method for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application without departing from the technical concept of this application also fall within the protection scope of the embodiments of this application.
Claims
1. A data processing method applied to electronic devices, characterized in that, include: Obtain the first data output by the target calculation module; Determine the write address of the first-in-first-out (FIFO) storage module of the electronic device, and write the first data to the storage unit corresponding to the write address; The FIFO storage module is a storage module corresponding to the read operation of the central processing unit (CPU). The number of data groups in the read operation is M. The FIFO storage module includes at least M+1 storage units, where M is a positive integer. Receive the read operation from the CPU; Determine the first write address at the current moment; Add a group address to the first write address to obtain the first read address corresponding to the read operation; Data is read from the FIFO storage module according to the first read address; During the CPU's data reading process, the read pointer moves according to the CPU's reading order, and the write pointer never exceeds the read pointer, regardless of whether writing is in progress.
2. The data processing method according to claim 1, characterized in that, Before obtaining the first data output by the target calculation module, the method includes: Determine the parameter information for the read operation; wherein the parameter information includes at least the number of data groups; Based on the parameter information, a FIFO storage module corresponding to the read operation is established.
3. The data processing method according to claim 1, characterized in that, After reading data from the FIFO storage module according to the first read address, the method includes: Data write operations of the FIFO storage module are disabled.
4. The data processing method according to claim 3, characterized in that, The data write operation of the shielded FIFO storage module includes: If there is a data write operation during execution, the first write address of the data write operation is controlled to not exceed the read address at the current time.
5. The data processing method according to claim 4, characterized in that, The control that the first write address of the data write operation does not exceed the read address at the current moment includes: If the first write address of a write operation exceeds the current read address, the data written by the write operation is discarded.
6. A data processing device, applied to electronic equipment, characterized in that, include: The acquisition module is used to acquire the first data output by the target calculation module. The write module is used to determine the write address of the first-in-first-out (FIFO) storage module of the electronic device and write the first data to the storage unit corresponding to the write address. The FIFO storage module is a storage module corresponding to the read operation of the central processing unit (CPU). The number of data groups in the read operation is M. The FIFO storage module includes at least M+1 storage units, where M is a positive integer. A receiving module is used to receive read operations from the CPU; The address determination module is used to determine the first write address at the current moment; add a group address to the first write address to obtain the first read address corresponding to the read operation; A read module is used to read data from the FIFO storage module according to the first read address; During the CPU's data reading process, the read pointer moves according to the CPU's reading order, and the write pointer never exceeds the read pointer, regardless of whether writing is in progress.
7. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method of any one of claims 1 to 5.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 5.
9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 5.