A process scheduling method and a computing device

Abstract

The application discloses a process scheduling method and a computing device. The method is executed in an operating system of the computing device, the computing device comprises a plurality of nodes connected in communication, each node comprises one or more processors and an internal memory, each processor is adapted to run a process, the internal memory of the node where the process is located comprises a virtual memory area of the process, the virtual memory area comprises a memory page, the method comprises the steps that in response to a request of the process accessing the memory page, it is judged whether the memory page is a shared memory page; if yes, it is judged whether the number of times of continuous access of the process to the memory page is greater than a first threshold; if yes, a processor whose load satisfies a predetermined condition is selected as a target processor from the node where the memory page is located or the nearest node, and the process is migrated to the target processor. According to the technical scheme of the application, the process can avoid accessing a remote memory far away, and the speed of the process accessing the shared memory is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a process scheduling method and a computing device. BACKGROUND

[0002] The basic feature of NUMA server is to have multiple CPU modules (nodes), each of which can include one or more CPUs and has independent local memory, I / O slots, etc. Since each node can be connected and interact information through the crossbar switch, each CPU can access the memory of the entire system. However, the speed of CPU accessing local memory is much higher than that of accessing remote memory (the memory of other nodes in the system).

[0003] When multiple processes run on the CPUs of different nodes and communicate, in order to solve the problem that the shared memory page accessed by the process is in a different node from the node where the process is located, and there is a cross-node access to the remote memory, resulting in slow access speed, according to the current process scheduling scheme under the NUMA architecture, the system will periodically scan the VMA (virtual memory area) of the process, and when scanning, it will detect whether the memory page of each VMA area meets the condition of setting the PAGE_NONE flag. If it meets the condition, the flag will be set. In this way, when the memory page is actually accessed, the pte_fault will be triggered, and the exception handling will be performed, mainly by migrating the process or migrating the memory to handle the exception, so as to solve the problem of process accessing remote memory and optimize the communication performance between processes in different nodes.

[0004] According to the above process scheduling scheme, for the mmap shared memory application mode, if it is a file mapping mode, multiple processes accessing different nodes will cause memory to be migrated back and forth; if it is an anonymous mapping, based on the memory allocation strategy, the memory page of the VMA area cannot be marked, resulting in the problem of process accessing remote memory cannot be solved. For the shemget shared memory application mode, based on the memory allocation strategy, the memory page of the VMA area cannot be marked, resulting in the problem of process accessing remote memory cannot be solved.

[0005] Therefore, a process scheduling method is needed to solve the problems in the above scheme. SUMMARY

[0006] Therefore, the present application provides a process scheduling method and a computing device to solve or at least alleviate the above problems.

[0007] According to an aspect of the present application, there is provided a process scheduling method, which is executed in an operating system of a computing device, the computing device comprising a plurality of nodes connected in communication, each node comprising one or more processors adapted to run a process and an internal memory, a virtual memory area of the process comprising memory pages being included in the internal memory of the node where the process is located, the method comprising the steps of: in response to a request of the process accessing a memory page, determining whether the memory page is a shared memory page; if the memory page is a shared memory page, determining whether a number of consecutive accesses of the memory page by the process is greater than a first threshold; if the number of consecutive accesses is greater than the first threshold, selecting a processor having a load satisfying a predetermined condition as a target processor from the node where the memory page is located or a nearest node, and migrating the process to the target processor.

[0008] Optionally, in the process scheduling method according to the present application, the step of determining whether the memory page is a shared memory page comprises: determining whether the memory page is provided with an exception flag; if the memory page is provided with the exception flag, determining whether a virtual memory area to which the memory page belongs has a shared flag; and if the virtual memory area has the shared flag, determining that the memory page is a shared memory page.

[0009] Optionally, in the process scheduling method according to the present application, the step of selecting a processor having a load satisfying a predetermined condition as a target processor comprises: selecting a processor having a load less than a second threshold as the target processor from the node where the memory page is located.

[0010] Optionally, in the process scheduling method according to the present application, the step of selecting a processor having a load less than a second threshold as the target processor from the node where the memory page is located comprises: selecting a first least idle processor from the node where the memory page is located, determining whether a load of the first least idle processor is less than the second threshold; and if the load of the first least idle processor is less than the second threshold, selecting the first least idle processor as the target processor.

[0011] Optionally, in the process scheduling method according to the present application, the step of selecting a processor having a load less than a second threshold as the target processor from the node where the memory page is located further comprises: if the load of the first least idle processor is greater than or equal to the second threshold, selecting a second least idle processor from a nearest node to the node where the memory page is located, determining whether a load of the second least idle processor is less than the second threshold; if the load of the second least idle processor is less than the second threshold, selecting the second least idle processor as the target processor; and if the load of the second least idle processor is greater than or equal to the second threshold, selecting the first least idle processor as the target processor.

[0012] Optionally, in the process scheduling method according to the present application, before judging whether the number of times that the process continuously accesses the memory page is greater than a first threshold, the method comprises the step of recording the number of times that the process continuously accesses the memory page.

[0013] Optionally, in the process scheduling method according to the present application, the step of judging whether the virtual memory region to which the memory page belongs has a shared mark further comprises: if the virtual memory region to which the memory page belongs does not have a shared mark, judging whether the memory page can be migrated; and if the memory page cannot be migrated, migrating the process to the node where the memory page is located.

[0014] Optionally, in the process scheduling method according to the present application, before responding to the request of the process to access the memory page, the method comprises the steps of: periodically scanning the virtual memory region of the process, judging whether the virtual memory region has a shared mark; and if the virtual memory region has a shared mark, judging whether the node where the memory page of the virtual memory region is located is the same as the node where the process is located, and if not, setting an exception mark for the memory page.

[0015] Optionally, in the process scheduling method according to the present application, the step of judging whether the virtual memory region has a shared mark further comprises: if the virtual memory region does not have a shared mark, determining whether the memory page is a file page and whether the memory page is a dirty page; if the memory page is a file page and is not a dirty page, judging whether the node where the memory page is located is the same as the node where the process is located, and if not, setting an exception mark for the memory page.

[0016] According to an aspect of the present application, there is provided a computing device comprising: at least one processor; a memory storing program instructions configured to be executed by the at least one processor, the program instructions comprising instructions for performing the process scheduling method as described above.

[0017] According to an aspect of the present application, there is provided a readable storage medium storing program instructions, which, when read and executed by a computing device, cause the computing device to perform the process scheduling method as described above.

[0018] According to the technical scheme of the present application, a process scheduling method is provided, an exception mark is set for a shared memory page, and when it is determined based on the exception mark and a shared mark that a process continuously accesses the shared memory page, the process is migrated. Wherein, a processor with the least load is selected as a target processor from a node where the memory page is located or a node closest to the memory page, and the process accessing the memory page is migrated to the target processor. In this way, the present application fully considers the distance between the target processor after process migration and the shared memory and the load of the target processor, and the process after migration can be in the same node as the shared memory or run in a processor of a node closest to the shared memory, so as to ensure that the process accesses the shared memory closest, avoid the process accessing a remote memory far away, improve the speed of process accessing the shared memory, and thus optimize inter-process communication and process running performance. In addition, according to the technical scheme of the present application, the memory is not migrated, so as to prevent the problem of repeatedly migrating the memory when multiple processes run in different nodes.

[0019] The above description is only a summary of the technical scheme of the present application, in order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to achieve the above and related purposes, certain illustrative aspects will be described herein in connection with the following description and drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings. Throughout the disclosure, like reference numerals generally refer to like parts or elements throughout the disclosure.

[0021] Figure 1 A schematic diagram of a computing device 100 according to one embodiment of the present application is shown;

[0022] Figure 2 , Figure 3 A flowchart of a process scheduling method 200 according to one embodiment of the present application is shown respectively;

[0023] Figure 4 A hardware structure schematic diagram of a computing device 100 according to one embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] Exemplary embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0025] The present disclosure provides a process scheduling scheme, so that the process can run on the processor of the relatively nearest node to access the shared memory page, to solve the problem of slow speed of process accessing the remote memory, and optimize the communication performance between processes in different nodes.

[0026] Figure 1 A schematic diagram of a computing device 100 according to an embodiment of the present disclosure is shown. As shown, the computing device 100 includes a hardware layer, an operating system 120, and one or more processes 110. The one or more processes 110 run based on the hardware layer and the operating system, and it should be noted that the number and types of processes are not limited by the present disclosure. Figure 1

[0027] The operating system 120 runs in the computing device 100, and the operating system 120 can provide a software running environment for the one or more processes 110. The operating system 120 includes a kernel 125, which is responsible for process management, memory management, file management (e.g., management of file storage space, directory management, file read-write management), device management (e.g., I / O request, buffer management, driver), etc.

[0028] The hardware layer can provide a hardware running environment for the operating system 120 and the processes 110 in the computing device. As shown, Figure 1 the hardware layer includes a plurality of nodes 150 connected in communication, and each node 150 includes one or more processors 151 and an internal memory 152 connected to the one or more processors 151. Here, the plurality of nodes 150 can be connected in communication through a crossbar switch to realize data interaction. Based on this, the processor 151 of each node 150 can access the internal memory 152 of all nodes in the computing device 100.

[0029] It should be noted that, Figure 1 The number of nodes 150 included in the hardware layer shown and the number of processors 151 included in each node 150 are exemplary, and the number of nodes and the number of processors in each node are not limited by the present disclosure.

[0030] ​It should be noted that each processor 151 can run a process. For each processor 151, the internal memory 152 at the same node as the processor 151 is the local memory of the processor 151, and the internal memory 152 at a different node from the processor 151 is the remote memory. It should be noted that the distance between the processor 151 and the local memory is the closest, so the speed of accessing the local memory is the fastest. In other words, the distance between the processor 151 and the local memory is less than the distance between the processor 151 and the remote memory, and therefore, the speed of the processor 151 accessing the local memory is much higher than the speed of accessing the remote memory.

[0031] When the process 110 runs on the processor, the kernel 125 of the operating system 120 can be applied to create a virtual memory area of the process in the internal memory 152 of the node 150 where the process is located (i.e., the local memory of the processor 151), so that the internal memory of the node where the process is located includes the virtual memory area created for the process. The virtual memory area includes memory pages.

[0032] When multiple processes 110 run on processors of different nodes and communicate, the multiple processes can communicate based on shared memory. Specifically, the process can apply for shared memory to the kernel 125 of the operating system through shmget, mmap, etc., so as to create a shared memory area in the internal memory 152 of the node 150 where the process 110 is located, so as to communicate with other processes based on the shared memory area. It should be noted that the shared memory area belongs to the virtual memory area, and the difference between the shared memory area and the ordinary virtual memory area is that the shared memory area has a shared flag. Based on this, whether the virtual memory area is a shared memory area can be determined by judging whether the virtual memory area has a shared flag.

[0033] According to an application scenario, when a first process runs on a first processor of a first node, a shared memory area can be created in the first internal memory of the first node. When a second process runs on a second processor of a second node, if data transmission with the first process is needed, the shared memory area created by the first process in the first internal memory of the first node needs to be accessed, so that for the second process, the remote memory needs to be accessed, and the access speed is slow.

[0034] To solve the technical problem existing in the application scenario, the operating system 120 executes the process scheduling method 200 of the application to avoid the process accessing the remote memory far away, and optimizes the communication performance between the processes running on different nodes. Specifically, the process scheduling method 200 of the application is executed in the kernel 125 of the operating system 120.

[0035] In an embodiment according to the present application, the operating system of the computing device 100 is configured to perform the process scheduling method 200 according to the present application. The operating system of the computing device 100 contains a plurality of program instructions for performing the process scheduling method 200 according to the present application, which can instruct the processor to perform the process scheduling method 200 according to the present application.

[0036] Figure 2 、 Figure 3 A flowchart of the process scheduling method 200 according to an embodiment of the present application is shown in FIG. 2. The method 200 is suitable for performing in the operating system of a computing device, such as the aforementioned computing device 100.

[0037] In an embodiment of the present application, one or more processes can run on the operating system, and the one or more processes can run on processors of different nodes. When a process runs on a processor, the process can apply to the kernel of the operating system for creating a virtual memory area of the process in the internal memory of the node where the process is located. In this way, the internal memory of the node where the process is located includes the virtual memory area created for the process. Further, the process can also apply to the kernel of the operating system for shared memory, so as to create a shared memory area in the internal memory of the node where the process is located, so that the process can communicate with other processes based on the shared memory area.

[0038] As shown in FIGS. 2A and 2B, the method 200 starts at step S210. Figure 2 Figure 3 In an embodiment, before performing step S210, the operating system can periodically scan the virtual memory area of each process to determine whether the virtual memory area of the process has a shared flag.

[0039] If the virtual memory area has a shared flag, it means that the virtual memory area is a shared memory area, and then it is further determined whether the node where the memory page of the virtual memory area (shared memory area) is located is the same as the node where the process is located. If not, an exception flag is set for the memory page of the virtual memory area (shared memory area). Here, the exception flag set for the memory page of the shared memory area (shared memory page) is, for example, a PAGE_NONE flag.

[0040] That is, when the virtual memory area of the process is a shared memory area and is not located in the same node as the process, an exception flag is set for the shared memory page.

[0041] That is, when the virtual memory area of the process is a shared memory area and is not located in the same node as the process, an exception flag is set for the shared memory page.

[0042] ​Additionally, if a virtual memory region does not have a shared flag, it indicates that the virtual memory region is not a shared memory region. Then: determine if a memory allocation policy exists. If a memory allocation policy exists, it is impossible to set an exception flag for the memory pages of the virtual memory region. If no memory allocation policy exists, continue to determine if the memory pages of the virtual memory region are file pages or dirty pages. If the memory pages of the virtual memory region are file pages and not dirty pages, further determine if the node where the memory pages of the virtual memory region reside is the same as the node where the process resides. If they are not the same, then an exception flag is set for the memory pages.

[0043] In this way, by identifying the abnormal markers of memory pages in the virtual memory region accessed by a process, the process accessing the memory page with the abnormal marker can be migrated to avoid the process accessing remote memory that is far away.

[0044] like Figure 2 As shown, in step S210, in response to a process's request to access a memory page, it is determined whether the memory page is a shared memory page. If it is determined that the memory page is a shared memory page, then step S220 is executed.

[0045] Specifically, step S210 can be performed according to the following steps:

[0046] like Figure 3 As shown, firstly, it is determined whether the memory page has an exception flag set. Here, the exception flag is, for example, the PAGE_NONE flag. It can be understood that by determining whether a memory page has an exception flag, it can be determined whether the memory page is a shared memory page.

[0047] If an exception flag is set on a memory page, it is further determined whether the virtual memory region to which the memory page belongs has a shared flag, in order to determine whether the virtual memory region accessed by the process is a shared memory region and whether the memory page accessed by the process is a shared memory page.

[0048] If the virtual memory region to which the memory page belongs has a shared flag, it indicates that the virtual memory region is a shared memory region, and correspondingly, the memory page is a shared memory page. In this case, proceed to step S220.

[0049] In step S220, the number of times the process continuously accesses the memory page is recorded, and it is determined whether the number of times the process continuously accesses the memory page is greater than the first threshold.

[0050] Finally, in step S230, if the number of consecutive memory page accesses by the process exceeds a first threshold, the process is migrated. From multiple processors located on the node where the accessed memory pages reside or from the nearest processor, a processor whose load meets predetermined conditions is selected as the target processor, and the process is migrated to the target processor.

[0051] If the number of times the process continuously accesses the memory page is less than or equal to a first threshold value, the process is not subjected to the migration processing.

[0052] It should be noted that the first threshold value is a minimum value set for the number of times the process continuously accesses the memory page. In the case where the number of times the process continuously accesses the memory page exceeds the first threshold value, it can be determined that the process needs to frequently access the memory page, and by migrating the process to a processor relatively closer to the memory page, the speed of the process accessing the memory page can be improved, so as to improve the performance of the process.

[0053] In an embodiment, the processor whose load satisfies the predetermined condition can be a processor whose load is less than a second threshold value. Here, the second threshold value is a maximum value of the load set for the processor. It should be noted that the present application does not specifically limit the second threshold value, which can be set by the person skilled in the art according to actual needs. In an implementation, the second threshold value is, for example, 600, and the occupancy rate of the processor is 10%.

[0054] Preferably, the processor whose load is less than the second threshold value can be selected from the node where the memory page is located as the target processor, so that after the process is migrated to the target processor, the migrated process can be in the same node as the shared memory page to be accessed.

[0055] Specifically, if there is a processor whose load is less than the second threshold value in the node where the memory page is located, the least idle processor (i.e., the processor with the smallest load) in the node where the memory page is located is determined as the target processor, and the process is migrated to the target processor. It can be understood that by judging whether the load of the least idle processor in the node where the memory page is located is less than the second threshold value, if the load of the least idle processor in the node where the memory page is located is less than the second threshold value, the least idle processor in the node can be directly selected as the target processor.

[0056] Further, from the multiple processors in the node where the memory page is located or the nearest node, the processor whose load satisfies the predetermined condition is selected as the target processor, which can be specifically implemented according to the following steps:

[0057] First, the least idle processor (first least idle processor) is selected from the node where the memory page is located, and it is judged whether the load of the first least idle processor is less than the second threshold value.

[0058] If it is less than the second threshold value, the first least idle processor is selected as the target processor. In this way, the process can be migrated to the least idle processor of the node where the memory page is located. In this case, the migrated process is closest to the memory page, and accesses the local memory, so the access speed is the fastest.

[0059] If the load of the first least busy processor is greater than or equal to the second threshold value, it indicates that there is no processor in the node where the memory page is located with a load less than the second threshold value. At this time, the least busy processor (the second least busy processor) can be selected from the node closest to the node where the memory page is located, and it is determined whether the load of the second least busy processor is less than the second threshold value.

[0060] If the load of the second least busy processor is less than the second threshold value, the second least busy processor can be selected as the target processor. In this way, the process can be migrated to the least busy processor in the node closest to the memory page. In this case, the process after migration is relatively close to the memory page, and the access speed is relatively fast.

[0061] In addition, if the load of the second least busy processor is greater than or equal to the second threshold value, it indicates that there is no processor in the node closest to the node where the memory page is located with a load less than the second threshold value. In this case, the first least busy processor selected from the node where the memory page is located can be determined as the target processor. In this way, while ensuring that the process after migration is closest to the memory page, the load of the processor running the process is as low as possible, and the process avoids accessing remote memory.

[0062] According to the above steps, the processor with the smallest load is selected as the target processor from the node where the memory page is located or the node closest to the memory page, and the process accessing the memory page is migrated to the target processor. In this way, the present application fully considers the distance between the target processor after process migration and the shared memory region accessed, and the load of the target processor. The process after migration can be in the same node as the shared memory region, or run in the processor in the node closest to the shared memory region.

[0063] In addition, when it is determined in step S210 whether the virtual memory region to which the memory page belongs has a shared mark, if it is determined that the virtual memory region to which the memory page belongs does not have a shared mark, it indicates that the virtual memory region is not a shared memory region, and it is further determined whether the memory page can be migrated. If the memory page cannot be migrated, the process can be migrated to the node where the memory page is located. If the memory page can be migrated, the memory page can be migrated to the node where the processor currently running the process is located.

[0064] According to the process scheduling method of the present invention, an exception flag is set for shared memory pages. When it is determined based on the exception flag and the shared memory flag that a process continuously accesses shared memory pages, the process is migrated. Specifically, the processor with the least load is selected from the node where the memory page is located or the node closest to the memory page as the target processor, and the process accessing the memory page is migrated to the target processor. In this way, the present invention fully considers the distance between the target processor after process migration and the accessed shared memory, as well as the load of the target processor. The migrated process can be located on the same node as the shared memory or run on the processor of the node closest to the shared memory, ensuring that the process accesses shared memory at the shortest distance and avoiding the process accessing distant memory, thereby improving the speed of process access to shared memory and optimizing inter-process communication and process execution performance. Furthermore, according to the technical solution of the present invention, memory migration is not performed, thus preventing the problem of repeated memory migration caused by multiple processes running on different nodes.

[0065] Figure 4 A schematic diagram of the hardware structure of a computing device 100 according to an embodiment of the present invention is shown. Figure 4 As shown, the computing device 100 may include an input device 90, a processor 91, an output device 92, a memory 93, and at least one communication bus 94. The communication bus 94 is used to realize communication connections between components. The memory 93 may include high-speed RAM memory, and may also include non-volatile memory (NVM), such as at least one disk storage device. The memory 93 may store various program instructions for performing various processing functions and implementing the process scheduling method in the embodiments of the present invention.

[0066] Optionally, the processor 91 may be implemented as a central processing unit (CPU), application-specific integrated circuit (ASIC), digital signal processor (DSP), digital signal processing device (DSPD), programmable logic device (PLD), field-programmable gate array (FPGA), controller, microcontroller, microprocessor or other electronic components, and the processor 91 is coupled to the input device 90 and output device 92 via wired or wireless connection.

[0067] Optionally, the input device 90 can include a plurality of input devices, such as at least one of a user interface facing a user, a device interface facing a device, a programmable interface of software, a camera, and a sensor. Optionally, the device interface facing a device can be a wired interface for data transmission between devices, and can also be a hardware insertion interface (such as a USB interface, a serial port, etc.) for data transmission between devices; optionally, the user interface facing a user can be, for example, a control button facing a user, a voice input device for receiving voice input, and a touch sensing device (such as a touch screen, a touch pad, etc.) for receiving touch input of a user; optionally, the programmable interface of software can be, for example, an entry for a user to edit or modify a program, such as an input pin interface or an input interface of a chip, etc.; optionally, the transceiver can be a radio frequency transceiver chip, a baseband processing chip, a transceiving antenna, etc. with communication functions. The audio input device such as a microphone can receive voice data. The output device 92 can include a display, an audio output device, etc.

[0068] In one embodiment of the present application, the computing device 100 includes one or more processors, and one or more readable storage media storing program instructions. When the program instructions are configured to be executed by the one or more processors, the computing device performs the process scheduling method in the embodiments of the present application.

[0069] The various techniques described herein can be implemented in connection with hardware or software or, where appropriate, with a combination of both. Thus, the methods and apparatus of the present application, or certain aspects or portions thereof, can take the form of program code (i.e., instructions) embodied in tangible media, such as removable hard disks, USB drives, floppy disks, CD-ROMs, or any other machine-readable storage medium wherein, when the program code is loaded into an apparatus, such as a computer, the apparatus becomes an implementation of the present application for practicing the methods.

[0070] In the case of program code execution on programmable computers, the mobile terminal generally includes a processor, a processor-readable storage medium (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store program code; the processor is configured to execute instructions in the program code stored in the memory to perform the process scheduling method of the present application.

[0071] By way of example, and not limitation, a readable medium includes a readable storage medium and a communication medium. A readable storage medium stores information such as computer readable instructions, data structures, program modules or other data. A communication medium conveys information such as computer readable instructions, data structures, program modules or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information delivery media. Combinations of the any of the above are also included within the scope of readable media.

[0072] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order to not obscure the understanding of this description.

[0073] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order to not obscure the understanding of this description.

[0074] Similarly, it is to be understood that the narrative provided above in the description of illustrative embodiments of the application sometimes describes individual features or groups of features in terms of the way in which the individual features or groups of features cooperate to provide the improved results. This collaboration between individual features or groups of features is not to be interpreted as a requirement that the individual features or groups of features cooperate to provide the improved results in every instance or in every example of the application. In fact, the improved results can be provided in certain instances or in certain examples of the application by only some of the individual features or groups of features described above.

[0075] Those skilled in the art will understand that the modules, or units, or components of the devices in the examples disclosed herein can be arranged in a device as described in the examples, or alternatively can be located in one or more devices different from the devices in the examples. The modules in the foregoing examples can be combined as a module or further divided into multiple sub-modules.

[0076] Those skilled in the art will appreciate that the modules in the apparatuses in the embodiments can be adapted and placed in one or more apparatuses other than the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and further can be split into multiple sub-modules or sub-units or sub-components. Any combination of all the features disclosed in the specification (including the accompanying claims, abstract and drawings), and any method or process or steps of any such methods or processes disclosed in the specification (including the accompanying claims, abstract and drawings) can be made, except that at least some of such features and / or processes or units are mutually exclusive, unless explicitly stated otherwise. Each feature disclosed in the specification (including the accompanying claims, abstract and drawings) can be replaced by alternative features serving the same, equivalent or similar purpose, unless explicitly stated otherwise.

[0077] Furthermore, those skilled in the art will appreciate that the features of the various embodiments described herein are not mutually exclusive and can be combined in different embodiments. For example, in the following claims, any of the embodiments claimed can be used in any combination.

[0078] Furthermore, some of the embodiments described herein are described as a method or combination of elements of a method implementable by a processor of a computer system or by other means of carrying out the function. Accordingly, a processor with the necessary instructions for carrying out such a method or element of a method forms a means for carrying out the method or element of a method. Furthermore, an element of a method described herein that is implemented as a means for carrying out a particular function performs that function whether or not recited as a means for carrying out that function.

[0079] As used herein, unless otherwise indicated, the use of the ordinal adjectives "first", "second", "third" and so on, in no way limits the number of objects that can be described by the terms. For example, a "first" object can be described simultaneously with a "second" object, even though only two objects can be described.

[0080] While the application has been described in accordance with the various embodiments shown and described, it is to be understood that the application is not limited to those precise embodiments, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present application. It is intended that the scope of the application should only be limited as recited in the appended claims.

Claims

1. A process scheduling method, executed in an operating system of a computing device, the computing device comprising multiple communicatively connected nodes, each node comprising one or more processors and internal memory, each processor being adapted to run a process, the internal memory of the node where the process resides comprising a virtual memory region for the process, the virtual memory region comprising memory pages, the method comprising the steps of: The virtual memory region of the process is periodically scanned to determine whether the virtual memory region has a shared tag; If the virtual memory region has a shared flag, then it is determined whether the node where the memory page of the virtual memory region is located is the same as the node where the process is located. If they are not the same, then an exception flag is set for the memory page. If the virtual memory region does not have a shared flag, then determine whether the memory page of the virtual memory region is a file page or a dirty page. If the memory page is a file page and not a dirty page, then determine whether the node where the memory page is located is the same as the node where the process is located. If they are not the same, then set an exception flag for the memory page. In response to a process's request to access a memory page, determining whether the memory page is a shared memory page includes: determining whether the memory page has an exception flag set; if an exception flag is set, determining whether the virtual memory region to which the memory page belongs has a shared flag; if the virtual memory region to which the memory page belongs has a shared flag, determining that the memory page is a shared memory page; if the virtual memory region to which the memory page belongs does not have a shared flag, determining whether the memory page can be migrated; if the memory page cannot be migrated, migrating the process to the node where the memory page is located. If the memory page is a shared memory page, then determine whether the number of times the process accesses the memory page consecutively is greater than a first threshold; If the load is greater than the first threshold, then a processor with a load less than the second threshold is selected as the target processor from the node where the memory page is located or the nearest node, and the process is migrated to the target processor.

2. The method of claim 1, wherein, The step of selecting a processor with a load less than a second threshold from the node where the memory page is located as the target processor includes: Select the first idle processor from the node where the memory page is located, and determine whether the load of the first idle processor is less than the second threshold; If it is less than the second threshold, then the first idle processor is selected as the target processor.

3. The method of claim 2, wherein, The step of selecting a processor with a load less than a second threshold from the node where the memory page is located as the target processor further includes: If the load of the first idle processor is greater than or equal to the second threshold, then the second idle processor is selected from the node closest to the node where the memory page is located, and it is determined whether the load of the second idle processor is less than the second threshold. If the load of the second idle processor is less than the second threshold, then the second idle processor is selected as the target processor. If the load of the second idle processor is greater than or equal to the second threshold, then the first idle processor is selected as the target processor.

4. The method of any one of claims 1-3, wherein, Before determining whether the number of consecutive accesses to the memory page by the process is greater than a first threshold, comprising the steps of: recording the number of consecutive accesses to the memory page by the process.

5. A computing device comprising: at least one processor; and a memory storing program instructions configured to be executed by the at least one processor, the program instructions comprising instructions for performing the method of any one of claims 1-4.

6. A readable storage medium storing program instructions which, when read and executed by a computing device, cause the computing device to perform the method of any one of claims 1-4. ​

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