A memory controller for improving data integrity and an operation method thereof

Abstract

The present invention relates to a memory controller (100) for improving data integrity and providing data security. The memory controller (100) includes a transmission data path for transmitting write data to a memory device (2); the transmission data path includes a scrambling component (4); the scrambling component (4) includes a scrambling logic (12) and an exclusive OR logic (14); the write data is divided into a first part and a second part; the input of the scrambling logic (12) includes the first part of the write data and an address associated with the write data to generate a pseudo-random output; the input of the exclusive OR logic (14) includes the second part of the write data, the pseudo-random output, and a fixed seed corresponding to the first part of the write data to generate scrambled data. In addition, the present invention also relates to a method of operating the memory controller (100).

Description

Technical Field

[0001] The present invention generally relates to a memory controller for improving data integrity and providing data security, and more particularly to a memory controller equipped with an error correction code (ECC) implementation and a data scrambling / descrambling implementation. The present invention also relates to a method of operating a memory controller. Background Art

[0002] Memory devices, such as dynamic random access memories (DRAMs), store electronic data, and a memory controller manages the electronic data stream to and from the memory device. For written data, some memory controllers scramble the electronic data and encode the scrambled data before storing the electronic data in the memory device. Among them, scrambling can be used to improve the signal-to-noise ratio on the DRAM interface, and encoding can be used to perform error correction coding or data recovery.

[0003] Reading the stored data involves decoding the stored data and descrambling the decoded data before returning the original electronic data to the user. To provide reliable data transmission, many efforts have been made to provide optimized memory controllers. Some of these examples are discussed in the following references.

[0004] GB2453259A discloses an integrated circuit that includes a transmission data path for transmitting data to one or more dynamic random access memory devices. The random access memory device includes scrambling logic to generate N uncorrelated pseudo-random outputs in parallel. The data to be transmitted with M bits and the pseudo-random outputs are input to XOR logic, thereby outputting M scrambled bits in parallel. Thus, the scrambled output has a substantially white spectrum. The scrambling logic uses a linear feedback shift register (LFSR), where the seed, which can itself be scrambled before use, is based on a memory address, such as a column address. The polynomial for the LFSR can be X 16 +X 13 +X 10 +X 9 +X 8 +X 4 +1. This scrambling method can be used to suppress power supply noise in, for example, a double data rate (DDR) memory system.

[0005] US2015012788A1 discloses a method for selecting scrambled and descrambled data in a storage system including an ECC and a scrambling engine with a seed table. The steps of the method include: an ECC encoding engine encodes data sent from a HOST interface and transmits the data to an LFSR scrambling engine; the LFSR scrambling engine scrambles the data and then the data is transmitted to a memory device; the LFSR scrambling engine creates a seed value and transmits the seed value to the seed table; the LFSR descrambling engine receives the seed value from the seed table and the scrambled data from the memory device, and descrambles the scrambled data based on the seed value and transmits it to the ECC decoding engine; and decodes the descrambled data received from the LFSR descrambling engine, and then obtains the original data sent from the host interface.

[0006] The foregoing references and other solutions may strive to provide an improved memory controller. However, they still have many limitations and deficiencies. For example, they only use the memory address as the scrambling / descrambling seed. Using only the memory address as the scrambling / descrambling seed will produce a predictable data pattern, which may cause signal integrity problems due to resonance. In addition, none of the memory controllers in the foregoing references disclose a modular ECC implementation that can support any DRAM interface width or protocol.

[0007] Therefore, there is still a need for a memory controller that can overcome the above problems and disadvantages. Summary of the Invention

[0008] The following brief description of the invention provides a basic understanding of certain aspects of the invention. This brief description is not an extensive overview of the invention, and its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description hereinafter.

[0009] An object of the present invention is to provide a memory controller that can improve data integrity and provide data security.

[0010] Another object of the present invention is to provide a data scrambling / descrambling implementation using multiple seeds.

[0011] Another object of the present invention is to provide a modular error correction code implementation that can support any DRAM interface width or protocol.

[0012] Another object of the present invention is to provide a modular error correction code implementation that can reduce routing congestion and simplify timing convergence across different data bytes with less power consumption.

[0013] Another object of the present invention is to provide a method for operating a memory controller to improve data integrity and provide data security.

[0014] Therefore, these objectives can be achieved by following the teachings of the present invention. The present invention relates to a memory controller for improving data integrity and providing data security. The memory controller includes a transmission data path for transmitting write data to a memory device; the transmission data path includes a scrambling component; the scrambling component includes scrambling logic and exclusive OR logic; the write data is divided into a first part and a second part; the input of the scrambling logic includes the first part of the write data and an address associated with the write data to generate a pseudo-random output; the input of the exclusive OR logic includes the second part of the write data, the pseudo-random output, and a fixed seed corresponding to the first part of the write data to generate scrambled data; the transmission data path further includes an error correction code encoding component, which includes a plurality of encoding paths, and each encoding path includes two error correction code encoders.

[0015] The memory controller further includes a receiving data path for receiving read data from the memory device. The receiving data path includes a descrambling component; the descrambling component includes descrambling logic, a first exclusive OR logic, and a second exclusive OR logic; the read data is divided into a first part and a second part; the input of the first exclusive OR logic includes the first part of the read data and a fixed seed corresponding to the first part of the read data to generate an output; the input of the descrambling logic includes the output and an address associated with the read data to generate a pseudo-random output; the input of the second exclusive OR logic includes the second part of the read data, the pseudo-random output, and a fixed seed corresponding to the first part of the read data to generate descrambled data; the receiving data path further includes an error correction code decoding component; the error correction code decoding component includes a plurality of decoding paths, and each decoding path includes two error correction code decoders.

[0016] In addition, the present invention relates to a method of operating a memory controller to improve data integrity and provide data security. The method includes the following steps: transmitting write data to the transmission data path; dividing the write data into a first part and a second part; generating a pseudo-random output through the scrambling logic based on the first part of the write data and an address associated with the write data; scrambling the second part of the write data through the exclusive OR logic in response to the pseudo-random output, and scrambling the first part of the write data in response to a fixed seed corresponding to the first part of the write data, thereby generating scrambled data; and encoding the scrambled data through the error correction code encoding component before transmitting the scrambled data to the memory device.

[0017] The method also includes the following steps: receiving read data from a memory device in a receive data path; decoding the read data through an error correction code decoding component; dividing the read data into a first part and a second part; generating an output through a first XOR logic based on the first part of the read data and a fixed seed corresponding to the first part of the read data; generating a pseudo-random output through a descrambling logic based on the output and an address associated with the read data; and descrambling the second part of the read data in response to the pseudo-random output and descrambling the first part of the read data in response to the fixed seed corresponding to the first part of the read data through a second XOR logic, thereby generating descrambled data.

[0018] The foregoing and other objects, features, aspects and advantages of the present invention will become more readily understood in conjunction with the detailed description provided herein below, with appropriate reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to understand the above-mentioned features of the present invention in detail, a more specific description of the present invention briefly summarized above can be drawn through embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present invention and are therefore not to be construed as limiting the scope of the present invention, because the present invention may allow other equivalent embodiments.

[0020] These and other features, benefits and advantages of the present invention will become apparent by reference to the following drawings, like reference numerals referring to like structures throughout the views, wherein:

[0021] Figure 1 A block diagram of a memory controller according to an embodiment of the present invention is shown.

[0022] Figure 2 A block diagram of a scrambling component according to an embodiment of the present invention is shown.

[0023] Figure 3 A block diagram of an implementation method of data scrambling and data descrambling according to an embodiment of the present invention is shown.

[0024] Figure 4 A block diagram of an error correction code encoding component according to an embodiment of the present invention is shown.

[0025] Figure 5 The embodiment of the present invention shows an implementation method of the error correction code.

[0026] Figure 6 A block diagram of an error correction code decoding component according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0027] As needed, detailed embodiments of the present invention are disclosed herein. However, it should be understood that the disclosed embodiments are merely examples of the present invention, which can be implemented in various forms. Therefore, the specific structural and functional details disclosed herein should not be construed as restrictive, but only as a basis for the claims. It should be understood that the accompanying drawings and their detailed description are not intended to limit the present invention to the specific form disclosed, but on the contrary, the present invention will cover all modifications, equivalent forms, and alternative forms falling within the scope of the present invention as defined by the claims. Among the terms used throughout this application, the word "may" means a permissive sense (i.e., it means there is a possibility), rather than a mandatory sense (i.e., it must). Similarly, the words "include, including, includes" mean including but not limited to. In addition, unless otherwise specified, the word "a, an" means "at least one", and the word "plurality" means one or more. In the case of using abbreviations or technical terms, they represent the general meanings recognized in the technical field.

[0028] Hereinafter, the present invention will be described with reference to the accompanying drawings through various embodiments, in which the reference numerals used in the drawings correspond to similar elements throughout the specification. However, the present invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the provided embodiments make the present disclosure sufficient and complete, and will fully convey the scope of the present invention to those skilled in the art. In the following detailed description, numerical values and ranges are provided for various aspects of the described embodiments. These numerical values and ranges should only be regarded as examples and are not intended to limit the scope of the claims. Additionally, many materials are identified as suitable for various aspects of the implementation. These materials will be regarded as exemplary and are not intended to limit the scope of the present invention.

[0029] The present invention will be described in more detail with reference to the accompanying drawings.

[0030] Figure 1A block diagram of a memory controller (100) according to an embodiment of the present invention is shown. The memory controller (100) includes a transmit data path and a receive data path. For write data, the transmit data path is configured to transmit the write data to a memory device (2) including but not limited to DRAM. Preferably, the transmit data path includes a scrambling component (4) and an error correction code encoding component (8). The transmit data path may be arranged such that the error correction code encoding component (8) is after the scrambling component (4). Alternatively, the transmit data path may also be arranged such that the scrambling component (4) is after the error correction code encoding component (8). For read data, the receive data path is configured to receive the read data from the DRAM. Preferably, the receive data path includes a descrambling component (6) and an error correction code decoding component (10). The receive data path may be arranged in a manner corresponding to the transmit data path to achieve a reverse processing flow. For example, when the error correction code encoding component (8) in the transmit data path is arranged after the scrambling component (4), the descrambling component (6) may be arranged after the error correction code decoding component (10) in the receive data path. Alternatively, when the scrambling component (4) in the transmit data path is arranged after the error correction code encoding component (8), the error correction code decoding component (10) may be arranged after the descrambling component (6) in the receive data path.

[0031] According to an embodiment of the present invention, the scrambling component (4), the descrambling component (6), the error correction code encoding component (8), and the error correction code decoding component (10) are respectively equipped with bypass paths in parallel to provide alternative paths for the data stream. When the error correction code encoding component (8) and the error correction code decoding component (10) are not used, the bypass paths can be used to bypass them. In addition, the bypass paths can also be used for testing and debugging purposes. For example, in the case of testing the scrambling component (4) and / or the error correction code encoding component (8), the bypass paths can be used to bypass the descrambling component (6) and / or the error correction code decoding component (10), so as to receive the original values to be compared with the expected values.

[0032] Figure 2A block diagram of a scrambling component (4) according to an embodiment of the present invention is shown. The scrambling component (4) includes a scrambling logic (12) and an exclusive - OR (XOR) logic (14). Preferably, the write data is divided into a first part and a second part. The input of the scrambling logic (12) includes the first part of the write data and an address associated with the write data to generate a pseudo - random output. In addition, the input of the XOR logic (14) includes the second part of the write data, the pseudo - random output, and a fixed seed corresponding to the first part of the write data to generate scrambled data. The scrambling logic (12) is initialized or seeded with the first part of the write data to ensure that even if the address and content are similar, the scrambled data will not be affected by content that generates patterns that may cause signal resonance, because after the first part of the write data is involved, the encrypted data will no longer be repeatable. In addition to the address, the first part of the write data is also applied as a scrambling seed, thereby providing a certain degree of data security because the scrambling seed is no longer predictable based solely on the address. An exclusive - OR operation is performed between the pseudo - random output and the fixed seed corresponding to the first part of the write data so that the scrambled data can be deterministically descrambled at a later stage. The scrambled data can then be encoded and / or stored in a DRAM.

[0033] According to an embodiment of the present invention, the scrambling logic (12) includes a linear feedback shift register (LFSR).

[0034] In one embodiment, the linear feedback shift register provides an output of 16 bits per cycle. Alternatively, as needed, the linear feedback shift register can output a different number of bits per cycle, including but not limited to 8, 32, and 64 bits. In this embodiment, the linear feedback shift register implements a 16 - bit polynomial as: X 16 +X 15 +X 13 +X 4+1. It is easy to understand that a linear feedback shift register can implement different polynomials as needed. In this embodiment, the address for seeding the linear feedback shift register includes the following bits: R[7], C[6], C[5], R[3], C[2], C[8], C[7], C[3], R[1], R[0], BG[1], BA[1], BA[0], BG[0], C[4], C[1]. "R" refers to row, "C" refers to column, "BG" refers to bank group, and "BA" refers to bank address. Additionally, in this embodiment, the write data for seeding the linear feedback shift register includes the following bits: constant 7, D

[18] , constant 6, D

[54] , constant 5, D[0], constant 4, D

[36] , constant 3, D[9], constant 2, D

[45] , constant 1, D

[63] , constant 0, D

[27] , where constants 0 - 7 can be 1'b0 or 1'b1. The fixed seed corresponding to the write data can be a string of binary numbers. In particular, the fixed seed corresponding to the write data is the same as the fixed seed corresponding to the read data.

[0035] According to an embodiment of the present invention, the descrambling component (6) includes a descrambling logic (16), a first XOR logic (14), and a second XOR logic (14). Preferably, the read data is divided into a first part and a second part. The input of the first XOR logic (14) includes the first part of the read data and the fixed seed corresponding to the first part of the read data to generate an output. The input of the descrambling logic (16) includes this output and the address associated with the read data to generate a pseudo-random output. Additionally, the input of the second XOR logic (14) includes the second part of the read data, the pseudo-random output, and the fixed seed corresponding to the first part of the read data to generate descrambled data. The descrambled data can then be decoded and / or returned to the user.

[0036] According to an embodiment of the present invention, the descrambling logic (16) includes a linear feedback shift register.

[0037] Figure 3A block diagram of a data scrambling and data descrambling implementation according to an embodiment of the present invention is shown. During implementation, the transmission data path and the reception data path are each 64 bits wide. Four copies of the LFSR-16 in each of the transmission data path and the reception data path can be used to generate a pseudo-random output for scrambling and descrambling data other than the data used as the data seed. The data used as the data seed is scrambled with a corresponding fixed seed so that the read data can be predictably scrambled. Before performing data descrambling in the reception data path, an exclusive OR operation is performed between the read data and the fixed seed. Additional exclusive OR logic (14) can be used to seed the LFSR-16 according to the address seed and the write data seed / the read data seed that has been exclusive ORed. Each copy of the LFSR-16 will obtain a different BL[1:0] value to generate a different pseudo-random output. For example, BL[1:0]=2'b00 is used for LFSR-16 copy 1, BL[1:0]=2'b01 is used for LFSR-16 copy 2, BL[1:0]=2'b10 is used for LFSR-16 copy 3, and BL[1:0]=2'b11 is used for LFSR-16 copy 4.

[0038] Figure 4 A block diagram of an error correction code encoding component (8) according to an embodiment of the present invention is shown. The error correction code encoding component (8) includes a plurality of encoding paths, and each encoding path includes two error correction code encoders. The two error correction code encoders are configured to transmit the error correction code to one of the adjacent encoding paths and distribute the error correction code on different data paths to achieve a wide data path implementation. Referring to Figure 4 , in data path 0, encoder 0 uses the data and the error correction code from the left adjacent data path to perform an encoding operation and outputs the encoded data and the error correction code. Encoder 1 performs encoding and transmits the error correction code to data path 1 on the right. In data path 1, encoder 0 uses the data and the error correction code from the left adjacent data path (data path 0) to perform an encoding operation and outputs the encoded data and the error correction code. Encoder 1 performs encoding and transmits the error correction code to the adjacent data path on the right (which can be data path 2) for subsequent encoding operations. The total number of data paths can be configured to support the DRAM interface width or protocol. For example, when each data path supports 8-bit data transmission, 9 data paths can be configured to support a 72-bit DRAM error correction code dual in-line memory module (DIMM) interface, as Figure 5 shown. In Figure 5Among them, each of bytes 0 - 8 represents a DRAM DQ byte. For example, byte 0 refers to DQ[7:0]. In addition, each of BL0 - 7 represents the DRAM burst length. For example, BL0 refers to burst length 0. Therefore, the BL0 row in the byte 0 column represents the burst length 0 data in DQ[7:0]. In addition, ECC0 refers to the error correction code information related to data 0.

[0039] Figure 6 A block diagram of an error correction code decoding component (10) according to an embodiment of the present invention is shown. The error correction code decoding component (10) includes a plurality of decoding paths, and each decoding path includes two error correction code decoders. The two error correction code decoders are configured to transmit the error correction code to each adjacent decoding path and distribute the error correction code on different data paths. Refer to Figure 6 , in data path 0, decoder 0 and decoder 1 use the data from the current path and the error correction codes from the adjacent data paths on the left and right to perform decoding operations in parallel. In data path 1, decoder 0 and decoder 1 use the data in the current path and the error correction codes in the adjacent data paths (data path 0 and data path 2) on the left and right to perform decoding operations. Similar to the error correction code encoding component (8), the total number of data paths of the error correction code decoding component (10) can be configured to support the DRAM interface width or protocol.

[0040] The present invention also relates to a method of operating a memory controller (100) to improve data integrity and provide data security. The method includes the following steps: transmitting the write data to a transmission data path; dividing the write data into a first part and a second part; generating a pseudo - random output based on the first part of the write data and the address associated with the write data through a scrambling logic (12); scrambling the second part of the write data in response to the pseudo - random output through an exclusive - OR logic (14), and scrambling the first part of the write data in response to a fixed seed corresponding to the first part of the write data to generate scrambled data; and transmitting the scrambled data to a memory device (2).

[0041] According to a first embodiment of the method of operating a memory controller (100), the method further includes the following step: encoding the scrambled data through an error correction code encoding component (8) before transmitting the scrambled data to the memory device (2).

[0042] According to a first embodiment of a method of operating a memory controller (100), the method further comprises the steps of: receiving read data from a memory device (2) in a receive data path; decoding the read data by an error correction code decoding component (10); dividing the read data into a first part and a second part; generating an output by a first exclusive-OR logic (14) based on the first part of the read data and a fixed seed corresponding to the first part of the read data; generating a pseudo-random output by a descrambling logic (16) according to the output and an address associated with the read data; and generating descrambled data by a second exclusive-OR logic (14) by descrambling the second part of the read data in response to the pseudo-random output and descrambling the first part of the received data in response to the fixed seed corresponding to the first part of the read data.

[0043] According to a second embodiment of a method of operating a memory controller (100), the write data may be encoded by an error correction code encoding component (8) before dividing the write data into a first part and a second part.

[0044] According to a second embodiment of a method of operating a memory controller (100), the method further comprises the steps of: receiving read data from a memory device (2) in a receive data path; dividing the read data into a first part and a second part; generating an output by a first exclusive-OR logic (14) based on the first part of the read data and a fixed seed corresponding to the first part of the read data; generating a pseudo-random output by a descrambling logic (16) based on the output and an address associated with the read data; generating descrambled data by a second exclusive-OR logic (14) by descrambling the second part of the read data in response to the pseudo-random output and descrambling the first part of the read data in response to the fixed seed corresponding to the first part of the read data; and decoding the descrambled data by an error correction code decoding component (10).

[0045] The above memory controller (100) overcomes the problems and disadvantages of existing solutions and also provides numerous advantages over existing solutions. For example, the data scrambling / descrambling implementation in the present invention utilizes multiple different elements such as an address, data, and a fixed seed corresponding to the data to improve data integrity and provide data security. Additionally, by configuring the number of data paths of the error correction code encoding component (8) and the error correction code decoding component (10), the error correction code implementation in the present invention can support any DRAM interface width or protocol. Moreover, compared with existing solutions that only employ a central encoder / decoder which may cause routing congestion, the modular error correction code implementation in the present invention can reduce the routing resources across a wide interface, simplifying the timing convergence across different data bytes with less power due to reducing the round-trip buffering for each data path.

[0046] To those skilled in the art, various modifications to these embodiments will be apparent from the specification and the drawings. The principles associated with the various embodiments described herein can be applied to other embodiments. Therefore, the description of the invention is not intended to be limited to the embodiments shown in the appended Figure 1 drawings, but rather to provide the broadest scope consistent with the principles, novel features, and inventive characteristics disclosed or suggested herein. Accordingly, all alternatives, modifications, and variations made in accordance with the present invention fall within the scope of the present invention and the appended claims.

[0047] In the appended claims of the present invention and the foregoing description, unless the context requires otherwise due to express language or necessary implication, the word "comprise" or variations thereof such as "comprises" or "comprising" are used in an inclusive sense. That is, in the various embodiments of the present invention, the presence of the stated features is specified but the presence or addition of other features is not excluded.

Claims

1. A memory controller (100) for improving data integrity and providing data security, comprising: A transmission data path for transmitting write data to a memory device (2), the transmission data path including a scrambling component (4); Wherein, the scrambling component (4) includes a scrambling logic (12) and an exclusive OR logic (14); Characterized in that: The write data is divided into a first part and a second part; Wherein, the input of the scrambling logic (12) includes the first part of the write data and an address associated with the write data to generate a pseudo-random output; The input of the exclusive OR logic (14) includes the second part of the write data, the pseudo-random output, and a fixed seed corresponding to the first part of the write data to generate scrambled data.

2. The memory controller (100) according to claim 1, wherein The scrambling logic (12) includes a linear feedback shift register.

3. The memory controller (100) according to claim 1, characterized in that, The transmission data path further includes an error correction code encoding component (8).

4. The memory controller (100) according to claim 3, characterized in that, The error correction code encoding component (8) includes a plurality of encoding paths, and each encoding path includes two error correction code encoders; the error correction code encoders are configured to transmit error correction codes to one of the adjacent encoding paths and distribute the error correction codes on different data paths.

5. The memory controller (100) according to claim 1, further comprising: A receiving data path for receiving read data from the memory device (2), the receiving data path including a descrambling component (6); Wherein, the descrambling component (6) includes a descrambling logic (16), a first exclusive OR logic (14), and a second exclusive OR logic (14); Characterized in that: The read data is divided into a first part and a second part; Wherein, the input of the first exclusive OR logic (14) includes the first part of the read data and a fixed seed corresponding to the first part of the read data to generate an output; The input of the descrambling logic (16) includes the output and an address associated with the read data to generate a pseudo-random output; The input of the second exclusive OR logic (14) includes the second part of the read data, the pseudo-random output, and a fixed seed corresponding to the first part of the read data to generate descrambled data.

6. The memory controller (100) according to claim 5, wherein The descrambling logic (16) includes a linear feedback shift register.

7. The memory controller (100) according to claim 5, characterized in that, The receiving data path further includes an error correction code decoding component (10).

8. The memory controller (100) according to claim 7, wherein, The error correction code decoding component (10) includes a plurality of decoding paths, and each decoding path includes two error correction code decoders; the error correction code decoders are configured to transmit error correction codes into each adjacent decoding path.

9. A method for operating a memory controller (100) to improve data integrity and provide data security, characterized in that, Including the following steps: A transmission data path for transmitting write data to a memory device (2); Dividing the write data into a first part and a second part; Generating a pseudo-random output based on the first part of the write data and an address associated with the write data through the scrambling logic (12); Scramble the second part of the write data in response to a pseudo-random output and scramble the first part of the write data in response to a fixed seed corresponding to the first part of the write data through an exclusive-OR logic (14) to generate scrambled data; And Transmit the scrambled data to a memory device (2).

10. The method according to claim 9, wherein The method further comprises the steps of: Before transmitting the scrambled data to the memory device (2), encode the scrambled data through an error correction code encoding component (8).

11. The method according to claim 10, characterized in that, The method further comprises the steps of: Receive read data from the memory device (2) in a receive data path; Decode the read data through an error correction code decoding component (10); Divide the read data into a first part and a second part; Generate an output through a first exclusive-OR logic (14) based on the first part of the read data and a fixed seed corresponding to the first part of the read data; Generate a pseudo-random output through a descrambling logic (16) based on the output and an address associated with the read data; and Descramble the second part of the read data in response to the pseudo-random output and descramble the first part of the read data in response to a fixed seed corresponding to the first part of the read data through a second exclusive-OR logic (14) to generate descrambled data.

12. The method according to claim 9, characterized in that, The method further comprises the steps of: Before dividing the write data into a first part and a second part, encode the write data through an error correction code encoding component (8).

13. The method according to claim 12, wherein The method further comprises the steps of: Receive read data from the memory device (2) in a receive data path; Divide the read data into a first part and a second part; Generate an output through a first exclusive-OR logic (14) based on the first part of the read data and a fixed seed corresponding to the first part of the read data; Generate a pseudo-random output through a descrambling logic (16) based on the output and an address associated with the read data; Descramble the second part of the read data in response to the pseudo-random output and descramble the first part of the read data in response to a fixed seed corresponding to the first part of the read data through a second exclusive-OR logic (14) to generate descrambled data; and Decode the descrambled data through an error correction code decoding component (10).

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