A method of manufacturing a semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method, relates to the technical field of semiconductors, and aims to improve the conductive performance of a ring gate transistor in the case that the threshold voltage of different ring gate transistors in a semiconductor device is regulated by adopting a dipole threshold regulation technology. The semiconductor device manufacturing method comprises the following steps: providing a substrate. The substrate has at least two types of regions. Each type of region is formed with a channel included in a corresponding ring gate transistor. A deposition process and a selective etching process are adopted to form a dipole layer with a corresponding thickness and a corresponding material on the outer periphery of the channel located on at least some of the regions, so that different types of regions correspond to different threshold regulation parameters. A gate dielectric layer and a gate electrode included in a corresponding ring gate transistor are sequentially formed on the dipole layer or the channel located on each type of region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a manufacturing method of semiconductor device. BACKGROUND

[0002] In the process of actually manufacturing the semiconductor device, the dipole threshold value regulation technology can be used to regulate the threshold voltage of different ring gate transistors in the semiconductor device without reducing the space for forming the gate, so as to not affect the filling of the subsequent gate and improve the yield of the semiconductor device.

[0003] However, the compatibility of the dipole threshold value regulation technology used in the existing manufacturing method of semiconductor device is poor, which leads to poor conductive performance of the ring gate transistor formed. SUMMARY

[0004] The present application aims to provide a manufacturing method of semiconductor device, which is used to improve the conductive performance of the ring gate transistor when the dipole threshold value regulation technology is used to regulate the threshold voltage of different ring gate transistors in the semiconductor device.

[0005] In order to achieve the above-mentioned purpose, the present application provides a manufacturing method of semiconductor device, which comprises the following steps:

[0006] A substrate is provided. The substrate has at least two types of regions. Each type of region is formed with a channel included in a corresponding ring gate transistor.

[0007] A deposition process and a selective etching process are used to form a dipole layer with a corresponding thickness and a corresponding material on the outer periphery of the channel located on at least a part of the regions, so that different types of regions correspond to different threshold regulation parameters.

[0008] A gate dielectric layer and a gate included in a corresponding ring gate transistor are sequentially formed on the dipole layer or the channel located on each type of region.

[0009] Compared with the prior art, the semiconductor device manufacturing method provided by the application has the following advantages: the substrate has a channel formed on each type of region; a dipole layer with a corresponding thickness and a corresponding material is formed on the outer periphery of the channel in at least a part of the type of region by using a deposition and selective etching process; the different types of regions correspond to different threshold value control parameters after the dipole layer is formed, so that the ring gate transistors in the different types of regions have different threshold voltages; and the dipole layer is directly formed on the outer periphery of the corresponding channel before the gate dielectric layer and the gate electrode of the ring gate transistor are formed. At this time, because the distance between the dipole layer and the corresponding channel is relatively short, the key elements in the dipole layer can be moved to the interface between the channel and the dipole layer without high-temperature annealing, so that the problem of poor compatibility caused by the change in the carrier transmission performance in the channel with a material containing germanium due to the high-temperature annealing process for the advancement of the key elements can be solved, and the conductivity of the ring gate transistor is improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0011] Figure 1 A flow chart of the semiconductor device manufacturing method provided by the embodiment of the application is shown in the figure;

[0012] Figure 2 A structure sectional view of the substrate in the embodiment of the application is shown in the figure;

[0013] Figure 3 A structure sectional view of the substrate after the interface layer is formed on the outer periphery of the channel in the embodiment of the application is shown in the figure;

[0014] Figure 4 A first structure sectional view of the substrate after the dipole material layer and the cover layer are formed in the embodiment of the application is shown in the figure;

[0015] Figure 5 A first structure sectional view of the substrate after the mask layer is formed in the embodiment of the application is shown in the figure;

[0016] Figure 6 A first structure sectional view of the substrate after the mask layer is formed in the embodiment of the application is shown in the figure;

[0017] Figure 7 A structure sectional view of the substrate after the mask layer and the cover layer are removed in the embodiment of the application is shown in the figure;

[0018] Figure 8A second structure sectional view after forming a dipole material layer and a cover layer in an embodiment of the present application;

[0019] Figure 9 A second structure sectional view after forming a mask layer in an embodiment of the present application;

[0020] Figure 10 A second structure sectional view after removing the dipole material layer and the cover layer on the regions to be removed under the mask function of the mask layer in an embodiment of the present application;

[0021] Figure 11 A structure sectional view after forming a dipole layer with a corresponding thickness and a corresponding material on the outer periphery of the channel in at least a partial region in an embodiment of the present application;

[0022] Figure 12 A structure sectional view after forming a corresponding ring gate transistor on each region in an embodiment of the present application.

[0023] The reference signs: 11 is a substrate, 111 is a first region, 112 is a second region, 113 is a third region, 12 is a channel, 13 is an interface layer, 14 is a dipole layer, 141 is a dipole material layer, 15 is a cover layer, 16 is a mask layer, 17 is a gate dielectric layer, and 18 is a gate. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, the description of well-known structures and techniques has been omitted to avoid obscuring the concept of the present disclosure.

[0025] In the drawings, various structure diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale in which certain details are exaggerated for clarity of presentation and may omit certain details. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the drawings are merely exemplary, and in actuality, there can be deviations due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0026] In the context of the present disclosure, when one layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element. In addition, if one layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0027] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited. The meaning of "several" is one or more, unless otherwise explicitly specified and limited.

[0028] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0029] In the actual manufacturing process of semiconductor devices, the method of "deposition-etching-deposition" is usually used to form gate stack structures with different thicknesses and / or different materials on the channels included in different transistors in the semiconductor device, so that different transistors correspond to different threshold control parameters, and the threshold voltage of different transistors in the semiconductor device is controlled. With the development of semiconductor technology, integrated circuits with higher performance and stronger functions require greater element density, and the size, size and space between various components, elements or between various elements themselves also need to be further reduced. For ring gate transistors, the space between the adjacent two nanowires or sheets in the channel included therein and between the nanowire or sheet and the substrate is small. It is difficult to form gate stack structures with different thicknesses and / or different materials in a smaller space, resulting in reduced yield and performance of semiconductor devices.

[0030] To solve the above technical problems, the skilled in the art develops a kind of to adopt the space-occupying dipole threshold regulation technology to realize the regulation of the threshold voltage of different transistors in semiconductor device.For example, in the case of the transistor being ring-gate transistor, after forming the channel included in corresponding ring-gate transistor on different types of regions, gate dielectric layer is formed on the outer periphery of the channel located on each type of region.Then form a dipole layer of corresponding thickness and corresponding material on the gate dielectric layer, and push the key elements (for example: lanthanum element in lanthanum oxide dipole layer) in the dipole layer to the interface by annealing treatment, so that different types of regions correspond to different threshold regulation parameters.Finally, remove the remaining dipole layer, realize the threshold voltage regulation of different ring-gate transistors, and do not reduce the formation space of gate, so as to not affect the filling of subsequent gate.

[0031] However, there are certain compatibility problems in the process of pushing the key elements in the dipole layer to the interface by the above annealing treatment.For example: in the case that the material of the channel included in the ring-gate transistor is germanium-silicon or germanium, the above annealing treatment will cause the transmission performance of carriers in the channel to change, and then the conductive performance of the ring-gate transistor will be poor.

[0032] To solve the above technical problems, the present application provides a semiconductor device manufacturing method.In the semiconductor device manufacturing method provided by the present application, before forming the gate dielectric layer and the gate of the ring-gate transistor, a dipole layer of corresponding thickness and corresponding material is directly formed on the outer periphery of the channel located on at least some type of region by deposition and selective etching process, to solve the poor compatibility problem that the transmission performance of carriers in the channel containing germanium changes due to the key element pushing by high-temperature annealing treatment in the prior art, and improve the conductive performance of the ring-gate transistor.

[0033] As shown in Figure 1 The present application provides a semiconductor device manufacturing method.The following will be described according to the sectional view of the operation shown in Figures 2 to 12 The manufacturing process will be described.Specifically, the semiconductor device manufacturing method includes:

[0034] As shown in Figure 2 A substrate 11 is provided.The substrate 11 has at least two types of regions.Each type of region is formed with a corresponding channel 12 included in the ring-gate transistor.

[0035] Specifically, the substrate can be a semiconductor substrate on which no structure is formed, such as a silicon substrate, a germanium-silicon substrate, a germanium substrate, etc., or a semiconductor substrate on which some structures are formed. Specifically, the material and structure of the substrate can be set according to actual needs. For example, in the case where the semiconductor device includes at least two layers of transistors, and the ring gate transistors subsequently formed on each type of region are ring gate transistors located at the second layer or above of the semiconductor device, the substrate can include a semiconductor substrate, at least one layer of transistors formed on the semiconductor substrate, and an interlayer dielectric layer separating adjacent layers of transistors, etc.

[0036] For the number of types of regions that the substrate has, because corresponding ring gate transistors will be subsequently formed on different types of regions that the substrate has, and the ring gate transistors located on different types of regions correspond to different threshold control parameters, the number of types of regions that the substrate has can be set according to the threshold control requirements of each ring gate transistor included in the semiconductor device in the actual application scenario. For example, in the case where the semiconductor device is a CMOS device, and one or more NMOS transistors (here and below, the device structure of the NMOS transistor is a ring gate transistor) included in the CMOS device correspond to a first threshold voltage, and one or more PMOS transistors (here and below, the device structure of the PMOS transistor is a ring gate transistor) included in the CMOS device correspond to a second threshold voltage, the substrate has two types of regions (i.e., a first type of region and a second type of region). Among them, the first type of region corresponds to the formation of the one or more NMOS transistors. The second type of region corresponds to the formation of the one or more PMOS transistors.

[0037] In addition, how many ring gate transistors included in each type of region that the substrate has are formed, and how the channels included in each ring gate transistor are distributed, can be set with reference to the number of ring gate transistors corresponding to the same threshold control parameter, and the distribution relationship of each ring gate transistor, which is not specifically limited here. For example, in the case where the semiconductor device includes two first ring gate transistors corresponding to a first threshold control parameter, four second ring gate transistors corresponding to a second threshold control parameter, and six third ring gate transistors corresponding to a third threshold control parameter, the substrate has one first type of region, one second type of region, and one third type of region. And, two first ring gate transistors included in the first type of region that the substrate has are formed. Four second ring gate transistors included in the second type of region that the substrate has are formed. Six third ring gate transistors included in the third type of region that the substrate has are formed.

[0038] For the channels included in the above-mentioned ring gate transistors, as Figure 2As shown, each of the ring gate transistors includes a channel 12 having at least one layer of nanowires or sheets formed above the substrate 11. Among them, the channels of the ring gate transistors located on different types of regions can have the same or different number of layers and spacing of nanowires or sheets. In addition, the material of the above-mentioned channels is semiconductor material. For example, the material of the channel can be Si 1-x Ge x . Among them, 0≤x≤1. For example: the material of the channel is Si 0.2 Ge 0.8 , Si 0.75 Ge 0.25 or Ge, etc.

[0039] In some cases, a shallow trench isolation, a side wall, a source region, a drain region and a dielectric layer can also be formed on each type of region. Specifically, the above-mentioned shallow trench isolation is used to define the active region of the substrate. The material contained in the shallow trench isolation can be SiN, Si3N4, SiO2 or SiCO, etc. The above-mentioned source region and drain region are respectively formed on both sides of the channel along the length direction thereof. The material of the source region and the drain region can be semiconductor material such as silicon, germanium silicon or germanium, etc. The above-mentioned dielectric layer is covered on the substrate, and the top height of the dielectric layer is equal to the maximum top height of the side wall. The side wall is formed between the dielectric layer and the gate dielectric layer and the gate of the ring gate transistor. The material of the above-mentioned side wall and dielectric layer can be insulating material such as silicon dioxide and silicon nitride, etc.

[0040] In practical applications, the fabrication process for forming the channel of a gate-around transistor on a substrate varies depending on factors such as the number and spacing of nanowires or sheets in different types of regions. The following is a simplified description of the fabrication process for forming the channel of a gate-around transistor on each type of region of the substrate, using the example of nanowires or sheets in different types of regions having the same number of nanowires or sheets, and nanowires or sheets in the same layer having the same spacing with adjacent structures: First, a stack of layers equal to the number of nanowires or sheets is formed on the substrate along the thickness direction. Each stack includes a sacrificial layer and a channel layer located on the sacrificial layer. Photolithography and etching processes are used to etch the stack and the substrate to form a first fin structure in each type of region. Next, a shallow trench isolation is formed on the portion of the substrate exposed outside the first fin structure. The top height of this shallow trench isolation is less than or equal to the bottom height of the bottommost sacrificial layer. The portion of the first fin structure exposed outside the shallow trench isolation is the second fin structure. Each second fin structure in each type of region includes a source region forming region, a drain region forming region, and a transition region located between the source region forming region and the drain region forming region. Then, a sacrificial gate and sidewalls are formed covering the periphery of the transition region of each second fin structure. The sidewalls are formed at least on both sides of the sacrificial gate along its width. The portions of each second fin structure located in the source region forming region and the drain region forming region are processed to form the source region and drain region included in the corresponding ring-gate transistor in each type of region. Next, a dielectric layer is formed covering the substrate, the top height of which is equal to the top height of the sacrificial gate. The sacrificial gate and the portion of the sacrificial layer located within the transition region are then removed, such that the portion of the channel layer located within the transition region forms the channel included in the ring-gate transistor.

[0041] It should be noted that the channel of the gate-ring transistor can be formed in various ways. How the above structure is formed is not the main feature of this invention; therefore, it is only briefly described in this specification to enable those skilled in the art to easily implement the invention. Those skilled in the art can certainly conceive of other ways to fabricate the above structure.

[0042] In one example, such as Figure 3 As shown, after providing a substrate 11 and before performing subsequent operations, the method for manufacturing the semiconductor device may further include the step of forming an interface layer 13 on the outer periphery of the channel 12 located in each type of region to reduce the surface roughness of the channel 12, improve the interface state of the channel 12, and further improve the conductivity of the gate-around transistor. For example, the interface layer 13 can be formed using processes such as chemical vapor deposition. The thickness of the interface layer 13 can be set according to actual needs and is not specifically limited here. For example, the thickness of the interface layer 13 can be greater than 0 and less than or equal to 0.7 nm.

[0043] like Figures 3 to 11As shown, the deposition process and the selective etching process are used to form the dipole layer 14 with corresponding thickness and corresponding material on the outer periphery of the channel 12 located on at least a part of the region, so that different regions correspond to different threshold control parameters.

[0044] Specifically, the corresponding dipole layer can be formed on the outer periphery of the channel located on each region. The corresponding dipole layer can also be formed only on the outer periphery of the channel located on a part of the region. Specifically, the number of regions corresponding to the formation of the corresponding dipole layer can be set according to the threshold control parameters corresponding to the ring gate transistor formed on the region subsequently, and the actual demand, which is not limited here. For example: Figure 11 and Figure 12 As shown, the semiconductor device includes a plurality of NMOS transistors, and the plurality of NMOS transistors correspond to three different threshold control parameters. At the same time, only the ring gate transistor corresponding to any two threshold control parameters of the three different threshold control parameters needs to form a corresponding dipole layer 14 on the outer periphery of the channel 12 included therein. In this case, the substrate 11 has three regions, and the corresponding dipole layer 14 can be formed only on the outer periphery of the channel 12 located on the first region 111 and the second region 112. The outer periphery of the channel 12 located on the third region 113 can not form a dipole layer 14.

[0045] In addition, the material and thickness of the dipole layer located on different regions can be set according to the actual demand, as long as it can be applied to the manufacturing method of the semiconductor device provided by the embodiment of the application. Among them, the material of the dipole layer located on different regions can be the same or different. For example: the semiconductor device includes a plurality of NMOS transistors, and the plurality of NMOS transistors correspond to different threshold control parameters. In this case, the material of the dipole layer formed on the outer periphery of the channel included by the NMOS transistor located on different regions can be the same or different. In addition, the thickness of the dipole layer located on different regions can be the same or different. For example: the semiconductor device is a CMOS device, and the NMOS transistor included by the CMOS device has the same threshold control parameter and is formed on the first region. The PMOS transistor included by the CMOS device has the same threshold control parameter and is formed on the second region. In this case, the thickness of the dipole layer formed on the outer periphery of the channel included by the NMOS transistor and the PMOS transistor located on different regions can be the same or different.

[0046] For the specific material of the dipole layer, the dipole layer can be any material that can achieve the purpose of threshold control. For example, the material of the dipole layer can be La2O3, Al2O3 or MgO, etc. Specifically, the material of the dipole layer corresponding to the ring gate transistor with different conductive types can be set according to actual needs. For example, the ring gate transistor located on at least one type of region is an NMOS transistor, and the material of the dipole layer corresponding to the NMOS transistor can be La2O3. For example, the ring gate transistor located on at least one type of region is a PMOS transistor, and the material of the dipole layer corresponding to the PMOS transistor can be Al2O3.

[0047] It should be noted that the embodiment of the present application realizes the control of the threshold voltage of different ring gate transistors through the dipole threshold control technology. Specifically, the dipole threshold control technology forms a dipole layer at the interface between the channel and the gate dielectric layer included in the ring gate transistor. When the ring gate transistor is in a working state, the dipole layer generates an electric field in the same direction as the motion direction of the carrier, thereby affecting the threshold voltage of the ring gate transistor. It can be envisaged that in the case of different materials and / or thicknesses of different dipole layers, the type and / or content of the key elements in the different dipole layers are different, thereby making the field strength of the electric field generated by the dipole layer with different materials and / or thicknesses when the ring gate transistor is working different, and further making the ring gate transistor with different materials and / or thicknesses of the dipole layer correspond to different threshold control parameters. Based on this, in the case that the conductive types of the ring gate transistors included in the semiconductor device are the same, at least one of the material and the thickness of the dipole layer located on different types of regions is different. For example, in the case that the ring gate transistors located on at least two types of regions are NMOS transistors, the material and / or thickness of the dipole layer corresponding to the NMOS transistors located on different types of regions are different. Specifically, whether the dipole layer corresponding to the NMOS transistors located on different types of regions is different in material, thickness, or both can be set according to actual needs. For example, in the case that the ring gate transistors located on at least two types of regions are PMOS transistors, the material and / or thickness of the dipole layer corresponding to the PMOS transistors located on different types of regions are different. Similarly, whether the dipole layer corresponding to the PMOS transistors located on different types of regions is different in material, thickness, or both can be set according to actual needs. Preferably, by setting the material of the dipole layer corresponding to the NMOS transistors or PMOS transistors located on different types of regions to be the same and the thickness to be different, different threshold control parameters corresponding to different NMOS transistors or PMOS transistors can be realized. At this time, the same deposition material can be used to realize the manufacturing of different dipole layers in the same deposition equipment, so as to simplify the manufacturing process of the semiconductor device.

[0048] In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figures 3 to 11 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figure 3 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figure 4 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figure 5 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figure 6 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figure 7 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figures 8 to 11 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region.

[0049] In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figures 4 to 11 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figures 4 to 11 In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region.

[0050] In one example, as shown in FIG. 1, the above-mentioned forming the dipole layer 14 with a corresponding thickness and a corresponding material on the outer periphery of the channel 12 located on at least a part of the class region can include the following steps: as shown in FIG. 2, forming a dipole material layer 141 on the outer periphery of the channel 12 located on each class region. Figure 5As shown, the base 11 has a first type of region 111, a second type of region 112, and a third type of region 113. The target region can be the first type of region 111 present in the base 11. In this case, the regions to be removed are the second type of region 112 and the third type of region 113. It is conceivable that the target region and the regions to be removed correspond to different regions depending on the number of executions. For example: Figure 5 As shown, the base 11 has a first type of region 111, a second type of region 112, and a third type of region 113. Where the execution count is equal to 1, the target region can be the first type of region 111 of the base 11. In this case, the regions to be removed are the second type of region 112 and the third type of region 113. Figure 9 As shown, when the number of executions is equal to 2, the target region is the first type region 111 and the second type region 112 of the base 11. At this time, the region to be removed is the third type region 113 of the base 11.

[0051] The material of the mask layer can be set according to actual needs, and no specific limitation is made here. For example, the mask layer can be a spin-coated carbon layer or a bottom anti-reflective layer, etc.

[0052] In actual application process, atomic layer deposition and other processes can be used to form the dipole material layer on the outer periphery of the channel located in each type of region. Then, a mask layer covering the target type of region can be formed by using spin coating and other processes. Under the mask effect of the mask layer, the part of the dipole material layer located in the type of region to be removed can be selectively removed by using dry etching or wet etching and other processes. Specifically, the process and etchant used for selectively removing the dipole material layer can be determined according to the material of the dipole material layer, which is not limited here. For example, in the case where the material of the dipole material layer is La2O3, HPM solution can be used to selectively remove the part of the dipole material layer located in the type of region to be removed. The mass ratio of HCL, H2O2 and H2O in the HPM solution can be set according to actual needs. For example, the mass ratio of the above-mentioned HCL, H2O2 and H2O can be 1:1:5. In another example, in the case where the material of the dipole material layer is Al2O3, APM solution can be used to selectively remove the part of the dipole material layer located in the type of region to be removed. The mass ratio of NH4OH, H2O2 and H2O in the APM solution can be set according to actual needs. For example, the mass ratio of the above-mentioned NH4OH, H2O2 and H2O can be 1:1:5. Finally, the mask layer can be removed by using dry etching or wet etching process. Specifically, the etching process and etchant used for removing the mask layer can be determined according to the material of the mask layer. For example, in the case where the material of the mask layer is spin-on carbon, the mask layer can be removed by using dry etching process and O2 plasma. One cycle is realized through the above process. Specifically, how many times the above operation needs to be performed can be set according to the number of types of regions for which the dipole layer needs to be formed and actual application scenarios.

[0053] It should be understood that in each operation described above, the dipole material layer is only formed on the channel or the interface layer. In actual application process, a cover layer can also be formed on the dipole material layer. The cover layer separates the dipole material layer from the external environment and the mask layer, preventing the dipole material layer from reacting with H2O in the external environment or the mask layer during operation, improving the quality of the manufactured dipole layer, and thus improving the yield of the obtained ring gate transistor. For example, in the case where the ring gate transistor located in at least one type of region is an NMOS transistor, and the material of the dipole layer corresponding to the NMOS transistor can be La2O3, a cover layer can be formed on the dipole material layer with the material of La2O3. Specifically, the material of the cover layer can be set according to actual application scenarios. For example, in the case where the material of the dipole material layer is La2O3, the material of the cover layer can be Al2O3.

[0054] In one example, in the case where a cover layer needs to be formed on the dipole material layer, as shown in FIG. 6, the cover layer can be formed on the dipole material layer by using atomic layer deposition and other processes.Figure 4 and Figure 8 As shown in FIG. 1 1, the step of forming the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially forming the dipole layer 14 and the cover layer 15 on the outer periphery of the channel 12 in each type of region. As shown in FIG. 12, the step of selectively removing the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially selectively removing the cover layer on the outer periphery of the channel 12 in each type of region and the dipole layer 14 on the outer periphery of the channel 12 in each type of region. Figure 6 and Figure 10 As shown in FIG. 1 1, the step of forming the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially forming the dipole layer 14 and the cover layer 15 on the outer periphery of the channel 12 in each type of region. As shown in FIG. 12, the step of selectively removing the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially selectively removing the cover layer on the outer periphery of the channel 12 in each type of region and the dipole layer 14 on the outer periphery of the channel 12 in each type of region. Figure 7 and Figure 11 As shown in FIG. 1 1, the step of forming the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially forming the dipole layer 14 and the cover layer 15 on the outer periphery of the channel 12 in each type of region. As shown in FIG. 12, the step of selectively removing the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially selectively removing the cover layer on the outer periphery of the channel 12 in each type of region and the dipole layer 14 on the outer periphery of the channel 12 in each type of region.

[0055] As shown in FIG. 1 1, the step of forming the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially forming the dipole layer 14 and the cover layer 15 on the outer periphery of the channel 12 in each type of region. As shown in FIG. 12, the step of selectively removing the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially selectively removing the cover layer on the outer periphery of the channel 12 in each type of region and the dipole layer 14 on the outer periphery of the channel 12 in each type of region. Figure 12 As shown in FIG. 1 1, the step of forming the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially forming the dipole layer 14 and the cover layer 15 on the outer periphery of the channel 12 in each type of region. As shown in FIG. 12, the step of selectively removing the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially selectively removing the cover layer on the outer periphery of the channel 12 in each type of region and the dipole layer 14 on the outer periphery of the channel 12 in each type of region.

[0056] As shown in FIG. 1 1, the step of forming the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially forming the dipole layer 14 and the cover layer 15 on the outer periphery of the channel 12 in each type of region. As shown in FIG. 12, the step of selectively removing the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially selectively removing the cover layer on the outer periphery of the channel 12 in each type of region and the dipole layer 14 on the outer periphery of the channel 12 in each type of region. Figure 11 and Figure 12 As shown in FIG. 1 1, the step of forming the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially forming the dipole layer 14 and the cover layer 15 on the outer periphery of the channel 12 in each type of region. As shown in FIG. 12, the step of selectively removing the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially selectively removing the cover layer on the outer periphery of the channel 12 in each type of region and the dipole layer 14 on the outer periphery of the channel 12 in each type of region.

[0057] As shown in FIG. 1 1, the step of forming the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially forming the dipole layer 14 and the cover layer 15 on the outer periphery of the channel 12 in each type of region. As shown in FIG. 12, the step of selectively removing the dipole layer 14 on the outer periphery of the channel 12 in each type of region corresponds to the step of sequentially selectively removing the cover layer on the outer periphery of the channel 12 in each type of region and the dipole layer 14 on the outer periphery of the channel 12 in each type of region.

[0058] From the above, the manufacturing method of the semiconductor device provided by the embodiment of the present application is known that the base has each type of region on which a corresponding channel of a ring gate transistor is formed. And, the deposition and selective etching process is used to form a dipole layer of corresponding thickness and corresponding material on the outer periphery of the channel located on at least a part of the type of region. Because the different type of region corresponds to different threshold value control parameters after the formation of the dipole layer, the ring gate transistor located on the different type of region has different threshold voltage. On this basis, the dipole layer is directly formed on the corresponding channel outer periphery before the formation of the gate dielectric layer and the gate of the ring gate transistor. At this time, because the distance between the dipole layer and the corresponding channel is close, the key element in the dipole layer can be moved to the interface between the channel and the dipole layer without high temperature annealing treatment, so as to solve the problem of poor compatibility in the prior art that the transmission performance of the carrier in the channel with germanium material changes by the high temperature annealing treatment to realize the key element promotion, and improve the conductive performance of the ring gate transistor.

[0059] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0060] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; The substrate has at least two types of regions; each type of region has a channel formed on it, which is included in the corresponding gate ring transistor. A dipole layer of appropriate thickness and material is formed on the periphery of the channel located on at least some of the regions described above using deposition and selective etching processes, so that different types of regions correspond to different threshold control parameters. The gate dielectric layer and gate of the corresponding ring gate transistor are sequentially formed on the dipole layer or the channel located in each type of region; in each type of region, the gate and the gate dielectric layer are in direct contact, and in at least some types of regions, the dipole layer is present between the channel and the gate dielectric layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The method employs deposition and selective etching processes to form a dipole layer of appropriate thickness and material on the outer periphery of the trench located in at least a portion of the described region, including: At least one dipole material layer is formed on the outer periphery of the channel located in each of the aforementioned regions; the thickness of the dipole material layer is greater than zero and less than or equal to the thickness of the dipole layer to be formed in the target region; the material of the dipole material layer is the same as the material of the dipole layer to be formed in the target region. A mask layer is formed on the substrate to expose the region to be removed; the region to be removed is the area on the substrate other than the target region. Under the masking effect of the mask layer, at least the portion of the dipole material layer located on the region to be removed is selectively removed; Remove the mask layer; Repeat the operation until the dipole layer of appropriate thickness and material is formed on the outer periphery of the channel located on at least a portion of the region described.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The mask layer is a spin-coated carbon layer or a bottom anti-reflective layer.

4. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The provision that at least a dipole material layer is formed on the periphery of the channel located in each type of region means that the dipole material layer and the capping layer are formed sequentially on the periphery of the channel located in each type of region. The step of selectively removing at least the portion of the dipole material layer located on the region to be removed under the masking effect of the mask layer is as follows: under the masking effect of the mask layer, the portion of the cover layer located on the region to be removed and the portion of the dipole material layer located on the region to be removed are selectively removed sequentially. After removing the mask layer, the above operation is repeated until a dipole layer of corresponding thickness and material is formed on the periphery of the channel located on at least a portion of the region. The method of manufacturing the semiconductor device further includes removing the remaining portion of the cover layer.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The gate-ring transistor located on at least one of the aforementioned regions is an NMOS transistor, and the dipole layer corresponding to the NMOS transistor is made of La2O3; and / or, When the dipole material layer is made of La2O3, HPM solution is used to selectively remove the portion of the dipole material layer located in the region to be removed.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, When the ring gate transistor located on at least two types of the regions is an NMOS transistor, the dipole layer corresponding to the NMOS transistor located on different types of the regions has different materials and / or thicknesses.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The gate-ring transistor located on at least one of the aforementioned regions is a PMOS transistor, and the dipole layer corresponding to the PMOS transistor is made of Al2O3; and / or, When the gate ring transistor located on at least two types of the regions is a PMOS transistor, the dipole layer corresponding to the PMOS transistor located on different types of the regions has different materials and / or thicknesses.

8. The method for manufacturing a semiconductor device according to claim 2, characterized in that, When the dipole material layer is made of Al2O3, an APM solution is used to selectively remove the portion of the dipole material layer located in the region to be removed.

9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that, After providing a substrate, and before forming a dipole layer of appropriate thickness and material on the periphery of the channel located on at least a portion of the aforementioned region using deposition and selective etching processes, the method for manufacturing the semiconductor device further includes: An interface layer is formed on the periphery of the channel located on each type of region.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that, The channel is made of Si. 1-x Ge x Where 0 ≤ x ≤ 1.

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