Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure manufacturing method provided by the present invention, a first oxide layer and a silicon nitride layer are first formed in the memory cell area and the logic circuit area; then, the logic circuit area is protected, and a first etching process is performed on the memory cell area to remove the silicon nitride layer on the top of the gate structure and the substrate in the memory cell area; then, a second oxide layer is deposited in the memory cell area and the logic circuit area, and a second etching process is performed on the memory cell area and the logic circuit area to form sidewalls of an ONO structure on the sidewalls of the gate structure in the memory cell area and the logic circuit area. Utilizing the manufacturing method provided by the present invention, only one etching process is performed on the logic circuit area, effectively preventing over-etching, protecting the sidewall structure from damage, and ensuring that subsequent processes are not affected, thereby helping to improve device yield and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] The existing method for forming a sidewall structure in a semiconductor device includes: step 1, providing a substrate, the substrate 100 including a memory cell area A and a logic circuit area B, and a plurality of gate structures (such as Figure 1A Step 2: depositing a spacer material layer on the substrate and the gate structure, as shown Figure 1B As shown, the sidewall material layer includes, for example, a first oxide layer 310, a silicon nitride layer 320, and a second oxide layer 500 (ONO structure); in step three, the sidewall material layer located on the top and sidewalls of the substrate and gate structure is etched away. However, after step three, especially in the memory cell area, the first oxide layer 310 cannot be completely removed, so step four is required to etch away the residual oxide on the substrate. Finally, a sidewall of the ONO structure is formed on the sidewall of the gate structure. In steps three and four, the sidewall material layers formed in the memory cell area A and the logic circuit area B are etched simultaneously.

[0003] However, performing two etching processes consecutively may easily lead to over-etching and damage to the sidewalls. Figure 1C As shown in the dotted box in the figure, the top of the silicon nitride layer is missing in the sidewall structure in the logic circuit area B. This affects the implementation of subsequent processes (for example, the missing top of the silicon nitride layer in the sidewall will cause the subsequent metal layer to grow out of alignment), resulting in the performance of the final device being affected, affecting the device yield and reliability. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof to solve the problem that the existing process of forming the sidewall structure in the semiconductor structure will cause damage to the sidewall, thereby affecting the implementation of subsequent processes and affecting the performance of the final device.

[0005] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0006] Providing a substrate, the substrate comprising a memory cell region and a logic circuit region, wherein gate structures are formed in both the memory cell region and the logic circuit region;

[0007] forming a first oxide layer and a silicon nitride layer in sequence to cover each of the gate structures and the substrate;

[0008] Covering the logic circuit area with a protective layer and exposing the memory cell area;

[0009] Using a first etching process, etching and removing the silicon nitride layer located on the top of the gate structure and on the substrate in the memory cell area;

[0010] removing the protective layer in the logic circuit area;

[0011] forming a second oxide layer to cover each of the gate structures and the substrate, wherein in the memory cell region, the second oxide layer fills the gaps between adjacent gate structures;

[0012] A second etching process is adopted to etch away the second oxide layer and the first oxide layer located between the top of the gate structure and the gate structure in the storage cell area, and to remove the second oxide layer, the silicon nitride layer and the first oxide layer located on the gate structure and the substrate in the logic circuit area, so as to form a sidewall structure on the sidewalls of the gate structure in the storage cell area and the logic circuit area.

[0013] Optionally, in the second etching process, an etching rate in the memory cell area is lower than an etching rate in the logic circuit area.

[0014] Optionally, the second etching process adopts dry etching.

[0015] Optionally, the first etching process adopts dry etching.

[0016] Optionally, the first oxide layer and the second oxide layer are silicon oxide, and are formed by a deposition process.

[0017] Optionally, the method further includes: pre-cleaning the substrate before forming the first oxide layer.

[0018] A semiconductor structure formed based on the above-mentioned manufacturing method is characterized by comprising:

[0019] A substrate, the substrate comprising a memory cell region and a logic circuit region, wherein gate structures are formed in both the memory cell region and the logic circuit region;

[0020] A sidewall spacer covers the sidewall of the gate structure, and the sidewall spacer includes a first oxide layer, a silicon nitride layer and a second oxide layer.

[0021] Optionally, a metal compound layer is formed on the top of the sidewall.

[0022] The manufacturing method of the semiconductor structure provided by the present invention first forms a first oxide layer and a silicon nitride layer in the memory cell area and the logic circuit area; then, the logic circuit area is protected and a first etching process is performed on the memory cell area to remove the silicon nitride layer on the top of the gate structure and the substrate in the memory cell area; then, a second oxide layer is deposited in the memory cell area and the logic circuit area, and a second etching process is performed on the memory cell area and the logic circuit area to form sidewalls of the ONO structure on the sidewalls of the gate structure in the memory cell area and the logic circuit area. Utilizing the manufacturing method provided by the present invention, only one etching process is performed on the logic circuit area, avoiding over-etching, protecting the sidewall structure from damage, and ensuring that subsequent processes are not affected, thereby helping to improve device yield and reliability. At the same time, the probability of over-etching in the memory cell area can also be reduced, effectively reducing the impact of the etching process on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1A-1C It is a schematic diagram of the structural changes of the side wall structure during the formation process in the prior art;

[0024] Figure 2 A flowchart of a method for manufacturing a semiconductor structure provided by one embodiment of the present invention;

[0025] Figures 3A-3F Schematic diagram of the structural changes of a semiconductor structure during the manufacturing process provided by one embodiment of the present invention;

[0026] In the figure,

[0027] 100 - substrate; A - memory cell area; B - logic circuit area; 210 / 220 - gate structure; 310 - first oxide layer; 320 - silicon nitride layer; 400 - protective layer; 500 - second oxide layer. DETAILED DESCRIPTION

[0028] As described in the background art, during the process of forming the sidewall structure, the sidewall material layer formed on the memory cell area and the logic circuit area is etched twice continuously, which is prone to over-etching and causing damage to the sidewall (such as Figure 1C As shown in the figure, this affects the implementation of subsequent processes, resulting in a decrease in the performance of the resulting device, and thus impacting the device yield and reliability. This embodiment provides a semiconductor structure and a method for manufacturing the same, wherein only a single etching process is performed on the logic circuit area, avoiding overetching, protecting the sidewall structure from damage, and ensuring that subsequent processes are not affected, thereby helping to improve device yield and reliability. Furthermore, the probability of overetching in the memory cell area can also be reduced, effectively minimizing the impact of the etching process on the substrate.

[0029] The semiconductor structure and its manufacturing method proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are all greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0030] Figure 2 Flowchart of a method for manufacturing a semiconductor structure provided by one embodiment of the present invention. Figure 2 As shown, the method for manufacturing a semiconductor structure provided in this embodiment includes the following steps.

[0031] Step S100: providing a substrate, wherein the substrate includes a memory cell region and a logic circuit region, wherein gate structures are formed in both the memory cell region and the logic circuit region.

[0032] FIG3 is a diagram showing the structural changes of a semiconductor structure during the manufacturing process according to an embodiment of the present invention. Figure 3A As shown, the substrate 100 includes a memory cell area A and a logic circuit area B, with gate structures formed on both the memory cell area A and the logic circuit area B (i.e., a gate structure 210 located in the memory cell area A and a gate structure 220 located in the logic circuit area B). The substrate 100 is made of, for example, single crystal silicon, polycrystalline silicon, or amorphous silicon, or a compound such as silicon, germanium, gallium arsenide, or silicon germanium. In this embodiment, the substrate 100 is, for example, a silicon substrate. Furthermore, in this embodiment, each gate structure 210 in the memory cell area A comprises, from bottom to top, a floating gate layer, a dielectric layer, and a first control gate layer (not shown), wherein the floating gate layer and the first control gate layer are made of, for example, polycrystalline silicon, and the dielectric layer is made of, for example, an ONO layer formed by stacking silicon oxide, silicon nitride, and silicon oxide. Each gate structure 220 in the logic circuit area B comprises, from bottom to top, a gate oxide layer and a second control gate layer (not shown), wherein the gate oxide layer is made of, for example, silicon oxide, and the second control gate layer is made of, for example, polycrystalline silicon.

[0033] Step S200: forming a first oxide layer and a silicon nitride layer in sequence to cover each of the gate structures and the substrate.

[0034] Specifically, such as Figure 3BAs shown, a first oxide layer 310 is sequentially formed on the surface of the gate structure 210 in the memory cell area A, the surface of the gate structure 220 in the logic circuit area B, and the exposed surface of the substrate 100. Then, a silicon nitride layer 320 is formed on the surface of the first silicon oxide layer 310, thereby forming a spacer material layer including two dielectric film layers. The material of the first oxide layer 310 is, for example, silicon oxide and can be formed by a deposition process; the silicon nitride layer 320 can also be formed by a deposition process.

[0035] Furthermore, the manufacturing method provided in this embodiment also includes: before forming the first oxide layer 310, pre-cleaning the substrate 100. That is, before the process starts, the substrate 100 is pre-cleaned to remove pollutants such as particles and organic matter on the surface of the substrate 100 to ensure the cleanliness of the surface of the substrate 100. Specifically, a wet cleaning process can be used to complete the pre-cleaning. The cleaning solution used is, for example, a mixture of ammonia water (NH4OH), hydrogen peroxide (H2O2) and water (H2O) (for example, the concentration ratio of NH4OH:H2O2:H2O is 1:1.5:50), which is used to remove photoresist residues, polymer residues, particles and other residues.

[0036] Step S300: Covering the logic circuit area with a protection layer and exposing the memory cell area.

[0037] like Figure 3C As shown, a protective layer 400 is covered on the silicon nitride layer 320 in the logic circuit region B to mask and protect the logic circuit region B. The protective layer 400 includes photoresist.

[0038] Step S400: using a first etching process to etch and remove the silicon nitride layer located on the top of the gate structure and on the substrate in the memory cell region.

[0039] like Figure 3D As shown, the silicon nitride layer 320 on the surface of the substrate 100 and the top of the gate structure 210 in the memory cell region A is removed by etching to form sidewalls of the ON structure on the sidewalls of the gate structure 210 in the memory cell region A.

[0040] The first etching process employs dry etching. Specifically, for example, an anisotropic dry etching process is employed to remove the silicon nitride layer. The dry etching employs, for example, a fluorine-based gas or a mixture of oxygen and nitrogen. The fluorine-based gas may include one or more of CF4, SiF4, NF3, C2F6, or CHF3.

[0041] Step S500: removing the protective layer in the logic circuit area, wherein the protective layer 400 can be removed by dry cleaning or wet cleaning.

[0042] Step S600: forming a second oxide layer to cover each of the gate structures and the substrate, wherein in the memory cell region, the second oxide layer fills the gaps between adjacent gate structures.

[0043] like Figure 3E As shown, a second oxide layer 500 is formed on the substrate and gate structure in the memory cell area A and the logic circuit area B. In the memory cell area A, the second oxide layer 500 covers the surface of the substrate 100 and the gate structure 210, fills the gap between adjacent gate structures 210, and covers the top of the gate structure 210. At this time, a spacer material layer comprising three dielectric film layers (i.e., an ONO structure) is formed on the sidewall of the gate structure 210, and a first oxide layer 310 and a second oxide layer 500 are formed on the top of the gate structure 210 and between the gate structure 210. In the logic circuit area B, the second oxide layer 500 covers the silicon nitride layer 320, and a spacer material layer comprising three dielectric film layers (i.e., an ONO structure) is formed on the surface of the gate structure 220 and the substrate. The material of the second oxide layer 500 is, for example, silicon oxide, and can be formed using a deposition process.

[0044] Step S700: A second etching process is used to etch away the second oxide layer and the first oxide layer located between the top of the gate structure and the gate structure in the memory cell area, and the second oxide layer, the silicon nitride layer and the first oxide layer located on the gate structure and the substrate in the logic circuit area, so as to form a sidewall structure on the sidewalls of the gate structure in the memory cell area and the logic circuit area.

[0045] like Figure 3F As shown, a second etching process is used to simultaneously etch the memory cell region A and the logic circuit region B to remove the second oxide layer 500 and the first oxide layer 310 located on top of and between the gate structure 210 in the memory cell region A. In the memory cell region B, the second oxide layer 500, the silicon nitride layer 310, and the first oxide layer 320 located on top of the gate structure 220 and on the substrate 100 are etched away. Thus, ONO spacer structures are formed on the sidewalls of the gate structures in the memory cell region A and the logic circuit region B.

[0046] The second etching process adopts dry etching, for example, an anisotropic dry etching process, and the gas used is, for example, fluorocarbon gas.

[0047] Furthermore, in the second etching process, an etching rate in the memory cell area is lower than an etching rate in the logic circuit area.

[0048] Specifically, in this embodiment, the distance between the gate structures 210 in the memory cell region A is smaller than the distance between the gate structures 220 in the logic circuit region B, and the height of the gate structures 210 in the memory cell region A is greater than the height of the gate structures 220 in the logic circuit region B. That is, the gate structures 210 in the memory cell region A are densely distributed, the gaps between adjacent gate structures 210 are smaller and deeper, resulting in a slower etching rate. In contrast, the gate structures 220 in the logic circuit region B are sparsely distributed, the gaps between adjacent gate structures 220 are larger and deeper, resulting in a faster etching rate. Therefore, in this embodiment, ON structures are first formed on the sidewalls of the gate structures in the memory cell region. In the second etching process, only the second oxide layer and the first oxide layer are removed in the memory cell region, reducing material consumption and effectively reducing the amount of residue on the substrate after etching. Additional etching processes are not required, thus avoiding over-etching. Furthermore, performing only a single etching process on the logic circuit region also effectively avoids over-etching.

[0049] In this embodiment, a first oxide layer and a silicon nitride layer are first formed in the memory cell area and the logic circuit area. Then, the logic circuit area is protected and a first etching process is performed on the memory cell area to remove the silicon nitride layer on top of the gate structure and on the substrate in the memory cell area. Next, a second oxide layer is deposited in the memory cell area and the logic circuit area, and a second etching process is simultaneously performed on the memory cell area and the logic circuit area to remove the second oxide layer and the first oxide layer located on top of and between the gate structure in the memory cell area, as well as the second oxide layer, silicon nitride layer, and first oxide layer located on the gate structure and the substrate in the logic circuit area, thereby forming ONO structure sidewalls on the sidewalls of the gate structure in the memory cell area and the logic circuit area. Utilizing the manufacturing method provided by the present invention, only a single etching process is performed on the logic circuit area, avoiding overetching, protecting the sidewall structure from damage, and ensuring that subsequent processes are not affected, thereby helping to improve device yield and reliability. At the same time, the probability of overetching in the memory cell area can be reduced, effectively reducing the impact of the manufacturing process on the substrate.

[0050] Based on the above-mentioned manufacturing method, this embodiment also provides a semiconductor structure, including: a substrate, the substrate including a memory cell area and a logic circuit area, and gate structures are formed in the memory cell area and the logic circuit area; a sidewall, covering the sidewall of the gate structure, the sidewall including a first oxide layer, a silicon nitride layer and a second oxide layer.

[0051] Furthermore, a metal compound is formed on the top of the sidewall, wherein the material of the metal compound layer is, for example, nickel-platinum compound.

[0052] At this time, since the formed sidewall structure is not damaged, especially there is no missing top of the silicon nitride layer in the sidewall, the probability of dislocation of the metal compound layer growth can be greatly reduced when the metal oxide layer is subsequently formed, which helps to improve the yield and reliability of semiconductor devices.

[0053] From the above, it can be seen that in the semiconductor structure and manufacturing method thereof provided in the embodiment of the present invention, a first oxide layer and a silicon nitride layer are first formed in the memory cell area and the logic circuit area; then the logic circuit area is protected, and a first etching process is performed on the memory cell area to remove the silicon nitride layer on the top of the gate structure and the substrate in the memory cell area; then, a second oxide layer is deposited in the memory cell area and the logic circuit area, and a second etching process is performed on the memory cell area and the logic circuit area to form side walls of the ONO structure on the side walls of the gate structure in the memory cell area and the logic circuit area. By utilizing the manufacturing method provided by the present invention, only one etching process is performed on the logic circuit area to avoid over-etching, protect the side wall structure from being damaged, and ensure that subsequent processes are not affected, thereby helping to improve the device yield and reliability. At the same time, the probability of over-etching in the memory cell area can also be reduced, effectively reducing the impact of the manufacturing process on the substrate.

[0054] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: Providing a substrate, the substrate comprising a memory cell region and a logic circuit region, wherein gate structures are formed in both the memory cell region and the logic circuit region; forming a first oxide layer and a silicon nitride layer in sequence to cover each of the gate structures and the substrate; Covering the logic circuit area with a protective layer and exposing the memory cell area; Using a first etching process, etching and removing the silicon nitride layer located on the top of the gate structure and on the substrate in the memory cell area; removing the protective layer in the logic circuit area; forming a second oxide layer to cover each of the gate structures and the substrate, wherein in the memory cell region, the second oxide layer fills the gaps between adjacent gate structures; A second etching process is adopted to etch away the second oxide layer and the first oxide layer located between the top of the gate structure and the gate structure in the storage cell area, and to remove the second oxide layer, the silicon nitride layer and the first oxide layer located on the gate structure and the substrate in the logic circuit area, so as to form a sidewall structure on the sidewalls of the gate structure in the storage cell area and the logic circuit area.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: In the second etching process, an etching rate in the memory cell region is lower than an etching rate in the logic circuit region.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The second etching process adopts dry etching.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first etching process adopts dry etching.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first oxide layer and the second oxide layer are silicon oxide and are formed by a deposition process.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: Before forming the first oxide layer, the substrate is pre-cleaned.

7. A semiconductor structure formed based on the manufacturing method according to any one of claims 1 to 6, characterized in that: include: A substrate, the substrate comprising a memory cell region and a logic circuit region, wherein gate structures are formed in both the memory cell region and the logic circuit region; A sidewall spacer covers the sidewall of the gate structure, and the sidewall spacer includes a first oxide layer, a silicon nitride layer and a second oxide layer.

8. The semiconductor structure according to claim 7, wherein: A metal compound layer is formed on the top of the sidewall.

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