Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising a substrate substrate; a first transistor, the first transistor comprising a first gate and a first active layer; the first gate is located on one side of the substrate substrate; the first active layer is located on one side of the substrate substrate, and the first active layer comprises a channel region, in a direction perpendicular to a plane where the substrate substrate is located, a part of the first active layer overlapping with the first gate is the channel region; a first insulating layer is located on a side of the first active layer away from the substrate substrate; a second insulating layer is located on a side of the first insulating layer away from the substrate substrate, and the second insulating layer contains hydrogen; the second insulating layer comprises a first opening, and in a direction perpendicular to a plane where the substrate substrate is located, the first opening overlaps with the channel region. The application improves the problem of uneven distribution of threshold voltage Vth and current Ion in the display panel, and improves the display performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, more particularly, to a display panel and a display device. BACKGROUND

[0002] At present, display technology penetrates into every aspect of people's daily life, accordingly, more and more materials and technologies are used in display screens. The display panel, as an important component of the display device, is used to realize the display function of the display device. At present, the mainstream display screens mainly include liquid crystal display panels and organic light-emitting display panels (OLED).

[0003] The liquid crystal display panel has the advantages of lightness, low power consumption and low radiation, and is widely used in various fields. The liquid crystal display panel usually includes a color film substrate and an array substrate arranged oppositely, and a liquid crystal layer between the color film substrate and the array substrate, the color film substrate is provided with a black matrix and a color resistance on the side close to the array substrate, the electric field between the pixel electrode and the common electrode in the display panel can make the liquid crystal molecules deflect, the light generated by the backlight assembly will be transmitted through the display panel after the liquid crystal molecules deflect, by adjusting the size of the electric field, the degree of deflection of the liquid crystal molecules can be different, and the light transmittance of the display panel is different when the degree of deflection of the liquid crystal molecules is different, the light quantity of the backlight assembly transmitted through the liquid crystal display panel is different, thereby realizing the display of the image; the organic light-emitting diode as a current type light-emitting device has been more and more applied in high-performance display, the OLED display panel has the advantages of self-luminous, wide viewing angle, fast response speed, high contrast, wide color gamut, low energy consumption, thin panel, rich color, flexible display, wide working temperature range and many other excellent characteristics, and is therefore known as the next generation of "star" flat panel display technology. The OLED display panel includes an anode and a cathode, and a hole transport layer, an organic light-emitting layer and an electron transport layer arranged between the anode and the cathode, the anode provides hole injection, and the cathode provides electron injection, under the drive of external voltage, the holes and electrons injected from the cathode and the anode recombine in the organic light-emitting layer to form an electron-hole pair (i.e. exciton) at the bound energy level, the exciton radiates and de-excites to emit photons, and visible light is generated.

[0004] The thin film transistor (TFT) in the prior art is the main driving element in the OLED display panel and the LCD display device, but the thin film transistor of the display panel in the prior art has the problem of short channel effect, which makes the stability of the thin film transistor poor.

[0005] Therefore, it is urgent to provide a display panel capable of changing the short channel effect of the transistor. SUMMARY

[0006] Therefore, the display panel and the display device are provided to improve the short channel effect of the display panel and improve the display performance.

[0007] In one aspect, the display panel is provided, comprising:

[0008] a substrate substrate;

[0009] a first transistor, the first transistor comprising a first gate and a first active layer;

[0010] the first gate is located on one side of the substrate substrate;

[0011] the first active layer is located on one side of the substrate substrate, and the first active layer comprises a channel region, and a portion of the first active layer overlapping the first gate in a direction perpendicular to a plane where the substrate substrate is located is the channel region;

[0012] a first insulating layer located on a side of the first active layer away from the substrate substrate;

[0013] a second insulating layer located on a side of the first insulating layer away from the substrate substrate, the second insulating layer containing hydrogen;

[0014] the second insulating layer comprises a first opening, and the first opening overlaps the channel region in a direction perpendicular to the plane where the substrate substrate is located.

[0015] In another aspect, the display device is provided, comprising the display panel.

[0016] Compared with the prior art, the display panel and the display device provided by the present application at least achieve the following beneficial effects:

[0017] The display panel provided by the present application comprises a first transistor disposed on a substrate substrate, the first transistor comprises a first gate and a first active layer, a portion of the first active layer overlapping the first gate in a direction perpendicular to a plane where the substrate substrate is located is a channel region, a first insulating layer and a second insulating layer are included on a side of the first active layer away from the substrate substrate, the second insulating layer contains hydrogen, the second insulating layer has a first opening, and a normal projection of the first opening on the plane where the substrate substrate is located overlaps a normal projection of the channel region on the plane where the substrate substrate is located. In the present application, the second insulating layer has an opening region, that is, a portion of the second insulating layer corresponding to the channel region is removed or the second insulating layer corresponding to the channel region is completely removed. In this way, the total volume of the second insulating layer is reduced, and the total content of hydrogen is also reduced. In this way, the problem of uneven distribution of threshold voltage Vth and current Ion of the transistor caused by uneven hydrogen content is reduced, the stability of the transistor performance is improved, and the display performance of the display panel is improved.

[0018] Of course, any product embodying the present application need not necessarily achieve all of the above-mentioned technical effects simultaneously.

[0019] Other features of the present application, and its advantages, will become apparent in the course of the following detailed description of exemplary embodiments of the application. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with the description, serve to explain the principles of the application.

[0021] Figure 1 is a plan view of a display panel in the related art;

[0022] Figure 2 is Figure 1 is a sectional view in the direction of A-A' in

[0023] Figure 3 is an exploded view of a display panel according to the present application;

[0024] Figure 4 is a plan view of a display panel according to the present application;

[0025] Figure 5 is Figure 4 is a sectional view in the direction of B-B' in

[0026] Figure 6 is a plan view of a display panel according to the present application;

[0027] Figure 7 is Figure 6 is a sectional view in the direction of C-C' in

[0028] Figure 8 is a plan view of a display panel according to the present application;

[0029] Figure 9 is Figure 8 is a sectional view in the direction of D-D' in

[0030] Figure 10 is Figure 8 is a sectional view in the direction of D-D' in

[0031] Figure 11 is Figure 10 is an enlarged view of the F region in

[0032] Figure 12 is a plan view of a display panel according to the present application;

[0033] Figure 13 isFigure 12 a cross-sectional view along the direction of E-E' of FIG. 1;

[0034] Figure 14 is a pixel circuit of a display panel provided by the present application;

[0035] Figure 15 is Figure 14 a layout of the pixel circuit;

[0036] Figure 16 is a schematic diagram of a plane structure of a display device provided by the present application. DETAILED DESCRIPTION

[0037] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements, numerical expressions, and numerical values of components and steps set forth in these embodiments are not limiting to the scope of the present application unless otherwise specifically stated.

[0038] The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the scope of the application, its application, or uses.

[0039] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered part of the specification.

[0040] In all of the compositions and methods disclosed and discussed herein, any specific values should be interpreted as merely exemplary, and are not intended to be limiting. Thus, other examples of the exemplary embodiments can have different values.

[0041] It should be noted that like references and characters herein relate to like items throughout the figures, and once an item is defined in one figure, it need not be discussed further in subsequent figures.

[0042] The thin film transistor (TFT) in the related art is a main driving element in an OLED display panel and an LCD display device. With the pixel driving circuit becoming more and more complex, such as a pixel driving circuit with multiple thin film transistors, such as 7T1C and 16T1C (T refers to a thin film transistor, and C refers to a storage capacitor), multiple thin film transistors need to be arranged in a pixel area. Since multiple thin film transistors need to be arranged in the pixel area, the size of the thin film transistor becomes smaller, and the channel region length of the semiconductor of the thin film transistor also becomes smaller. If the thin film transistor is driven by general design parameters, the problem of the electronic energy of the channel region being in contact with the drain being raised will occur, the drain current is relatively serious, which is the short channel effect. The short channel effect will cause the threshold voltage Vth of the thin film transistor to be negatively shifted seriously, thereby affecting the stability of the thin film transistor, and further affecting the display performance of the display panel. The inventors have found in research that Figure 1 and Figure 2 , Figure 1 is a plan view of a display panel in the related art, Figure 2 is a sectional view in the direction of A-A' in Figure 1 , the display panel in Figure 1 includes a substrate 01 and a transistor T' on one side of the substrate 01. The transistor T' includes an active layer 02, a gate metal layer 03, a gate insulating layer 06 between the active layer 02 and the gate metal layer 03, a first insulating layer 07 and a second insulating layer 08, a source 04 and a drain 05. The active layer 02 includes a channel region 021 and an edge region 02. The channel region 021 refers to an area overlapping the gate metal layer 03. The edge region 02 also has a contact region. The contact region refers to an area where the source 04 or the drain 05 is in contact with the active layer 02 through a via. The first insulating layer 07 is located on a side of the active layer 02 away from the substrate 01. The second insulating layer 08 is located on a side of the first insulating layer 07 away from the substrate 01. The second insulating layer 08 contains hydrogen. For the transistor, the source-drain conductorization is mainly determined by two parts. One is hydrogen diffusion, that is, H in the second insulating layer 08 diffuses to the source-drain to form a large number of electrons, H+O 2- →OH - +e - , thereby realizing the conductorization of the source-drain. The other is the doping amount of the active layer, B+M-O→B2O3+V OFor the short channel transistor, in order to reduce the short channel effect, the doping dose is usually small, so the source and drain conductorization is mainly realized by hydrogen diffusion in the second insulating layer 08, but the second insulating layer 08 is provided in the whole surface, and when the source and drain are conductive, the hydrogen in the second insulating layer 08 is distributed in the whole surface, so the distribution is uneven, and the hydrogen content diffused to the active layer 02 is also uneven, and the hydrogen diffused to the active layer 02 combines with the cations in the active layer 02 to form electrons, so the number of electrons formed is also uneven, and the distribution difference occurs, and the threshold voltage Vth and current Ion of the transistor are affected by the number of carriers (electrons), thus causing the problem of uneven distribution of the threshold voltage Vth and current Ion of the transistor, affecting the performance stability of the transistor, and thus affecting the display performance of the display panel.

[0043] Therefore, the present application provides a display panel and a display device for improving the problem of uneven distribution of the threshold voltage Vth and current Ion of the transistor, improving the performance reliability of the transistor, and the specific embodiments of the display panel and the display device will be described in detail below.

[0044] Reference Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 , Figure 3 is a disassembled schematic view of a display panel provided by the present application, Figure 4 is a planar structure schematic view of a display panel provided by the present application;

[0045] Figure 5 is Figure 4 B-B' direction of a section view; Figure 6 is a planar structure schematic view of another display panel provided by the present application, Figure 7 is Figure 6 C-C' direction of a section view, Figure 4-7 The display panel 100 in the display panel 100 includes: a substrate 1; a first transistor T1, the first transistor T1 includes a first gate 3 and a first active layer 2; the first gate 3 is located on one side of the substrate 1; the first active layer 2 is located on one side of the substrate 1, and the first active layer 2 includes a channel region 21, and the part of the first active layer 2 overlapping with the first gate 3 in the direction perpendicular to the plane where the substrate 1 is located is the channel region 21; a first insulating layer 7 is located on the side of the first active layer 2 away from the substrate 1; a second insulating layer 8 is located on the side of the first insulating layer 7 away from the substrate 1, and the second insulating layer 8 contains hydrogen; the second insulating layer 8 includes a first opening 81, and the first opening 81 overlaps with the channel region 21 in the direction perpendicular to the plane where the substrate 1 is located.

[0046] Reference Figure 5and Figure 7 as shown, Figure 5 and Figure 7 The first transistor T1 is only schematically shown as a top-gate case, and of course the first transistor T1 can also be a bottom-gate case, which is not shown here. Figure 5 and Figure 7 In the first gate 3 is located on the side of the active layer away from the substrate 1, and the first gate 3 and the first active layer 2 include a first gate insulating layer 6 between them, Figure 5 and Figure 7 In the first gate insulating layer 6 and the first insulating layer 7 are not patterned. When the first transistor T1 is a bottom gate, the first gate 3 is located on the side of the first active layer 2 close to the substrate 1.

[0047] In the direction perpendicular to the plane of the substrate 1, the part of the first active layer 2 overlapping the first gate 3 is the channel region 21, and of course the first active layer 2 includes an edge region 22 in addition to the channel region 21. It should be noted that the first opening 81 overlaps the channel region 21 in the direction perpendicular to the plane of the substrate 1, which can be that the first opening 81 partially overlaps the channel region 21 in the direction perpendicular to the plane of the substrate 1, or that the first opening 81 is located within the channel region 21 in the direction perpendicular to the plane of the substrate 1, or that the channel region 21 is located within the first opening 81 in the direction perpendicular to the plane of the substrate 1, which is not specifically limited here, Figure 4-7 In the first opening 81 is only schematically shown as located within the channel region 21 in the direction perpendicular to the plane of the substrate 1. Figure 5 In the second opening 81 does not penetrate the second insulating layer 8, Figure 3 and Figure 7 In the second opening 81 penetrates the second insulating layer 8.

[0048] The material of the first insulating layer 7 can be silicon oxide, and the material of the second insulating layer 8 can be silicon nitride, and of course the materials of the first insulating layer 7 and the second insulating layer 8 are not specifically limited here. It can be understood that, Figure 5 and Figure 7 In the first opening 81 is only schematically shown as located within the channel region 21 in the direction perpendicular to the plane of the substrate 1. That is, the area of the first opening 81 is smaller than the area of the channel region 21, and the size of the first opening 81 is not specifically limited here, as long as the first opening 81 overlaps the channel region 21 in the direction perpendicular to the plane of the substrate 1.

[0049] It can be understood that in the direction perpendicular to the plane where the substrate 1 is located, the first opening 81 overlaps with the channel region 21, that is, the second insulating layer 8 is removed in the position corresponding to the channel region 21, so that the total hydrogen content in the second insulating layer 8 is reduced, and the influence of uneven hydrogen distribution is reduced.

[0050] As described above, in the related art, the second insulating layer 08 is provided in the whole area, and when the source and drain are conductive, the hydrogen in the second insulating layer 08 is distributed in a wide area, so the distribution is uneven, and the hydrogen content diffused to the active layer 02 is also uneven. The hydrogen diffused to the active layer 02 combines with the cations in the active layer 02 to form electrons, so the number of electrons formed is also uneven, and the distribution is different. The threshold voltage Vth and the current Ion of the transistor are affected by the number of carriers (electrons), so the problem of uneven distribution of the threshold voltage Vth and the current Ion of the transistor is caused, the performance stability of the transistor is affected, and the display performance of the display panel is affected. In the present application, the second insulating layer 8 has the first opening 81, and part or all of the second insulating layer 8 in the position corresponding to the channel region 21 is removed, that is, the thickness of the second insulating layer 8 in the position corresponding to the channel region 21 is reduced. In this way, the total volume of the second insulating layer 8 is reduced, and the total content of hydrogen is also reduced. In this way, the problem of uneven distribution of the threshold voltage Vth and the current Ion of the transistor caused by uneven hydrogen content is reduced, the performance stability of the transistor is improved, and the display performance of the display panel 100 is improved.

[0051] In some optional embodiments, referring to Figure 8 and Figure 9 , Figure 8 is another planar structure schematic view of a display panel provided by the present application, Figure 9 is Figure 8 a cross-sectional view in the direction of D-D' in the present application. In the direction perpendicular to the plane where the substrate 1 is located, the second insulating layer 8 does not overlap with the channel region 21.

[0052] Specifically, the second insulating layer 8 includes the first opening 81 and a part other than the first opening 81 (that is, the part remaining after the first opening 81 is removed, that is, the non-opening part 82). Here, it is referred to that the orthographic projection of the non-opening part 82 on the plane where the substrate 1 is located does not overlap with the orthographic projection of the channel region 21 on the plane where the substrate 1 is located, that is, the part corresponding to the first opening 81 is completely removed, and the remaining part of the second insulating layer 8 does not overlap with the channel region 21 of the first active layer 2. The larger the removed part of the second insulating layer 8, the smaller the remaining part, and the smaller the total hydrogen content, and the smaller the influence of uneven hydrogen diffusion distribution.

[0053] In some optional embodiments, the first transistor T1 further comprises a first electrode 10, the first electrode 10 is located on the side of the second insulating layer 8 away from the substrate 1, and the first electrode 10 is electrically connected with the first active layer 2. Optionally, the second insulating layer 8 only retains the part overlapping with the source / drain electrode, which can further reduce the volume of the second insulating layer 8, so that the hydrogen content is further reduced, thereby further reducing the influence of uneven hydrogen distribution.

[0054] In some optional embodiments, continuing to refer to Figure 8 and Figure 9 , the thickness of the second insulating layer 8 is less than or equal to 500 angstroms.

[0055] In the present application, the thickness of the second insulating layer 8 is thinned, that is, the thickness of the second insulating layer 8 is less than the thickness in the prior art. For example, the thickness of the second insulating layer 8 is 500 angstroms, 450 angstroms, 400 angstroms, 350 angstroms, 300 angstroms, 250 angstroms, 200 angstroms, 150 angstroms, 100 angstroms, or 50 angstroms. The smaller the thickness of the second insulating layer 8 is, the more conducive to improving the problem of uneven hydrogen distribution.

[0056] On the one hand, thinning the second insulating layer 8 can further reduce the hydrogen content and further reduce the influence of uneven hydrogen distribution.

[0057] Furthermore, when manufacturing the display panel 100, the first electrode 10 (source electrode 4 or drain electrode 5) also needs to be manufactured, the first electrode 10 is located on the side of the second insulating layer 8 away from the substrate 1, and the first electrode 10 is electrically connected with the first active layer 2. The first electrode 10 is usually formed by a mask etching method, and the first opening 81 of the second insulating layer 8 is also realized by an etching process. If the second insulating layer 8 is thinned, the second insulating layer 8 can be etched to form the first opening 81 when over-etching 10. One process can etch the first opening 81 of the second insulating layer 8, and at the same time, the first electrode 10 is manufactured. This not only facilitates over-etching of the second insulating layer 8, but also saves one etching process and mask, reduces process complexity, and saves production cost.

[0058] In another aspect, when the display panel 100 is a flexible display panel 100, the substrate 1 is usually made of a flexible material, such as polyurethane, etc. In the manufacturing of the display panel 100, the flexible substrate 1 is first arranged on a glass, and then the manufacturing of each film layer is performed. The driving circuit, the light-emitting layer (usually including an anode, a light-emitting material, and a cathode), the encapsulation layer, and the touch layer are manufactured on the substrate 1. Of course, the light-emitting layer, the encapsulation layer, and the touch layer are not shown in the drawings. After the manufacturing of the touch layer is completed, the display panel 100 is removed from the glass. In the process of removing, if the film layer stack is too thick and the stress is too large, the problem of wrinkles may occur. Since the second insulating layer 8 has the first opening 81, that is, the part corresponding to the channel region 21 is dug out, the problem of wrinkles can be improved. Of course, in the present application, the thickness of the second insulating layer 8 is thinned, and of course, the problem of wrinkles can also be improved.

[0059] In some optional embodiments, continuing to refer to Figure 8 and Figure 9 , the first transistor T1 includes a first pole 10, the first pole 10 is located on the side of the second insulating layer 8 away from the substrate 1, and the first pole 10 is electrically connected with the first active layer 2.

[0060] The orthographic projection of the second insulating layer 8 on the plane where the substrate 1 is located is a first orthographic projection 41, the orthographic projection of the first pole 10 on the plane where the substrate 1 is located is a second orthographic projection 42, the first orthographic projection 41 covers the second orthographic projection 42, and the minimum distance between the edge of the first orthographic projection 41 to the edge of the second orthographic projection 42 is not greater than 2 μm.

[0061] Specifically, the first pole 10 in the present application can be a source electrode 4 or a drain electrode 5. Optionally, the first pole 10 is electrically connected with the first insulating layer 7 through a via. The orthographic projection of the second insulating layer 8 on the plane where the substrate 1 is located is a first orthographic projection 41, the orthographic projection of the first pole 10 on the plane where the substrate 1 is located is a second orthographic projection 42, and the first orthographic projection 41 covers the second orthographic projection 42, that is, the orthographic projection area of the second insulating layer 8 is greater than the orthographic projection area of the first pole 10. It can be understood that the edge of the first orthographic projection 41 refers to the side close to the second orthographic projection 42, and the edge of the second orthographic projection 42 refers to the side close to the first orthographic projection 41. Thus, the minimum distance between the edge of the first orthographic projection 41 to the edge of the second orthographic projection 42 refers to the nearest distance between the first orthographic projection 41 and the second orthographic projection 42.

[0062] Of course, in the embodiment, the minimum distance between the edge of the first orthographic projection 41 to the edge of the second orthographic projection 42 is d1, d1 is not greater than 2 μm, at this time, the manufacturing process can be met, and only one mask is needed, and the source-drain metal is etched to form the first electrode 10 and the second insulating layer 8, at this time, the area of the second insulating layer 8 is the minimum value allowed by the process conditions, and the optimal effect of improving the uneven distribution of hydrogen under the process conditions can be achieved.

[0063] In some optional embodiments, continuing to refer to Figure 8 and Figure 9 , the orthographic projection of the second insulating layer 8 on the plane where the substrate substrate 1 is located is the first orthographic projection 41, the orthographic projection of the first gate 3 on the plane where the substrate substrate 1 is located is the third orthographic projection 43, the first orthographic projection 41 and the third orthographic projection 43 do not overlap, and the minimum distance between the edge of the first orthographic projection 41 to the edge of the third orthographic projection 43 is greater than 3 μm.

[0064] Specifically, the orthographic projection of the second insulating layer 8 on the plane where the substrate substrate 1 is located is the first orthographic projection 41, the orthographic projection of the first gate 3 on the plane where the substrate substrate 1 is located is the third orthographic projection 43, the first orthographic projection 41 and the third orthographic projection 43 do not overlap, and the minimum distance between the edge of the first orthographic projection 41 to the edge of the third orthographic projection 43 is d2, d2 is greater than 3 μm, for example, d2 = 4.2 μm, as described above, when the source-drain conductor is formed, the short channel transistor mainly relies on hydrogen diffusion, and the distribution of hydrogen in the second insulating layer 8 is uneven, so if the distance between the orthographic projection of the second insulating layer 8 on the plane where the substrate substrate 1 is located in the first transistor T1 and the orthographic projection of the first gate 3 on the plane where the substrate substrate 1 is located is increased, the first gate 3 will not be contacted during the hydrogen diffusion process, which is beneficial to improve the short channel effect.

[0065] In some optional embodiments, continuing to refer to Figure 9 , the first transistor T1 includes the first electrode 10, the first electrode 10 is located on the side of the second insulating layer 8 away from the substrate substrate 1, and the first electrode 10 is electrically connected with the first active layer 2;

[0066] The first electrode 10 includes oppositely arranged first face 51 and second face 52, and side face 53, the first face 51 is located on the side of the second face 52 close to the substrate substrate 1, the side face 53 is connected with the first face 51 and the second face 52 respectively, and the included angle between the first face 51 and the side face 53 is an acute angle.

[0067] It should be noted that if the first pole 10 forms an undercut, that is, the included angle between the side surface 53 and the first surface 51 is obtuse, the first transistor T1 will generate heat during operation, the second surface 52 and the side surface 53 will be retracted to form a sharp angle, causing local heating and burns, so the angle α between the first surface 51 and the side surface 53 in the first pole 10 should be smooth and acute. In the present embodiment, the first pole 10 includes the oppositely arranged first surface 51 and second surface 52, and the side surface 53. The first surface 51 is located on the side of the second surface 52 close to the substrate 1. The side surface 53 is connected to the first surface 51 and the second surface 52 respectively. The included angle between the first surface 51 and the side surface 53 in the present application is acute α, which can prevent the second surface 52 and the side surface 53 from forming a sharp angle to cause local heating and burns.

[0068] In some optional embodiments, continuing to refer to Figure 9 , the material of the second insulating layer 8 includes SiNx.

[0069] Silicon nitride SiNx has the following functions in a display panel: as a gate insulating layer, it has excellent insulating properties, high field breakdown strength, and low electron defect density; as a passivation layer, it has high dielectric constant, strong ability to block alkali metal ions, hard and wear-resistant quality, good hydrophobicity, and low pinhole density; as a gate interface layer, it has good insulating properties and lower electron defect density, and more importantly, it can reduce the interface state between the gate insulating layer and the amorphous silicon layer, and optimize the performance of the thin film transistor. In the present embodiment, silicon nitride is used as an etching buffer layer to reduce hydrogen content, thereby reducing the influence of uneven hydrogen distribution.

[0070] It should be noted that the material of the second insulating layer 8 in the present application is silicon nitride SiNx, which is used to prevent the undercut problem on the first insulating layer 7 (material: silicon oxide) when etching the source and drain metal to form the first pole 10. If the first pole 10 is directly formed on the first insulating layer 7 (material: silicon oxide) to form an undercut, that is, the included angle between the side surface 53 and the first surface 51 is obtuse, the first pole 10 will generate heat during operation. If the second surface 52 and the side surface 53 are retracted to form a sharp angle, local heating and burns will occur. Therefore, the angle α between the first surface 51 and the side surface 53 in the first pole 10 should be smooth and acute. In the present embodiment, the first pole 10 includes the oppositely arranged first surface 51 and second surface 52, and the side surface 53. The first surface 51 is located on the side of the second surface 52 close to the substrate 1. The side surface 53 is connected to the first surface 51 and the second surface 52 respectively. In the present application, the second insulating layer 8 is silicon nitride, which is used as an etching buffer layer due to its excellent physical properties. After etching the source and drain metal, the included angle between the first surface 51 and the side surface 53 is acute α, which can prevent the second surface 52 and the side surface 53 from forming a sharp angle to cause local heating and burns.

[0071] In some alternative embodiments, referring to Figure 10 and Figure 11 , Figure 10 is Figure 8 a further cross-sectional view of the direction of D-D' in Figure 11 is Figure 10 a partial enlarged view of the F region in, from the direction in which the substrate substrate 1 points to the second insulating layer 8, the first electrode 10 includes the first metal 101, the second metal 102, and the third metal 103 which are stacked, the third metal 103 is a fourth orthogonal projection 44 in the orthogonal projection of the plane where the substrate substrate 1 is located, the second metal 102 is a fifth orthogonal projection 45 in the orthogonal projection of the plane where the substrate substrate 1 is located, the first metal 101 is a sixth orthogonal projection 46 in the orthogonal projection of the plane where the substrate substrate 1 is located, the fifth orthogonal projection 45 covers the fourth orthogonal projection 44, the sixth orthogonal projection 46 covers the fifth orthogonal projection 45, and the minimum distance between the edge of the fifth orthogonal projection 45 to the edge of the sixth orthogonal projection 46 is d, wherein 50nm≤d≤200nm.

[0072] It can be understood that the film layer structure of the first electrode 10 in the embodiment is also applicable to the display panel 100 in the above Figure 6 , which will not be described here.

[0073] Specifically, the first pole 10 can be the source electrode 4 or the drain electrode 5, and in the embodiment, the first pole 10 is a laminated structure, and from the substrate 1 to the second insulating layer 8, the first pole 10 includes a laminated first metal 101, a second metal 102, and a third metal 103, for example, titanium / aluminum / titanium, and of course, the materials of the first metal 101, the second metal 102, and the third metal 103 are not specifically limited. The third metal 103 is projected onto the plane of the substrate 1 as a fourth projection 44, the second metal 102 is projected onto the plane of the substrate 1 as a fifth projection 45, the fifth projection 45 covers the fourth projection 44, that is, the area of the fifth projection 45 is greater than the area of the fourth projection 44, the first metal 101 is projected onto the plane of the substrate 1 as a sixth projection 46, the sixth projection 46 covers the fifth projection 45, and the area of the sixth projection 46 is greater than the area of the fifth projection 45, so that the side surface of the first pole 10 as a whole forms an inclined angle, rather than an inverted cut. Optionally, the minimum distance d between the edge of the fifth projection 45 and the edge of the sixth projection 46 is greater than or equal to 50 nm and less than or equal to 200 nm, and of course, the minimum distance m between the edge of the fourth projection 44 and the edge of the fifth projection 45 can also be greater than or equal to 50 nm and less than or equal to 200 nm. For example, the minimum distance d between the edge of the fifth projection 45 and the edge of the sixth projection 46 can be 50 nm, 100 nm, 150 nm, or 200 nm, and the minimum distance m between the edge of the fourth projection 44 and the edge of the fifth projection 45 can be 50 nm, 100 nm, 150 nm, or 200 nm. The minimum distance between the edge of the fifth projection 45 and the edge of the sixth projection 46 cannot be too large or too small. If the minimum distance between the edge of the fifth projection 45 and the edge of the sixth projection 46 is too small, the manufacturing process will be increased, and if the minimum distance between the edge of the fifth projection 45 and the edge of the sixth projection 46 is too large, the space occupied by the first pole 10 will be increased. In the present application, the minimum distance d between the edge of the fifth projection 45 and the edge of the sixth projection 46 is greater than or equal to 50 nm and less than or equal to 200 nm, so that the complexity of the manufacturing process is not increased, and the space occupied by the first pole 10 is not increased.

[0074] In some optional embodiments, continuing to refer to Figure 4 to 10 , the first active layer 2 includes a metal oxide.

[0075] Optionally, the metal oxide material can be IGZO (indium gallium zinc oxide) or other metal oxides, which are not specifically limited here. Of course, IGZO is an amorphous oxide containing indium, gallium, and zinc, and the carrier mobility is 20-30 times that of amorphous silicon, which can greatly improve the charge rate of the display panel 100 and improve the response speed of the display panel 100.

[0076] In some optional embodiments, referring to Figure 12 and Figure 13 , Figure 12 is a schematic diagram of a plane structure of a display panel provided by the present application, Figure 13 is Figure 12 a sectional view in the direction of E-E' in the figure, the display panel 100 in the embodiment further comprises: the first transistor T1 comprises a first electrode 10, the first electrode 10 is located on the side of the second insulating layer 8 away from the substrate 1, and the first electrode 10 is electrically connected with the first active layer 2; the second transistor T2 comprises a second electrode 9, a second gate 12 and a second active layer 11; the second electrode 9 and the first electrode 10 are arranged in the same layer; the second active layer 11 is located on the side of the substrate 1 close to the second electrode 9, and the second electrode 9 is electrically connected with the second active layer 11 through a via hole; the second gate 12 is located on the side of the second active layer 11 close to the second electrode 9.

[0077] As can be seen from Figure 13 , the second transistor T2 is also schematically illustrated as a top gate, the second active layer 11 of the second transistor T2 is located on the side of the substrate 1, the second gate 12 is located on the side of the second active layer 11 close to the second electrode 9, the second electrode 9 is electrically connected with the second active layer 11 through a via hole, and the first active layer 2 is located on the side of the second gate 12 close to the second electrode 9, that is, in the direction perpendicular to the plane in which the substrate 1 is located, the first active layer 2 is located between the second active layer 11 and the first electrode 10.

[0078] Optionally, the second electrode 9 and the first electrode 10 are arranged in the same layer and can be manufactured through the same process. Optionally, the second transistor T2 also comprises the first insulating layer 7 and the second insulating layer 8, the first insulating layer 7 in the second transistor T2 is arranged in the same layer as the first insulating layer 7 in the first transistor T1, and the second insulating layer 8 in the second transistor T2 is arranged in the same layer as the second insulating layer 8 in the first transistor T1. It should be noted that, because the second transistor T2 can be set as a long-channel transistor, there is no short-channel effect, so the second insulating layer 8 can not be provided with the first opening 81 for the second transistor T2.

[0079] The display panel 100 in the present application comprises two kinds of transistors, for example, metal oxide transistors and low-temperature polysilicon transistors, which are suitable for a wider range of applications.

[0080] Referring to Figure 14 and Figure 15 , Figure 14 is a pixel circuit of a display panel provided by the present application, Figure 15 is Figure 14The pixel circuit 200 includes a reference signal line VREF, a first control signal line S01, a second control signal line S02, and an emission control line EM, a data line DATA, and a power voltage signal line PVDD, and drives the light emitting diode L. The pixel circuit 200 further includes:

[0081] A third transistor M06, a gate of the third transistor M06 is electrically connected with the emission control line EM, a source of the third transistor M06 is electrically connected with a drain of the driving transistor M0, and a drain of the third transistor M06 is electrically connected with the light emitting diode L;

[0082] A fourth transistor M01, a gate of the fourth transistor M01 is electrically connected with the emission control line EM, and a source of the fourth transistor M01 is electrically connected with the power voltage signal line PVDD;

[0083] A fifth transistor M02, a gate of the fifth transistor M02 is electrically connected with the second control signal line S02, a source of the fifth transistor M02 is electrically connected with the data line DATA, and a drain of the fifth transistor M02 is electrically connected with a source of the driving transistor M0;

[0084] A sixth transistor M05, a gate of the sixth transistor M05 is electrically connected with the first control signal line S1, and a source of the sixth transistor M05 is electrically connected with the reference signal line VREF;

[0085] The driving transistor M0, a gate of the driving transistor M0 is electrically connected with a drain of the sixth transistor M05, a source of the driving transistor M0 is electrically connected with a drain of the fourth transistor M01 and a drain of the fifth transistor M02 respectively, and a drain of the driving transistor M0 is electrically connected with a source of the third transistor M06;

[0086] A seventh transistor M04, a gate of the seventh transistor M04 is electrically connected with the second control signal line S2, a source of the seventh transistor M04 is electrically connected with a drain of the driving transistor M0, and a drain of the seventh transistor M042 is electrically connected with a gate of the driving transistor M0;

[0087] An eighth transistor M03, a gate of the eighth transistor M03 is electrically connected with the second control signal line S2, a source of the eighth transistor M03 is electrically connected with the reference signal line VREF, and a drain of the eighth transistor M03 is electrically connected with a drain of the third transistor M06.

[0088] In the embodiment, the sixth transistor M05 and the seventh transistor M04 can adopt the first transistor T1 in the above embodiment, the fourth transistor M01, the fifth transistor M02, the eighth transistor M03, the driving transistor M0 and the third transistor M06 can adopt the second transistor T2 in the above embodiment, and the display panel 100 comprises both the metal oxide transistor and the low-temperature polysilicon transistor, so that the driving performance is improved.

[0089] In some optional embodiments, continuing to refer to Figure 12 and Figure 13 , the second active layer 11 comprises low-temperature polysilicon.

[0090] It can be understood that the low-temperature polysilicon transistor has a faster electron migration rate, and in the embodiment, the second active layer 11 adopts low-temperature polysilicon, so that the electron migration rate of the second transistor T2 is improved.

[0091] In the display panel 100 in the embodiment, the first transistor T1 can be a metal oxide transistor, that is, the first active layer 2 is metal oxide, and the second transistor T2 can be a low-temperature polysilicon transistor, that is, the second active layer 11 is low-temperature polysilicon, and the display panel 100 comprises both the metal oxide transistor and the low-temperature polysilicon transistor, so that the driving performance is improved.

[0092] The embodiment further provides a display device 1000 comprising the display panel 100. Figure 16 , Figure 16 is a plan view of a display device provided by the embodiment. Figure 16 The display device 1000 provided by the embodiment comprises the display panel 100, wherein the display panel is the display panel 100 provided by any one of the above embodiments. Figure 16 The embodiment only takes a mobile phone as an example to describe the display device 1000, and it can be understood that the display device provided by the embodiment can be a computer, a television, a vehicle-mounted display panel or other display devices having a display function, and the embodiment does not specifically limit this. The display device provided by the embodiment has the beneficial effects of the display panel provided by the embodiment, and specific descriptions of the array substrate can be referred to the above embodiments, and the embodiment will not be described here.

[0093] It can be known from the above embodiments that the display panel and the display device provided by the embodiment at least have the following beneficial effects:

[0094] The display panel of the present application comprises a first transistor disposed on a substrate, the first transistor comprising a first gate and a first active layer, a part of the first active layer overlapping the first gate in a direction perpendicular to a plane where the substrate is located is a channel region, the first active layer comprises a first insulating layer and a second insulating layer on a side of the first active layer away from the substrate, the second insulating layer contains hydrogen, the second insulating layer has a first opening, a normal projection of the first opening on the plane where the substrate is located overlaps a normal projection of the channel region on the plane where the substrate is located, in the present application, the second insulating layer has an opening region, that is, the second insulating layer corresponding to the channel region is partially removed or the second insulating layer corresponding to the channel region is completely removed, so as to reduce the total volume of the second insulating layer and the total content of hydrogen, so as to reduce the problem of uneven distribution of threshold voltage Vth and current Ion of the transistor caused by uneven hydrogen content, improve the stability of the transistor performance, and thus improve the display performance of the display panel.

[0095] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, but not for limiting the scope of the present application. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A display panel, characterized by, Comprising: a substrate substrate; a first transistor, the first transistor comprising a first gate and a first active layer; the first gate is located on one side of the substrate substrate; the first active layer is located on one side of the substrate substrate, the first active layer comprises a channel region, in a direction perpendicular to a plane where the substrate substrate is located, a portion of the first active layer overlapping with the first gate is the channel region; a first insulating layer is located on one side of the first active layer away from the substrate substrate; a second insulating layer is located on one side of the first insulating layer away from the substrate substrate, the second insulating layer contains hydrogen; the second insulating layer comprises a first opening, in a direction perpendicular to a plane where the substrate substrate is located, the first opening overlaps with the channel region; the first transistor comprises a first electrode, the first electrode is located on one side of the second insulating layer away from the substrate substrate, and the first electrode is electrically connected with the first active layer; a first projection of the second insulating layer in the plane where the substrate substrate is located is a first projection, a second projection of the first electrode in the plane where the substrate substrate is located is a second projection, the first projection covers the second projection, and a minimum distance between edges of the first projection and edges of the second projection is d1, d1 is not greater than 2 μm; a third projection of the first gate in the plane where the substrate substrate is located is a third projection, the first projection and the third projection do not overlap, and a minimum distance between edges of the first projection and edges of the third projection is d2, d2 is greater than 3 μm.

2. The display panel of claim 1, wherein, In a direction perpendicular to a plane where the substrate substrate is located, the second insulating layer does not overlap with the channel region.

3. The display panel of claim 2, wherein, A thickness of the second insulating layer is less than or equal to 500 angstroms.

4. The display panel of claim 1, wherein: the first electrode comprises a first surface and a second surface arranged oppositely, and a side surface, the first surface is located on a side of the second surface close to the substrate substrate, the side surface is connected with the first surface and the second surface respectively, and an included angle between the first surface and the side surface is an acute angle.

5. The display panel of claim 1, wherein, A material of the second insulating layer comprises SiNx.

6. The display panel of claim 5, wherein, In a direction from the substrate substrate to the second insulating layer, the first electrode comprises a first metal, a second metal and a third metal stacked, a fourth projection of the third metal in the plane where the substrate substrate is located is a fourth projection, a fifth projection of the second metal in the plane where the substrate substrate is located is a fifth projection, a sixth projection of the first metal in the plane where the substrate substrate is located is a sixth projection, the fifth projection covers the fourth projection, the sixth projection covers the fifth projection, and a minimum distance between edges of the fifth projection and edges of the sixth projection is d, wherein 50 nm≤d≤200 nm.

7. The display panel of claim 1, wherein, The first active layer comprises a metal oxide.

8. The display panel of claim 1, wherein, Further comprising: the first transistor comprises a first electrode, the first electrode is located on one side of the second insulating layer away from the substrate substrate, and the first electrode is electrically connected with the first active layer; a second transistor, the second transistor comprising a second electrode, a second gate and a second active layer; The second electrode and the first electrode are arranged in the same layer. The second active layer is located on one side of the substrate close to the second electrode, and the second electrode is electrically connected with the second active layer through a via hole. The second gate electrode is located on one side of the second active layer close to the second electrode.

9. The display panel of claim 8, wherein, The second active layer comprises low-temperature polysilicon.

10. A display device, characterized by comprising: The display panel comprises the display panel according to any one of claims 1-9.

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