Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising: a first side and a second side for display, comprising: a base substrate; a display area comprising a first display area and a second display area, the first display area comprising a plurality of pixel unit groups, each of the plurality of pixel unit groups comprising a plurality of first pixel units, each of the plurality of first pixel units comprising a pixel area and an opening area; a plurality of first power lines located in the pixel area; a shielding layer comprising a hollow area and a shielding area; for a pixel unit group, the opening area of ​​each first pixel unit at least partially overlaps with the shielding area of ​​the shielding layer, the opening area of ​​at least one first pixel unit comprises a first shielding connection portion at least partially overlaps with the shielding area of ​​the shielding layer, and the shielding layer is connected to at least one first power line of the plurality of first power lines via the first shielding connection portion. The display substrate can connect a DC signal to the shielding layer without reducing pixel density, thereby preventing the shielding layer from being in a floating state.

Description

[0001] This application is a divisional application of the invention patent application with the application date of June 30, 2020, application number 202010623663.4, and invention name “Display substrate and display device” Technical Field

[0002] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0003] Based on the design of the under-screen camera, the display panel usually includes a high pixel density (Pixels Per Inch, PPI) area and a low PPI area. However, the light transmittance of the low PPI area of ​​the usual display panel is low, which is not conducive to improving the display effect of the camera in the imaging area. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side opposite to the first side, comprising: a base substrate; a display area, arranged on the base substrate, comprising a first display area and a second display area at least partially surrounding the first display area, wherein the first display area allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate for sensing, the first display area comprising a plurality of pixel unit groups arranged at intervals, each of the plurality of pixel unit groups comprising a plurality of first pixel units, each of the plurality of first pixel units comprising a pixel area and an opening area; a plurality of first power lines, located in the pixel area and configured to be connected to the plurality of pixel unit groups to provide a first power supply voltage to the plurality of pixel unit groups; a shielding layer, arranged in the pixel area; on the substrate, and located on the side of the first power line close to the substrate, including a hollow area and a blocking area; for a pixel unit group, the opening area of ​​each first pixel unit at least partially overlaps with the blocking area of ​​the blocking layer, the opening area of ​​at least one first pixel unit includes a first blocking connection portion, which at least partially overlaps with the blocking area of ​​the blocking layer, and the blocking layer is connected to at least one first power line of the multiple first power lines through the first blocking connection portion to receive the first power supply voltage; the multiple first power lines are located on the side of the first blocking connection portion away from the substrate, the blocking layer is located on the side of the first blocking connection portion close to the substrate, and the first blocking connection portion is located between the blocking layer and the multiple first power lines.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the blocking layer is connected to the first blocking connection portion through a first via hole, and the first blocking connection portion is connected to the at least one first power line through a second via hole.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes a first insulating layer, a second insulating layer and a third insulating layer, wherein the first insulating layer is located between the blocking layer and the first blocking connection portion, the second insulating layer is located between the first insulating layer and the first blocking layer connection portion, and the third insulating layer is located between the first blocking connection portion and the plurality of first power lines; or, the second insulating layer is located between the first blocking connection portion and the plurality of first power lines, and the third insulating layer is located between the second insulating layer and the plurality of first power lines, the blocking layer is connected to the first blocking connection portion through a first via hole passing through the first insulating layer, and the first blocking connection portion is connected to the at least one first power line through a second via hole passing through the second insulating layer and the third insulating layer; or, the blocking layer is connected to the first blocking connection portion through a first via hole passing through the first insulating layer and the second insulating layer, and the first blocking connection portion is connected to the at least one first power line through a second via hole passing through the third insulating layer.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projections of the first via and the second via on the base substrate do not overlap; the first power line includes a protrusion, the orthographic projection of the second via on the base substrate overlaps with the orthographic projection of the protrusion on the base substrate, and the orthographic projection of the first via on the base substrate overlaps with the orthographic projection of the first power line on the base substrate.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, adjacent pixel unit groups are connected by wiring, and the orthographic projections of the multiple pixel unit groups and the wiring on the base substrate fall within the orthographic projection of the shielding area of ​​the shielding layer on the base substrate.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second display area includes a plurality of second pixel units arranged in an array and a plurality of second power lines, each of the plurality of second pixel units includes a pixel area and an opening area; the plurality of second power lines are configured to be connected to the plurality of second pixel units to provide a second power supply voltage to the plurality of second pixel units, and the second power supply voltage is the same as the first power supply voltage; for one second pixel unit, the opening area of ​​each second pixel unit at least partially overlaps with the blocking area of ​​the blocking layer, and the opening area of ​​at least one second pixel unit includes a second blocking connection portion, and the second blocking connection portion at least partially overlaps with the blocking area of ​​the blocking layer.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the orthographic projection of the second display area on the base substrate falls within the orthographic projection of the blocking area of ​​the blocking layer on the base substrate.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the plurality of first pixel units and the plurality of second pixel units includes a pixel driving circuit and a light-emitting device, and the pixel driving circuit is configured to drive the light-emitting device to emit light.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor and a storage capacitor; the active layers of the first reset transistor, the compensation transistor, the second light-emitting control transistor and the second reset transistor are located in a first semiconductor layer extending along a first direction, the active layers of the data writing transistor and the first light-emitting control transistor are located in a second semiconductor layer extending along a second direction, the first semiconductor layer and the second semiconductor layer are connected and formed as one piece through the active layer of the driving transistor, the active layer of the driving transistor is located on an imaginary line of the active layer of the first reset transistor in the first direction, the active layers of the compensation transistor and the data writing transistor are respectively located on both sides of the active layer of the driving transistor, and are located on a side of the active layer of the driving transistor close to the active layer of the first reset transistor. The active layers of the second light-emitting control transistor and the first light-emitting control transistor are respectively located on both sides of the active layer of the driving transistor and on the side of the active layer of the driving transistor away from the active layer of the first reset transistor. The active layer of the second reset transistor is located on the side of the active layer of the second light-emitting control transistor away from the active layer of the compensation transistor. The compensation transistor includes a first gate extending along the first direction and a second gate extending along the second direction. The second gate and the gate of the second light-emitting control transistor and the gate of the second reset transistor extending along the second direction are arranged side by side in the first direction. The gate of the data writing transistor and the gate of the first light-emitting control transistor extend along the second direction and are arranged side by side in the first direction. The gate of the first reset transistor and the gate of the driving transistor extend along the second direction and are arranged side by side in the first direction. The gate of the driving transistor is formed integrally with the first plate of the storage capacitor.

[0013] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a gate line, a light-emitting control signal line, a first reset signal line and a second reset signal line extending along the second direction, the gate of the first reset transistor and the first reset signal line are connected and formed as one body, the second gate of the compensation transistor and the gate of the data writing transistor are connected and formed as one body with the gate line, the gate of the second light-emitting control transistor and the gate of the first light-emitting control transistor are connected and formed as one body with the light-emitting control signal line, and the gate of the second reset transistor is connected and formed as one body with the second reset signal line.

[0014] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a data line, wherein the data line is connected to the active layer of the data writing transistor and is configured to provide a data signal, the orthographic projection of the first power line on the base substrate at least partially overlaps with the orthographic projections of the active layer of the first reset transistor and the active layer of the driving transistor on the base substrate, and the orthographic projection of the data line on the base substrate is located on a side of the orthographic projection of the second semiconductor layer on the base substrate away from the orthographic projection of the first power line on the base substrate.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel driving circuit further includes a first transfer electrode, which is connected to the active layer of the second light-emitting control transistor, the active layer of the second reset transistor, and the first pole of the light-emitting device through a via, and the orthographic projection of the first transfer electrode on the base substrate is located between the orthographic projections of the active layer of the second reset transistor and the active layer of the driving transistor on the base substrate.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, for each of the multiple second pixel units, the orthographic projection of the second blocking connection portion on the base substrate is located between the orthographic projection of the active layer of the second reset transistor on the base substrate and the orthographic projection of the second power line on the base substrate, and at least partially overlaps with the orthographic projection of the second power line on the base substrate.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, for each pixel unit group, the first blocking connection portion is located between two adjacent first pixel units in each pixel unit group in the first direction.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the first blocking connection portion on the base substrate is located between the orthographic projection of the active layer of the second reset transistor on the base substrate and the orthographic projection of the first power line on the base substrate, and at least partially overlaps with the orthographic projection of the first power line on the base substrate.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first shielding connection portion is located at both ends of each pixel unit group, and is connected to at least one of the plurality of first power lines corresponding to each pixel unit group.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first shielding connection portion is located at one end of each pixel unit group and is connected to at least one of the plurality of first power lines corresponding to the pixel unit group.

[0021] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a fourth insulating layer, a first conductive layer, a second conductive layer and a third conductive layer; the first conductive layer includes the gate line, the second conductive layer includes the second plate of the storage capacitor, and the third conductive layer includes the first power line. In a direction perpendicular to the base substrate, the fourth insulating layer is located between the blocking layer and the active layer of the transistor, the first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the gate line and the second conductive layer, and the third insulating layer is located between the second plate of the storage capacitor and the third conductive layer.

[0022] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first blocking connection portion is located in the first conductive layer or the second conductive layer.

[0023] At least one embodiment of the present disclosure further provides a display device, comprising the display substrate and a sensor provided by any embodiment of the present disclosure, wherein the sensor is arranged on the second side of the display substrate, and the sensor is configured to receive light from the first side of the display substrate; the orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0025] Figure 1A A schematic plan view of a display substrate provided in at least one embodiment of the present disclosure;

[0026] Figure 1B A partially enlarged schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0027] Figure 1C A partially enlarged schematic diagram of a display substrate provided by at least another embodiment of the present disclosure;

[0028] Figure 1D For the Figure 1A A schematic cross-sectional view of line B1-B2 shown in FIG;

[0029] Figure 2 A schematic diagram of an arrangement of pixel units in a second display area provided by at least one embodiment of the present disclosure;

[0030] Figure 3 A schematic diagram of a first display area of ​​a display panel provided in at least one embodiment of the present disclosure;

[0031] Figure 4 A schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 5 A schematic diagram of a pixel driving circuit provided in at least one embodiment of the present disclosure;

[0033] Figure 6A for Figure 5 A schematic diagram of a stacked structure of a pixel driving circuit shown in ;

[0034] Figure 6B for Figure 5 Another schematic diagram of a stacked structure of a pixel driving circuit shown in ;

[0035] Figure 7 A schematic cross-sectional view along line AA' provided in at least one embodiment of the present disclosure;

[0036] Figure 8 for Figure 6A A plan view of a semiconductor pattern of a display substrate is shown;

[0037] Figure 9 for Figure 6A A plan view of the first conductive layer of the display substrate is shown;

[0038] Figure 10 for Figure 6A A plan view of the second conductive layer of the display substrate is shown;

[0039] Figure 11 for Figure 6A A plan view of the third conductive layer of the display substrate shown;

[0040] Figure 12AA schematic diagram of an example of a display substrate provided by at least one embodiment of the present disclosure;

[0041] Figure 12B for Figure 12A A plan view of a shielding area LS1 of a shielding layer LS of a display substrate is shown;

[0042] Figure 12C for Figure 12A A plan view of a semiconductor pattern of a display substrate is shown;

[0043] Figure 12D for Figure 12A A plan view of the first conductive layer of the display substrate is shown;

[0044] Figure 12E for Figure 12A A plan view of the second conductive layer of the display substrate is shown;

[0045] Figure 12F for Figure 12A A plan view of the third conductive layer of the display substrate shown;

[0046] Figure 13A A schematic diagram of an example of another display substrate provided in at least one embodiment of the present disclosure;

[0047] Figure 13B for Figure 13A A plan view of a shielding area LS1 of a shielding layer LS of a display substrate is shown;

[0048] Figure 13C for Figure 13A A plan view of a semiconductor pattern of a display substrate is shown;

[0049] Figure 13D for Figure 13A A plan view of the first conductive layer of the display substrate is shown;

[0050] Figure 13E for Figure 13A A plan view of the second conductive layer of the display substrate is shown;

[0051] Figure 13F for Figure 13A A plan view of the third conductive layer of the display substrate shown;

[0052] Figure 14A A schematic diagram of an example of another display substrate provided for at least one embodiment of the present disclosure;

[0053] Figure 14B for Figure 14A A plan view of a shielding area LS1 of a shielding layer LS of a display substrate is shown;

[0054] Figure 14C for Figure 14A A plan view of a semiconductor pattern of a display substrate is shown;

[0055] Figure 14D for Figure 14A A plan view of the first conductive layer of the display substrate is shown;

[0056] Figure 14E for Figure 14A A plan view of the second conductive layer of the display substrate is shown;

[0057] Figure 14F for Figure 14A A plan view of the third conductive layer of the display substrate shown;

[0058] Figure 15A A schematic diagram of an example of another display substrate provided for at least one embodiment of the present disclosure;

[0059] Figure 15B for Figure 15A A plan view of a shielding area LS1 of a shielding layer LS of a display substrate is shown;

[0060] Figure 15C for Figure 15A A plan view of a semiconductor pattern of a display substrate is shown;

[0061] Figure 15D for Figure 15A A plan view of the first conductive layer of the display substrate is shown;

[0062] Figure 15E for Figure 15A A plan view of the second conductive layer of the display substrate is shown;

[0063] Figure 15F for Figure 15A A plan view of the third conductive layer of the display substrate shown;

[0064] Figure 16 A schematic diagram of a display device provided in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0066] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0067] OLED (Organic light-emitting diode) display technology is highly competitive in the display market due to its advantages such as wide viewing angle, high contrast, fast response, low power consumption, foldability, and flexibility. With the widespread development and in-depth application of OLED technology, the demand for displays with a high screen-to-body ratio is growing stronger. Under-display camera technology places the front camera below the screen, eliminating the notch area required for the front camera, increasing the screen-to-body ratio and providing a better viewing experience.

[0068] In order to allow more light to pass through the display panel and reach the front camera, it is necessary to reduce the PPI of the screen's translucent display area, that is, to reduce the pixel density. However, there are a large number of slits between the pixel circuit lines and the signal lines between pixels. When light passes through these slits, diffraction and interference will occur, resulting in uneven brightness when the light reaches the camera, causing glare (excessive brightness in a certain part of the field of view or excessive brightness changes before and after), reducing the visibility of objects, reducing the camera imaging quality, and easily causing visual fatigue.

[0069] Currently, one solution is to add a metal layer as a shielding layer to block the pixel circuit and wiring position to prevent light from passing through these slits and causing interference. However, these metal layers are in a floating state and will interfere with the signal of the pixel circuit, affecting the display effect. Therefore, it is necessary to pass a DC signal through these metal layers to stabilize the voltage. However, if the connection is made directly from the pixel circuit, space is required to place the connection hole, which will increase the pixel size and reduce the resolution of the screen. If the connection is only made from the IC (Integrated chip) end, it will cause a large voltage drop in the wiring, affecting the display quality.

[0070] At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side opposite to the first side, comprising: a base substrate; a display area, disposed on the base substrate, comprising a first display area and a second display area at least partially surrounding the first display area, wherein the first display area allows light from the first side of the display substrate to at least partially transmit to the second side of the display substrate for sensing, the first display area comprising a plurality of pixel unit groups arranged at intervals, each of the plurality of pixel unit groups comprising a plurality of first pixel units, each of the plurality of first pixel units comprising a pixel area and an opening area; a plurality of first power supply lines, located in the pixel area and configured to be connected to the plurality of pixel unit groups to provide a first power supply to the plurality of pixel unit groups voltage; a blocking layer, arranged on the base substrate and located on the side of the first power line close to the base substrate, including a hollow area and a blocking area; for a pixel unit group, the opening area of ​​each first pixel unit at least partially overlaps with the blocking area of ​​the blocking layer, the opening area of ​​at least one first pixel unit includes a first blocking connection portion, which at least partially overlaps with the blocking area of ​​the blocking layer, and the blocking layer is connected to at least one first power line of the plurality of first power lines through the first blocking connection portion to receive the first power supply voltage; the plurality of first power lines are located on the side of the first blocking connection portion away from the base substrate, the blocking layer is located on the side of the first blocking connection portion close to the base substrate, and the first blocking connection portion is located between the blocking layer and the plurality of first power lines.

[0071] The display substrate provided by the embodiment of the present disclosure can connect a DC signal to the shielding layer without reducing the pixel density, thereby preventing the shielding layer from being in a floating state and preventing the signal jump of the shielding layer from interfering with the pixel driving circuit, while reducing the voltage drop of the first power line and improving the display quality of the display panel.

[0072] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0073] Figure 1A A schematic plan view of a display substrate provided in at least one embodiment of the present disclosure; Figure 1B A partially enlarged schematic diagram of a display substrate provided by at least one embodiment of the present disclosure; Figure 1C A partially enlarged schematic diagram of a display substrate provided by at least another embodiment of the present disclosure; Figure 1D For the Figure 1A Schematic cross-section along the midline B1-B2.

[0074] For example, Figure 1AAs shown, at least one embodiment of the present disclosure provides a display substrate 1 including a base substrate 100 and a display area. The display area is disposed on the base substrate 100 and includes a first display area 10 (e.g., a light-transmitting display area) and a second display area 20 (e.g., a normal display area). The display substrate 1 may further include a peripheral area 30 that surrounds (e.g., partially surrounds) the display area. The second display area 20 surrounds (e.g., partially surrounds) the first display area 10.

[0075] For example, the display substrate 1 provided in at least one embodiment of the present disclosure may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the embodiments of the present disclosure do not limit the specific type of the display substrate.

[0076] For example, Figure 1D As shown, the first display area 10 is a light-transmitting display area, that is, it allows light from the first side S1 (e.g., the display side) of the display substrate 1 to be at least partially transmitted to the second side S2 (e.g., the non-display side) of the display substrate 1, that is, the incident light from the display side is transmitted through the first display area 10 to reach the non-display side of the display substrate 1. A sensor 192 can also be provided on the second side S2 of the display substrate 1 to receive the transmitted light, thereby realizing corresponding functions (e.g., imaging, infrared sensing, distance sensing, etc.). For example, the sensor 192 is provided on the second side S2 of the display substrate 1, and the orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10, and is configured to receive and process light from the first side S1 of the display substrate 1. The light from the first side S1 of the display substrate 1 can be collimated light along the normal direction of the display substrate 1 (e.g., the Z1 direction) or non-collimated light.

[0077] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 can be implemented in the form of a chip, etc. The sensor 192 is disposed on the second side S2 (the side facing away from the user) of the display substrate 1. The sensor 192 at least partially overlaps with the first display area 10 in the normal direction of the display surface of the display substrate.

[0078] For example, sensor 192 can be an image sensor, capable of capturing images of the external environment facing the light-collecting surface of sensor 192. For example, it can be a CMOS image sensor or a CCD image sensor. Sensor 192 can also be an infrared sensor, a distance sensor, or the like. Sensor 192 can be used to implement a camera in a mobile terminal such as a mobile phone or notebook, and can further include optical devices such as lenses, reflectors, or optical waveguides to modulate the optical path as needed. The embodiments of the present disclosure do not limit the type, function, or configuration of sensor 192.

[0079] The sensor 192 is mounted on the first side S2 of the display substrate using double-sided tape or other methods. The orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10, and is configured to receive light from the first side S1. Thus, the first display area 10 facilitates the placement of the sensor 192 while providing display.

[0080] For example, Figure 1B as well as Figure 1C As shown, the first display area 10 includes a first sub-pixel array (composed of gray boxes in the first display area 10), and the first sub-pixel array includes a plurality of pixel unit groups P1 (gray boxes in the first display area 10) arranged in a first direction Y1 and a second direction X1 intersecting the first direction Y1. Each of the plurality of pixel unit groups P1 includes at least one first pixel unit (e.g., a plurality of first pixel units) (described in detail later). The first pixel unit includes a first light-emitting device and a first pixel driving circuit directly connected to each other, and the first pixel driving circuit is configured to drive the first light-emitting device to emit light. The first light-emitting device and the first pixel driving circuit are located in the same pixel area and are not separated from each other in position.

[0081] It should be noted that the first direction Y1 and the second direction X1 may or may not intersect perpendicularly. For example, the acute angle at which the first direction Y1 and the second direction X1 intersect each other may be within a range of less than or equal to 10° and greater than or equal to 45°. The drawings of the embodiments of the present disclosure illustrate the perpendicular intersection of the first direction Y1 and the second direction X1 as an example.

[0082] There are gaps between the plurality of pixel unit groups P1 allowing light to pass through, i.e., blank areas in the first display area 10 , allowing incident light from the first side S1 to be transmitted through the gaps between adjacent pixel unit groups P1 to ensure the light transmittance of the first display area 10 .

[0083] For example, Figure 1B As shown, the plurality of first pixel unit groups P1 are arranged in a staggered arrangement between two adjacent columns. That is, the pixel unit groups P1 in the first column and the pixel unit groups P1 in the second column are staggered in the second direction X1 and are distributed in different rows. For example, the pixel unit groups P1 in adjacent columns are in different rows.

[0084] For example, Figure 1C As shown, the plurality of pixel unit groups P1 are arranged in multiple rows and columns, that is, the pixel unit groups P1 in the first column are spaced and adjacent to the pixel unit groups P1 in the second column in the second direction X1.

[0085] For example, Figure 1B as well as Figure 1CAs shown, the second display area 20 includes a second sub-pixel array (composed of white boxes in the second display area 20), and the second sub-pixel array includes a plurality of second pixel units C (white boxes in the second display area 20). Each of the plurality of second pixel units C includes a second light-emitting device and a second pixel driving circuit directly connected to each other, and the second pixel driving circuit is configured to drive the second light-emitting device to emit light. The second light-emitting device and the second pixel driving circuit are located in the same pixel area and are not separated from each other in position. For example, the arrangement of the second pixel units in the second display area 20 is as follows Figure 2 As shown,

[0086] For example, the pixel density of the second display area is greater than the pixel density of the first display area. Figure 1B as well as Figure 1C As shown, the arrangement density of the pixel unit group P1 in the first display area 10 is lower than the arrangement density of the second pixel units C in the second display area 20. In other words, the resolution of the first display area 10 is set lower than that of the second display area 20 to leave space for light to pass through, that is, the density of pixels arranged for display in the first display area 10 is lower than that of the second display area 20.

[0087] Figure 2 A schematic diagram of the arrangement of pixel units in a second display area provided in at least one embodiment of the present disclosure. Figure 3 Schematic diagram of the first display area of ​​the display panel provided in at least one embodiment of the present disclosure. Figure 2 and Figure 3 As shown, the first display area 10 and the second display area 20 of the display substrate respectively include a plurality of pixel unit groups P1, for example, Figure 2 and Figure 3 It is only schematically shown that each pixel unit group P1 includes 4 pixel units P0. For example, the 4 pixel units P0 are the first sub-pixel unit 101, the second sub-pixel unit 102, the third sub-pixel unit 103 and the fourth sub-pixel unit 104. The embodiments of the present disclosure are not limited to this.

[0088] It should be noted that each pixel unit group P1 may also include two pixel units P0 (such as Figures 14A-14E As shown) or 3 pixel units P0 (as shown Figures 15A-15E The embodiments of the present disclosure are not limited to this.

[0089] For example, in Figure 14A In the example shown, a pixel group may further include two sub-pixels, for example, a first sub-pixel 101 and a second sub-pixel 102. For example, the first sub-pixel 101 is a red sub-pixel and the second sub-pixel 102 is a green sub-pixel. Figure 15AIn the embodiment shown, a first pixel group P1 may further include three sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel. For example, the three sub-pixels are located in a row; for example, Figure 12A In the example shown, a pixel group may also include four sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, the third sub-pixel 103 is a blue sub-pixel, and the fourth sub-pixel 104 is a green sub-pixel. In other embodiments, the pixel group may also use pixel units of other colors. Of course, in other embodiments, the arrangement of the multiple sub-pixels P0 in the display panel is not limited to Figure 2 and Figure 3 The embodiments of the present disclosure are not limited to this.

[0090] For example, Figure 2 As shown, in the second display area 20 , the pixel units P0 are evenly and regularly arranged, which will not be described in detail here.

[0091] For example, Figure 3 As shown, the display substrate also includes a gate line 113 and a data line 313. The gate line 113 and the data line 313 are insulated from each other. Each gate line 113 connects a row of sub-pixels, and each data line 313 connects a column of sub-pixels. For example, the gate line 113 is configured to provide a scan signal to a row of sub-pixels. The data line 313 is configured to provide a data signal to a column of sub-pixels.

[0092] For example, Figure 3 As shown, the data line 313 includes a first data line DL1. The first data line DL1 is at least located in the first display area 10. For example, the first data line DL1 extends from the first display area 10 to the second display area 20. Figure 3 As shown, the gate lines 113 include a first gate line GL1 , and the first gate line GL1 extends from the second display area 20 to the first display area 10 .

[0093] For clarity and brevity, Figure 3 The connection relationship between adjacent pixel groups P1 in the first display area 10 is only schematically shown and does not constitute a limitation to the present disclosure. Figure 4 A schematic diagram of a display substrate provided in at least one embodiment of the present disclosure. Figure 4 As shown, the display substrate further includes a first power line VDD1 , and is configured to be connected to the plurality of pixel unit groups P1 to provide a first power voltage to the plurality of pixel unit groups P1 .

[0094] For example, Figure 4 As shown, the display substrate further includes a shielding layer LS, which is disposed on the base substrate 100 and is located on the side of the first power line VDD1 close to the base substrate 100, including a hollow area LS2 and a shielding area LS1. For example, the hollow area LS2 corresponds to Figure 3 As shown in FIG, the light-transmitting region R0 between adjacent first pixel unit groups. Figure 3 and 4 As shown, the light-transmitting region R0 is surrounded by two adjacent first gate lines GL1 and two adjacent first data lines DL1 , but the present invention is not limited thereto.

[0095] For example, the first display area 10 includes a plurality of light-transmitting regions R0; the light-transmitting regions R0 are located between adjacent first pixel groups P1. The light-transmitting regions R0 are transparent to ambient light. For example, the light-transmitting regions R0 may include a base substrate and a transparent insulating layer located on the base substrate. The light-transmitting regions R0 do not have light-blocking structures, such as metal traces. For example, the light-transmitting regions R0 are located within the region enclosed by four adjacent pixel unit groups P1 and the traces connecting the pixel unit groups P1, but are not limited thereto.

[0096] For example, Figure 4 As shown, adjacent pixel unit groups are connected via wiring (e.g., a first data line DL1, a first power line 311, a gate line GL1, a first reset signal line 111, a second reset signal line 112, a light-emitting control signal line 110, and an initialization signal line 210). For example, the orthographic projections of the plurality of pixel unit groups P0 and the wiring on the base substrate 100 fall within the orthographic projection of the shielding area LS1 of the shielding layer LS on the base substrate 100. That is, the shielding area LS1 shields a large number of slits between the wiring connecting the first pixel unit groups and between the internal connections of the first pixel unit groups, thereby avoiding diffraction and interference caused when light passes through these slits, and avoiding glare caused by uneven brightness when the light reaches the camera.

[0097] For example, in the embodiments of the present disclosure, Figure 6A As shown, each of the plurality of first pixel units P0 includes a pixel area A11 (i.e., a region of transistors, capacitors, and wiring in the first pixel unit, for example, the plurality of power lines 311 (for example, for the first pixel unit P0, the power line 311 is the first power line VDD1, for the second pixel unit C, the power line 311 is the second power line VDD2, the following embodiments are the same and will not be repeated) located in the pixel area A11 and an opening area A12. For example, the opening area is Figure 6B The area obtained by reducing the size of the first pixel unit P0 shown in FIG. Figure 6BThe pixel driving circuit line width, aspect ratio of each transistor, size of the capacitor, size of the connection hole and the centralized placement of the lines shown in FIG are such that the first pixel unit P0 has an open area A12 (as shown in FIG. Figure 6A ), thereby improving the light transmittance of the display panel. For example, in the embodiment of the present disclosure, the pixel area A11 is centrally placed above the pixel unit group P0 (i.e., the solid line rectangular frame) to reduce the space occupied by the drive circuit while maintaining the pixel resolution. Therefore, a portion of space (i.e., the opening area A12) can be left free for placing the first shielding connection portion SP1 and the connection holes V1 / V2 that connect the shielding layer LS to the first power line 311. A specific comparison diagram of a normal pixel unit and a pixel unit after size reduction is shown in FIG. Figure 6B and Figure 6A shown.

[0098] For example, Figure 6A The size of the pixel driving circuit in (i.e. the size of the pixel driving circuit after reduction) is Figure 6B The size of the pixel driver circuit shown in the figure (i.e., the size of the pixel driver circuit before reduction) can be one-fourth of the size shown in the figure. Of course, it can also be one-sixth, one-half, etc., as long as the corresponding functions can be achieved. The embodiments of the present disclosure do not limit this. For example, in some examples, for an FHD resolution under-screen camera screen, the size of the pixel driver circuit can be compressed to the QHD level while maintaining the FHD level pixel resolution. Therefore, some space can be left to place the shielding connection portion LS2 and the connection hole connected to the shielding layer LS.

[0099] In the above-mentioned embodiment of the present disclosure, reducing the size of the pixel driving circuit of the first pixel unit can facilitate the transmission of light, and at the same time facilitate the connection between the shielding layer and the first power line or other power lines without changing the pixel resolution, so that a DC signal can be connected to the shielding layer without reducing the pixel density, thereby preventing the shielding layer from being in a floating state and causing signal interference to the pixel driving circuit, reducing the voltage drop of the first power line, and improving the display quality of the display panel.

[0100] To ensure uniform etching of the shielding layer, a shielding layer is also placed beneath the pixel circuits in the normal display area. For example, the orthographic projection of the second display area 20 on the base substrate 100 falls within the orthographic projection of the shielding region LS2 of the shielding layer LS on the base substrate 100. For example, since the second display area 20 does not include the light-transmitting region R0, the portion of the shielding layer LS corresponding to the second display area 20 can be solid, i.e., without any hollowed-out areas, thereby shielding the gaps between the individual pixel driver circuits in the second display area 20 and the gaps between the wiring connecting the individual pixel driver circuits.

[0101] Since, a normal pixel driving circuit (eg, Figure 6B The pixel driving circuit shown in FIG is relatively compact, and the size occupied by the driving circuit wiring is equal to the pixel density, so there is no remaining space for placing the shielding connection part and the connection hole connected to the shielding layer LS.

[0102] In order to ensure that the pixel density remains unchanged, the pixel driving circuit in the second display area 20 adopts the same structure as the pixel driving circuit in the first display area 10, that is, it also adopts Figure 6A Structure and dimensions shown.

[0103] For example, for the second display area 20, if Figure 1B and Figure 1C As shown, the second display area 20 includes a plurality of second pixel units C arranged in an array and a plurality of second power lines VDD2. The structure of each of the plurality of second pixel units C is as shown in FIG. Figure 6A As shown, for example, it includes a pixel area A11 and an opening area A12.

[0104] For example, a plurality of second power lines VDD2 are configured to be connected to a plurality of second pixel cells C to provide a second power voltage to the plurality of second pixel cells C. For example, the second power voltage is the same as the first power voltage. For example, the plurality of second power lines VDD2 extend along the second direction X1, and one second power line VDD2 provides the second power voltage to a column of second pixel cells C.

[0105] It should be noted that, in order to distinguish the different areas where the power line 311 is located, the power line 311 located in the first display area 10 is called the first power line VDD1, and the power line 311 located in the second display area 20 is called the second power line VDD2. The signals provided by the two are the same, that is, the first power supply voltage is the same as the second power supply voltage, and there is no essential difference.

[0106] For example, for a second pixel unit C, the opening area A12 of each second pixel unit C at least partially overlaps with the blocking area LS1 of the blocking layer LS, that is, the second pixel unit C adopts the reduced size. Figure 6A After the pixel structure shown in FIG, an opening area is left to facilitate the connection between the shielding layer LS and the second power line VDD2, so as to provide a DC signal to the shielding layer LS and prevent the shielding layer LS from floating.

[0107] For example, the opening area A12 of at least one second pixel unit C includes a second blocking connection portion SP2, the second blocking connection portion SP2 at least partially overlaps with the blocking area LS2 of the blocking layer LS, and the blocking layer LS is connected to at least one of the multiple second power lines VDD2 through the second blocking connection portion SP2 to receive the second power supply voltage, thereby providing a DC signal to the blocking layer LS to avoid floating of the blocking layer LS.

[0108] Figure 7 A schematic cross-sectional view taken along line AA' is provided for at least one embodiment of the present disclosure. The following description will be made by taking the first pixel unit P0 as an example, and the embodiments of the present disclosure are not limited thereto.

[0109] For example, Figure 6A and Figure 7 As shown, the shielding layer LS (eg, the shielding area LS1 thereof) is connected to the first shielding connection portion SP1 through a first via hole V1, and the first shielding connection portion SP1 is connected to at least one first power line VDD1 through a second via hole V2.

[0110] For example, Figure 7 As shown, the display substrate further includes a first insulating layer G11, a second insulating layer G12, a third insulating layer ILD and a fourth insulating layer G10. For example, the first insulating layer G11 is located between the shielding layer LS (eg, its shielding area LS1) and the first shielding layer connecting portion SP1.

[0111] For example, Figure 7 As shown, the second insulating layer G12 is located between the first insulating layer G11 and the first shielding connection portion SP1, and the third insulating layer ILD is located between the first shielding connection portion SP1 and the multiple first power lines VDD1; or, the second insulating layer G12 is located between the first shielding connection portion SP1 and the multiple first power lines VDD1, and the third insulating layer ILD is located between the second insulating layer G12 and the multiple first power lines VDD1. Figure 7 The positional relationship of the second insulating layer G12 is not specifically shown in the figure and may be determined according to actual conditions. The embodiments of the present disclosure do not limit this.

[0112] For example, in some examples, the shielding layer LS is connected to the first shielding connection portion SP1 through a first via hole penetrating the first insulating layer G11, and the first shielding connection portion SP1 is connected to at least one first power line VDD1 through a second via hole penetrating the second insulating layer G12 and the third insulating layer ILD; or, for example, in other examples, such as Figure 7 As shown, the shielding layer LS is connected to the first shielding connection portion SP1 via a first via V1 penetrating the first insulating layer G11 and the second insulating layer G12. The first shielding connection portion SP1 is connected to at least one first power line VDD1 via a second via penetrating the third insulating layer ILD. That is, the first shielding connection portion SP1 can be located in either the first conductive layer or the second conductive layer. Figure 7 A schematic diagram is shown in which the first shielding connection portion SP1 is located in the second conductive layer, but the embodiments of the present disclosure are not limited to this. The first conductive layer and the second conductive layer will be described below and will not be repeated here. For example, the following description uses the example of the first shielding connection portion being located in the first conductive layer, but the embodiments of the present disclosure are not limited to this.

[0113] Figure 8 for Figure 6A A plan view of a semiconductor pattern of a display substrate is shown; Figure 9 for Figure 6A A plan view of the first conductive layer of the display substrate is shown; Figure 10 for Figure 6A A plan view of the second conductive layer of the display substrate is shown; Figure 11 for Figure 6A A plan view of the third conductive layer of the display substrate is shown.

[0114] like Figure 7 As shown, the fourth insulating layer G10 is located between the blocking layer LS and the active layer of the transistor (eg, the active layer A7 of the second reset transistor T1 ).

[0115] For example, Figures 8-11 As shown, the first conductive layer LY1 includes the gate line GL1, the second conductive layer LY2 includes the second plate C12 of the storage capacitor C1, and the third conductive layer LY3 includes the first power line VDD1. For example, in a direction perpendicular to the base substrate 100, the first insulating layer G11 is located between the active layer A7 and the first conductive layer LY1, the second insulating layer G12 is located between the gate line and the second conductive layer LY2, and the third insulating layer ILD is located between the second plate C12 of the storage capacitor C1 and the third conductive layer LY3. For example, the first shielding connection SP1 is located Figure 9 The first conductive layer LY1 is shown, but the embodiments of the present disclosure are not limited thereto.

[0116] For example, Figure 5 As shown, the pixel driving circuit includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. For example, each transistor and capacitor includes a first electrode and a second electrode. For an introduction to the connection relationship and operating principle of the pixel driving circuit, reference can be made to the description in the art and will not be repeated here.

[0117] For example, Figure 8 As shown, the active layers A6, A3, A5, and A7 of the first reset transistor T6, the compensation transistor T3, the second light-emitting control transistor T5, and the second reset transistor T7 are located in the first semiconductor layer A01 extending along the first direction Y1, and the active layers A2 and A4 of the data writing transistor T2 and the first light-emitting control transistor T4 are located in the second semiconductor layer A02 extending along the second direction X1. The first semiconductor layer A01 and the second semiconductor layer A02 are connected through the active layer A1 of the driving transistor T1 and are formed as one piece.

[0118] For example, Figure 6A and 8 As shown, the active layer A1 of the driving transistor T1 is located on an imaginary line in the first direction Y1 of the active layer A6 of the first reset transistor T6, the active layers A3 and A2 of the compensation transistor T3 and the data writing transistor T2 are respectively located on both sides of the active layer A1 of the driving transistor T1, and are located on a side of the active layer A1 of the driving transistor T1 close to the active layer A6 of the first reset transistor T6, that is, in the second direction Y1, the active layers A3 and A2 of the compensation transistor T3 and the data writing transistor T2 are located above the active layer A1 of the driving transistor T1, and the active layers A5 and A4 of the second light-emitting control transistor T5 and the first light-emitting control transistor T4 are respectively located on both sides of the active layer A1 of the driving transistor T1, and are located on a side of the active layer A1 of the driving transistor T1 away from the active layer A6 of the first reset transistor T6, for example, below the active layer A1 of the driving transistor T1 in the second direction Y1.

[0119] For example, Figure 6A and 9 As shown, the active layer A7 of the second reset transistor T7 is located on a side of the active layer A5 of the second light-emitting control transistor T5 away from the active layer of the compensation transistor T3. The compensation transistor T3 includes a first gate G31 extending along the first direction Y1 and a second gate G32 extending along the second direction X1. The second gate G32, the gate G5 of the second light-emitting control transistor T5 extending along the second direction X2, and the gate of the second reset transistor T7 (not shown in the figure) are arranged side by side in the first direction Y1. The gate G2 of the data writing transistor T2 and the gate G4 of the first light-emitting control transistor T4 extend along the second direction X1 and are arranged side by side in the first direction Y1.

[0120] For example, the gate G6 of the first reset transistor T6 and the gate G1 of the driving transistor T1 extend along the second direction X1 and are arranged side by side in the first direction Y1. The gate G1 of the driving transistor T1 is integrally formed with the first plate C11 of the storage capacitor C1.

[0121] For example, the display substrate further includes a gate line 113 extending along the second direction Y1 , a light emission control signal line 110 , a first reset signal line 111 , and a second reset signal line (integrated with the gate of the second reset transistor T7 ).

[0122] For example, the gate G6 of the first reset transistor T6 is connected to the first reset signal line 111 and is formed as one piece, the second gate G32 of the compensation transistor T3 and the gate G2 of the data writing transistor T2 are connected to the gate line 113 and are formed as one piece, the gate G6 of the second light-emitting control transistor T6 and the gate G5 of the first light-emitting control transistor T5 are connected to the light-emitting control signal line 110 and are formed as one piece, and the gate of the second reset transistor T7 is connected to the second reset signal line and is formed as one piece.

[0123] For example, the display substrate further includes a gate line 113 extending along the second direction Y1, a light emission control signal line 110, a first reset signal line 111, and a second reset signal line 112. For example, the gate of the first reset transistor T6 is connected to the first reset signal line 111 and formed integrally therewith, the second gate G32 of the compensation transistor T3 and the gate G2 of the data writing transistor T2 are connected to the gate line 113 and formed integrally therewith, the gate G5 of the second light emission control transistor T5 and the gate G4 of the first light emission control transistor T4 are connected to the light emission control signal line 110 and formed integrally therewith, and the gate G7 of the second reset transistor T7 is connected to the second reset signal line 112 and formed integrally therewith.

[0124] For example, the display substrate further includes a data line 313, which is connected to the active layer A4 of the data write transistor T4 and is configured to provide a data signal DATA. The orthographic projection of the first power line VDD1 on the base substrate 100 at least partially overlaps with the orthographic projections of the active layer A6 of the first reset transistor T6 and the active layer A1 of the driving transistor T1 on the base substrate 100. The orthographic projection of the data line 313 on the base substrate 100 is located on a side of the orthographic projection of the second semiconductor layer A02 on the base substrate 100 that is away from the orthographic projection of the first power line VDD1 on the base substrate 100.

[0125] For example, Figure 6A and Figure 11 The pixel driving circuit further includes a first transfer electrode EC1, which is connected to the active layer of the second light-emitting control transistor T5, the active layer A7 of the second reset transistor T7, and the first electrode E1 of the light-emitting device 20 through a via hole. The orthographic projection of the first transfer electrode EC1 on the base substrate 100 is located between the orthographic projections of the active layer A7 of the second reset transistor T7 and the active layer A1 of the driving transistor T1 on the base substrate 100.

[0126] For example, for each of the multiple second pixel units C, the orthographic projection of the second blocking connection portion SP2 on the base substrate 100 is located between the orthographic projection of the active layer A7 of the second reset transistor T7 on the base substrate 100 and the orthographic projection of the second power line VDD2 on the base substrate 100, and at least partially overlaps with the orthographic projection of the second power line VDD2 on the base substrate 100, thereby leaving the opening area A12 vacant.

[0127] For example, reference Figure 5 , the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The light-emitting control signal line 110 is configured to provide a light-emitting control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, and the third power line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vinit to the pixel circuit 10. The initialization signal Vinit is a constant voltage signal, and its size can be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vinit can be less than or equal to the second voltage signal ELVSS. For example, the pixel circuit outputs a driving current under the control of a scan signal SCAN, a data signal DATA, an initialization signal Vinit, a first voltage signal ELVDD, a second voltage signal ELVSS, a light emitting control signal EM, and the like to drive the light emitting element 20 to emit light. Driven by its corresponding pixel circuit 10, the light emitting element 20 emits red light, green light, blue light, or white light, for example.

[0128] like Figure 5 As shown, the driving transistor T1 of the pixel circuit 10 is electrically connected to the light emitting element 20 and outputs a driving current to drive the light emitting element 20 to emit light under the control of the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, the second voltage signal ELVSS and other signals.

[0129] For example, the display panel provided in an embodiment of the present disclosure further includes: a data driver circuit and a scan driver circuit. The data driver circuit is configured to provide a data signal DATA to the sub-pixel P0 according to instructions from the control circuit; the scan driver circuit is configured to provide signals such as an emission control signal EM, a scan signal SCAN, and a first reset control signal RST1 and a second reset signal RST2 to the sub-pixel P0 according to instructions from the control circuit. For example, the control circuit includes an external integrated circuit (IC), but is not limited thereto. For example, the scan driver circuit may be a GOA (Gate Driver On Array) structure mounted on the display panel, or a driver chip (IC) structure bonded to the display panel. For example, different driver circuits may be used to provide the emission control signal EM and the scan signal SCAN, respectively. For example, the display panel further includes a power supply (not shown) to provide the aforementioned voltage signals. The power supply may be a voltage source or a current source, as required. The power supply is configured to provide the first voltage signal ELVDD, the second power supply voltage ELVSS, and the initialization signal Vinit, etc., to the sub-pixel P0 via the first power line 311, the third power line 312, and the initialization signal line 210, respectively.

[0130] like Figure 5 As shown, the second electrode C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first electrode C11 of the storage capacitor C1 is electrically connected to the second electrode T12 of the threshold compensation transistor T1. The gate T20 of the data write transistor T2 is electrically connected to the gate line 113, and the first electrode T21 and the second electrode T22 of the data write transistor T2 are electrically connected to the data line 313 and the first electrode T11 of the drive transistor T1, respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first electrode T31 of the threshold compensation transistor T3 is electrically connected to the second electrode T12 of the drive transistor T1, and the second electrode T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the drive transistor T1.

[0131] For example, Figure 5 As shown, the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control signal line 110 .

[0132] For example, Figure 5As shown, the first electrode T41 and the second electrode T42 of the first light-emitting control transistor T4 are electrically connected to the first power line 311 and the first electrode T11 of the driving transistor T1, respectively. The first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T16 and the pixel electrode E1 (which can be the anode of the OLED) of the light-emitting element 20, respectively. The common electrode E2 (which can be the common electrode of the OLED, such as the cathode) of the light-emitting element 20 is electrically connected to the third power line 312.

[0133] For example, Figure 5 As shown, the gate electrode T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first electrode T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (first initialization signal line 211), and the second electrode T62 of the first reset transistor T6 is electrically connected to the gate electrode T10 of the driving transistor T1. The gate electrode T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first electrode T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (second initialization signal line 212), and the second electrode T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.

[0134] Figure 8 shows a semiconductor pattern SCP, Figure 9 The first conductive layer LY1 is shown, and a first insulating layer G11 is provided between the first conductive layer LY1 and the semiconductor pattern SCP. The semiconductor pattern SCP is doped using the first conductive layer LY1 as a mask, so that the area of ​​the semiconductor pattern SCP not covered by the first conductive layer LY1 retains semiconductor properties, forming a channel of a thin film transistor, while the area of ​​the semiconductor pattern SCP covered by the first conductive layer LY1 is conductive, forming a source or drain of the thin film transistor. Figure 6A An active layer is shown after the semiconductor pattern SCP is partially conductively formed.

[0135] like Figure 9 As shown, the first conductive layer LY1 includes a first reset control signal line 111, a second reset control signal line (not shown), a light emitting control signal line 110, a gate line 113 and a first electrode C11 of the storage capacitor C1.

[0136] Figure 10The second conductive layer LY2 is shown, with a second insulating layer G12 disposed between the second conductive layer LY2 and the first conductive pattern layer LY1. The second conductive layer LY2 includes an initialization signal line 210 and a second electrode C12 of the storage capacitor C1. The second electrode C12 of the storage capacitor C1 has an opening. An interlayer insulating layer ILD is disposed between the second conductive layer LY2 and the third conductive layer LY3. For details regarding the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the first conductive layer LY1, the second conductive layer LY2, and the third conductive layer LY3, please refer to the description in the art and will not be repeated here.

[0137] Figure 11 The third conductive layer LY3 is shown. The third conductive layer LY3 includes a first power line 311 , a data line 313 , a first connection electrode EC1 , a second connection electrode EC2 , and a first electrode E1 of the light emitting element 20 .

[0138] For example, Figure 11 As shown, the first power line 311 includes a protrusion 3111, and the orthographic projection of the second via hole V2 on the substrate overlaps with the orthographic projection of the protrusion 3111 on the substrate, that is, the first shielding connection portion SP1 is connected to the protrusion 3111 of the first power line S11 through the second via hole V2. The orthographic projection of the first via hole V1 on the substrate overlaps with the orthographic projection of the first power line 311 on the substrate. For example, Figure 6A and Figure 7 As shown, the first via hole V1 and the second via hole V2 are arranged left and right. Of course, they can also be arranged up and down in the first direction Y1. The embodiment of the present disclosure is not limited to this.

[0139] For example, in the embodiment of the present disclosure, the orthographic projections of the first via hole V1 and the second via hole V2 on the base substrate do not overlap, that is, the two are arranged up and down or left and right. This can simplify the process and avoid problems such as easy breakage of the film layer caused by the overlapping orthographic projections of the first via hole and the second via hole on the base substrate, difficulty in implementing the process, and a large slope and unevenness of the first power line 311.

[0140] It should be noted that the transistors used in some embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In one embodiment of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is the second pole, so the first pole and the second pole of all or part of the transistors in the embodiment of the present disclosure can be interchangeable as needed. For example, the first pole of the transistor described in the embodiment of the present disclosure may be the source, and the second pole may be the drain; or, the first pole of the transistor may be the drain, and the second pole may be the source.

[0141] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. The embodiments of the present disclosure are described by taking the case where all transistors are P-type transistors as an example. Based on the description and teaching of the implementation method in the present disclosure, ordinary technicians in this field can easily think of using N-type transistors for at least some of the transistors in the pixel circuit of the embodiment of the present disclosure, that is, using N-type transistors or a combination of N-type transistors and P-type transistors, without having to make creative work. Therefore, these implementation methods are also within the scope of protection of the present disclosure.

[0142] Figure 6A The 7T1C pixel circuit is used as an example for illustration, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and capacitors included in the pixel circuit. For example, in other embodiments, the pixel circuit of the display base panel may also have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T3C structure, and the embodiments of the present disclosure do not limit this.

[0143] For example, the base substrate 100 in at least one embodiment of the present disclosure may be a glass plate, a quartz plate, a metal plate, or a resin plate. For example, the base substrate may be made of an organic material, such as a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the base substrate 100 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.

[0144] For example, the materials of the first insulating layer G11, the second insulating layer G12, the third insulating layer ILD and the fourth insulating layer BL may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resin, or other suitable materials, and the embodiments of the present disclosure are not limited to this.

[0145] For example, the material of the third conductive layer LY3 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy or any other suitable composite material, which is not limited in the embodiments of the present disclosure. For example, the material of the shielding layer LS, the first conductive layer LY1 and the second conductive layer LY2 may be the same as the material of the third conductive layer LY3, and no further details are given here.

[0146] For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of the present disclosure are not limited to this. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited to this.

[0147] The following schematic diagrams illustrate several examples of the first shielding connection portion. For example, the first shielding connection portion may be located in the middle, at both ends, or at one end of two rows of first pixel units in the first display area, and the embodiments of the present disclosure are not limited thereto.

[0148] Figure 12A A schematic diagram of an example of a display substrate provided by at least one embodiment of the present disclosure; Figure 12B for Figure 12A A plan view of a shielding area LS1 of a shielding layer LS of a display substrate is shown; Figure 12C for Figure 12A A plan view of a semiconductor pattern of a display substrate is shown; Figure 12D for Figure 12A A plan view of the first conductive layer of the display substrate is shown; Figure 12E for Figure 12A A plan view of the second conductive layer of the display substrate is shown; Figure 12F for Figure 12A A plan view of the third conductive layer of the display substrate is shown.

[0149] For example, Figure 12A As shown, a pixel unit group includes four first pixel units 101, 102, 103 and 104. For example, Figure 12A As shown, for each pixel unit group, the first shielding connection portion SP1 is located between two adjacent first pixel units in each pixel unit group in the first direction Y1. Figures 12B to 12F For related introduction, please refer to Figures 8-11 Description.

[0150] For example, in Figure 12A In the example shown, the orthographic projection of the first shielding connection portion SP1 on the base substrate 100 is located between the orthographic projection of the active layer A7 of the second reset transistor T7 on the base substrate 100 and the orthographic projection of the first power line VDD1 on the base substrate 100, and at least partially overlaps with the orthographic projection of the first power line VDD1 on the base substrate 100 (for example, as shown in FIG. Figure 6A shown).

[0151] For example, Figure 12AAs shown, in the first direction Y1, the first power line 311 between two adjacent pixel unit groups is connected by a third wire L3, the first data line DL1 includes a first portion DL11 and a second portion DL12, the first portion DL11 of the first data line DL1 partially overlaps with the third wire L3, the second portion DL12 of the first data line DL1 at least partially overlaps with the third wire L3, and the first portion DL11 of the first data line DL1 and the second portion DL12 of the first data line DL1 are respectively located in different layers. For example, Figure 12A The first portion DL11 of the first data line DL1 on the left side is located Figure 12E The second conductive layer LY2 shown in FIG. 1 is provided with a second portion DL12 of the first data line DL1 on the right side. Figure 12D For example, referring to the first conductive layer LY1 Figure 12A 、 12D , 12E, the first portion DL11 and the second portion DL12 of the first data line DL1 and the third conductive line L3 are located between adjacent pixel unit groups.

[0152] For example, Figure 12F As shown, the third wire L3 is integrally formed with the first power line 311, and the first power lines 311 of two adjacent pixel unit groups are connected, so that adjacent pixel unit groups are connected by only one third wire, thereby reducing the wiring area and improving the light transmittance.

[0153] For example, reference Figure 12F , two first data lines DL1 are provided, and the two first data lines DL1 are connected to two adjacent columns of sub-pixels respectively. Figure 12F As shown, the first portion DL11 and the second portion DL12 are respectively connected to the two first data lines DL1 and overlap with the orthographic projection of the same third conductive line L3 on the substrate BS. This arrangement allows the data lines between the pixel unit groups in two adjacent columns of sub-pixels to be hidden under the third conductive line, thereby reducing the wiring area and improving light transmittance.

[0154] For example, Figure 12B As shown, the shielding area LS1 includes a first portion LS11, a second portion LS12, a third portion LS13 and a fourth portion LS14, which are respectively Figure 12A For example, the orthographic projection of the third portion LS13 of the shielding area LS1 on the substrate overlaps with the orthographic projection of the third portion LS13 of the shielding area LS1 on the substrate. Figure 12AThe third wire L3 connected to the previous pixel unit group, the first part DL11 and the second part DL12 of the first data line DL1 overlap in the orthographic projection on the substrate, thereby shielding the third wire L3, the first part DL11 and the second part DL12 of the first data line DL1 and the gap between them. The orthographic projection of the fourth part LS14 of the shielding area LS1 on the substrate overlaps Figure 12A The orthographic projections of the first portion LS11 and the second portion LS12 of the first data line DL1 on the substrate overlap. The orthographic projections of the first portion LS11 and the second portion LS12 of the shielding area LS1 on the substrate overlap with the orthographic projections of the lines connecting the left and right pixel groups, respectively.

[0155] like Figure 12C As shown, since the shielding connection portion SP1 is located between adjacent first pixel units, to facilitate the placement of the shielding connection portion SP1, the active layer of the second reset transistor in the previous first pixel unit in the same column of the same pixel unit group extends along the first direction Y1 and is connected to the active layer of the first reset transistor T6 in the next first pixel unit in the same column. It should be noted that the embodiments of the present disclosure are not limited to this.

[0156] Figure 13A A schematic diagram of an example of another display substrate provided in at least one embodiment of the present disclosure; Figure 13B for Figure 13A A plan view of a shielding area LS1 of a shielding layer LS of a display substrate is shown; Figure 13C for Figure 13A A plan view of a semiconductor pattern of a display substrate is shown; Figure 13D for Figure 13A A plan view of the first conductive layer of the display substrate is shown; Figure 13E for Figure 13A A plan view of the second conductive layer of the display substrate is shown; Figure 13F for Figure 13A A plan view of the third conductive layer of the display substrate is shown.

[0157] For example, Figure 13A The display substrate shown is Figure 12AThe display substrate shown is similar, except that the first blocking connection portion SP1 is located at both ends of each pixel unit group and is connected to at least one of the multiple first power lines VDD1 corresponding to each pixel unit group. For example, the first blocking connection portion SP1 located at both ends can be connected to the same first power line VDD1, or can be connected to two different first power lines VDD1 corresponding to the pixel unit group. In other words, the two first blocking connection portions can be located in the same column or in different columns, and the embodiments of the present disclosure are not limited to this.

[0158] like Figure 13B As shown, the shielding area LS1 only includes the portions LS21, LS22, LS23 and LS24 extending along the second direction X1, which shield the wirings connected to the left and right pixel unit groups respectively. Figure 13A The third conductive line connecting the upper and lower pixel unit groups, the first portion and the second portion of the first data line DL1 extend along the second direction X1 respectively. Figure 12B Compared to the example in Figure 13B The shielding area LS1 shown in FIG. 1 does not include a portion extending along the first direction Y1 .

[0159] It should be noted that when the shielding connection portion SP1 is located at both ends, as shown in FIG. Figure 13B As shown, the semiconductor layers of the first pixel units are consistent, that is, the first pixel units located in the same column are not connected, and the active layer of the second reset transistor is connected to the Figure 12C The difference also includes a bending portion T74.

[0160] Figure 14A A schematic diagram of an example of another display substrate provided for at least one embodiment of the present disclosure; Figure 14B for Figure 14A A plan view of a shielding area LS1 of a shielding layer LS of a display substrate is shown; Figure 14C for Figure 14A A plan view of a semiconductor pattern of a display substrate is shown; Figure 14D for Figure 14A A plan view of the first conductive layer of the display substrate is shown; Figure 14E for Figure 14A A plan view of the second conductive layer of the display substrate is shown; Figure 14F for Figure 14A A plan view of the third conductive layer of the display substrate is shown. Figure 15A A schematic diagram of an example of another display substrate provided for at least one embodiment of the present disclosure; Figure 15B for Figure 15A A plan view of a shielding area LS1 of a shielding layer LS of a display substrate is shown; Figure 15C for Figure 15A A plan view of a semiconductor pattern of a display substrate is shown; Figure 15D for Figure 15A A plan view of the first conductive layer of the display substrate is shown; Figure 15E for Figure 15A A plan view of the second conductive layer of the display substrate is shown; Figure 15F for Figure 15A A plan view of the third conductive layer of the display substrate is shown.

[0161] For example, Figure 14A As shown, a pixel unit group includes two first pixel units 101 and 102. For example, Figure 15A As shown, one pixel unit group includes three first pixel units 101 , 102 and 103 .

[0162] Figure 15B The occlusion area in Figure 12B The occlusion area is similar to that in FIG, except that it also includes a protrusion, and the same parts are not repeated here.

[0163] For example, Figure 14A and 15A As shown, the first shielding connection portion SP1 is located at one end of each pixel unit group and is connected to at least one of the plurality of first power lines VDD1 corresponding to the pixel unit group. For example, the first shielding connection portion SP1 is connected to the first power line VDD1 connected to the first pixel unit 101, but this is not limited in the embodiments of the present disclosure.

[0164] For example, Figure 14B As shown, when the first blocking connection portion SP1 is located at one end or both ends of each pixel unit group, the blocking area LS1 of the blocking layer LS further includes a protrusion LS11 to overlap with the first blocking connection portion SP1, thereby avoiding light diffraction and other phenomena.

[0165] It should be noted that the above-mentioned embodiments only schematically show the number and position of the first blocking connection parts SP1. Of course, the number of first blocking connection parts SP1 corresponding to the display substrate of different embodiments can be more or less, and the position can also change. The embodiments of the present disclosure do not limit this.

[0166] It should be noted that the connection method of the second shielding portion SP2 in the second display area 20 to the shielding layer LS and the second power line VDD2 is basically the same as the connection method of the first shielding portion SP2 in the first display area 10. For details, please refer to the above Figure 7 、 Figures 12A-15FThe relevant description will not be repeated here. For example, each second pixel unit C in the second display area 20 corresponds to a second shielding portion, so that the ELVDD signal is connected to the shielding layer LS in each pixel circuit, a stable DC signal is input to the shielding layer LD, and a large ELVDD signal network is formed in the entire display area, which is beneficial to reduce the wiring voltage drop, increase the display uniformity, and improve the display effect. At the same time, the shading layer LS of the first display area 10 is connected to the shading layer LS of the second display area 20 and is formed as a whole, thereby forming a complete ELVDD signal network, further reducing the wiring voltage drop of the power lines (i.e., the first power line VDD1 and the second power line VDD2) that provide the ELVDD signal, and improving the display effect.

[0167] Figure 16 A schematic diagram of a display device provided in at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2, which may include the display substrate 1 of any of the above embodiments.

[0168] For example, Figure 16 As shown, the display device 2 may further include a flexible circuit board and a control chip. For example, the flexible circuit board may be bonded to the bonding area of ​​the display substrate 1, and the control chip may be mounted on the flexible circuit board, thereby electrically connecting to the display area. Alternatively, the control chip may be directly bonded to the bonding area, thereby electrically connecting to the display area.

[0169] For example, the control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through separately provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer executable codes, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0170] For example, the display device 2 provided in at least one embodiment of the present disclosure can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigation system, etc. The display device 2 may also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0171] For example, Figure 16 as well as Figures 1A-1DAs shown, the display device 2 further includes a sensor 192. The sensor 192 is disposed on the second side S2 (e.g., the non-display side) of the display substrate 1. The sensor 192 is configured to receive light (e.g., collimated light or uncollimated light) from the first side S1 (e.g., the display side) of the display substrate 1. The orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10.

[0172] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc. The sensor 192 can be implemented as a chip, etc. The sensor 192 is disposed on the non-display side S2 (the side facing away from the user) of the display substrate.

[0173] For example, the sensor 192 and the first display area 10 at least partially overlap in the normal direction of the display surface of the display substrate.

[0174] For example, sensor 192 can be an image sensor, capable of capturing images of the external environment facing the light-collecting surface of sensor 192. For example, it can be a CMOS image sensor or a CCD image sensor. Sensor 192 can also be an infrared sensor, a distance sensor, or the like. Sensor 192 can be used to implement a camera in a mobile terminal such as a mobile phone or notebook, and can further include optical devices such as lenses, reflectors, or optical waveguides to modulate the optical path as needed. The embodiments of the present disclosure do not limit the type, function, or configuration of sensor 192.

[0175] The sensor 192 is mounted on the non-display side S2 of the display panel using double-sided tape or other methods. The orthographic projection of the sensor 192 on the base substrate 100 at least partially overlaps with the first display area 10, and is configured to receive light from the first side S1. Thus, the first display area 10 facilitates the placement of the sensor 192 while providing display.

[0176] It should be noted that for the sake of clarity and brevity, the embodiments of this disclosure do not provide all components of the display device. To implement the substrate function of the display device, those skilled in the art may provide and configure other structures not shown according to specific needs, and the embodiments of this disclosure do not limit this.

[0177] Regarding the technical effects of the display device provided by the above embodiment, reference may be made to the technical effects of the display substrate provided in the embodiments of the present disclosure, which will not be repeated here.

[0178] There are a few points to note:

[0179] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0180] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0181] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate having a first side for display and a second side opposite to the first side, comprising: substrate; A display area is provided on the base substrate, comprising a first display area and a second display area at least partially surrounding the first display area, wherein the first display area allows light from a first side of the display substrate to at least partially transmit to the second side of the display substrate for sensing, the first display area comprises a plurality of pixel unit groups arranged at intervals, each of the plurality of pixel unit groups comprises a plurality of first pixel units, each of the plurality of first pixel units comprises a pixel area and an opening area, and the opening area is obtained by reducing the size of the first pixel unit; a plurality of first power supply lines, located in the pixel region and configured to be connected to the plurality of pixel unit groups to provide a first power supply voltage to the plurality of pixel unit groups; a shielding layer, provided on the base substrate and located on a side of the first power line close to the base substrate, comprising a hollow area and a shielding area; For one pixel unit group, the opening area of ​​each first pixel unit at least partially overlaps with the shielding area of ​​the shielding layer. The orthographic projection of the outer edge of each pixel unit group in the plurality of pixel unit groups on the substrate is an irregular shape, wherein the orthographic projection of each pixel unit group on the substrate is located within the orthographic projection of the outer edge on the substrate. The outer edge of each pixel unit group includes a wiring or a light shielding layer. The pixel unit group includes a first light emitting control transistor, a first reset transistor and a second reset transistor. The display substrate further includes a hollowed-out area, wherein an orthographic projection of the hollowed-out area on the base substrate and an orthographic projection of the active layer of the second reset transistor on the base substrate are arranged side by side along a second direction, and the orthographic projection of the hollowed-out area on the base substrate is an area enclosed by the orthographic projection of the active layer of the first light-emitting control transistor on the base substrate, the orthographic projection of the active layer of the second reset transistor on the base substrate, and the orthographic projection of the first reset transistor of the next row of pixel driving circuits on the base substrate.

2. The display substrate according to claim 1, further comprising a data line and an initialization signal line, wherein The data line is configured to provide a data signal to the pixel unit group, and the initialization signal line is configured to provide an initialization signal to the pixel unit group; The wiring includes the data line or the initialization signal line.

3. The display substrate according to claim 1, wherein The opening area of ​​the first pixel unit includes a first shielding connection portion, which at least partially overlaps with the shielding area of ​​the shielding layer, and the shielding layer is connected to at least one first power line of the plurality of first power lines through the first shielding connection portion to receive the first power supply voltage; The plurality of first power lines are located on a side of the first shielding connection portion away from the base substrate, the shielding layer is located on a side of the first shielding connection portion close to the base substrate, and the first shielding connection portion is located between the shielding layer and the plurality of first power lines.

4. The display substrate according to claim 3, wherein: The shielding layer is connected to the first shielding connection portion through a first via hole, and the first shielding connection portion is connected to the at least one first power line through a second via hole.

5. The display substrate according to claim 4, wherein: The display substrate further includes a first insulating layer, a second insulating layer and a third insulating layer, wherein the first insulating layer is located between the blocking layer and the first blocking connection portion. The second insulating layer is located between the first insulating layer and the first shielding layer connecting portion, and the third insulating layer is located between the first shielding connecting portion and the plurality of first power lines; or the second insulating layer is located between the first shielding connecting portion and the plurality of first power lines, and the third insulating layer is located between the second insulating layer and the plurality of first power lines. The shielding layer is connected to the first shielding connection part through a first via hole penetrating the first insulating layer, and the first shielding connection part is connected to the at least one first power line through a second via hole penetrating the second insulating layer and the third insulating layer; or, the shielding layer is connected to the first shielding connection part through a first via hole penetrating the first insulating layer and the second insulating layer, and the first shielding connection part is connected to the at least one first power line through a second via hole penetrating the third insulating layer. The display substrate according to claim 5 , wherein: The orthographic projections of the first via hole and the second via hole on the base substrate do not overlap; The first power line includes a protrusion, the orthographic projection of the second via on the base substrate overlaps with the orthographic projection of the protrusion on the base substrate, and the orthographic projection of the first via on the base substrate overlaps with the orthographic projection of the first power line on the base substrate.

7. The display substrate according to any one of claims 1 to 6, wherein: Adjacent pixel unit groups are connected via the routing lines, and the orthographic projections of the plurality of pixel unit groups and the routing lines on the base substrate fall within the orthographic projection of the shielding area of ​​the shielding layer on the base substrate.

8. The display substrate according to any one of claims 1 to 6, wherein: The second display area includes a plurality of second pixel units arranged in an array and a plurality of second power lines, and each of the plurality of second pixel units includes a pixel area and an opening area; The plurality of second power lines are configured to be connected to the plurality of second pixel units to provide a second power voltage to the plurality of second pixel units, wherein the second power voltage is the same as the first power voltage; Wherein, for a second pixel unit, the opening area of ​​each second pixel unit at least partially overlaps with the shielding area of ​​the shielding layer, The opening area of ​​the second pixel unit includes a second blocking connection portion, and the second blocking connection portion at least partially overlaps with the blocking area of ​​the blocking layer.

9. The display substrate according to any one of claims 1 to 6, wherein: The orthographic projection of the second display area on the base substrate falls within the orthographic projection of the shielding area of ​​the shielding layer on the base substrate.

10. The display substrate according to claim 8, wherein Each of the plurality of first pixel units and the plurality of second pixel units comprises a pixel driving circuit and a light emitting device, wherein the pixel driving circuit is configured to drive the light emitting device to emit light; Wherein, the pixel driving circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first light emitting control transistor, a second light emitting control transistor, a first reset transistor, a second reset transistor and a storage capacitor; The active layers of the first reset transistor, the compensation transistor, the second light emission control transistor, and the second reset transistor are located in a first semiconductor layer extending along a first direction, the active layers of the data write transistor and the first light emission control transistor are located in a second semiconductor layer extending along a second direction, and the first semiconductor layer and the second semiconductor layer are connected and integrally formed via the active layer of the drive transistor. The active layer of the driving transistor is located on an imaginary line of the active layer of the first reset transistor in the first direction, The active layers of the compensation transistor and the data writing transistor are respectively located on both sides of the active layer of the driving transistor, and are located on a side of the active layer of the driving transistor close to the active layer of the first reset transistor. The active layers of the second light emitting control transistor and the first light emitting control transistor are respectively located on both sides of the active layer of the driving transistor, and are located on a side of the active layer of the driving transistor away from the active layer of the first reset transistor. The active layer of the second reset transistor is located on a side of the active layer of the second light emission control transistor away from the active layer of the compensation transistor. The compensation transistor includes a first gate extending along the first direction and a second gate extending along the second direction. The second gate is arranged side by side with the gate of the second light emission control transistor and the gate of the second reset transistor extending along the second direction in the first direction. The gate of the data writing transistor and the gate of the first light emission control transistor extend along the second direction and are arranged side by side in the first direction. The gate of the first reset transistor and the gate of the driving transistor extend along the second direction and are arranged side by side in the first direction. The gate of the driving transistor is formed integrally with the first plate of the storage capacitor.

11. The display substrate according to claim 10, further comprising a gate line, a light emitting control signal line, a first reset signal line, and a second reset signal line extending along the second direction, in, The gate of the first reset transistor is connected to the first reset signal line and formed integrally, The second gate of the compensation transistor and the gate of the data writing transistor are connected to the gate line and formed integrally. The gate of the second light emission control transistor and the gate of the first light emission control transistor are connected to the light emission control signal line and are integrally formed. The gate of the second reset transistor is connected to the second reset signal line and is formed integrally with the second reset transistor.

12. The display substrate according to claim 11, further comprising a data line, wherein The data line is connected to the active layer of the data writing transistor and is configured to provide a data signal. The orthographic projection of the first power line on the base substrate at least partially overlaps with the orthographic projections of the active layer of the first reset transistor and the active layer of the drive transistor on the base substrate, The orthographic projection of the data line on the base substrate is located on a side where the orthographic projection of the second semiconductor layer on the base substrate is away from the orthographic projection of the first power line on the base substrate.

13. The display substrate according to claim 12, wherein: The pixel driving circuit further includes a first switching electrode, wherein the first switching electrode is connected to the active layer of the second light emitting control transistor, the active layer of the second reset transistor, and the first electrode of the light emitting device through a via hole. The orthographic projection of the first switching electrode on the base substrate is located between the orthographic projections of the active layer of the second reset transistor and the active layer of the driving transistor on the base substrate; For each of the plurality of second pixel units, the orthographic projection of the second blocking connection portion on the base substrate is located between the orthographic projection of the active layer of the second reset transistor on the base substrate and the orthographic projection of the second power line on the base substrate, and at least partially overlaps with the orthographic projection of the second power line on the base substrate.

14. The display substrate according to claim 13, wherein: For each pixel unit group, the first blocking connection portion of the opening area is located between two adjacent first pixel units in each pixel unit group in the first direction.

15. The display substrate according to claim 13, wherein: The orthographic projection of the first blocking connection portion of the opening area on the base substrate is located between the orthographic projection of the active layer of the second reset transistor on the base substrate and the orthographic projection of the first power line on the base substrate, and at least partially overlaps with the orthographic projection of the first power line on the base substrate.

16. The display substrate according to claim 3, wherein: The first shielding connection portion of the opening area is respectively located at two ends of each pixel unit group and is connected to at least one of the plurality of first power lines corresponding to each pixel unit group; or, The first shielding connection portion is located at one end of each pixel unit group and is connected to at least one of a plurality of first power lines corresponding to the pixel unit group.

17. The display substrate according to claim 13, further comprising a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer; in, The first conductive layer includes the gate line, the second conductive layer includes the second plate of the storage capacitor, and the third conductive layer includes the first power line. In a direction perpendicular to the substrate, The fourth insulation layer is located between the blocking layer and the active layer of the transistor, The first insulating layer is located between the active layer and the first conductive layer, The second insulating layer is located between the gate line and the second conductive layer. The third insulating layer is located between the second plate of the storage capacitor and the third conductive layer.

18. The display substrate according to claim 17, wherein: The first shielding connection portion of the opening area is located in the first conductive layer or the second conductive layer.

19. A display device comprising the display substrate according to any one of claims 1 to 18 and a sensor, wherein: The sensor is disposed on the second side of the display substrate, and the sensor is configured to receive light from the first side of the display substrate; The orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area.

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