Multi-trench silicon carbide junction barrier Schottky diode and preparation method thereof

Abstract

The present application is applicable to the field of microelectronics technology and provides a multi-trench silicon carbide junction barrier Schottky diode and a preparation method thereof. In the multi-trench silicon carbide junction barrier Schottky diode, an N-type epitaxial layer is provided on a substrate layer, a plurality of PN junction trenches are provided on the N-type epitaxial layer, the plurality of PN junction trenches are arranged in a lateral spaced relationship, a plurality of Schottky trenches are provided between two adjacent PN junction trenches, the plurality of Schottky trenches are arranged in a lateral spaced relationship, a P-type region is provided below each PN junction trench, a Schottky metal layer is provided on the N-type epitaxial layer, a plurality of first protrusions adapted to the PN junction trenches and a plurality of second protrusions adapted to the Schottky trenches are provided on the Schottky metal layer, each first protrusion is located in a corresponding PN junction trench, and each second protrusion is located in a corresponding Schottky trench. The multi-trench silicon carbide junction barrier Schottky diode of the present application can solve the problem that current silicon carbide junction barrier Schottky diodes cannot effectively increase current density.

Description

Technical Field

[0001] The present application belongs to the field of microelectronics technology, and in particular relates to a multi-trench silicon carbide junction barrier Schottky diode and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) junction-barrier Schottky diodes are devices that combine PN and Schottky junctions. Their basic cellular structure involves inserting a Schottky junction between two PN junctions. These two PN junctions pinch off the electric field, reducing the electric field strength at the Schottky junction. This results in SiC junction-barrier Schottky diodes with low reverse recovery time and ultra-soft recovery characteristics, making them widely used in power supply applications. With the increasing demand for SiC junction-barrier Schottky diodes, corresponding performance requirements are being placed on them. Among these challenges, effectively increasing the current density of SiC junction-barrier Schottky diodes is a pressing issue. Summary of the Invention

[0003] The embodiments of the present application provide a multi-trench silicon carbide junction barrier Schottky diode, which can solve the problem that the current silicon carbide junction barrier Schottky diode cannot effectively increase the current density.

[0004] In a first aspect, an embodiment of the present application provides a multi-trench silicon carbide junction barrier Schottky diode, comprising a substrate layer, an N-type epitaxial layer, and a Schottky metal layer;

[0005] The N-type epitaxial layer is arranged on the substrate layer, and a plurality of PN junction trenches are arranged on the N-type epitaxial layer, and the plurality of PN junction trenches are arranged at intervals along the lateral direction. A plurality of Schottky trenches are arranged between two adjacent PN junction trenches, and the plurality of Schottky trenches are arranged at intervals along the lateral direction. A P-type region is arranged under each PN junction trench. The Schottky metal layer is arranged on the N-type epitaxial layer, and a plurality of first protrusions adapted to the PN junction trenches and a plurality of second protrusions adapted to the Schottky trenches are provided on the Schottky metal layer, each of the first protrusions is located in the corresponding PN junction trench, and each of the second protrusions is located in the corresponding Schottky trench.

[0006] In a possible implementation manner of the first aspect, a width of each of the PN junction trenches is 0.1-0.5 μm.

[0007] In a possible implementation manner of the first aspect, a width of each of the Schottky trenches is 0.1-1 μm.

[0008] In a possible implementation manner of the first aspect, a depth of each of the PN junction trenches is the same as a depth of each of the Schottky trenches.

[0009] In a possible implementation manner of the first aspect, the substrate layer is an N-type doped silicon carbide substrate.

[0010] In a second aspect, an embodiment of the present application provides a preparation method, which is applied to any of the multi-trench silicon carbide junction barrier Schottky diodes described above, comprising:

[0011] Depositing a silicon dioxide layer on the N-type epitaxial layer, and performing photolithography on the silicon dioxide layer to obtain a plurality of silicon dioxide hard masks;

[0012] After depositing a polysilicon layer on the silicon dioxide hard mask, etching the polysilicon layer to obtain a plurality of polysilicon support pillars; wherein the two polysilicon support pillars between two adjacent silicon dioxide hard masks serve as a polycrystalline unit;

[0013] After removing the silicon dioxide hard mask, silicon nitride is deposited on the polysilicon support pillars, leaving a gap of a preset width between two adjacent polycrystalline units;

[0014] Etching the silicon nitride to expose the upper boundary of the polysilicon support column to obtain a plurality of silicon nitride support columns;

[0015] After removing the polysilicon support pillars, the N-type epitaxial layer is etched using the plurality of silicon nitride support pillars as a mask to obtain a plurality of silicon carbide trenches;

[0016] After depositing the glass preparation in the silicon carbide trench, etching the glass preparation so that the upper boundary of the glass preparation is lower than the upper boundary of the silicon nitride support column or the upper boundary of the glass preparation is flush with the upper boundary of the silicon nitride support column;

[0017] After depositing photoresist on the glass preparation and the silicon nitride support pillar, photolithography is performed on the photoresist to obtain a PN junction implantation region;

[0018] removing the glass preparation at the PN junction injection region to obtain a PN junction trench;

[0019] Removing the photoresist, and implanting aluminum ions into the PN junction trench to obtain a P-type region, wherein a PN junction is formed at an interface between the P-type region and the N-type epitaxial layer;

[0020] removing the silicon nitride support column and the glass preparation to obtain a Schottky trench;

[0021] A Schottky metal is deposited on the N-type epitaxial layer to obtain the multi-trench silicon carbide junction barrier Schottky diode.

[0022] In a possible implementation manner of the second aspect, the thickness of the silicon dioxide layer is 1-3 μm.

[0023] In a possible implementation manner of the second aspect, a line width of photolithography performed on the silicon dioxide layer is 1-2 μm.

[0024] In a possible implementation manner of the second aspect, the thickness of the polysilicon layer is 0.1-0.5 μm, and the width of the polysilicon support pillar is 0.1-1 μm.

[0025] In a possible implementation manner of the second aspect, the preset width is 0.1-0.5 μm.

[0026] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0027] The present invention provides a multi-trench silicon carbide junction barrier Schottky diode, wherein an N-type epitaxial layer is disposed on a substrate layer, a plurality of PN junction trenches are disposed on the N-type epitaxial layer, the plurality of PN junction trenches are spaced laterally apart, a plurality of Schottky trenches are disposed between two adjacent PN junction trenches, the plurality of Schottky trenches are spaced laterally apart, a P-type region is disposed below each PN junction trench, and a Schottky metal layer is disposed on the N-type epitaxial layer. The Schottky metal layer is provided with a plurality of first protrusions adapted to the PN junction trenches and a plurality of second protrusions adapted to the Schottky trenches, each first protrusion being located in a corresponding PN junction trench and electrically contacting the P-type region, and each second protrusion being located in a corresponding Schottky trench. Multiple Schottky trenches are disposed between two PN junction trenches. After Schottky metal is deposited, Schottky junctions are formed on both the sidewalls and bottom walls of the Schottky trenches, thereby increasing the area of ​​the Schottky junctions, improving the proportion of the Schottky junctions, and effectively improving the current density. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 1 is a schematic structural diagram of a multi-trench silicon carbide junction barrier Schottky diode provided in one embodiment of the present application;

[0030] Figure 2 This is a structural diagram of the multi-trench silicon carbide junction barrier Schottky diode provided in one embodiment of the present application;

[0031] Figure 3 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0032] Figure 4 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0033] Figure 5 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0034] Figure 6 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0035] Figure 7 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0036] Figure 8 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0037] Figure 9 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0038] Figure 10 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0039] Figure 11 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0040] Figure 12 This is a structural diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application;

[0041] Figure 13 This is a structural schematic diagram of the preparation process of a multi-trench silicon carbide junction barrier Schottky diode provided by another embodiment of the present application.

[0042] 1. Substrate layer; 2. N-type epitaxial layer; 3. Silicon dioxide hard mask; 4. Polysilicon support column; 5. Silicon nitride support column; 6. Glass preparation; 7. Photoresist; 8. PN junction injection region; 9. PN junction trench; 10. P-type region; 11. Schottky trench; 12. Schottky metal layer; 13. First protrusion; 14. Silicon carbide trench; 15. Second protrusion. DETAILED DESCRIPTION

[0043] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0044] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0045] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0046] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0047] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0048] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0049] like Figure 1As shown, an embodiment of the present application provides a multi-trench silicon carbide junction barrier Schottky diode, comprising a substrate layer 1, an N-type epitaxial layer 2, and a Schottky metal layer 12. The N-type epitaxial layer 2 is disposed on the substrate layer 1, and the Schottky metal layer 12 is disposed on the N-type epitaxial layer 2.

[0050] Specifically, a plurality of PN junction trenches 9 are provided on the N-type epitaxial layer 2. The plurality of PN junction trenches 9 are spaced apart in a laterally spaced manner, and a P-type region 10 is provided below each PN junction trench 9. The PN junction trenches 9 are used to implant aluminum ions to form the P-type region 10. A PN junction is formed at the interface between the P-type region 10 and the N-type epitaxial layer 2. The PN junction trenches 9 are also used to deposit Schottky metal to form a first protrusion 13 on the Schottky metal layer 12. The first protrusion 13 is in electrical contact with the P-type region 10.

[0051] Multiple Schottky trenches 11 are provided between two adjacent PN junction trenches 9, and are spaced apart laterally. The Schottky trenches 11 are used to deposit Schottky metal to form second protrusions 15 on the Schottky metal layer 12. The second protrusions 15 form a Schottky junction at the interface with the N-type epitaxial layer 2.

[0052] A plurality of Schottky trenches 11 are arranged between the two PN junction trenches 9. After the Schottky metal is deposited, Schottky junctions are formed on the sidewalls and bottom walls of the Schottky trenches 11, thereby increasing the area of ​​the Schottky junction, improving the proportion of the Schottky junction, and effectively improving the current density.

[0053] It should be noted that the horizontal Figure 1 From left to right direction.

[0054] Furthermore, the width of each PN junction trench 9 is 0.1-0.5 μm.

[0055] Specifically, the present application controls the width of the PN junction trench 9 to be below 1 μm. Assuming that the lateral spacing between the two PN junction trenches 9 remains unchanged, the width of the PN junction trench 9 becomes narrower, which is equivalent to increasing the area of ​​the Schottky junction between the two PN junction trenches 9 and increasing the proportion of the Schottky junction, thereby achieving the effect of effectively improving the current density.

[0056] Furthermore, the width of each Schottky trench 11 is 0.1-1 μm.

[0057] Specifically, the width of the Schottky trench 11 is set to 0.1-1 μm, so that the distance between the two PN junction trenches 9 can be made smaller, thereby further reducing the leakage current.

[0058] Furthermore, the depth of each PN junction trench 9 is the same as the depth of each Schottky trench 11 .

[0059] Specifically, the depth of the PN junction trench 9 is the same as the depth of the Schottky trench 11 , so that the present application can etch the PN junction trench 9 and the Schottky trench 11 with the same depth in one step, which is a simple process.

[0060] Furthermore, the substrate layer 1 is an N-type doped silicon carbide substrate.

[0061] The present application also provides a preparation method for the multi-trench silicon carbide junction barrier Schottky diode described in any one of the above items, comprising:

[0062] Step S1, preparing a substrate layer 1.

[0063] Specifically, the substrate layer 1 is an N-type doped silicon carbide substrate.

[0064] Step S2: preparing an N-type epitaxial layer 2 on the substrate layer 1.

[0065] Specifically, an N-type epitaxial layer 2 is grown on the upper surface of the substrate layer 1 .

[0066] Step S3: depositing a silicon dioxide layer on the N-type epitaxial layer 2 and performing photolithography on the silicon dioxide layer to obtain a plurality of silicon dioxide hard masks 3.

[0067] Specifically, a silicon dioxide layer with a thickness of 1-3 μm is deposited on the N-type epitaxial layer 2, and the silicon dioxide layer is photolithographically processed at a line width of 1-2 μm, wherein a photoresist 7 is used as a mask. After etching, the photoresist 7 is removed to obtain a plurality of silicon dioxide hard masks 3. The specific structure is as follows: Figure 2 shown.

[0068] Step S4: After depositing a polysilicon layer on the silicon dioxide hard mask 3, the polysilicon layer is etched to obtain a plurality of polysilicon support pillars 4, wherein two polysilicon support pillars 4 between two adjacent silicon dioxide hard masks 3 serve as a polycrystalline unit.

[0069] Specifically, after depositing a polysilicon layer with a thickness of 0.1-0.5 μm on the silicon dioxide hard mask 3, the polysilicon layer is dry-etched to obtain a plurality of polysilicon support pillars 4. The specific structure is as follows: Figure 3 As shown, two polysilicon support pillars 4 between two adjacent silicon dioxide hard masks 3 serve as a polycrystalline unit.

[0070] Furthermore, the thickness of the polysilicon layer determines the width of the polysilicon support pillar 4 .

[0071] Furthermore, the width of the polysilicon support pillar 4 is 0.1-1 μm, and the width of the polysilicon support pillar 4 is equal to the width of the Schottky trench 11 .

[0072] Step S5: After removing the silicon dioxide hard mask 3, silicon nitride is deposited on the polysilicon support pillars 4, leaving a gap of a preset width between two adjacent polycrystalline units.

[0073] Specifically, wet chemical method or high selectivity dry etching is used to remove the silicon dioxide hard mask 3 and retain multiple polysilicon support pillars 4. The specific structure is as follows: Figure 4 After removing the silicon dioxide hard mask 3, silicon nitride is deposited on the multiple polysilicon support pillars 4. The thickness of the silicon nitride can completely fill the gaps in the polycrystalline unit, and a gap of 0.1-0.5μm is left between two adjacent polycrystalline units. This gap determines the width of the PN junction implantation region 8 in the later stage.

[0074] Step S6: etching the silicon nitride to expose the upper boundaries of the polysilicon support pillars 4 to obtain a plurality of silicon nitride support pillars 5.

[0075] Specifically, the silicon nitride is dry-etched without a mask to completely expose the upper edge of the polysilicon support column 4 for easy removal later. After the etching is completed, multiple silicon nitride support columns 5 are obtained. The specific structure is as follows: Figure 5 shown.

[0076] Step S7 : After removing the polysilicon support pillars 4 , the N-type epitaxial layer 2 is etched using the plurality of silicon nitride support pillars 5 as a mask to obtain a plurality of silicon carbide trenches 14 .

[0077] Specifically, wet etching or dry etching is used to remove the polysilicon support pillars 4, leaving a plurality of silicon nitride support pillars 5. The specific structure is as follows: Figure 6 After removing the polysilicon support pillars 4, multiple silicon nitride support pillars 5 are used as masks to etch the N-type epitaxial layer 2 to obtain multiple silicon carbide trenches 14 with the same depth and different widths. The specific structure is shown in FIG. Figure 7 shown.

[0078] It should be noted that the widths of the silicon carbide trenches 14 may also be the same.

[0079] Step S8 , after depositing the glass preparation 6 in the silicon carbide groove 14 , the glass preparation 6 is etched so that the upper boundary of the glass preparation 6 is lower than the upper boundary of the silicon nitride support column 5 or the upper boundary of the glass preparation 6 is flush with the upper boundary of the silicon nitride support column 5 .

[0080] Specifically, after depositing the glass preparation 6 containing silicon oxide in the silicon carbide trench 14, the glass preparation 6 is subjected to maskless dry etching to make the upper boundary of the glass preparation 6 lower than the upper boundary of the silicon nitride support column 5 or to make the upper boundary of the glass preparation 6 flush with the upper boundary of the silicon nitride support column 5. The specific structure is as follows: Figure 8 shown.

[0081] Exemplarily, the glass preparation 6 includes BPSG (borophosphosilicate glass) or USG (Undoped Silica Glass).

[0082] Step S9 , after depositing photoresist 7 on the glass preparation 6 and the silicon nitride support pillar 5 , photolithography is performed on the photoresist 7 to obtain a PN junction implantation region 8 .

[0083] Specifically, after depositing photoresist 7 on the glass preparation 6 and the silicon nitride support column 5, the photoresist 7 is photoetched to expose the PN junction injection region 8 to be injected. The specific structure is as follows: Figure 9 Among them, it is preferred that the wider PN junction injection region 8 is used as the opening to facilitate the alignment of the photolithography machine and to avoid lateral diffusion, resulting in the connection of the two PN junction injection regions 8.

[0084] Step S10 , removing the glass preparation 6 at the PN junction implantation region 8 to obtain a PN junction trench 9 .

[0085] Specifically, the glass preparation 6 at the PN junction injection region 8 is removed by wet method to obtain the PN junction trench 9. The specific structure is as follows: Figure 10 shown.

[0086] Step S11 , removing the photoresist 7 , and implanting aluminum ions into the PN junction trench 9 to obtain a P-type region 10 . A PN junction is formed at the interface between the P-type region 10 and the N-type epitaxial layer 2 .

[0087] Specifically, the photoresist 7 is removed, and aluminum ions are implanted at high temperature in the PN junction trench 9 to obtain a P-type region 10. A PN junction is formed at the interface between the P-type region 10 and the N-type epitaxial layer 2. The specific structure is as follows: Figure 11 shown.

[0088] Step S12: remove the silicon nitride support column 5 and the glass preparation 6 to obtain the Schottky trench 11.

[0089] Specifically, the silicon nitride support column 5 and the glass preparation 6 are removed to obtain the Schottky trench 11, a carbon film is deposited, and a high temperature annealing treatment is performed. The specific structure is as follows: Figure 12 As shown, there are two Schottky trenches 11 .

[0090] Step S13: depositing a Schottky metal on the N-type epitaxial layer 2 to obtain the multi-trench silicon carbide junction barrier Schottky diode.

[0091] Specifically, a Schottky metal is deposited on the N-type epitaxial layer 2 to form a Schottky metal layer 12. The Schottky metal is deposited on the PN junction trench 9 and the Schottky trench 11 to form a first protrusion 13 and a second protrusion 15 on the Schottky metal layer 12. The first protrusion 13 is in electrical contact with the P-type region 10, and a Schottky junction is formed at the interface between the second protrusion 15 and the N-type epitaxial layer 2. The specific structure is as follows: Figure 13 As shown. Two Schottky trenches 11 are set between the two PN junction trenches 9. After the Schottky metal is deposited, Schottky junctions are formed on the sidewalls and bottom walls of the Schottky trenches 11, increasing the area of ​​the Schottky junctions and improving the proportion of the Schottky junctions, effectively improving the current density. The width of the Schottky trenches 11 is 0.1-1μm, which makes the distance between the two PN junction trenches 9 smaller, further reducing the leakage current.

[0092] In summary, the present application forms a polysilicon support column, cooperates with silicon nitride deposition and etching, and forms a silicon nitride support column 5 with different opening widths. The silicon nitride support column 5 is used as a mask to etch out silicon carbide grooves 14 with the same depth and different widths in one step, and fill them with glass preparation 6. Then, selective openings are made, and the silicon nitride support column 5 and the glass preparation 6 are used as masks for selective injection. Then, the silicon nitride support column 5 and the glass preparation 6 are removed, and Schottky metal is deposited to obtain a multi-trench silicon carbide junction barrier Schottky diode. The obtained multi-trench silicon carbide junction barrier Schottky diode increases the area of ​​the Schottky junction, increases the proportion of the Schottky junction, and effectively increases the current density. At the same time, since the width of the Schottky trench 11 is 0.1-1μm, the distance between the two PN junction trenches 9 becomes smaller, further reducing the leakage current.

[0093] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0094] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for preparing a multi-trench silicon carbide junction barrier Schottky diode, characterized in that: include: Depositing a silicon dioxide layer on the N-type epitaxial layer, and performing photolithography on the silicon dioxide layer to obtain a plurality of silicon dioxide hard masks; After depositing a polysilicon layer on the silicon dioxide hard mask, etching the polysilicon layer to obtain a plurality of polysilicon support pillars; wherein the two polysilicon support pillars between two adjacent silicon dioxide hard masks serve as a polycrystalline unit; After removing the silicon dioxide hard mask, silicon nitride is deposited on the polysilicon support pillars, leaving a gap of a preset width between two adjacent polycrystalline units; Etching the silicon nitride to expose the upper boundary of the polysilicon support column to obtain a plurality of silicon nitride support columns; After removing the polysilicon support pillars, the N-type epitaxial layer is etched using the plurality of silicon nitride support pillars as a mask to obtain a plurality of silicon carbide trenches; After depositing the glass preparation in the silicon carbide trench, etching the glass preparation so that the upper boundary of the glass preparation is lower than the upper boundary of the silicon nitride support column or the upper boundary of the glass preparation is flush with the upper boundary of the silicon nitride support column; After depositing photoresist on the glass preparation and the silicon nitride support pillar, photolithography is performed on the photoresist to obtain a PN junction implantation region; removing the glass preparation at the PN junction injection region to obtain a PN junction trench; Removing the photoresist, and implanting aluminum ions into the PN junction trench to obtain a P-type region, wherein a PN junction is formed at an interface between the P-type region and the N-type epitaxial layer; removing the silicon nitride support column and the glass preparation to obtain a Schottky trench; A Schottky metal is deposited on the N-type epitaxial layer to obtain the multi-trench silicon carbide junction barrier Schottky diode.

2. The preparation method according to claim 1, wherein The thickness of the silicon dioxide layer is 1-3 μm.

3. The preparation method according to claim 1, wherein The silicon dioxide layer is photolithographically processed to have a line width of 1-2 μm.

4. The preparation method according to claim 1, wherein The thickness of the polysilicon layer is 0.1-0.5 μm, and the width of the polysilicon support column is 0.1-1 μm.

5. The preparation method according to claim 1, wherein The preset width is 0.1-0.5 μm.

6. A multi-trench silicon carbide junction barrier Schottky diode prepared by the preparation method according to any one of claims 1 to 5, characterized in that: including a substrate layer, an N-type epitaxial layer and a Schottky metal layer; The N-type epitaxial layer is arranged on the substrate layer, and a plurality of PN junction trenches are arranged on the N-type epitaxial layer, and the plurality of PN junction trenches are arranged at intervals along the lateral direction. A plurality of Schottky trenches are arranged between two adjacent PN junction trenches, and the plurality of Schottky trenches are arranged at intervals along the lateral direction. A P-type region is arranged under each PN junction trench. The Schottky metal layer is arranged on the N-type epitaxial layer, and a plurality of first protrusions adapted to the PN junction trenches and a plurality of second protrusions adapted to the Schottky trenches are provided on the Schottky metal layer, each of the first protrusions is located in the corresponding PN junction trench, and each of the second protrusions is located in the corresponding Schottky trench.

7. The multi-trench silicon carbide junction barrier Schottky diode according to claim 6, wherein: The width of each PN junction trench is 0.1-0.5 μm.

8. The multi-trench silicon carbide junction barrier Schottky diode according to claim 6 or 7, wherein: The width of each Schottky trench is 0.1-1 μm.

9. The multi-trench silicon carbide junction barrier Schottky diode according to claim 6 or 7, characterized in that: The depth of each of the PN junction trenches is the same as the depth of each of the Schottky trenches.

10. The multi-trench silicon carbide junction barrier Schottky diode according to claim 6 or 7, characterized in that: The substrate layer is an N-type doped silicon carbide substrate.

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