Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a first conductive type well, a second conductive type drift region, an anode, a cathode, a gate oxide layer and a gate. The substrate comprises a recess structure region and a non-recess structure region outside the recess structure region, and a recess structure is formed in the recess structure region. The recess structure is located in part of the first conductive type well and the second conductive type drift region. The anode is located in the second conductive type drift region. The cathode is located in the first conductive type well. The gate oxide layer is located on part of the bottom surface of the recess structure and part of the substrate of the non-recess structure region, so that the gate oxide layer is in a stepped type. The gate is located on the gate oxide layer and is in a stepped type. The application can improve the on-current speed of the device and the withstand voltage capacity of the device by forming the recess structure on the substrate and arranging part of the gate oxide layer and the gate in the recess structure to form the stepped gate oxide layer and the gate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of the semiconductor industry and technology, the power semiconductor market has an increasing demand for switching devices with high speed and high efficiency. Insulated-gate bipolar transistors (IGBTs), especially laterally insulated-gate bipolar transistors (LIGBTs), have attracted widespread attention due to their low drive power consumption, low on-resistance, and high voltage withstand capability. However, as the requirements of the power semiconductor market become increasingly stringent, the on-current speed and voltage withstand capability of IGBT devices still need further improvement. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method to improve the device's voltage withstand capability and conduction current speed.

[0004] To achieve the above and other related objectives, the present invention provides a semiconductor device, comprising:

[0005] A substrate, wherein the substrate includes a groove structure region and a non-groove structure region other than the groove structure region, and a groove structure is formed in the groove structure region;

[0006] A first conductivity type well is located in the substrate;

[0007] The second conductivity type drift region is located in the substrate, adjacent to or spaced apart from the first conductivity type well, and the groove structure is located in part of the first conductivity type well and the second conductivity type drift region;

[0008] The anode is located in the drift region of the second conductivity type;

[0009] The cathode is located in the first type of conductivity well;

[0010] A gate oxide layer is located on a portion of the bottom surface of the grooved structure and a portion of the substrate in the non-grooved structure region, such that the gate oxide layer is stepped.

[0011] A gate is located on the gate oxide layer, and the gate is stepped.

[0012] Optionally, in the semiconductor device, the semiconductor device further includes:

[0013] A deep second conductivity type well region is located at the bottom of the substrate;

[0014] A first conductivity type drift region is located on the deep second conductivity type well region, and the first conductivity type well and the second conductivity type drift region are located in the first conductivity type drift region.

[0015] Optionally, in the semiconductor device, the semiconductor device further includes an isolation region, the isolation region including a second conductivity type well and a first injection region located in the second conductivity type well, the second conductivity type well and the first conductivity type well being isolated by the shallow trench isolation structure.

[0016] Optionally, in the semiconductor device, the gate oxide layer includes a first portion on a portion of the substrate in the first conductivity type well in the non-groove structure region, a third portion on the bottom surface of the groove structure in the second conductivity type drift region, and a second portion between the first portion and the third portion, wherein the thickness of the first portion is less than the thickness of the second portion and the third portion.

[0017] Optionally, in the semiconductor device, the semiconductor device further includes a metal silicide layer located on the cathode, anode, and gate.

[0018] To achieve the above-mentioned objectives and other related objectives, the present invention also provides a method for fabricating the aforementioned semiconductor device, comprising the following steps:

[0019] A substrate is provided, wherein the substrate includes a grooved structure region and a non-grooved structure region outside the grooved structure region;

[0020] Ion implantation is performed on the substrate to form a first conductivity type well and a second conductivity type drift region, wherein the second conductivity type drift region is adjacent to or spaced apart from the first conductivity type well;

[0021] A groove structure region is defined on the substrate of the groove structure region, and the substrate of the groove structure region is etched to form a groove structure, wherein the groove structure is located in the first conductivity type well and the second conductivity type drift region;

[0022] A stepped gate oxide layer is formed on a portion of the bottom surface of the groove structure and a portion of the substrate in the non-groove structure region;

[0023] A stepped gate is formed on the gate oxide layer;

[0024] The substrate is ion implanted to form an anode in a drift region of the second conductivity type and a cathode in a trap of the first conductivity type.

[0025] Optionally, in the method for fabricating the semiconductor device, before the steps of forming the first conductivity type well and the second conductivity type drift region, the method further includes:

[0026] The substrate is implanted with ions of the second conductivity type to form a deep second conductivity type well region;

[0027] The deep second conductivity type well region is implanted with first conductivity type ions and second conductivity type ions to form a first conductivity type drift region and a second conductivity type well adjacent to the first conductivity type drift region.

[0028] Optionally, in the method for fabricating the semiconductor device, a shallow trench isolation structure is further formed in the substrate, and the shallow trench isolation structure is located between the first conductivity type well and the second conductivity type well.

[0029] Optionally, in the method for fabricating the semiconductor device, the step of ion implantation of the substrate to form an anode in the second conductivity type drift region and a cathode in the first conductivity type well further includes: forming a first implantation region located in the second conductivity type well.

[0030] Optionally, in the method for fabricating the semiconductor device, the step of forming a stepped gate oxide layer on the substrate includes:

[0031] A first gate oxide layer is formed on the substrate;

[0032] The first gate oxide layer is subjected to photolithography and etching to form a patterned first gate oxide layer, and the patterned first gate oxide layer is located on a portion of the bottom surface of the groove structure and a portion of the substrate of the non-groove structure region.

[0033] A second gate oxide layer is formed on the substrate and the patterned first gate oxide layer;

[0034] The second gate oxide layer is etched to form a patterned second gate oxide layer.

[0035] Optionally, in the method for fabricating the semiconductor device, after the step of ion implantation of the substrate to form an anode in the second conductivity type drift region and a cathode in the first conductivity type trap, the method further includes: forming a metal silicide layer on the cathode, anode, and gate.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] In the semiconductor device and its fabrication method provided by the present invention, by forming a groove structure on the substrate and disposing a portion of the gate oxide layer and the gate in the groove structure to form a stepped gate oxide layer and the gate, a parasitic electric field exists between the anode and the gate, which increases the speed at which anode holes are injected into the drift region of the second conductivity type, thereby increasing the conduction current speed of the device; moreover, the device can have high withstand voltage capability by setting the gate oxide layer. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0039] Figures 2-8 This is a schematic diagram of the structure of each step in the semiconductor device fabrication process according to an embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram of the structure of a semiconductor device with an applied operating voltage according to an embodiment of the present invention;

[0041] in Figures 1-9 middle,

[0042] 10-Substrate, 101-Deep second conductivity type well region, 102-First conductivity type drift region, 103-Second conductivity type drift region, 104-First conductivity type well, 105-Second conductivity type well, 106-Shallow trench isolation structure, 107-Groove structure, 1071-Bottom surface, 1072-Side surface, 1081-First implantation region, 1082-Second implantation region, 1083-Third implantation region, 1084-Fourth implantation region, 1085-Fifth implantation region, 1086-Sixth implantation region, 20-Gate oxide layer, 201-First gate oxide layer, 2011-Patterned first gate oxide layer, 202-Second gate oxide layer, 30-Patterned photoresist layer, 40-Gate, 50-Sidewall, 60-Metal silicide layer. Detailed Implementation

[0043] The semiconductor device and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0044] See Figure 1 The semiconductor device provided by the present invention includes:

[0045] The substrate 10 includes a groove structure region and a non-groove structure region outside the groove structure region, and a groove structure 107 is formed in the groove structure region.

[0046] A first conductivity type well 104 is located in the substrate 10;

[0047] The second conductivity type drift region 103 is located in the substrate 10, adjacent to or spaced apart from the first conductivity type well 104, and the groove structure 107 is located in part of the first conductivity type well 104 and the second conductivity type drift region 103.

[0048] The anode is located in the drift region 103 of the second conductivity type;

[0049] The cathode is located in the first conductivity type trap 104;

[0050] A gate oxide layer 20 is located on a portion of the bottom surface 1071 of the groove structure 107 and a portion of the substrate 10 of the non-groove structure region, so that the gate oxide layer 20 is stepped;

[0051] Gate 40 is located on the gate oxide layer 20 and is stepped.

[0052] In this embodiment, the semiconductor device can be an IGBT, more preferably a LIGBT. The substrate 10 is preferably a silicon substrate, more preferably a P-type silicon substrate. The substrate 10 includes a grooved structure region and a non-grooved structure region other than the grooved structure region, wherein the grooved structure region is the region where the grooved structure 107 is formed, and the non-grooved structure region is the region where the grooved structure does not exist. The grooved structure 107 includes two side surfaces 1072 and a bottom surface 1071.

[0053] The substrate 10 has a second conductivity type drift region 103, a first conductivity type well 104, an anode located in the second conductivity type drift region 103, and a cathode located in the first conductivity type well 104. The anode and cathode are located in the substrate on both sides of the groove structure, i.e., in the substrate of the non-groove structure region. The anode includes a second injection region 1082, a fourth injection region 1084, and a third injection region 1083 located between the second injection region 1082 and the fourth injection region 1084. The cathode includes a fifth injection region 1085 and a sixth injection region 1086 adjacent to the fifth injection region 1085, and the sixth injection region 1086 is close to the gate 40. The second injection region 1082, the fourth injection region 1084, and the fifth injection region 1085 are preferably of the first conductivity type, and the third injection region 1083 and the sixth injection region 1086 are preferably of the second conductivity type. For example, the second injection region 1082, the third injection region 1083, the fourth injection region 1084, the fifth injection region 1085, and the sixth injection region 1086 are the first P-type injection region, the second N-type injection region, the second P-type injection region, the third P-type injection region, and the third N-type injection region.

[0054] In addition, a deep second conductivity type well region 101 and a first conductivity type drift region 102 located on the bottom of the substrate 10 are formed therein, and the second conductivity type drift region 103 and the first conductivity type well 104 are located in the first conductivity type drift region 102.

[0055] An isolation region is also formed in the substrate 10. This isolation region includes a second conductivity type well 105 located on the deep second conductivity type well region 101 and a first implantation region 1081 located within the second conductivity type well 105. The first implantation region 1081 is of a second conductivity type, for example, a first N-type implantation region. The second conductivity type well 105 is isolated from the first conductivity type well 104 by a shallow trench isolation structure (STI) 106. This isolation region can be integrated with other devices for use in different voltage environments.

[0056] The gate oxide layer 20 includes a first portion A on a portion of the substrate in the first conductivity type well in the non-groove structure region, a third portion C on the bottom surface of the groove structure in the second conductivity type drift region, and a second portion B between the first portion A and the third portion C. The thickness of the first portion A is less than the thicknesses of the second portion B and the third portion C. The thickness of the first portion A is preferably 5 nm to 50 nm, and the first portion A is located on the upper surface of the substrate in the non-groove structure region. The area of ​​the upper surface of the substrate 10 covered by the first portion A only needs to be sufficient to provide a turn-on voltage. The first portion A is used for the turn-on voltage; because the thickness of the first portion A is small, the turn-on voltage of the fabricated semiconductor device will be relatively low. The thickness of the second portion B is preferably 10 nm to 70 nm, and the second portion B is located on the upper surface of a portion of the substrate in the non-groove structure region connected to the substrate covered by the first portion A, the side surface of the groove structure, and the bottom surface of a portion of the groove structure 107. The thickness of the second portion B is greater than the thickness of the first portion A. The greater thickness of the second portion B can improve the withstand voltage capability and higher voltage threshold of the semiconductor device. The thickness of the third portion C is preferably 10nm to 70nm, and the thickness of the third portion C is greater than the thickness of the first portion A. The third portion C is located on the bottom surface of the groove structure 107 and is used to form a stepped gate. When the groove structure 107 moves towards the first conductivity type well 104, the resistance of the second conductivity type drift region 103 decreases, and the withstand voltage decreases; when the groove structure 107 moves towards the second conductivity type drift region 103, the resistance of the second conductivity type drift region 103 increases, and the withstand voltage increases. Furthermore, when the position of the groove structure 107 remains unchanged, and the bottom width of the groove structure 107 increases, the resistance of the second conductivity type drift region 103 increases, and the withstand voltage increases. In this embodiment, increasing the thickness of the gate oxide layer 20 can increase the threshold voltage of the device; that is, the threshold voltage of the device can be adjusted by adjusting the thickness of the gate oxide layer.

[0057] The semiconductor device also includes a sidewall 50 located on the sidewall of the gate 40. The gate 40 is located on the gate oxide layer 20, therefore, a portion of the gate 40 is located in the groove structure, making the gate 40 also stepped. Since the bottom surface 1071 of the groove structure is lower than the upper surface of the substrate 10 of the non-grooved structure in the vertical direction, specifically, the height of the bottom surface 1071 of the groove structure is lower than the height of the substrate surface where the anode is located, there will be a potential difference between the gate and the anode corresponding to the bottom surface of the groove structure. This will create a parasitic electric field from the anode to the stepped gate, increasing the speed at which holes from the anode are injected into the drift region of the second conductivity type, thereby reducing the on-resistance of the device and increasing the on-current speed.

[0058] The semiconductor device further includes a metal silicide layer 60, which is metallized by SAB self-alignment to reduce the contact resistance of subsequent via connections. The metal silicide layer 60 is located on the cathode, anode, and gate 40.

[0059] The semiconductor device can also be a symmetrical structure, with the vertical line where the anode is located as the axis of symmetry. That is, a groove structure is formed in the substrate on both sides of the anode, and a stepped gate oxide layer and a gate are formed on the substrate on both sides of the anode. The symmetrical structure shares the anode, the second conductivity type drift region, the first conductivity type drift region, and the deep second conductivity type well region. (See [reference needed]). Figure 1 .

[0060] Semiconductor devices with symmetrical structures can improve their voltage withstand capability and conduction current speed; at the same time, the isolation region can be integrated with other devices and applied to different voltage environments.

[0061] The first conductivity type can be P-type or N-type; the second conductivity type has the opposite polarity to the first conductivity type, that is, the second conductivity type can be N-type or P-type. In this embodiment, the first conductivity type is preferably P-type, and the corresponding second conductivity type is preferably N-type. For example, the semiconductor device includes a substrate, a deep N-well region located in the substrate, a P-type drift region and an N-type well located in the deep N-well region, a P-type well and an N-type drift region located in the P-type drift region, a shallow trench isolation structure located between the N-type well and the P-type well, a first N-type implantation region located in the N-type well, a cathode located in the P-type well, an anode located in the N-type drift region, a groove located above the N-type drift region and the P-type well, a gate oxide layer located on the substrate, a gate located on the gate oxide layer, a sidewall located on the gate sidewall, and a metal silicide layer located on the gate, anode, and cathode.

[0062] The method for fabricating the semiconductor device includes the following steps:

[0063] Step S1: Provide a substrate 10, wherein the substrate 10 includes a groove structure region and a non-groove structure region outside the groove structure region;

[0064] Step S2: Ion implantation is performed on the substrate 10 to form a first conductivity type well 104 and a second conductivity type drift region 103, wherein the second conductivity type drift region 103 is adjacent to or spaced apart from the first conductivity type well 104.

[0065] Step S3: Define a groove structure region on the substrate of the groove structure region, and etch the substrate of the groove structure region to form a groove structure 107, wherein the groove structure 107 is located in the first conductivity type well 104 and the second conductivity type drift region 103;

[0066] Step S4: A stepped gate oxide layer is formed on a portion of the bottom surface 1071 of the groove structure 107 and on a portion of the substrate 10 in the non-groove structure region;

[0067] Step S5: Form a stepped gate 40 on the gate oxide layer 20;

[0068] Step S6: Ion implantation is performed on the substrate 10 to form an anode in the second conductivity type drift region 103 and a cathode in the first conductivity type trap 104.

[0069] In step S1, the substrate 10 is preferably a silicon substrate, and more preferably a P-type silicon substrate.

[0070] See Figure 2 Before step S2, the following is also included:

[0071] The substrate 10 is implanted with ions of a second conductivity type to form a deep second conductivity type well region 101. For example, the substrate 10 is implanted with deep N-well (DNW) to form a deep N-well region.

[0072] The deep second conductivity type well region 101 is implanted with first conductivity type ions and second conductivity type ions to form a first conductivity type drift region 102 and a second conductivity type well 105 adjacent to the first conductivity type drift region 102.

[0073] In the process of forming the deep second conductivity type well region 101, a photoresist layer is first formed on the substrate 10; then the photoresist layer is etched, that is, the photoresist on the substrate surface corresponding to the deep second conductivity type well region 101 is removed, while the photoresist at other locations is retained; then, second conductivity type ion implantation is performed on the substrate to form the deep second conductivity type well region 101; finally, the photoresist layer is removed. The process of forming the first conductivity type drift region 102, the second conductivity type drift region 103, the first conductivity type well 104, and the second conductivity type well 105 in the deep second conductivity type well region 101 is similar to that of the deep second conductivity type well region 101, that is, the corresponding photoresist layer is first formed on the substrate, then ion implantation is performed, and finally the photoresist layer is removed.

[0074] In step S2, ion implantation is performed on the substrate 10 to form a first conductivity type well 104 and a second conductivity type drift region 103. Specifically, the first conductivity type drift region 102 is implanted with second conductivity type ions and first conductivity type ions to form a second conductivity type drift region 103 and a first conductivity type well 104. The anode is located in the second conductivity type drift region 103, the cathode is located in the first conductivity type well 104, and at least a portion of the first conductivity type well 104 and the second conductivity type drift region 103 are located below the bottom surface 1071 of the groove structure.

[0075] A shallow trench isolation structure 106 is also formed between the second conductivity type well 105 and the first conductivity type well 104. The region between the two shallow trench isolation structures is an active region, while the region outside the shallow trench isolation structure 106 where the second conductivity type well 105 is located is an isolation region. The fabrication method of the shallow trench isolation structure 106 is a conventional method and will not be described in detail here.

[0076] See Figure 3 In step S3, a groove structure region is defined on the substrate 10 of the groove structure region, and the substrate of the groove structure region is etched to form a groove structure 107. The groove structure 107 includes a bottom surface 1071 and a side surface 1072. The groove structure 107 is located in the second conductivity type drift region 103 and the first conductivity type well 104 that is adjacent to or spaced apart from the second conductivity type drift region 103, that is, the second conductivity type drift region 103 and the first conductivity type well 104 are located below the bottom surface of the groove structure 107. As long as the first conductivity type well 104 and the second conductivity type drift region 103 exist simultaneously below the groove structure 107, the withstand voltage capability of the device can be adjusted by moving the position and adjusting the width of the groove structure 107.

[0077] See Figures 3-7In step S4, a stepped gate oxide layer 20 is formed on a portion of the bottom surface 1071 of the groove structure 107 and on a portion of the substrate 10 in the non-groove structure region.

[0078] Step S4 specifically includes:

[0079] Step S41: Form a first gate oxide layer 201 on the substrate 10;

[0080] Step S42: Perform photolithography and etching on the first gate oxide layer 201 to form a patterned first gate oxide layer 2011, wherein the patterned first gate oxide layer 2011 is located on a portion of the bottom surface of the groove structure and a portion of the substrate in the non-groove structure region. That is, part of the etched first gate oxide layer will be located in the groove junction 107, specifically, part of the patterned first gate oxide layer 2011 is located on the bottom surface 1071 and the side surface 1072 of the groove structure;

[0081] Step S43: Form a second gate oxide layer 202 on the substrate 10 and the patterned first gate oxide layer 2011;

[0082] Step S44: Etch the second gate oxide layer 202 to form a patterned second gate oxide layer.

[0083] See Figure 3 In step S41, a first gate oxide layer 201 is formed on the substrate 10. That is, after forming the groove structure 107, the first gate oxide layer 201 is formed using an ISSG process (In-situ Moisture Generation Process). The thickness of the first gate oxide layer 201 is preferably 5 nm to 50 nm. The first gate oxide layer 201 covers the entire surface of the substrate, including the upper surface of the substrate in the non-groove structure region and the side and bottom surfaces of the groove structure.

[0084] See Figures 4-5In step S42, the first gate oxide layer 201 is first subjected to photolithography, that is, a patterned photoresist layer 30 is formed on the upper surface of the first gate oxide layer 201; then, using the patterned photoresist layer 30 as a mask, the first gate oxide layer 201 is etched to form a patterned first gate oxide layer 2011. The etching is preferably dry etching. The patterned first gate oxide layer 2011 covers part of the bottom surface of the groove structure and part of the substrate in the non-groove structure area, so that the patterned first gate oxide layer presents a stepped shape. The patterned first gate oxide layer 2011 must cover the bottom surface of the second conductivity type drift region 103, but the area covered is not limited. As long as it covers the bottom surface of the second conductivity type drift region 103, after the gate 40 is subsequently formed, a parasitic electric field exists between the anode and the stepped gate 40, which increases the speed of hole injection into the drift region from the anode, thereby reducing the on-resistance of the device and increasing the on-current.

[0085] See Figure 6 In step S43, a second gate oxide layer 202 is formed on the substrate 10 and the patterned first gate oxide layer 2011. That is, the second gate oxide layer 202 covers the upper surface of the substrate 10 (i.e., the substrate not covered by the patterned first gate oxide layer) and the patterned first gate oxide layer 2011. The thickness of the second gate oxide layer 202 is preferably 5 nm to 20 nm. That is, after forming the patterned first gate oxide layer 2011, another oxide layer is grown using the ISSG process.

[0086] See Figure 7 In step S44, the second gate oxide layer 202 is etched to form a patterned second gate oxide layer. The etched second gate oxide layer is located on the first gate oxide layer and a portion of the upper surface of the substrate. Specifically, the patterned second gate oxide layer completely covers the patterned first gate oxide layer and partially covers the upper surface of the substrate 10 in the non-groove structure region. The area of ​​the upper surface of the substrate 10 in the non-groove structure region covered by the patterned second gate oxide layer only needs to be sufficient to provide a turn-on voltage.

[0087] The patterned first gate oxide layer 2011 and the patterned second gate oxide layer constitute the gate oxide layer 20. The threshold voltage of the device can be adjusted by adjusting the thickness of the gate oxide layer 20; as the thickness of the gate oxide layer increases, the threshold voltage increases.

[0088] Continue reading Figure 7In step S5, a stepped gate 40 and sidewalls 50 located on both sides of the gate 40 are formed on the gate oxide layer 20. That is, after forming the gate oxide layer 20, a polysilicon layer is deposited on the gate oxide layer 20 and polysilicon etching is performed to form the gate 40, and finally the sidewall process is completed to form the sidewalls 50.

[0089] See Figure 8 In step S6, the substrate 10 is implanted with ions of a second conductivity type and ions of a first conductivity type to form an anode in the drift region of the second conductivity type and a cathode in the trap of the first conductivity type. The cathode is located on the side of the gate 40 away from the groove structure, and the anode is located on the side of the groove structure away from the gate.

[0090] The anode includes a second injection region 1082, a fourth injection region 1084, and a third injection region 1083 located between the second injection region 1082 and the fourth injection region 1084. The cathode includes a fifth injection region 1085 and a sixth injection region 1086 adjacent to the fifth injection region 1085, and the sixth injection region 1086 is close to the gate 40.

[0091] While forming the cathode and anode, a first injection region 1081 is formed in the second conductivity type well 105.

[0092] Continue reading Figure 8 Following step S6, subsequent processes such as SAB are included to obtain the device, for example, forming a metal silicide layer 60 on the cathode, anode, and gate. The material of the metal silicide layer 60 is preferably a metal silicide. In this embodiment, a metal silicide film structure can be formed by the SAB process, and then the film structure can be opened by the etching process to form the metal silicide layer 60.

[0093] In this embodiment, the first conductivity type can be either P-type or N-type; the second conductivity type has the opposite polarity to the first conductivity type, that is, the second conductivity type can be either N-type or P-type. In this embodiment, the first conductivity type is preferably P-type, and the corresponding second conductivity type is preferably N-type.

[0094] The semiconductor device fabricated in this embodiment can improve the conduction current speed and simultaneously adjust the threshold voltage and withstand voltage capability of the device. In addition, the semiconductor device also has an isolation region, which allows for effective integration with other devices and application under different voltage environments. For example, see... Figure 9The device provides a gate voltage of 5V to 10V to open the channel, providing an anode voltage of PHV and a cathode voltage of 0V. In this embodiment, the operating voltage of the device can be customized as needed, and is not limited to the voltages specified in this embodiment. When the semiconductor device is turned on, the special structure of the stepped gate creates a parasitic electric field between the anode and the stepped gate, increasing the speed at which anode holes are injected into the drift region of the second conductivity type. This can reduce the on-resistance of the device and increase the on-current. In this embodiment, the threshold voltage of the device can be adjusted by changing the thickness of the stepped gate oxide layer; the withstand voltage capability of the device can be changed by adjusting the length and position of the groove structure.

[0095] In summary, the present invention forms a groove structure on the substrate and sets part of the gate oxide layer and the gate in the groove structure to form a stepped gate oxide layer and gate, so that there is a parasitic electric field between the anode and the gate, which improves the conduction current speed of the device; and the setting of the gate oxide layer makes the device have high voltage withstand capability.

[0096] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0097] Furthermore, it should be understood that the invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive”, unless the context clearly indicates otherwise. Structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way unless the context clearly indicates otherwise.

Claims

1. A semiconductor device, characterized in that, include: A substrate, wherein the substrate includes a groove structure region and a non-groove structure region other than the groove structure region, and a groove structure is formed in the groove structure region; A first conductivity type well is located in the substrate; The second conductivity type drift region is located in the substrate, adjacent to or spaced apart from the first conductivity type well, and the groove structure is located in part of the first conductivity type well and the second conductivity type drift region; The anode is located in the drift region of the second conductivity type, and the height of the bottom surface of the groove structure is lower than the height of the substrate surface where the anode is located. The cathode is located in the first type of conductivity well; A gate oxide layer is located on a portion of the bottom surface of the groove structure and a portion of the substrate in the non-grooved structure region, such that the gate oxide layer is stepped; wherein the gate oxide layer includes a first portion located on a portion of the substrate in the first conductivity type well in the non-grooved structure region, a third portion located on the bottom surface of the groove structure in the second conductivity type drift region, and a second portion located between the first portion and the third portion, wherein the thickness of the first portion is less than the thickness of the second portion and the third portion; A gate is located on the gate oxide layer, and the gate is stepped.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: A deep second conductivity type well region is located at the bottom of the substrate; A first conductivity type drift region is located on the deep second conductivity type well region, and the first conductivity type well and the second conductivity type drift region are located in the first conductivity type drift region.

3. The semiconductor device as described in claim 1, characterized in that, The semiconductor device further includes an isolation region comprising a second conductivity type well and a first injection region located within the second conductivity type well, wherein the second conductivity type well and the first conductivity type well are separated by a shallow trench isolation structure.

4. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes a metal silicide layer located on the cathode, anode, and gate.

5. A method for fabricating a semiconductor device according to any one of claims 1 to 4, characterized in that, Includes the following steps: A substrate is provided, wherein the substrate is designed with a grooved structure region and a non-grooved structure region other than the grooved structure region; Ion implantation is performed on the substrate to form a first conductivity type well and a second conductivity type drift region, wherein the second conductivity type drift region is adjacent to or spaced apart from the first conductivity type well; A groove structure region is defined on the substrate of the groove structure region, and the substrate of the groove structure region is etched to form a groove structure, wherein the groove structure is located in the first conductivity type well and the second conductivity type drift region; A stepped gate oxide layer is formed on a portion of the bottom surface of the groove structure and a portion of the substrate in the non-grooved structure region; wherein the gate oxide layer includes a first portion on a portion of the substrate in the first conductivity type well in the non-grooved structure region, a third portion on the bottom surface of the groove structure in the second conductivity type drift region, and a second portion between the first portion and the third portion, wherein the thickness of the first portion is less than the thickness of the second portion and the third portion; A stepped gate is formed on the gate oxide layer; The substrate is ion implanted to form an anode in a drift region of the second conductivity type and a cathode in a trap of the first conductivity type, wherein the bottom of the groove structure is lower than the height of the substrate surface where the anode is located.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, Prior to the steps of forming the first conductivity type well and the second conductivity type drift region, the method further includes: The substrate is implanted with ions of the second conductivity type to form a deep second conductivity type well region; The deep second conductivity type well region is implanted with first conductivity type ions and second conductivity type ions to form a first conductivity type drift region and a second conductivity type well adjacent to the first conductivity type drift region.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, A shallow trench isolation structure is also formed in the substrate, and the shallow trench isolation structure is located between the first conductivity type well and the second conductivity type well.

8. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The step of ion implanting the substrate to form an anode in a second conductivity type drift region and a cathode in a first conductivity type well further includes: forming a first implantation region located in the second conductivity type well.

9. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The step of forming a stepped gate oxide layer on a portion of the bottom surface of the grooved structure and a portion of the substrate in the non-grooved structure region includes: A first gate oxide layer is formed on the substrate; The first gate oxide layer is subjected to photolithography and etching to form a patterned first gate oxide layer, and the patterned first gate oxide layer is located on a portion of the bottom surface of the groove structure and a portion of the substrate of the non-groove structure region. A second gate oxide layer is formed on the substrate and the patterned first gate oxide layer; The second gate oxide layer is etched to form a patterned second gate oxide layer.

10. The method for fabricating a semiconductor device as described in claim 5, characterized in that, After performing ion implantation on the substrate to form an anode in a second conductivity type drift region and a cathode in a first conductivity type trap, the method further includes forming a metal silicide layer on the cathode, anode, and gate.

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