Low-energy LDPC encoder and method for use in power Internet of Things systems

Abstract

This invention relates to a low-energy LDPC encoder and method for use in power Internet of Things (IoT) systems, belonging to the field of wireless IoT communication. The invention aims to address the problem that existing channels consume more energy due to the numerous high-low level transitions in the transmitted encoded information. A shift controller receives the encoded signal and sends a shift control signal to a shift register and a shift-bit storage module. The shift register, upon receiving the shift control signal, smooths the encoded signal and sends it to the LDPC encoding sequence composition module. The shift-bit storage module receives the encoded signal and the shift control signal, calculates the number of bits for each high level in the smoothed signal generated by the shift control signal in the encoded signal, where the first bit of the encoded signal is 0. The LDPC encoding sequence composition module combines the smoothed signal and the number of bits into a serial signal for LDPC encoding, resulting in an LDPC encoding sequence. This reduces the number of high-low level transitions in the encoded signal.

Description

Technical Field

[0001] This invention relates to LDPC encoders, belonging to the field of wireless Internet of Things (IoT) communication. Background Technology

[0002] With the rapid development of 5G, wireless IoT communication is gradually becoming a reality. Through wireless IoT communication systems, power companies can achieve one-to-many wireless communication and remote control, significantly saving manpower. However, current wireless IoT systems used in power systems often generate excessive high and low voltage level changes during the encoding process, resulting in relatively high energy consumption.

[0003] The dramatic increase in signal throughput in modern devices has posed significant challenges to all aspects of coding. Low-density parity-check codes (LDPC) were proposed by Gallager in his doctoral dissertation in the 1960s. This coding method can approximate the Shannon limit well and has good performance. Furthermore, the decoding complexity of this coding scheme is very low, offering excellent flexibility. With the deepening of wireless communication research, this coding method has gradually become a focus of attention.

[0004] However, due to the inherent characteristics of the power system wireless IoT—namely, a large number of users, concentrated communication time distribution, and 24 / 7 operation—reducing energy consumption has become an urgent need. While traditional encoders perform well in terms of stability and bit error rate, the numerous high-to-low level transitions involved in transmitting encoded information in the channel make the communication system more energy-intensive. Therefore, smoothing the encoded signal in the channel, i.e., reducing the number of high-to-low level transitions, is key to reducing the energy consumption of the power system wireless IoT. Summary of the Invention

[0005] This invention addresses the problem that existing communication channels involve numerous high-low level transitions in the transmitted encoded information, leading to increased energy consumption in the communication system. A low-energy LDPC encoder and method for use in power Internet of Things (IoT) systems are provided.

[0006] A low-energy LDPC encoder for use in power Internet of Things (IoT) systems, comprising a shift controller, a shift register, a shift bit storage module, and an LDPC encoding sequence composition module.

[0007] The shift controller is connected to both the shift register and the shift value storage module, and is used to send shift control signals to the shift register and the shift value storage module after receiving the encoded signal;

[0008] The shift register is connected to the LDPC encoded sequence composition module. After receiving the shift control signal, it converts the encoded signal into a smooth signal and sends it into the LDPC encoded sequence composition module.

[0009] The shift bit storage module is connected to the LDPC encoded sequence composition module. It is used to receive the encoded signal and the shift control signal, calculate the number of bits of each high level in the smooth signal generated by the shift control signal in the encoded signal, where the first bit of the encoded signal is 0, and send the bit number to the LDPC encoded sequence composition module.

[0010] The LDPC encoding sequence composition module is used to combine a smooth signal and a number of bits into a serial signal for LDPC encoding to obtain an LDPC encoding sequence.

[0011] Preferably, the shift register includes a first shift register, a second shift register, and a bit-inverting module.

[0012] The shift memory module includes an accumulator and a register.

[0013] The shift controller is connected to shift register 1, shift register 2, and accumulator. It is used to determine the first and last bits of the input encoded signal. If the first bit of the encoded signal is 1, a high level is sent to shift register 1 for each 1 bit in the encoded signal, and a high level is sent to shift register 2 for each 0 bit in the encoded signal. If the first bit of the encoded signal is 0, a high level is sent to shift register 2 for each 0 bit in the encoded signal, and a high level is sent to shift register 1 for each 1 bit in the encoded signal.

[0014] The first shift register is connected to the LDPC encoding sequence composition module. It is used to receive the high level sent by the shift controller in sequence, and combine the high level sent in sequence into a serial signal and send it to the LDPC encoding sequence composition module.

[0015] The accumulator is connected to the register and is used to calculate the number of bits in the encoded signal for each high level stored in the first shift register based on the encoded signal and the high level sent by the shift controller, where the first bit is the 0th bit, and the number of bits is passed into the register when a high level is received from the shift controller.

[0016] The register is connected to the encoding sequence composition module and is used to sequentially receive the serial signal composed of bits from the accumulator and send it to the LDPC encoding sequence composition module.

[0017] The second shift register is connected to the bit-inverting module and is used to receive the high-level signals sent by the shift controller in sequence, and to form a serial signal from the sequentially sent high-level signals and send it to the bit-inverting module.

[0018] The bit-inverting module is connected to the LDPC encoded sequence composition module and is used to invert each high-level bit of the serial signal sent from the second shift register, and send the inverted serial signal to the LDPC encoded sequence composition module.

[0019] The LDPC encoding sequence composition module is used to encode and sort the number of bits, the serial signal from the No. 1 shift register, and the inverted serial signal to obtain the LDPC encoding sequence.

[0020] Preferably, the initial values ​​of shift register 1 and shift register 2 are both set to 0.

[0021] Preferably, the bit-inverting module is a NOT gate.

[0022] Preferably, the order of the LDPC encoding sequence is: number of bits + serial signal from shift register 1 + inverted serial signal.

[0023] A method based on a low-energy LDPC encoder applied to a power Internet of Things (IoT) system, the method comprising the following steps:

[0024] Step 1: After receiving the encoded signal, send the shift control signal;

[0025] Step 2: After receiving the shift control signal, convert the encoded signal into a smooth signal;

[0026] Step 3: Receive the encoded signal and the shift control signal, and calculate the number of bits in the encoded signal for each high level in the smooth signal generated by the shift control signal, where the first bit of the encoded signal is 0;

[0027] Step 4: Combine the smooth signal and the number of bits into a serial signal and perform LDPC encoding to obtain the LDPC encoded sequence.

[0028] According to the method for implementing a low-energy LDPC encoder applied to a power Internet of Things system, the specific process of step 1 is as follows:

[0029] The first bit of the input encoded signal is judged. If the first bit of the encoded signal is 1, a high level is sent to shift register 1 for each 1 in the encoded signal, and a high level is sent to shift register 2 for each 0 in the encoded signal. If the first bit of the encoded signal is 0, a high level is sent to shift register 2 for each 0 in the encoded signal, and a high level is sent to shift register 1 for each 1 in the encoded signal.

[0030] Step 2 is as follows:

[0031] Step 21: Use shift register 1 to receive high-level signals sequentially and combine the received high-level signals into a serial signal;

[0032] Step 22: Use shift register number 2 to receive high-level signals sequentially and combine the received high-level signals into a serial signal;

[0033] The serial signals obtained in steps 23, 21, and 22 are combined into a smooth signal;

[0034] Step 3 is as follows:

[0035] Step 31: Calculate the number of high-level bits in the encoded signal in shift register 1, where the first bit of the encoded signal is 0.

[0036] Step 32: Receive the received bits sequentially to form a serial signal;

[0037] Step 33: Invert each high-level value in the serial signal sent from the second shift register to obtain the inverted serial signal;

[0038] Step 34: Encode and sort the number of bits, the serial signal from shift register 1, and the inverted serial signal to obtain the LDPC encoded sequence.

[0039] According to the method of implementing the low-energy LDPC encoder applied to the power Internet of Things system, the initial values ​​of shift register 1 and shift register 2 are both set to 0.

[0040] According to the method of implementing a low-power LDPC encoder applied to the power Internet of Things system, each high-level average of the serial signal sent from the second shift register is inverted using a NOT gate.

[0041] According to the method of implementing the low-energy LDPC encoder applied to the power Internet of Things system, the order of the LDPC encoding sequence is: number of bits + serial signal from shift register No. 1 + inverted serial signal.

[0042] The beneficial effects of this invention are as follows:

[0043] This application reduces the energy consumption of the entire Internet of Things (IoT) system by decreasing the number of high-low level transitions in the transmitted coded signal. Applied to power IoT systems, this application utilizes LDPC encoding, which meets the requirements of low energy consumption, strong anti-interference capabilities, low bit error rate, and the ability to handle multiple inputs and outputs, necessary for power IoT systems with high information throughput, concentrated communication time, and 24 / 7 operation. Furthermore, this application exhibits good stability and a simple encoding method.

[0044] advantage:

[0045] 1. This invention greatly reduces the number of high and low level transitions of the encoded signal in the original channel transmission. For a power Internet of Things system with high throughput, all-weather operation, and relatively concentrated time, this will significantly reduce its energy consumption.

[0046] 2. This application introduces a simple encoding preprocessing system that is easy to implement and highly stable.

[0047] 3. This application employs low-density parity-check (LDPC) encoding, which is characterized by ease of decoding, low error rate, and high stability. Applying it to power Internet of Things (IoT) systems can improve the signal stability of the system. Attached Figure Description

[0048] Figure 1 A schematic diagram illustrating the overall principle of low-energy LDPC encoding and decoding applied to power Internet of Things systems;

[0049] Figure 2 This is a schematic diagram of a low-energy LDPC encoder used in power Internet of Things (IoT) systems. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this invention.

[0051] Specific implementation method one: Refer to Figure 2 This embodiment describes a low-energy LDPC encoder applied to a power Internet of Things (IoT) system. The encoder includes a shift controller 1, a shift register 2, a shift bit storage module 3, and an LDPC encoding sequence composition module 4.

[0052] The shift controller 1 is connected to both the shift register 2 and the shift value storage module 3, and is used to send shift control signals to the shift register 2 and the shift value storage module 3 after receiving the encoded signal;

[0053] Shift register 2 is connected to LDPC encoding sequence composition module 4. After receiving the shift control signal, it converts the encoded signal into a smooth signal and sends it into LDPC encoding sequence composition module 4.

[0054] The shift bit storage module 3 is connected to the LDPC encoding sequence composition module 4. It is used to receive the encoding signal and the shift control signal, calculate the number of bits of each high level in the smooth signal generated by the shift control signal in the encoding signal, wherein the first bit of the encoding signal is 0, and send the bit number to the LDPC encoding sequence composition module 4.

[0055] LDPC encoding sequence composition module 4 is used to combine the smooth signal and the number of bits into a serial signal and perform LDPC encoding to obtain the LDPC encoding sequence.

[0056] In this embodiment, the specific encoding steps are as follows:

[0057] Step 1: Determine the first and second digits of the signal.

[0058] At the start of encoding, the first bit of the signal to be encoded is checked to see if it is 1. If the first bit is 1, shift information is sent to shift register 1; if the first bit is 0, shift information is sent to shift register 2.

[0059] Step 2: Register the 1 or 0 signal to the shift controller

[0060] After the previous step, we can initially select the shift registers to be stored and transfer the first bit signal (1 or 0) to the first bit of the corresponding shift register. Next, we check each bit of the signal to be encoded with a 1 or 0: For the signal to be transferred to shift register one, if a 0 is encountered, no shift signal is output; if a 1 is encountered, a high-level signal is output to shift register one. For the signal to be transferred to shift register two, if a 1 is encountered, no shift control signal is output; if a 0 is encountered, a high-level shift control signal is output. When a cluster of signals is stored and output, the output of shift register two is inverted bit by bit.

[0061] Step 3: Add up the numbers that have been moved.

[0062] The signal to be encoded is split into two paths: one enters the shift controller, and the other enters the accumulator. The accumulator calculates the position of the signal stored in the shift register relative to the original signal to be encoded. When the shift controller sends a high-level signal, the digits in the accumulator are transferred to the register. After a set of signals is transmitted, the non-zero digit sequence in the register, along with the digits in the shift register, enters the encoding sequence for LDPC encoding and transmission.

[0063] This encoder consists of a shift controller, a shift register, and a shift value storage module. The shift controller issues shift control signals, and the shift register stores the signal after smoothing the signal to be encoded. This signal, along with the shift value, forms a serial signal for LDPC encoding.

[0064] like Figure 1 As shown, the signal to be encoded first enters the shift controller. The shift controller judges the first and second bits of the signal and sends a shift signal to the shift register. The shift register stores the signal sent by the shift controller (the initial value of the shift register is set to 0). At the same time, the accumulator accumulates the shifted number and stores the accumulated number in the register. Finally, the digital signal in the register and the digital signal in the shift register are combined into a serial signal for encoding.

[0065] like Figure 2As shown in the figure, this is the low-power module of the LDPC encoder in this application. We can see that the signal to be encoded first enters the shift controller. The shift controller first judges the first bit of the input signal to see if it is 1. If the first bit is 1, the shift controller outputs a high level to shift register 1 (the shift register is initially set to 0). Shift register 1 stores this high-level signal. For each 1 in the signal, the shift controller sends a high level to shift register 1. After a cluster of signals is sent, the stored signal is placed into the sequence to be encoded. If the first bit is 0, the shift controller sends a high-level signal to shift register 2 (the shift register is initially set to 0). Shift register 2 stores the 1. After each 0, the shift controller sends a high-level signal to shift register 2, which stores it. After a cluster of signals is sent, all data in shift register 2 is inverted bit by bit. Finally, shift register 2 inputs the digital signal in shift register 2 into the sequence to be encoded for LDPC encoding.

[0066] Both the accumulator and the registers are initialized to 0. The accumulator accumulates the first few bits of the digital signal stored in shift register 1, excluding the first bit. The signal to stop accumulating comes from the shift controller. When the shift controller outputs a high-level shift signal, the accumulator stops accumulating and stores the internal number in the corresponding position in the register. Finally, after all the signals in a cluster have been sent, the numbers in the registers, shift register 1, and shift register 2 are entered into the encoding sequence for LDPC encoding.

[0067] In this embodiment, such as Figure 1 As shown, after obtaining the LDPC encoded sequence through the LDPC encoded sequence composition module 4, the LDPC encoded sequence is then decoded by LDPC decoding. The decoded sequence obtained after decoding is received by the external device as a receiving signal through the shift register in the decoding process.

[0068] Specific Implementation Method Two: This implementation method further illustrates the low-energy LDPC encoder applied to the power Internet of Things system described in Specific Implementation Method One. In this implementation method, shift register 2 includes shift register 2-2, shift register 2-1, and bit-inverting module 2-3.

[0069] The shift storage module 3 includes an accumulator 3-1 and a register 3-3.

[0070] Shift controller 1 is connected to shift register 2-2, shift register 2-1, and accumulator 3-1. It is used to determine the first and last bits of the input encoded signal. If the first bit of the encoded signal is 1, a high level is sent to shift register 2-2 for each bit of the encoded signal that is 1, and a high level is sent to shift register 2-1 for each bit of the encoded signal that is 0. If the first bit of the encoded signal is 0, a high level is sent to shift register 2-1 for each bit of the encoded signal that is 0, and a high level is sent to shift register 2-1 for each bit of the encoded signal that is 1.

[0071] Shift register 2-2 is connected to LDPC encoding sequence composition module 4 and is used to receive high-level signals sent by shift controller 1 in sequence, and to assemble the high-level signals sent in sequence into a serial signal and send it to LDPC encoding sequence composition module 4.

[0072] Accumulator 3-1 is connected to register 3-3 and is used to calculate the number of bits in the encoded signal for each high level stored in shift register 2 based on the encoded signal and the high level sent by shift controller 1, where the first bit is bit 0. When a high level is received from shift controller 1, the number of bits is transferred to register 3-3.

[0073] Register 3-3 is connected to the encoding sequence composition module 4 and is used to sequentially receive the bit-based serial signal sent by accumulator 3-1 and send it to the LDPC encoding sequence composition module 4.

[0074] Shift register 2-1 is connected to bit-inverting module 2-3, which is used to receive high-level signals sent by shift controller 1 in sequence, and to form a serial signal from the sequentially sent high-level signals and send it to bit-inverting module;

[0075] Bit-inverting module 2-3 is connected to LDPC encoding sequence composition module 4. It is used to invert each high-voltage bit of the serial signal sent from shift register 2-1 to 2-3, and then send the inverted serial signal to LDPC encoding sequence composition module 4.

[0076] LDPC encoding sequence component module 4 is used to encode and sort the number of bits, the serial signal from shift register 2-2, and the inverted serial signal to obtain the LDPC encoding sequence.

[0077] In this embodiment, the signal for the accumulator to stop accumulating comes from the shift controller. When the shift controller outputs a high-level shift signal, the accumulator stops accumulating and stores the internal number in the corresponding position in the register. Finally, after all the signals in a cluster have been sent, the numbers in the register and the numbers in the shift register are entered into the encoding sequence for LDPC encoding.

[0078] In this embodiment, the content of this application is as follows: 1. If the first bit of the encoded signal is 1, the shift controller sends a shift signal to the shift register that is not connected to the bit-inverting module 3-2.

[0079] 2. If the first bit is 0, the shift controller sends a shift signal to the shift register connected to the bit-inverting module 3-2.

[0080] 3. The accumulator accumulates 0 for each of the first digits.

[0081] An example of implementing this application: If the signal to be encoded is 10011100, then the digital signal in the shift register is 11110000, and the digital signal in the register is 0345. These are then fed into the encoding sequence 034511110000 in the order of register + shift register. We can see that the number of high-low level changes in this encoded signal is very small, and in a power system, the proportion of '1' in the signal to be encoded is very small. Therefore, the number of shift bits is very small, thus achieving the function of reducing energy consumption by reducing the number of high-low level transitions in the encoded signal.

[0082] In this example, the first bit is 1. The high level output of the four 1s in the encoded signal is sent to shift register 1, resulting in four high levels (four 1s). When encountering the four 0s in the encoded signal, one high level is output to shift register 2, resulting in four high levels (four 1s). These four 1s are then inverted to become four 0s. Simultaneously, the positions of the four 1s in shift register 1 in the encoded signal are calculated, with the first bit being bit 0, and the next bits being bit 1, bit 2, and so on. Therefore, the four 1s in shift register 1 are located at bits 0, 3, 4, and 5 respectively. Inverting the four 1s in shift register 1 and the four 1s in shift register 2, resulting in four 0s, forms the LDPC encoding sequence 034511110000.

[0083] Specific Implementation Method 3: This implementation method further illustrates the low-energy LDPC encoder applied to the power Internet of Things system described in Specific Implementation Method 2. In this implementation method, the initial values ​​of shift register 2-2 and shift register 2-1 are both set to 0.

[0084] Specific Implementation Method Four: This implementation method further illustrates the low-energy LDPC encoder applied to the power Internet of Things system described in Specific Implementation Method One. In this implementation method, the bit-inverting module 2-3 is an NOT gate.

[0085] Specific Implementation Method 5: This implementation method further explains the low-energy LDPC encoder applied to the power Internet of Things system described in Specific Implementation Method 2. In this implementation method, the order of the LDPC encoding sequence is: number of bits + serial signal from shift register 2-2 + inverted serial signal.

[0086] Specific Implementation Method Six: This implementation method is based on the low-energy LDPC encoder applied to the power Internet of Things system described in Specific Implementation Method One. The method includes the following steps:

[0087] Step 1: After receiving the encoded signal, send the shift control signal;

[0088] Step 2: After receiving the shift control signal, convert the encoded signal into a smooth signal;

[0089] Step 3: Receive the encoded signal and the shift control signal, and calculate the number of bits in the encoded signal for each high level in the smooth signal generated by the shift control signal, where the first bit of the encoded signal is 0;

[0090] Step 4: Combine the smooth signal and the number of bits into a serial signal and perform LDPC encoding to obtain the LDPC encoded sequence.

[0091] Specific Implementation Method Seven: This implementation method further explains the method for implementing a low-energy LDPC encoder in a power Internet of Things system as described in Specific Implementation Method Six. In this implementation method, step 1 is specifically as follows:

[0092] The first bit of the input encoded signal is judged. If the first bit of the encoded signal is 1, a high level is sent to shift register 2-2 for each bit of the encoded signal that is 1, and a high level is sent to shift register 2-1 for each bit of the encoded signal that is 0. If the first bit of the encoded signal is 0, a high level is sent to shift register 2-1 for each bit of the encoded signal that is 0, and a high level is sent to shift register 2-1 for each bit of the encoded signal that is 1.

[0093] Step 2 is as follows:

[0094] Step 21: Use shift register 2-2 to receive high-level signals sequentially and combine the received high-level signals into a serial signal.

[0095] Step 22: Use shift register 2-1 to receive high-level signals sequentially, and combine the received high-level signals into a serial signal;

[0096] The serial signals obtained in steps 23, 21, and 22 are combined into a smooth signal;

[0097] Step 3 is as follows:

[0098] Step 31: Calculate the number of high-level bits in the encoded signal in shift register 2-2, where the first bit of the encoded signal is 0.

[0099] Step 32: Receive the received bits sequentially to form a serial signal;

[0100] Step 33: Invert each high-level value in the serial signal sent from shift register 2-1 to obtain the inverted serial signal;

[0101] Step 34: Encode and sort the number of bits, the serial signal from shift register 2-2, and the inverted serial signal to obtain the LDPC encoded sequence.

[0102] An example of implementing this application: If the signal to be encoded is 10011100, then the digital signal in the shift register is 11110000, and the digital signal in the register is 0345. These are then fed into the encoding sequence 034511110000 in the order of register + shift register. We can see that the number of high-low level changes in this encoded signal is very small, and in a power system, the proportion of '1' in the signal to be encoded is very small. Therefore, the number of shift bits is very small, thus achieving the function of reducing energy consumption by reducing the number of high-low level transitions in the encoded signal.

[0103] Specific Implementation Method Eight: This implementation method further illustrates the method for implementing a low-energy LDPC encoder applied to a power Internet of Things system as described in Specific Implementation Method Seven. In this implementation method, the initial values ​​of shift register 2-2 and shift register 2-1 are both set to 0.

[0104] Specific Implementation Method Nine: This implementation method further illustrates the method for implementing a low-energy LDPC encoder applied to a power Internet of Things system as described in Specific Implementation Method Seven. In this implementation method, the high-level average of each serial signal sent from shift register 2-1 is inverted using a NOT gate.

[0105] Specific Implementation Method 10: This implementation method further illustrates the method for implementing a low-energy LDPC encoder applied to a power Internet of Things system as described in Specific Implementation Method 7. In this implementation method, the order of the LDPC encoding sequence is: number of bits + serial signal from shift register 2-2 + inverted serial signal.

Claims

1. A low-energy LDPC encoder for use in power Internet of Things (IoT) systems, characterized in that, The encoder includes a shift controller (1), a shift register (2), a shift bit storage module (3), and an LDPC encoding sequence composition module (4). The shift controller (1) is connected to both the shift register (2) and the shift number storage module (3) and is used to send shift control signals to the shift register (2) and the shift number storage module (3) after receiving the encoded signal; The shift register (2) is connected to the LDPC encoding sequence composition module (4) and is used to convert the encoded signal into a smooth signal and send it into the LDPC encoding sequence composition module (4) after receiving the shift control signal. The shift storage module (3) is connected to the LDPC encoding sequence composition module (4) and is used to receive the encoding signal and the shift control signal, calculate the number of bits of each high level in the smooth signal generated by the shift control signal in the encoding signal, wherein the first bit of the encoding signal is 0, and send the bit number to the LDPC encoding sequence composition module (4). The LDPC encoding sequence composition module (4) is used to combine the smooth signal and the number of bits into a serial signal and perform LDPC encoding to obtain the LDPC encoding sequence.

2. The low-energy LDPC encoder for power Internet of Things systems according to claim 1, characterized in that, The shift register (2) includes shift register 1 (2-2), shift register 2 (2-1), and a bitwise inverting module (2-3). The shift storage module (3) includes an accumulator (3-1) and a register (3-3). The shift controller (1) is connected to shift register 1 (2-2), shift register 2 (2-1) and accumulator (3-1) to determine the first and second bits of the input encoded signal. If the first bit of the encoded signal is 1, a high level is sent to shift register 1 (2-2) for each bit of the encoded signal that is 1, and a high level is sent to shift register 2 (2-1) for each bit of the encoded signal that is 0. If the first bit of the encoded signal is 0, a high level is sent to shift register 2 (2-1) for each bit of the encoded signal that is 0, and a high level is sent to shift register 2 (2-1) for each bit of the encoded signal that is 1. The first shift register (2-2) is connected to the LDPC encoding sequence composition module (4) and is used to receive the high level sent by the shift controller (1) in sequence, and to form a serial signal from the high level sent in sequence and send it to the LDPC encoding sequence composition module (4); The accumulator (3-1) is connected to the register (3-3) to calculate the number of bits in the encoded signal for each high level stored in the first shift register (2-2) based on the encoded signal and the high level sent by the shift controller (1), where the first bit is the 0th bit, and the number of bits is passed into the register (3-3) when a high level is received from the shift controller (1); Register (3-3) is connected to LDPC encoded sequence composition module (4) and is used to receive the bit-based serial signal sent by accumulator (3-1) and send it to LDPC encoded sequence composition module (4) in sequence; The second shift register (2-1) is connected to the bit-inverting module (2-3) and is used to receive the high level sent by the shift controller (1) in sequence, and to form a serial signal from the high level sent in sequence and send it to the bit-inverting module. The bit-inverting module (2-3) is connected to the LDPC encoding sequence composition module (4) and is used to invert each high-voltage bit of the serial signal sent from the second shift register (2-1) and send the inverted serial signal to the LDPC encoding sequence composition module (4). The LDPC encoding sequence composition module (4) is used to encode and sort the number of bits, the serial signal sent from the first shift register (2-2), and the inverted serial signal to obtain the LDPC encoding sequence.

3. The low-energy LDPC encoder for power Internet of Things systems according to claim 2, characterized in that, The initial values ​​of shift register 1 (2-2) and shift register 2 (2-1) are both set to 0.

4. The low-energy LDPC encoder for power Internet of Things systems according to claim 1, characterized in that, The bitwise NOT module (2-3) is an NOT gate.

5. The low-energy LDPC encoder for power Internet of Things systems according to claim 2, characterized in that, The order of the LDPC encoded sequence is: number of bits + serial signal from shift register 1 (2-2) + inverted serial signal.

6. The method for implementing a low-energy LDPC encoder in a power Internet of Things system according to claim 1, characterized in that, The method includes the following steps: Step 1: After receiving the encoded signal, send the shift control signal; Step 2: After receiving the shift control signal, convert the encoded signal into a smooth signal; Step 3: Receive the encoded signal and the shift control signal, and calculate the number of bits in the encoded signal for each high level in the smooth signal generated by the shift control signal, where the first bit of the encoded signal is 0; Step 4: Combine the smooth signal and the number of bits into a serial signal and perform LDPC encoding to obtain the LDPC encoded sequence.

7. The method for implementing a low-energy LDPC encoder in a power Internet of Things system according to claim 6, characterized in that, Step 1 is as follows: The first bit of the input encoded signal is judged. If the first bit of the encoded signal is 1, a high level is sent to shift register 1 (2-2) for each 1 in the encoded signal, and a high level is sent to shift register 2 (2-1) for each 0 in the encoded signal. If the first bit of the encoded signal is 0, a high level is sent to shift register 2 (2-1) for each 0 in the encoded signal, and a high level is sent to shift register 1 (2-2) for each 1 in the encoded signal. Step 2 is as follows: Step 21: Use shift register 1 (2-2) to receive high levels sequentially and combine the received high levels into a serial signal; Step 22: Use shift register 2-1 to receive high-level signals sequentially and combine the received high-level signals into a serial signal; The serial signals obtained in steps 23, 21, and 22 are combined into a smooth signal; Step 3 is as follows: Step 31: Calculate the number of high-level bits in the encoded signal in shift register 1 (2-2), where the first bit of the encoded signal is 0. Step 32: Receive the received bits sequentially to form a serial signal; Step 33: Invert each high-level value in the serial signal sent from shift register 2 (2-1) to obtain the inverted serial signal; Step 34: Encode and sort the number of bits, the serial signal from shift register 1 (2-2), and the inverted serial signal to obtain the LDPC encoded sequence.

8. The method for implementing a low-energy LDPC encoder in a power Internet of Things system according to claim 7, characterized in that, The initial values ​​of shift register 1 (2-2) and shift register 2 (2-1) are both set to 0.

9. The method for implementing a low-energy LDPC encoder in a power Internet of Things system according to claim 7, characterized in that, The high-level average of each serial signal sent from shift register 2 (2-1) is inverted using a NOT gate.

10. The method for implementing a low-energy LDPC encoder in a power Internet of Things system according to claim 7, characterized in that, The order of the LDPC encoded sequence is: number of bits + serial signal from shift register 1 (2-2) + inverted serial signal.

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