Overcurrent detection circuit and wireless charging device

Abstract

The application relates to an overcurrent detection circuit. The overcurrent detection circuit comprises a potential translation circuit which generates a corresponding switching signal according to a received timing signal; an adjusting circuit which adjusts the terminal voltage of a sampling circuit to be consistent with the terminal voltage of a transistor to be detected according to the switching signal sent by the potential translation circuit; and a sampling circuit which samples the conduction current of the transistor to be detected after the terminal voltage is consistent with the terminal voltage of the transistor to be detected, thereby obtaining a sampling current. Since the terminal voltage of the sampling circuit is consistent with the terminal voltage of the transistor to be detected, the sampling current obtained by sampling can accurately indicate the conduction current of the transistor to be detected. Therefore, a more accurate overcurrent detection signal can be generated based on the comparison result between the accurate sampling current and a reference signal, so that the accuracy of the overcurrent detection result is improved, and the generation of an incorrect off signal to affect the normal operation of an electric energy transmission circuit and the normal charging process of an electronic product is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to an overcurrent detection circuit and a wireless charging device. BACKGROUND

[0002] With the popularity of wireless charging devices, more and more users choose wireless charging devices to charge electronic products. The wireless charging device converts a direct current power into an alternating current power through an internal power transmitting circuit, and then transmits the power to the electronic product through a coil. At present, the power transmission of the power transmitting circuit in the wireless charging device is generally realized by a full-bridge circuit composed of four high-voltage N-type MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) tubes. In order to protect the power transmitting circuit and the electronic product, current limiting protection is often needed for the MOS tubes of the full-bridge circuit. Therefore, it is necessary to sample the conduction current of the MOS tube in real time to determine whether it exceeds the preset current, so as to close the MOS tube in time and protect the power transmitting circuit and the electronic product.

[0003] In the prior art, the conduction current of the high-side high-voltage N-type MOS tube is sampled. Since the drain end of the sampling MOS tube for sampling the current is connected in series with a resistor, the sampling current of the sampling MOS tube flowing through the resistor will cause a voltage drop, resulting in that the terminal voltage of the sampling MOS tube is not equal to that of the high-side high-voltage N-type MOS tube. At this time, the sampling current collected by the sampling MOS tube cannot accurately indicate the conduction current of the high-side high-voltage N-type MOS tube, which reduces the accuracy of the sampling result, and may cause an error shutdown signal according to the inaccurate sampling current, thereby affecting the normal operation of the power transmitting circuit and the normal charging process of the electronic product. SUMMARY

[0004] To solve the above technical problems, the present application provides an overcurrent detection circuit and a wireless charging device.

[0005] In a first aspect, the present application provides an overcurrent detection circuit, comprising:

[0006] a potential translation circuit, configured to generate a switching signal according to a received timing signal;

[0007] an adjustment circuit, electrically connected with the potential translation circuit, the sampling circuit and the transistor to be measured, and configured to adjust the terminal voltage of the sampling circuit to be consistent with the terminal voltage of the transistor to be measured according to the switching signal sent by the potential translation circuit;

[0008] The sampling circuit is electrically connected with the transistor to be tested in the full-bridge circuit, and is configured to sample the conduction current of the transistor to be tested to obtain a sampling current when a terminal voltage of the sampling circuit is consistent with a terminal voltage of the transistor to be tested.

[0009] The comparison circuit is electrically connected with the sampling circuit through the adjusting circuit, and is configured to generate an overcurrent detection signal based on a comparison result of the sampling current and a reference signal.

[0010] Optionally, the sampling circuit comprises an isolation circuit and a sampling transistor, the isolation circuit is electrically connected with a gate terminal of the transistor to be tested and a gate terminal of the sampling transistor respectively, a drain terminal of the sampling transistor is electrically connected with a drain terminal of the transistor to be tested and a power supply port respectively, and a source terminal of the sampling transistor is electrically connected with the adjusting circuit.

[0011] The isolation circuit is configured to short the gate terminal of the transistor to be tested and the gate terminal of the sampling transistor when a driving signal is detected, and isolate the gate terminal of the first transistor and the gate terminal of the sampling transistor when an off signal is detected.

[0012] The sampling transistor is configured to sample the conduction current of the transistor to be tested to obtain the sampling current.

[0013] Optionally, the isolation circuit comprises a first isolation transistor and a second isolation transistor, a drain terminal of the first isolation transistor is electrically connected with the gate terminal of the transistor to be tested, a gate terminal of the first isolation transistor is electrically connected with the source terminal of the sampling transistor, and a source terminal of the first isolation transistor is electrically connected with the gate terminal of the sampling transistor.

[0014] The gate terminal and the source terminal of the second isolation transistor are electrically connected with the gate terminal of the sampling transistor, and a drain terminal of the second isolation transistor is electrically connected with the source terminal of the sampling transistor.

[0015] Optionally, the adjusting circuit comprises a feedback circuit and a timing control circuit electrically connected, the timing control circuit is electrically connected with the potential translation circuit and the transistor to be tested, and is configured to control a pass state between the feedback circuit and the transistor to be tested according to the switching signal.

[0016] The feedback circuit is electrically connected with the timing control circuit and the sampling transistor, and is configured to adjust the terminal voltage of the sampling transistor to be consistent with the terminal voltage of the transistor to be tested based on the pass state between the transistor to be tested.

[0017] Optionally, the feedback circuit comprises an operational amplifier and a proportional adjustment circuit, a positive input terminal of the operational amplifier is electrically connected with the timing control circuit, a negative input terminal of the operational amplifier is electrically connected with a source terminal of the sampling transistor, and an output terminal of the operational amplifier is electrically connected with the proportional adjustment circuit.

[0018] The proportional adjustment circuit is electrically connected with the comparison circuit and the source terminal of the sampling transistor respectively.

[0019] Optionally, the timing control circuit comprises a first switch transistor, a second switch transistor and a third switch transistor, a source terminal of the first switch transistor is electrically connected with the positive input terminal of the operational amplifier and a drain terminal of the third switch transistor respectively, a gate terminal of the first switch transistor is electrically connected with the potential translation circuit, and a drain terminal of the first switch transistor is electrically connected with a source terminal of the transistor to be tested.

[0020] A gate terminal of the second switch transistor is electrically connected with the potential translation circuit and a gate terminal of the third switch transistor respectively, a source terminal of the second switch transistor is electrically connected with the power supply port and a source terminal of the third switch transistor respectively, and a drain terminal of the second switch transistor is electrically connected with the negative input terminal of the operational amplifier.

[0021] Optionally, the proportional adjustment circuit comprises a first adjustment transistor and a plurality of second adjustment transistors connected with the first adjustment transistor in parallel, a gate terminal of the first adjustment transistor is electrically connected with the output terminal of the operational amplifier and a gate terminal of the second adjustment transistor respectively, a source terminal of the first adjustment transistor is electrically connected with the source terminal of the sampling transistor and a source terminal of the second adjustment transistor respectively, a drain terminal of the first adjustment transistor is electrically connected with the comparison circuit, and a drain terminal of the second adjustment transistor is grounded.

[0022] Optionally, the comparison circuit comprises a comparison resistor, a reference voltage source and a comparator, a first terminal of the comparison resistor is electrically connected with the drain terminal of the adjustment transistor and a positive input terminal of the comparator respectively, a second terminal of the comparison resistor is electrically connected with a negative input terminal of the comparator through the reference voltage source, and the second terminal of the comparison resistor is also grounded.

[0023] The comparison resistor is configured to generate a corresponding sampling voltage based on the sampling current flowing therethrough.

[0024] The reference voltage source is configured to output a reference voltage, wherein the reference signal comprises the reference voltage.

[0025] The comparator is configured to generate the overcurrent detection signal based on a comparison result of the sampling voltage and the reference voltage.

[0026] Optionally, the comparison circuit further comprises a plurality of resistance branches in parallel with the comparison resistance, each of the resistance branches comprising a shunt resistance and a switch connected in series.

[0027] In a second aspect, the present application provides a wireless charging device, comprising a power supply module and an electric energy transmitting circuit electrically connected, the electric energy transmitting circuit comprising a full-bridge circuit and the overcurrent detection circuit of any one of the first aspect.

[0028] Based on the overcurrent detection circuit, the potential translation circuit generates a corresponding switch signal according to the received timing signal; the adjustment circuit adjusts the terminal voltage of the sampling circuit to be consistent with the terminal voltage of the transistor to be tested according to the switch signal sent by the potential translation circuit; and the sampling circuit samples the on-current of the transistor to be tested after the terminal voltage is consistent with the terminal voltage of the transistor to be tested, so as to obtain a sampling current. Since the terminal voltage of the sampling circuit is consistent with the terminal voltage of the transistor to be tested, there is no resistance voltage division, and the sampling current obtained by sampling can accurately indicate the on-current of the transistor to be tested. Therefore, the comparison result between the accurate sampling current and the reference signal can generate a more accurate overcurrent detection signal, thereby improving the accuracy of the overcurrent detection result and avoiding the generation of an incorrect off signal to affect the normal operation of the electric energy transmitting circuit and the normal charging process of the electronic product. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0031] Figure 1 An application environment diagram of the overcurrent detection circuit in an embodiment;

[0032] Figure 2 A half-side structure diagram of the full-bridge circuit in an embodiment;

[0033] Figure 3 A structure block diagram of the overcurrent detection circuit in an embodiment;

[0034] Figure 4 A partial structure diagram of the overcurrent detection circuit in an embodiment;

[0035] Figure 5Waveform diagram of relevant signals in the overcurrent detection circuit in one embodiment;

[0036] Figure 6 Waveform diagram of relevant signals in the overcurrent detection circuit in one embodiment;

[0037] Figure 7 Partial structural schematic diagram of the overcurrent detection circuit in one embodiment;

[0038] Figure 8 Partial structural schematic diagram of the overcurrent detection circuit in one embodiment;

[0039] Figure 9 Structural schematic diagram of the operational amplifier in one embodiment;

[0040] Figure 10 Structural schematic diagram of the operational amplifier in one embodiment;

[0041] Figure 11 Partial structural schematic diagram of the overcurrent detection circuit in one embodiment;

[0042] Figure 12 Structural schematic diagram of the overcurrent detection circuit in one embodiment;

[0043] Figure 13 Waveform diagram of relevant signals in the overcurrent detection circuit in one embodiment;

[0044] Figure 14 Structural schematic diagram of the overcurrent detection circuit in one embodiment;

[0045] Figure 15 Partial structural schematic diagram of the overcurrent detection circuit in one embodiment;

[0046] Figure 16 Structural schematic diagram of the overcurrent detection circuit in one embodiment;

[0047] Figure 17 Partial structural schematic diagram of the overcurrent detection circuit in one embodiment;

[0048] Figure 18 Partial structural schematic diagram of the overcurrent detection circuit in one embodiment. DETAILED DESCRIPTION

[0049] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0050] Figure 1 An application environment diagram of the overcurrent detection circuit in an embodiment. Referring to Figure 1 , the overcurrent detection circuit is applied to a wireless charging system. The wireless charging system includes a wireless charging device 100 and an electronic device 200. The wireless charging device 100 and the electronic device 200 are wirelessly charged through a coil in the wireless charging device 100. The electronic device 200 can be, but is not limited to, a mobile phone, a tablet computer, electronic paper, an electronic photo frame, and a wearable device.

[0051] The wireless charging device 100 includes an electrically connected power supply module and an electric energy transmission circuit. The power supply module is configured to provide electric energy for the electric energy transmission circuit. The electric energy transmission circuit includes a full-bridge circuit configured to perform electric energy power transmission and an overcurrent detection circuit configured to perform overcurrent detection on the full-bridge circuit. The full-bridge circuit includes four high-voltage N-type MOS transistors. The working mode of the MOS transistors includes an amplification mode and a switching mode. The four high-voltage N-type MOS transistors work in the switching mode. The high-voltage MOS transistor refers to a MOS transistor whose voltage difference between the drain and the source can exceed the range of ±5V, but the voltage difference between the gate and the source cannot exceed the range of ±5V. For example, the V GS must be between -5V and +5V, otherwise the gate of the MOS transistor will be broken down, causing device damage. The low-voltage MOS transistor refers to a MOS transistor whose voltage differences among the three terminals (the gate, the source, and the drain) cannot exceed the range of ±5V.

[0052] In the present embodiment, in order to distinguish between high-voltage and low-voltage MOS transistors, the high-voltage MOS transistors are named with “H” at the beginning, and the low-voltage MOS transistors are named with “L” at the beginning. Meanwhile, the second character in the name is used to indicate the type of the MOS transistor, in which P represents a P-type MOS transistor and N represents an N-type MOS transistor. In addition, for the low-voltage P-type MOS transistors working at the power supply port VPWR, a high-voltage isolation ring needs to be added during layout design to safely protect the high potential difference among the three terminals (the gate, the source, and the drain) of the MOS transistors relative to the ground terminal GND.

[0053] As Figure 2As shown, the source end of the high-side high-voltage N-type MOS tube HN0 and the drain end of the low-side high-voltage N-type MOS tube HN1 are electrically connected to form a half-bridge structure of the full-bridge circuit, two half-bridge structures are connected in parallel to form the full-bridge circuit, the gate end of the high-side high-voltage N-type MOS tube HN0 is electrically connected with the high-side driving module HS DRV, the drain end of the high-side high-voltage N-type MOS tube HN0 is electrically connected with the power supply port VPWR, and the source end of the high-side high-voltage N-type MOS tube HN0 is also electrically connected with the half-bridge output port SW, the gate end of the low-side high-voltage N-type MOS tube HN1 is electrically connected with the low-side driving module LS DRV, and the source end of the low-side high-voltage N-type MOS tube HN1 is grounded.

[0054] In one embodiment, Figure 3 FIG. 1 is a flow diagram of an overcurrent detection circuit according to an embodiment of the present application. Figure 3 The overcurrent detection circuit comprises:

[0055] The potential translation circuit 110 is configured to generate a switching signal according to a received timing signal.

[0056] Specifically, the potential translation circuit 110 receives a low-stage potential timing signal through a timing port and converts the low-stage potential timing signal to output a high-stage potential timing signal, i.e., the switching signal, for controlling the adjustment circuit 120 to perform corresponding adjustment.

[0057] The adjustment circuit 120 is electrically connected with the potential translation circuit 110, the sampling circuit 130, and the transistor to be measured, respectively, and is configured to adjust the terminal voltage of the sampling circuit 130 to be consistent with the terminal voltage of the transistor to be measured according to the switching signal sent by the potential translation circuit 110.

[0058] Specifically, the transistor to be measured is a high-side high-voltage N-type MOS tube HN0 in the full-bridge circuit, and the adjustment circuit 120 is electrically connected with the source end of the high-side high-voltage N-type MOS tube HN0.

[0059] The sampling circuit 130 is electrically connected with the transistor to be measured in the full-bridge circuit, and is configured to sample the conduction current of the transistor to be measured to obtain a sampling current when the terminal voltage of the sampling circuit 130 is consistent with the terminal voltage of the transistor to be measured.

[0060] Specifically, the sampling circuit 130 is electrically connected with the gate end of the high-side high-voltage N-type MOS tube HN0, that is, is electrically connected with the high-side drive module HS DRV, and is used to sample the conduction current of the high-side high-voltage N-type MOS tube HN0 when the high-side drive module HS DRV sends a drive signal to the high-side high-voltage N-type MOS tube HN0 and the terminal voltage of the sampling circuit 130 is consistent with the terminal voltage of the high-side high-voltage N-type MOS tube HN0, to obtain a sampling current. Since the sampling current is sampled when the terminal voltage of the sampling circuit 130 is consistent with the terminal voltage of the high-side high-voltage N-type MOS tube HN0, the obtained sampling current can accurately indicate the conduction current of the high-side high-voltage N-type MOS tube HN0.

[0061] Compared with the prior art, the sampling circuit 130 can sample the current without a series resistor, and the obtained sampling current is no longer affected by the manufacturing process and temperature coefficient of the resistor, thereby improving the accuracy and stability of the sampling current.

[0062] The comparison circuit 140 is electrically connected with the sampling circuit 130 through the adjusting circuit 120, and is used to generate an overcurrent detection signal based on the comparison result of the sampling current and a reference signal.

[0063] Specifically, the reference signal specifically includes a reference voltage and a reference current, and the overcurrent detection signal can be generated according to the comparison result of the sampling current and the reference current; or the sampling current can be converted into a corresponding sampling voltage, and the overcurrent detection signal can be generated according to the comparison result of the sampling voltage and the reference voltage. The accurate overcurrent detection signal is generated based on the accurate sampling current, and the overcurrent detection signal is used to indicate whether the conduction current of the high-side high-voltage N-type MOS tube HN0 exceeds an overcurrent threshold. When the overcurrent detection signal indicates that the conduction current of the high-side high-voltage N-type MOS tube HN0 exceeds the overcurrent threshold, a subsequent turn-off signal can be generated according to the overcurrent detection signal, and the turn-off signal is used to turn off the high-side high-voltage N-type MOS tube HN0 to avoid damaging the power transmission circuit and the electronic device 200 performing wireless charging. The accurate overcurrent detection signal can avoid the influence on the normal operation of the power transmission circuit and the normal charging process of the electronic device 200 due to the mistaken turn-off of the high-side high-voltage N-type MOS tube HN0.

[0064] In one embodiment, as shown in FIG. 1, Figure 4 the sampling circuit 130 includes an isolation circuit 131 and a sampling transistor, the isolation circuit 131 is electrically connected with the gate end of the to-be-measured transistor and the gate end of the sampling transistor respectively; the drain end of the sampling transistor is electrically connected with the drain end of the to-be-measured transistor and a power supply port respectively, and the source end of the sampling transistor is electrically connected with the adjusting circuit 120;

[0065] The isolation circuit 131 is configured to short the gate terminal of the transistor under test and the gate terminal of the sampling transistor when a driving signal is detected, and isolate the gate terminal of the transistor under test and the gate terminal of the sampling transistor when a cutoff signal is detected.

[0066] The sampling transistor is configured to sample the on current of the transistor under test to obtain the sampling current.

[0067] Specifically, as shown in Figure 4 The sampling transistor is a high-voltage N-type MOS tube HN2, which is a current sampling tube of the same structure type as the high-side high-voltage N-type MOS tube HN0. Generally, the gate size of the high-voltage N-type MOS tube HN2 is much smaller than that of the high-side high-voltage N-type MOS tube HN0, but they are in a certain proportional relationship.

[0068] When the high-side driving module HS DRV sends a driving signal to the high-side high-voltage N-type MOS tube HN0, i.e., when the high-side high-voltage N-type MOS tube HN0 is in an on state, the isolation circuit 131 is in an on state to short the gate terminal of the high-side high-voltage N-type MOS tube HN0 and the gate terminal of the high-voltage N-type MOS tube HN2, so that the gate potential of the high-side high-voltage N-type MOS tube HN0 is consistent with the gate potential of the high-voltage N-type MOS tube HN2. The source terminal of the high-side high-voltage N-type MOS tube HN0 and the source terminal of the high-voltage N-type MOS tube HN2 are electrically connected to the regulating circuit 120, and the regulating circuit 120 controls the source potential of the high-side high-voltage N-type MOS tube HN0 to be consistent with the source potential of the high-voltage N-type MOS tube HN2, so that the gate-source voltage of the high-side high-voltage N-type MOS tube HN0 is equal to the gate-source voltage of the high-voltage N-type MOS tube HN2, i.e., the V GS of the high-side high-voltage N-type MOS tube HN0 is equal to the V

[0069] In addition, the drain terminal of the high-side high-voltage N-type MOS tube HN0 and the drain terminal of the high-voltage N-type MOS tube HN2 are electrically connected to the power supply port VPWR, i.e., the drain potential of the high-side high-voltage N-type MOS tube HN0 is consistent with the drain potential of the high-voltage N-type MOS tube HN2, and the regulating circuit 120 controls the source potential of the high-side high-voltage N-type MOS tube HN0 to be consistent with the source potential of the high-voltage N-type MOS tube HN2, so that the drain-source voltage of the high-side high-voltage N-type MOS tube HN0 is equal to the drain-source voltage of the high-voltage N-type MOS tube HN2, i.e., the V DS of the high-side high-voltage N-type MOS tube HN0 is equal to the V

[0070] As shown in Figure 4As shown, when the high-side driving module HS DRV sends a cutoff signal to the high-side high-voltage N-type MOS tube HN0, i.e. when the high-side high-voltage N-type MOS tube HN0 is in a cutoff state, the gate terminal potential of the high-side high-voltage N-type MOS tube HN0 approaches the ground terminal potential (GND), and the isolation circuit 131 is also in a cutoff state, for disconnecting the connection between the gate terminal of the high-side high-voltage N-type MOS tube HN0 and the gate terminal of the high-voltage N-type MOS tube HN2, preventing the gate terminal potential of the high-voltage N-type MOS tube HN2 from changing to the ground terminal potential, avoiding the potential difference between the gate terminal and the source terminal of the high-voltage N-type MOS tube HN2 exceeding the range of ±5V, and preventing the gate terminal of the high-voltage N-type MOS tube HN2 from being broken down, so the isolation circuit 131 bears the large voltage difference between the gate terminal of the high-side high-voltage N-type MOS tube HN0 and the gate terminal of the high-voltage N-type MOS tube HN2.

[0071] When the high-side driving module HS DRV sends a driving signal to the high-side high-voltage N-type MOS tube HN0, and the terminal voltage of the high-side high-voltage N-type MOS tube HN0 and the terminal voltage of the high-voltage N-type MOS tube HN2 are both kept consistent, the high-voltage N-type MOS tube HN2 will conduct a sampling current through the isolation circuit 131.

[0072] The working mode of the MOS tube includes an amplification mode and a switching mode. In the embodiment, the high-voltage N-type MOS tubes HN0, HN1 and HN2 all work in the switching mode, at which time the channel between the source and the drain will present a linear resistance characteristic. The on-resistance R DSON The calculation formula is as follows:

[0073]

[0074] Wherein, μ and C ox are process parameters, W and L are the gate width and gate length of the MOS tube respectively, V GS is the working voltage difference between the gate G and the source S of the MOS tube, and V TH is the on-voltage value of the MOS tube, which is determined by the process and the device type.

[0075] If at this time a voltage V DS is applied between the source and the drain of the MOS tube, its on-current I DS is represented as:

[0076]

[0077] As can be seen from the above formula, under the known process conditions (μ, C OX , V TH are determined), the on-current I DS of the MOS tube working in the switching mode is proportional to W / L, and is inversely proportional to (VGS - V TH ) is proportional to V DS .

[0078] In the existing design circuit diagram, because the high-voltage N-type MOS tube HN2 is connected in series with the resistor, the V DS of the high-voltage N-type MOS tube HN2 is not equal to the V DS of the high-side high-voltage N-type MOS tube HN0, which results in that the ratio between the sampling current of the high-voltage N-type MOS tube HN2 and the on current of the high-side high-voltage N-type MOS tube HN0 is not equal to the ratio between their gate sizes, and the sampling current of the high-voltage N-type MOS tube HN2 is also related to the size of the resistor, thereby affecting the accuracy of the sampling current.

[0079] Therefore, when the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2 are of the same type (V TH ), and the V GS and V DS of the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2 are all the same, the current ratio of the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2 is equal to the ratio between their gate sizes, that is, the ratio between the on current of the high-side high-voltage N-type MOS tube HN0 and the sampling current of the high-voltage N-type MOS tube HN2 is equal to the ratio between the gate size of the high-side high-voltage N-type MOS tube HN0 and the gate size of the high-voltage N-type MOS tube HN2, the on current of the high-side high-voltage N-type MOS tube HN0 is denoted as I HN0 , the sampling current of the high-voltage N-type MOS tube HN2 is denoted as I HN2 , the gate size of the high-side high-voltage N-type MOS tube HN0 is denoted as , and the gate size of the high-voltage N-type MOS tube HN2 is denoted as , then

[0080] That is, when the high-voltage N-type MOS tube HN2 and the high-side high-voltage N-type MOS tube HN0 are both turned on, the potentials of the gate, source and drain of the high-voltage N-type MOS tube HN2 are respectively kept consistent with the corresponding potentials of the gate, source and drain of the high-side high-voltage N-type MOS tube HN0, that is, the working voltages V DS and V GS between the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2 are completely equal, and the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2 are high-voltage N-type MOS tubes of the same structure type, so the sampling current is not affected by the process conditions and the external environment (such as temperature), and can accurately indicate the on current of the high-side high-voltage N-type MOS tube HN0 according to the ratio between the gate sizes of the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2.

[0081] Referring to Figure 5 and Figure 6 , wherein the t1-t2 time period is used to indicate that the high-side high-voltage N-type MOS tube is in the off state, and the low-side high-voltage N-type MOS tube HN1 is in the on state, and the t2-t3 time period is used to indicate that the high-side high-voltage N-type MOS tube HN0 is in the on state, and the low-side high-voltage N-type MOS tube HN1 is in the off state. Figure 5 In the equation hn0_g indicates the gate potential of the high-side high-voltage N-type MOS tube HN0, hn2_g indicates the gate potential of the high-voltage N-type MOS tube HN2, and pwm indicates the input signal for controlling the on state of the high-side high-voltage N-type MOS tube HN0, Figure 6 In the equation hn2_s indicates the source potential of the high-voltage N-type MOS tube HN2, SW indicates the potential of the half-side output port, and SW indicates the source potential of the high-side high-voltage N-type MOS tube HN0.

[0082] From Figure 5 and Figure 6 , it can be seen that when the high-side high-voltage N-type MOS tube HN0 is in the on state, the gate potential and the source potential between the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2 are equal, that is, their V GS and V DS are equal. Therefore, according to the formula, according to the sampling current collected by the high-voltage N-type MOS tube HN2, and the ratio of the gate size between the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2, the on current of the high-side high-voltage N-type MOS tube HN0 can be obtained, such as the ratio between the gate size (W HN0 / L HN0 ) of the high-side high-voltage N-type MOS tube HN0 and the gate size (W HN2 / L HN2 ) of the high-voltage N-type MOS tube HN2 is n, then the sampling current of the high-voltage N-type MOS tube HN2 is equal to 1 / n of the on current of the high-side high-voltage N-type MOS tube HN0, that is, the sampling current can be used to accurately indicate the on current of the high-side high-voltage N-type MOS tube HN0.

[0083] In one embodiment, the isolation circuit 131 includes a first isolation transistor and a second isolation transistor, the drain of the first isolation transistor is electrically connected to the gate of the to-be-measured transistor, the gate of the first isolation transistor is electrically connected to the source of the sampling transistor, and the source of the first isolation transistor is electrically connected to the gate of the sampling transistor.

[0084] The gate terminal and the source terminal of the second isolation transistor are both electrically connected to the gate terminal of the sampling transistor, and the drain terminal of the second isolation transistor is electrically connected to the source terminal of the sampling transistor.

[0085] Specifically, such as Figure 7 As shown, when the high-side high-voltage N-type MOS transistor HN0 is turned on, since the gate terminal hn0_g of HN0 is higher than its source terminal SW by a driving voltage (the BOOT-SW voltage difference in the figure), the first isolation transistor HP1 uses the parasitic diode between its drain and source (shown by the dotted line in the figure) to trigger the first isolation transistor HP1 to turn on automatically, thereby short-circuiting the gate terminal of the high-side high-voltage N-type MOS transistor HN0 and the gate terminal of the high-voltage N-type MOS transistor HN2. At this time, the second isolation transistor LP1 does not work.

[0086] When high-side high-voltage N-type MOS transistor HN0 is turned off, the gate potential of high-side high-voltage N-type MOS transistor HN0 approaches ground potential. At this time, the parasitic diode of the first isolation transistor HP1 is reverse-biased and turned off, causing the first isolation transistor HP1 to also be turned off, thereby isolating and preventing the gate potential of high-voltage N-type MOS transistor HN2 from changing toward ground potential. The source and drain terminals of the first isolation transistor HP1 bear the significant voltage difference between the gate of high-voltage N-type MOS transistor HN2 and the gate of high-side high-voltage N-type MOS transistor HN0. Because the forward-bias voltage drop generated by the parasitic diode of the second isolation transistor LP1 (shown as a dashed line in the figure) does not exceed 0.7V, it can be used to limit the potential difference between the gate of high-voltage N-type MOS transistor HN2 and its source to no less than -0.7V, preventing the potential difference between the gate of high-voltage N-type MOS transistor HN2 and its source from exceeding the ±5V range and preventing the gate of high-voltage N-type MOS transistor HN2 from breakdown.

[0087] Therefore, the first isolation transistor HP1 and the second transistor LP1 jointly ensure that the gate-source voltage V GS It works within the voltage range of ±5V. That is, adding the first isolation transistor HP1 and the second transistor LP1 between the gate terminal of the high-voltage N-type MOS transistor HN2 and the gate terminal of HN0 can ensure that when the high-side high-voltage N-type MOS transistor HN0 is turned on, the operating voltage V GS The gate terminal of the high-voltage N-type MOS transistor HN2 is safely protected when the high-side high-voltage N-type MOS transistor HN0 is turned off.

[0088] In one embodiment, the regulating circuit 120 includes a feedback circuit and a timing control circuit 122 electrically connected to each other. The timing control circuit 122 is electrically connected to the potential shift circuit 110 and the transistor under test, respectively, and is configured to control the on / off state between the feedback circuit and the transistor under test according to the switching signal.

[0089] The feedback circuit is electrically connected with the timing control circuit and the sampling transistor respectively, and is configured to adjust the end voltage of the sampling transistor to be consistent with the end voltage of the transistor to be tested based on the on-off state between the transistor to be tested.

[0090] Specifically, the timing control circuit 122 is electrically connected with the source end of the high-side high-voltage N-type MOS tube HN0 and the potential translation circuit 110 respectively, and the feedback circuit is electrically connected with the source end of the high-voltage N-type MOS tube HN2.

[0091] When the high-side high-voltage N-type MOS tube HN0 is turned on, the timing control circuit 122 controls the on-off state between the feedback circuit and the high-side high-voltage N-type MOS tube HN0 to be turned on according to the switching signal, at this time, the feedback circuit adjusts the source end potential of the high-voltage N-type MOS tube HN2 to the output potential of the half-side output end SW, and keeps the source end potential of the high-side high-voltage N-type MOS tube HN0 consistent.

[0092] In one embodiment, the feedback circuit comprises an operational amplifier and a proportional adjustment circuit 121, the positive input end of the operational amplifier is electrically connected with the timing control circuit 122, the negative input end of the operational amplifier is electrically connected with the source end of the sampling transistor, and the output end of the operational amplifier is electrically connected with the proportional adjustment circuit 121; the proportional adjustment circuit 121 is electrically connected with the comparison circuit 140 and the source end of the sampling transistor respectively.

[0093] Specifically, as shown in Figure 8 The OP is used to indicate the operational amplifier, the positive input end of the operational amplifier is electrically connected with the source end of the high-side high-voltage N-type MOS tube HN0 through the timing control circuit 122, the negative input end of the operational amplifier is electrically connected with the source end of the high-voltage N-type MOS tube HN2, and the output end of the operational amplifier is electrically connected with the proportional adjustment circuit 121, based on the working principle of the negative feedback of the operational amplifier, when the high-side high-voltage N-type MOS tube HN0 and the timing control circuit 122 are both in the turned-on state, the operational amplifier OP controls the proportional adjustment circuit 121 through the negative feedback, so that the source end potential of the high-voltage N-type MOS tube HN2 is equal to the source end potential of the high-side high-voltage N-type MOS tube HN0, that is, the working voltage V DS of the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2 is equal.

[0094] When the high-side high-voltage N-type MOS tube HN0 and the timing control circuit 122 are both in the turned-off state, the potential of the positive and negative input ends of the operational amplifier is pulled up to the potential of the power supply port VPWR to enter the reset state.

[0095] Figure 9 andFigure 10 The internal structure of the operational amplifier OP is shown in FIG. 1. Since the positive and negative input terminals of the operational amplifier OP work near the supply port VPWR, the input terminals of the operational amplifier OP need to use an N-type differential pair, such as the differential pair composed of NPN transistors Q1 and Q2 as shown in FIG. 2, or the differential pair composed of low-voltage N-type MOS transistors LN30 and LN31 as shown in FIG. 3. Figure 9 The operational amplifier OP uses a sleeve-type common-source and common-gate amplification structure composed of MOS transistors LP20, LP21, HP20, HP21, HN20, HN21, LN20, LN21, etc., which can achieve high gain of the operational amplifier OP, reduce system offset of the input terminals of the operational amplifier, and ensure that the source voltage of the high-side high-voltage N-type MOS transistor HN0 is completely equal to the source voltage of the high-voltage N-type MOS transistor HN2. Figure 10

[0096] Figure 9 The input differential pair composed of NPN transistors can achieve higher gain and lower offset, but occupies a larger layout area and has a small current at the input terminal. The input differential pair composed of N-type MOS transistors occupies a smaller layout area and has no current at the input terminal. The design of the two types of input differential pairs can meet different application requirements as needed. Figure 10 In one embodiment, the timing control circuit 122 includes a first switch transistor, a second switch transistor, and a third switch transistor. The sources of the first switch transistor are respectively electrically connected to the positive input terminal of the operational amplifier and the drain of the third switch transistor. The gate of the first switch transistor is electrically connected to the potential translation circuit 110. The drain of the first switch transistor is electrically connected to the source of the transistor under test.

[0097] The gates of the second switch transistor are respectively electrically connected to the potential translation circuit 110 and the gate of the third switch transistor. The sources of the second switch transistor are respectively electrically connected to the supply port and the source of the third switch transistor. The drain of the second switch transistor is electrically connected to the negative input terminal of the operational amplifier.

[0098] Specifically, as shown in FIG. 4, HP4 is used to indicate the first switch transistor, LP2 is used to indicate the second switch transistor, and LP3 is used to indicate the third switch transistor. The switch signal includes first and second switch signals that are mutually inverted. The first switch signal is used to control the first switch transistor, and the second switch signal is used to control the second and third switch transistors.

[0099] Figure 11

[0100] ​​​Since the operational amplifier needs to be designed as high potential input according to the requirement of the regulating circuit architecture, the first switch transistor is needed to isolate the positive input end of the operational amplifier from the source end of the high-side high-voltage N-type MOS tube HN0. When the potential shifting circuit 110 sends the first switch signal indicating conduction to the first switch transistor, and sends the second switch signal indicating cut-off to the second switch transistor and the third transistor, the first switch transistor is turned on, the positive and negative input ends of the operational amplifier sample the source end potentials of the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2, and the second switch transistor and the third switch transistor are cut off, which will not interfere with the positive and negative input potentials of the operational amplifier.

[0101] When the potential shifting circuit 110 sends the first switch signal indicating cut-off to the first switch transistor, and sends the second switch signal indicating conduction to the second switch transistor and the third transistor, the potential of the half-side output port is pulled down to the ground potential by the low-side high-voltage N-type MOS tube HN1 which is turned on, the first switch transistor is cut off to block the low potential of the half-side output port from affecting the input end of the operational amplifier, and at the same time, the second switch transistor and the third switch transistor are turned on to pull up the positive and negative input ends of the operational amplifier to the potential of the power supply port VPWR to enter the reset state, so as to maintain the high potential input of the operational amplifier.

[0102] In one embodiment, as shown in FIG. 1, Figure 12 The potential shifting circuit 110 includes a Zener diode D1, a current source IB1, an inverter INV1, a first control transistor HN3, a second control transistor HN4, a third control transistor HP5, a fourth control transistor HP6, a fifth regulating transistor LP4, and a sixth regulating transistor LP5, which together constitute the potential shifting circuit 110, wherein:

[0103] The negative electrode of the Zener diode D1 is electrically connected to the power supply port VPWR, the positive electrode of the Zener diode D1 is grounded through the current source IB1, and the positive electrode of the Zener diode D1 is also electrically connected to the gate end of the third control transistor HP5 and the gate end of the fourth control transistor HP6.

[0104] The gate end of the first control transistor HN3 is electrically connected to the timing port and the input end of the inverter INV1, the source end of the first control transistor HN3 is commonly grounded with the source end of the second control transistor HN4, and the drain end of the first control transistor HN3 is electrically connected to the drain end of the third control transistor HP5.

[0105] The gate end of the second control transistor HN4 is electrically connected to the output end of the inverter INV1, and the drain end of the second control transistor HN4 is electrically connected to the drain end of the fourth control transistor HP6.

[0106] The gate terminal of the third control transistor HP5 is electrically connected with the gate terminal of the fourth control transistor HP6, the source terminal of the third control transistor HP5 is electrically connected with the drain terminal of the fifth regulating transistor LP4 and the first signal output terminal respectively, and the first signal output terminal is used for outputting a first switch signal.

[0107] The source terminal of the fourth control transistor HP6 is electrically connected with the drain terminal of the sixth regulating transistor LP5 and the second signal output terminal respectively, and the second signal output terminal is used for outputting a second switch signal.

[0108] The gate terminal of the fifth regulating transistor LP4 is electrically connected with the drain terminal of the sixth regulating transistor LP5, and the source terminal of the fifth regulating transistor LP4 is electrically connected with the power supply terminal VPWR.

[0109] The gate terminal of the sixth regulating transistor LP5 is electrically connected with the drain terminal of the fifth regulating transistor LP4, and the source terminal of the sixth regulating transistor LP5 is electrically connected with the power supply terminal VPWR.

[0110] Specifically, the low potential time sequence signal input by the time sequence port is converted and output as two high potential time sequence signals which are mutually inverse through the inverter INV1, the first control transistor HN3, the second control transistor HN4, the third control transistor HP5, the fourth control transistor HP6, the fifth regulating transistor LP4 and the sixth regulating transistor LP5, that is, the first switch signal and the second switch signal are obtained, the time sequence signal input by the time sequence port is recorded as the ISEN_ON signal, the first switch signal is recorded as the cn signal, and the second switch signal is recorded as the cp signal.

[0111] In the embodiment, when the ISEN_ON signal is high, the cn signal is used for turning on the first switch transistor HP4, and the cp signal is used for turning off the second switch transistor LP2 and the third switch transistor LP3, at this time, the positive and negative input terminals of the operational amplifier OP sample the source potential of the high-side high-voltage N-type MOS transistor HN0 and the high-voltage N-type MOS transistor HN2 respectively; when the ISEN_ON signal is low, the cn signal is used for turning off the first switch transistor HP4, and the cp signal is used for turning on the second switch transistor LP2 and the third switch transistor LP3, at this time, the positive and negative input terminals of the operational amplifier OP are pulled up to the potential of the power supply terminal VPWR and enter the reset state.

[0112] The PWM signal is an input signal for controlling the on-off state of the high-side high-voltage N-type MOS tube HN0 and the low-side high-voltage N-type MOS tube HN1. In the embodiment, when the PWM signal is at a high level, the high-side high-voltage N-type MOS tube HN0 is turned on, and the low-side high-voltage N-type MOS tube HN1 is turned off, at which time the potential of the half-side output port SW is pulled up to the potential of the power supply port VPWR; when the PWM signal is at a low level, the high-side high-voltage N-type MOS tube HN0 is turned off, and the low-side high-voltage N-type MOS tube HN1 is turned on, at which time the potential of the half-side output port SW is pulled down to the ground potential.

[0113] The timing sequence waveform diagram of the ISEN_ON signal, the cn signal, the cp signal, and the PWM signal can refer to Figure 13 , wherein the t1-t2 time period indicates that the high-side high-voltage N-type MOS tube HN0 is in an off state, and the low-side high-voltage N-type MOS tube HN1 is in an on state, and the t2-t3 time period indicates that the high-side high-voltage N-type MOS tube HN0 is in an on state, and the low-side high-voltage N-type MOS tube HN1 is in an off state.

[0114] Referring to Figure 13 , there is a slight delay between the rising edge / falling edge of the ISEN_ON signal and the rising edge / falling edge of the PWM signal, and the PWM signal rises earlier than the ISEN_ON signal, so as to ensure that the high-side high-voltage N-type MOS tube HN0 is turned on for a period of time based on the PWM signal, and then the first switch transistor is turned on by the ISEN_ON signal to sample the stable on current; the ISEN_ON signal falls earlier than the PWM signal, so as to ensure that the first switch transistor is turned off before the potential of the half-side output port SW is pulled down to the ground potential, and the connection between the source end of the high-side high-voltage N-type MOS tube HN0 and the positive input end of the operational amplifier OP is disconnected, and at the same time, the positive and negative input ends of the operational amplifier OP are pulled up to the potential of the power supply port VPWR for safe protection.

[0115] In one embodiment, the proportional adjustment circuit includes a first adjustment transistor and a plurality of second adjustment transistors connected in parallel with the first adjustment transistor, the gate end of the first adjustment transistor is electrically connected with the output end of the operational amplifier and the gate end of the second adjustment transistor, the source end of the first adjustment transistor is electrically connected with the source end of the sampling transistor and the source end of the second adjustment transistor, the drain end of the first adjustment transistor is electrically connected with the comparison circuit, and the drain end of the second adjustment transistor is grounded.

[0116] Specifically, as Figure 14 shown, the proportional adjustment circuit 121 includes a first adjustment transistor HP2 and can further include a plurality of second adjustment transistors connected in parallel with the first adjustment transistor. The second transistors are connected in parallel to proportionally shunt the sampling current, and the proportional adjustment circuit 121 is connected in parallel with the first adjustment transistor.Figure 15 The proportional adjusting circuit 121 comprises first adjusting transistor HP2 and second adjusting transistor HP3 connected in parallel, HP2 and HP3 are high-voltage P-type MOS transistors of the same structure type, the source end of the first adjusting transistor HP2 is electrically connected with the source end of the high-voltage N-type MOS transistor HN2, the negative input end of the operational amplifier OP and the source end of the second adjusting transistor HP3 respectively, the gate end of the first adjusting transistor HP2 is electrically connected with the gate end of the second adjusting transistor HP3 and the output end of the operational amplifier OP, and the drain end of the first adjusting transistor HP2 is electrically connected with the comparison circuit 140. The source end of the second adjusting transistor HP3 is electrically connected with the source end of the high-voltage N-type MOS transistor HN2 and the negative input end of the operational amplifier OP respectively, and the drain end of the second adjusting transistor HP3 is grounded.

[0117] When the MOS transistor works in the amplification mode, its source-drain current formula is as follows:

[0118]

[0119] The first adjusting transistor HP2 and the second adjusting transistor HP3 both work in the amplification mode, since the gate ends of the first adjusting transistor HP2 and the second adjusting transistor HP3 are connected, and the source ends of the first adjusting transistor HP2 and the second adjusting transistor HP3 are connected with the source end of the high-voltage N-type MOS transistor HN2, so the gate-source voltages V GS of the first adjusting transistor HP2 and the second adjusting transistor HP3 are the same. Combined with the formula, the current ratio between the first adjusting transistor HP2 and the second adjusting transistor HP3 is equal to the gate size ratio of the first adjusting transistor HP2 and the second adjusting transistor HP3. Therefore, if the ratio between the gate size (W HP3 / L HP3 ) of the second adjusting transistor HP3 and the gate size (W HP2 / L HP2 ) of the first adjusting transistor HP2 is m, then the shunt current generated by the first adjusting transistor HP2 is equal to 1 / m of the shunt current of the second adjusting transistor HP3, and the shunt current generated by the first adjusting transistor HP2 is equal to 1 / (m+1) of the sampling current of the high-voltage N-type MOS transistor HN2, equal to 1 / n(m+1) of the on current of the high-side high-voltage N-type MOS transistor HN0, and the overcurrent threshold I OCP_HN0 of the high-side high-voltage N-type MOS transistor HN0 is equal to 1 / n(m+1) of the on current of the high-side high-voltage N-type MOS transistor HN0. The calculation formula is as follows:

[0120]

[0121] The shunt current generated by the first adjusting transistor HP2 is sent to the comparison circuit for comparison with the reference signal, so as to generate a corresponding overcurrent detection signal, the overcurrent detection signal is used to indicate whether the on current of the high-side high-voltage N-type MOS transistor HN0 exceeds the corresponding overcurrent threshold, and whether a corresponding off signal needs to be generated is judged according to the overcurrent detection signal.

[0122] Figure 15 Corresponding circuit is suitable for application case that the minimum size limit of high-voltage N-type MOS tube HN2 cannot meet the proportional relationship between the sampling current and the conduction current, or the current proportion is not accurate due to the excessive proportion of the gate size of high-side high-voltage N-type MOS tube HN0 and high-voltage N-type MOS tube HN2, and the sampling current cannot be further reduced. At this time, multiple parallel regulating transistors need to be added to proportionally shunt the sampling current.

[0123] In one embodiment, the comparison circuit 140 includes a comparison resistor, a reference voltage source, and a comparator. The first end of the comparison resistor is electrically connected to the drain of the regulating transistor and the positive input of the comparator, respectively. The second end of the comparison resistor is electrically connected to the negative input of the comparator through the reference voltage source, and is also grounded.

[0124] The comparison resistor is used to generate a corresponding sampling voltage based on the sampling current flowing therethrough.

[0125] The reference voltage source is used to output a reference voltage, wherein the reference signal includes the reference voltage.

[0126] The comparator is used to generate the overcurrent detection signal based on the comparison result of the sampling voltage and the reference voltage.

[0127] Specifically, as shown in Figure 16 R1 is used to indicate the comparison resistor, VREF is used to indicate the reference voltage source, and COMP is used to indicate the comparator. The sampling current generates a voltage drop through the comparison resistor, i.e., generates a corresponding sampling voltage. The comparator compares the sampling voltage with the reference voltage output by the reference voltage source, and outputs an overcurrent detection signal according to the comparison result. According to the overcurrent detection signal, it is determined whether the conduction current of the high-side high-voltage N-type MOS tube HN0 exceeds the overcurrent threshold value. When the overcurrent detection signal is high, it indicates that the sampling voltage is greater than the reference voltage, and also indicates that the conduction current of the high-side high-voltage N-type MOS tube HN0 is greater than the overcurrent threshold value. When the overcurrent detection signal is low, it indicates that the sampling voltage is less than or equal to the reference voltage, and also indicates that the conduction current of the high-side high-voltage N-type MOS tube HN0 is less than or equal to the overcurrent threshold value.

[0128] From Figure 16 The overcurrent threshold value I of the high-side high-voltage N-type MOS tube HN0 can be calculated as follows: OCP_HN0

[0129]

[0130] Wherein, n represents the gate size ratio between the high-side high-voltage N-type MOS tube HN0 and the high-voltage N-type MOS tube HN2. ​

[0131] In one embodiment, the comparison circuit 140 further comprises a plurality of resistance branches in parallel with the comparison resistance, each of the resistance branches comprising a shunt resistance and a switch in series.

[0132] Specifically, on the basis of Figure 16 , a programmable design of overcurrent detection can be realized by adding a plurality of resistance branches in parallel with the comparison resistance, as shown in Figure 17 , wherein the first end of each shunt resistance R2 to Rn is connected to the first end of the comparison resistance, and the second end of each shunt resistance R2 to Rn is connected to ground in series with a switch. Each switch can be realized by a normal low-voltage N-type MOS tube working in switch mode, or other devices or integrated circuits that can realize switch function can also be used.

[0133] In the above embodiment, overcurrent detection is realized by comparing the sampling voltage generated by the sampling current flowing through the resistance with the reference voltage. The overcurrent threshold of the high-side high-voltage N-type MOS tube HN0 can be calculated by the known reference voltage and resistance size, as shown in Figure 17 , by controlling the on-off state of the switches sw2 to swn, the parallel connection of any one shunt resistance or multiple shunt resistances R2 to Rn with the comparison resistance can be realized, and the resistance value of the resistance through which the sampling current flows is changed. Combined with the known reference voltage and the gate size ratio, different overcurrent thresholds of the high-side high-voltage N-type MOS tube HN0 can be designed, thereby facilitating the application of various electronic products with different overcurrent threshold requirements. Figure 17 , assuming that the corresponding state value is equal to 1 when the switch is closed, and the corresponding state value is equal to 0 when the switch is open, then the programmable overcurrent threshold I OCP_HN0 of the high-side high-voltage N-type MOS tube HN0 can be expressed as follows:

[0134]

[0135] By setting the corresponding state value of each switch, the overcurrent threshold of the high-side high-voltage N-type MOS tube HN0 can be flexibly configured to adapt to different application scenarios.

[0136] In the above embodiment, overcurrent detection is realized by comparing the voltage generated by the sampling current flowing through the resistance with the reference voltage, as shown in Figure 18 , the sampling current can also be compared with the reference current IREF after being scaled by the low-voltage N-type MOS tube LN40 and the low-voltage N-type MOS tube LN41, and the overcurrent detection signal OCP_OUT is obtained through the logic gate INV. The low-voltage N-type MOS tube LN40 and the low-voltage N-type MOS tube LN41 work in amplification mode, and the gate-source voltage V GS between them is equal, so if the gate size (WLN40 / L LN40 ) and the gate size (W LN41 / L LN41 ) of the low-voltage N-type MOS transistor LN41 is k, then the over-current threshold I OCP_HN0 The calculation formula is as follows:

[0137] I OCP_HN0 = nkI REF

[0138] That is, the designed over-current threshold is used to determine the trigger condition of the turn-off signal for the conduction current of the high-side high-voltage N-type MOS transistor HN0 in different application scenarios.

[0139] It should be noted that, in this document, relational terms such as“first” and“second”, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between or among the entities or actions. Moreover, the terms“comprises”,“comprising”, or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, over-current detection circuit, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, over-current detection circuit, article, or apparatus. An element proceeded by“comprises a...” does not, without more constraints, exclude the existence of additional identical elements in the process, over-current detection circuit, article, or apparatus that comprises the element.

[0140] The above description is merely one specific implementation of the application, and persons skilled in the art can understand or implement the application based on the above description. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An overcurrent detection circuit, characterized by comprising: The overcurrent detection circuit comprises: a potential translation circuit configured to generate a switching signal according to a received timing signal; an adjustment circuit electrically connected to the potential translation circuit, the sampling circuit and the transistor to be tested, and configured to adjust an end voltage of the sampling circuit to be consistent with an end voltage of the transistor to be tested according to the switching signal sent by the potential translation circuit; the sampling circuit is electrically connected to the transistor to be tested in the full-bridge circuit, and is configured to sample a conduction current of the transistor to be tested when the end voltage of the sampling circuit is consistent with the end voltage of the transistor to be tested, to obtain a sampling current; a comparison circuit electrically connected to the sampling circuit through the adjustment circuit, and configured to generate an overcurrent detection signal based on a comparison result of the sampling current and a reference signal; the sampling circuit comprises an isolation circuit and a sampling transistor, the isolation circuit is electrically connected to a gate end of the transistor to be tested and a gate end of the sampling transistor, a drain end of the sampling transistor is electrically connected to a drain end of the transistor to be tested and a power supply port, and a source end of the sampling transistor is electrically connected to the adjustment circuit; the isolation circuit is configured to short the gate end of the transistor to be tested and the gate end of the sampling transistor when a driving signal is detected, and isolate the gate end of the transistor to be tested and the gate end of the sampling transistor when an off signal is detected; the sampling transistor is configured to sample the conduction current of the transistor to be tested to obtain the sampling current; the isolation circuit comprises a first isolation transistor and a second isolation transistor, a drain end of the first isolation transistor is electrically connected to the gate end of the transistor to be tested, a gate end of the first isolation transistor is electrically connected to the source end of the sampling transistor, and a source end of the first isolation transistor is electrically connected to the gate end of the sampling transistor, a gate end and a source end of the second isolation transistor are electrically connected to the gate end of the sampling transistor, and a drain end of the second isolation transistor is electrically connected to the source end of the sampling transistor.

2. The overcurrent detection circuit according to claim 1, characterized by the adjustment circuit comprises a feedback circuit and a timing control circuit electrically connected, the timing control circuit is electrically connected to the potential translation circuit and the transistor to be tested, and is configured to control a pass-through state between the feedback circuit and the transistor to be tested according to the switching signal; the feedback circuit is electrically connected to the timing control circuit and the sampling transistor, and is configured to adjust the end voltage of the sampling transistor to be consistent with the end voltage of the transistor to be tested based on the pass-through state between the transistor to be tested.

3. The overcurrent detection circuit of claim 2, wherein the feedback circuit comprises an operational amplifier and a proportional adjustment circuit, a positive input end of the operational amplifier is electrically connected to the timing control circuit, a negative input end of the operational amplifier is electrically connected to the source end of the sampling transistor, and an output end of the operational amplifier is electrically connected to the proportional adjustment circuit; the proportional adjustment circuit is electrically connected to the comparison circuit and the source end of the sampling transistor.

4. The overcurrent detection circuit of claim 3, wherein The timing control circuit comprises a first switch transistor, a second switch transistor and a third switch transistor, source ends of the first switch transistor are electrically connected with a positive input end of the operational amplifier and a drain end of the third switch transistor respectively, a gate end of the first switch transistor is electrically connected with the potential translation circuit, and a drain end of the first switch transistor is electrically connected with a source end of the transistor to be tested. Gate ends of the second switch transistor are electrically connected with the potential translation circuit and a gate end of the third switch transistor respectively, source ends of the second switch transistor are electrically connected with the power supply port and a source end of the third switch transistor respectively, and a drain end of the second switch transistor is electrically connected with a negative input end of the operational amplifier.

5. The overcurrent detection circuit of claim 3, wherein The proportional adjustment circuit comprises a first adjustment transistor and a plurality of second adjustment transistors connected in parallel with the first adjustment transistor, a gate end of the first adjustment transistor is electrically connected with an output end of the operational amplifier and a gate end of the second adjustment transistor respectively, source ends of the first adjustment transistor are electrically connected with source ends of the sampling transistor and the second adjustment transistor respectively, a drain end of the first adjustment transistor is electrically connected with the comparison circuit, and drain ends of the second adjustment transistor are grounded.

6. The overcurrent detection circuit of claim 5, wherein, The comparison circuit comprises a comparison resistor, a reference voltage source and a comparator, a first end of the comparison resistor is electrically connected with a drain end of the adjustment transistor and a positive input end of the comparator respectively, a second end of the comparison resistor is electrically connected with a negative input end of the comparator through the reference voltage source, and the second end of the comparison resistor is also grounded. The comparison resistor is used for generating a corresponding sampling voltage based on the sampling current flowing therethrough. The reference voltage source is used for outputting a reference voltage, wherein the reference signal comprises the reference voltage. The comparator is used for generating the overcurrent detection signal based on a comparison result of the sampling voltage and the reference voltage.

7. The overcurrent detection circuit of claim 6, wherein The comparison circuit further comprises a plurality of resistance branches connected in parallel with the comparison resistor, each of the resistance branches comprises a shunt resistor and a switch connected in series.

8. A wireless charging device, comprising: The power supply module and the electric energy transmission circuit are electrically connected, the electric energy transmission circuit comprises a full-bridge circuit and the overcurrent detection circuit according to any one of claims 1-7.

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