Semiconductor structure, method of manufacturing the same, and semiconductor memory device
By using atomic layer deposition and in-situ water vapor generation processes to form an oxide layer in DRAM, combined with multiple etching techniques, the problem of the gate insulating layer being difficult to shrink during DRAM miniaturization was solved, resulting in smaller size and more stable electrical performance.
CN114899093BActive Publication Date: 2026-07-24CHANGXIN MEMORY TECH INC
View PDF 2 Cites 0 Cited by
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-29
- Publication Date
- 2026-07-24
AI Technical Summary
Technical Problem
When DRAM technology nodes fall below 15nm, it becomes difficult to miniaturize the gate insulating layer and gate electrode, leading to increased leakage current and affecting electrical performance.
Method used
The first oxide layer is formed by atomic layer deposition, and the second oxide layer is formed by in-situ water vapor generation. The first oxide layer is removed layer by layer by multiple etching processes. The second oxide layer is used as an etching stop layer to ensure that the surface of the second oxide layer is flat and uniform.
Benefits of technology
It achieves the ability to accommodate gate electrodes, reduce leakage current, and improve electrical performance even when DRAM technology nodes are below 15nm.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN114899093B_ABST
Abstract
The embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof and a semiconductor storage device. The preparation method comprises: providing a semiconductor substrate, the semiconductor substrate having a trench; forming a first oxide layer on the inner wall of the trench by using an atomic layer deposition process; forming a second oxide layer between the first oxide layer and the inner wall of the trench by using an in-situ water vapor generation process, the second oxide layer and the second oxide layer being of the same material; and etching and removing part of the first oxide layer by using an etching process with the second oxide layer as an etching stop layer, and repeatedly performing the etching process for multiple times until the first oxide layer is completely removed. The preparation method of the present disclosure can accurately control the complete removal of the first oxide layer without damaging the surface of the second oxide layer, so as to make the surface of the finally exposed second oxide layer flat, reduce the size of the gate insulating layer, and improve the electrical performance of the semiconductor structure.
Need to check novelty before this filing date? Find Prior Art