Display panel and display device

Abstract

This invention provides a display panel and a display device. The demultiplexing transistor in the display panel includes a source, a drain, an active pattern, a first gate, and a second gate. The source and drain are located on one side of the active pattern, the first gate is located on one side of the active pattern, and the second gate is located on one side of the active pattern. The active pattern is electrically connected to the source and drain through vias within a via region. The first gate and the second gate are loaded with operating voltages of different polarities. When this demultiplexing transistor is working, the different polarities of the operating voltages loaded on the first gate and the second gate allow for adjustment and control of the threshold voltage of the entire demultiplexing transistor, effectively alleviating the technical problem of poor stability in existing demultiplexing transistors.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Medium and large-sized display panels are equipped with demultiplexing circuits (i.e., demux circuits in the following text). The demultiplexing control switch (i.e., muxTFT in the following text) operates under positive voltage for a long time. The threshold voltage Vth of the muxTFT will be forward biased, which will reduce the stability of the demultiplexing circuit and thus lead to display abnormalities.

[0003] Therefore, the existing demultiplexing control switch has a technical problem of poor stability and needs to be improved. Summary of the Invention

[0004] The present invention provides a display panel and a display device to alleviate the technical problem of poor stability in existing demultiplexing control switches.

[0005] To solve the above problems, the technical solution provided by the present invention is as follows:

[0006] This invention provides a display panel, the display panel including a demultiplexing circuit, the demultiplexing circuit including a demultiplexing transistor; wherein:

[0007] The demultiplexing transistor includes a source, a drain, an active pattern, a first gate, and a second gate. The source and the drain are located on one side of the active pattern, the first gate is located on one side of the active pattern, and the second gate is located on one side of the active pattern. The active pattern is electrically connected to the source and the drain through vias in the via region.

[0008] In the same demultiplexing transistor, the first gate and the second gate are spaced apart, and the first region where the orthogonal projection of the second gate on the active pattern is located is between the second region where the orthogonal projection of the first gate on the active pattern is located and the via region.

[0009] In the display panel provided in the embodiments of the present invention, the first gate and the second gate are disposed on the same layer.

[0010] In the display panel provided in the embodiments of the present invention, the second gate includes a first sub-gate and a second sub-gate, and the first gate is located between the first sub-gate and the second sub-gate.

[0011] In the display panel provided in the embodiments of the present invention, the first sub-gate and the second sub-gate have the same orthographic projection on the active pattern.

[0012] In the display panel provided in this embodiment of the invention, the first sub-gate and the second sub-gate are loaded with the same operating voltage.

[0013] In the display panel provided in the embodiments of the present invention, the first gate and the second gate are loaded with operating voltages of different polarities.

[0014] In the display panel provided in this embodiment of the invention, the polarity of the working voltage applied to the first gate is positive, and the polarity of the working voltage applied to the second gate is negative.

[0015] In the display panel provided in this embodiment of the invention, the operating voltage range of the first gate is 0 to 30 volts, and the operating voltage range of the second gate is -30 volts to -1 volt.

[0016] In the display panel provided in the embodiments of the present invention, the display panel includes a compensation driving circuit, which is used to adjust the operating voltage of the second gate loading according to the threshold voltage of the demultiplexing transistor.

[0017] Furthermore, this application also provides a display device that includes the display panel described in the above embodiments.

[0018] The beneficial effects of this invention are as follows: This invention provides a display panel and a display device. The demultiplexing transistor in the display panel includes a source, a drain, an active pattern, a first gate, and a second gate. The source and the drain are located on one side of the active pattern, the first gate is located on one side of the active pattern, and the second gate is located on one side of the active pattern. The active pattern is electrically connected to the source and the drain through vias in the via region. In the same demultiplexing transistor, the first gate and the second gate are spaced apart, and the first gate and the second gate are loaded with operating voltages of different polarities. Based on the fact that the threshold voltage Vth offset of the transistor is related to the sign and magnitude of the operating voltage, when the demultiplexing transistor is working, the first gate and the second gate are loaded with operating voltages of different polarities. This allows for the adjustment and control of the threshold voltage of the entire demultiplexing transistor, effectively alleviating the technical problem of poor stability in existing demultiplexing transistors and improving circuit stability. Attached Figure Description

[0019] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0020] Figure 1 A schematic cross-sectional view of a demultiplexing transistor in the prior art;

[0021] Figure 2This is a circuit diagram of a demultiplexing circuit in the prior art;

[0022] Figure 3 This is a timing diagram of a demultiplexing circuit in the prior art.

[0023] Figure 4 A cross-sectional schematic diagram of a demultiplexing transistor provided in an embodiment of the present invention;

[0024] Figure 5 An equivalent circuit diagram of a demultiplexing transistor provided in an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of parameters of a demultiplexing transistor provided in an embodiment of the present invention;

[0026] Figure 7 A circuit diagram of a demultiplexing circuit provided in an embodiment of the present invention;

[0027] Figure 8 This is a schematic diagram of the working timing of a demultiplexing circuit provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0030] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0031] Figure 1 This diagram illustrates a cross-sectional view of a demultiplexing transistor provided for the prior art. The diagram uses a top-gate (gate above the active layer pattern) structure transistor as an example. Other structures such as bottom-gate (gate below the active layer pattern) have similar technical problems and will not be described in detail here.

[0032] Please see Figure 1 The demultiplexing transistor, from bottom to top, comprises: a substrate m1, a buffer layer m2, a first insulating layer m3, an active layer pattern m4 (formed by patterning an entire surface of the active layer; in this application, the active layer pattern is made of metal oxides such as indium gallium zinc oxide), a second insulating layer m5, a gate m6, a third insulating layer m7, a source m81, and a drain m82. For ease of explanation below, the active layer pattern is spatially divided into a first via region S11 (corresponding to the connection region of the source m81), a second via region S12 (corresponding to the connection region of the drain m82), an active region S13 (corresponding to the orthographic projection region of the gate m6 on the active layer pattern m4), a first conductive region S14 located between the first via region S11 and the active region S13, and a second conductive region S15 located between the second via region S12 and the active region S13.

[0033] During the fabrication process, the first conductive region S14 and the second conductive region S15 need to be conductive to reduce the resistance of the active layer and ensure the normal transport of electrons in the channel (the part of the active layer pattern m4 in the active region S13). The process is relatively complex.

[0034] Figure 2 A circuit diagram of a demultiplexing circuit provided by the prior art. Figure 3 A timing diagram of a demultiplexing circuit provided for existing technology; such as Figure 2 as well as Figure 3As shown, the demultiplexing circuit 20 includes at least demultiplexing transistor 21a and demultiplexing transistor 21b, and the signal output terminal of each demultiplexing transistor is connected to a data signal line (e.g., Figure 2 As shown, the signal output terminal of demultiplexing transistor 21a is connected to data signal line 22a, the signal output terminal of demultiplexing transistor 21b is connected to data signal line 22b, the signal input terminal of demultiplexing transistor is connected to data driver chip 30, and the control terminal of each demultiplexing transistor is connected to control signal line (e.g., ...). Figure 2 As shown, the control terminal of demultiplexing transistor 21a is connected to control signal line 23a, and the control output terminal of demultiplexing transistor 21b is connected to control signal line 23b, as follows. Figure 3 As shown, the operating voltage of the demultiplexing transistor (i.e., the voltage when the control signals EN1 and EN2 turn on the corresponding transistors) is positive, generally around 20V. If the demultiplexing transistor operates under positive voltage for a long time, its threshold voltage Vth will become positively biased, causing the stability of the demultiplexing circuit to decrease, which in turn leads to display abnormalities.

[0035] Existing demultiplexing control switches suffer from poor stability, a problem that can be alleviated by the embodiments of the present invention.

[0036] Specifically, the display panel provided in this application includes a demultiplexing circuit, which includes a demultiplexing transistor; wherein:

[0037] The demultiplexing transistor includes a source, a drain, an active pattern, a first gate, and a second gate. The source and the drain are located on one side of the active pattern, the first gate is located on one side of the active pattern, and the second gate is located on one side of the active pattern. The active pattern is electrically connected to the source and the drain through vias in the via region.

[0038] In the same demultiplexing transistor, the first gate and the second gate are spaced apart, and the first gate and the second gate are loaded with operating voltages of different polarities.

[0039] This embodiment provides a display panel in which a demultiplexed transistor includes a source, a drain, an active pattern, a first gate, and a second gate. The source and drain are located on one side of the active pattern, the first gate is located on one side of the active pattern, and the second gate is located on one side of the active pattern. The active pattern is electrically connected to the source and drain through vias within a via region. In the same demultiplexed transistor, the first gate and the second gate are spaced apart, and the first gate and the second gate are loaded with operating voltages of different polarities. Based on the fact that the threshold voltage Vth offset of a transistor is related to the sign and magnitude of the operating voltage, when the demultiplexed transistor is working, the first gate and the second gate are loaded with operating voltages of different polarities. This allows for adjustment and control of the threshold voltage of the entire demultiplexed transistor, effectively alleviating the poor stability problem of existing demultiplexed transistors and improving circuit stability.

[0040] Figure 4 This is a cross-sectional schematic diagram of a demultiplexing transistor provided in an embodiment of the present invention. The diagram uses a top-gate (gate above the active layer pattern) structure transistor as an example for illustration. Other structures such as bottom-gate (gate below the active layer pattern) transistors have similar technical problems and will not be described further. Figure 4 As shown, in one embodiment, the display panel provided by this embodiment of the invention includes a plurality of pixel driving circuits, each of the pixel driving circuits including a demultiplexing transistor, wherein:

[0041] The demultiplexing transistor, from bottom to top, comprises: a substrate m1, a buffer layer m2, a first insulating layer m3, an active layer pattern m4 (formed by patterning an entire surface of the active layer; in this application, the material of the active layer pattern is a metal oxide such as indium gallium zinc oxide), a second insulating layer m5, a first gate m61, and a second gate (including...). Figure 4 The active layer pattern includes a first sub-gate m62 and a second sub-gate m63, a third insulating layer m7, a source m81, and a drain m82. For ease of explanation below, the active layer pattern is spatially divided into via regions (including a first via region S11 corresponding to the connection region of the source m81, a second via region S12 corresponding to the connection region of the drain m82, and a second region S13 (i.e., the first via region S11 corresponding to the connection region of the source m81, the second via region S12 corresponding to the connection region of the drain m82, and the second via region S13 corresponding to the connection region of the drain m82). Figure 1 The active region S13 corresponds to the orthographic projection region of the first gate m61 on the active layer pattern m4, and the first region (including the orthographic projection region S16 corresponding to the first sub-gate m62 on the active layer pattern m4 and the orthographic projection region S17 corresponding to the second sub-gate m63 on the active layer pattern m4) are shown in the figure. The spatial relative positions of each region are as follows: Figure 4As shown, further details are omitted. In the same demultiplexing transistor, the first gate and the second gate are spaced apart, and the first gate and the second gate are loaded with operating voltages of different polarities.

[0042] Operating voltages with different polarities refer to voltages that are positive and negative.

[0043] Figure 5 An equivalent circuit diagram of a demultiplexing transistor provided in an embodiment of the present invention; Figure 4 The equivalent circuit of the demultiplexing transistor shown is as follows: Figure 5 As shown, the equivalent circuit corresponding to the demultiplexing transistor is formed by three sub-transistors connected in series. These are: the first sub-transistor T11, which is formed by the first sub-gate m62 and the active layer pattern in the orthographic projection region S16; the second sub-transistor T12, which is formed by the first gate m61 and the active layer pattern in the second region S13; and the third sub-transistor T13, which is formed by the second sub-gate m63 and the active layer pattern in the orthographic projection region S17. In this circuit, when the demultiplexing transistor is working, the resistance of each sub-transistor T11, the second sub-transistor T12, and the third sub-transistor T13 are all turned on, and the resistance of the entire demultiplexing transistor is approximately 0. Compared with the prior art, the resistance of the demultiplexing transistor is significantly reduced. According to I = U / R, U is the voltage across the source and drain, Vds. Since Vds remains unchanged, the total resistance R decreases, so the total current I increases, that is, the on-state current (Ion) increases. At the same time, since it is not necessary to perform conductor processing on the first region (including the orthographic projection region S16 corresponding to the first sub-gate m62 on the active layer pattern m4 and the orthographic projection region S17 corresponding to the second sub-gate m63 on the active layer pattern m4), one conductor processing step can be reduced.

[0044] Figure 6 This is a schematic diagram of the parameters of a demultiplexing transistor provided in an embodiment of the present invention; as shown below. Figure 6 It can be seen that when a normal gate control signal (e.g., +20V) is applied to the first gate m61, the gate control signal Vg1 applied to the first sub-gate m62 is linearly negatively correlated with the threshold voltage Vth of the entire demultiplexing transistor. Figure 6 By fitting the sample points shown, we can obtain... Figure 6 The dashed line in the code; the function corresponding to this dashed line is as follows:

[0045] y = -0.324x + 1.87;

[0046] Where y represents the threshold voltage Vth, x represents the gate control signal Vg1, and the goodness of fit is 0.9625. The closer the goodness of fit is to 1, the better the fit effect.

[0047] according to Figure 6 As can be seen, to prevent the demux TFT from being easily forward biased, this application can apply a negative bias voltage to the first sub-gate m62 and the second sub-gate m63, with a bias voltage range of -1V to -30V. The specific bias voltage value is determined according to the actual application. The Vth modulation effect of the demux TFT is as follows: Figure 6 As shown.

[0048] The gate voltage signal of the first sub-gate m62 can be equal to or different from the gate voltage signal of the second sub-gate m63. The compensation driving circuit can adjust the working voltage of the second gate according to the threshold voltage of the demultiplexing transistor. The first gate m61 can be given a normal gate control signal.

[0049] In one embodiment, such as Figure 4 As shown, the first gate m61 and the second gate (m62 and m63) are disposed on the same layer. Specifically, the first gate m61 and the second gate (m62 and m63) are patterned in one process by a metal layer disposed on the insulating layer m5. The co-location of the first gate and the second gate eliminates the need for a mask, simplifying the manufacturing process of the display panel.

[0050] In one embodiment, such as Figure 4 As shown, the second gate includes a first sub-gate m62 and a second sub-gate m63, with the first gate m61 located between the first sub-gate m62 and the second sub-gate m63. Specifically, the second gate is divided into two parts, respectively disposed on both sides of the first gate m61 and located above regions S16 (a part of the lightly doped region) and S17 (a part of the lightly doped region). In this embodiment, dividing the second gate into two parts increases the area of ​​the second gate, thereby increasing the corresponding area of ​​the gate and the channel region, which in turn reduces the resistance of the demultiplexed transistor in the driving circuit and increases the on-state current (Ion).

[0051] In one embodiment, such as Figure 4 As shown, the first sub-gate m62 and the second sub-gate m63 have the same orthographic projection on the active layer pattern m4. Specifically, in this embodiment, the shape and aspect ratio of the first sub-gate m62 and the second sub-gate m63 can be exactly the same to reduce the manufacturing difficulty of the mask.

[0052] In one embodiment, the first width of the first sub-gate (i.e., the length of region S16) is different from the second width of the second sub-gate (i.e., the length of region S17), which reduces the precision requirements of the fabrication process. It should be noted that in this embodiment, the first width and the second width specifically refer to the lateral lengths of the first and second sub-gates.

[0053] In one embodiment, in the first extending direction of the active layer pattern m4 (i.e. Figure 4 In the horizontal direction (as shown in the diagram), the width of the first sub-gate m62 is smaller than the width of the first gate m61, and the width of the second sub-gate m63 is smaller than the width of the first gate m61. It should be noted that the first extension direction refers to the horizontal extension direction of the cross-sectional structure diagram of the display panel provided in this embodiment of the invention. Specifically, the range of the first width and the second width is greater than or equal to 3 micrometers, with no maximum limit, but must be smaller than the width of the first gate m61.

[0054] In one embodiment, the resistivity of the portion of the semiconductor material of the active layer pattern m4 connected to the source m81 and the drain m82 within the via region is the same as the resistivity of the portion within the first region S13 and the second region (S16 and S17).

[0055] Resistivity is a physical quantity used to represent the electrical resistance of various materials. The resistance of a conductor made of a certain material that is 1 meter long and has a cross-sectional area of ​​1 square meter is numerically equal to the resistivity of that material. It reflects the property of a material to impede the flow of electric current, and it is not only related to the type of material but also affected by external factors such as temperature, pressure, and magnetic fields.

[0056] Specifically, the resistivity of the heavily doped region (i.e., region S11) below the source m81 and the heavily doped region (i.e., region S12) below the drain m82 are the same as the resistivity of the lightly doped region (i.e., region S16) and the lightly doped region (i.e., region S17).

[0057] In one embodiment, the first sub-gate m62 and the second sub-gate m63 are subjected to the same operating voltage. Based on this, the first sub-gate m62 and the second sub-gate m63 can be electrically connected, thereby reducing the number of gate control signals.

[0058] In one embodiment, the operating voltage applied to the first sub-gate m62 and the second sub-gate m63 can be the power supply voltage VSS (typically -20V, etc.), which can maximize the electron migration efficiency of the active layer pattern in regions S16 and S17, reduce the electron migration difficulty of the entire transistor, and further improve the on-state current (Ion) of the entire transistor.

[0059] In one embodiment, the semiconductor material of the active layer pattern m4 includes indium gallium zinc oxide (IGNOW). Specifically, the doping degree of the IGNOW semiconductor material varies in different regions of the active layer pattern. For example, the concentration of IGNOW doped impurities is higher in heavily doped regions and in lightly doped regions, while the concentration of IGNOW doped impurities is lower in lightly doped regions. Semiconductor doping is used to improve the electrical performance of the semiconductor; the different doping degrees of IGNOW semiconductor material in different regions also reflect the different electrical performance in different regions.

[0060] In one embodiment, the first sub-gate and the second sub-gate are loaded with the same operating voltage; this embodiment can connect the first sub-gate and the second sub-gate electrically and then connect them to the same signal, reducing circuit complexity.

[0061] In one embodiment, the polarity of the operating voltage applied to the first gate is positive, and the polarity of the operating voltage applied to the second gate is negative; this embodiment is compatible with mainstream panels.

[0062] In one embodiment, the operating voltage range of the first gate load is 0 to 30 volts, and the operating voltage range of the second gate load is -30 volts to -1 volt; this embodiment is compatible with mainstream panel power supply designs.

[0063] In one embodiment, the display panel includes a compensation driving circuit, which is used to adjust the operating voltage of the second gate load according to the threshold voltage of the demultiplexing transistor; for example, this embodiment can be based on Figure 6 The relationship between the voltage and the threshold voltage required determines the operating voltage for the second gate loading.

[0064] Figure 7 This is a circuit diagram of the demultiplexing circuit provided in this application. Figure 8 A timing diagram of the demultiplexing circuit provided in this application.

[0065] like Figure 7 As shown, the demultiplexing circuit 70 includes at least one demultiplexing transistor 71a (i.e., Figure 7The transistor formed by connecting sub-transistors 71a1, 71a2, and 71a3 in series) and another demultiplexing transistor 71b (i.e. Figure 7 The demultiplexing transistor (which consists of sub-transistors 71b1, 71b2, and 71b3 connected in series) has a data signal line connected to its signal output terminal, such as... Figure 7 As shown, the signal output terminal of the demultiplexing transistor 71a is connected to the data signal line 72a, the signal output terminal of the demultiplexing transistor 71b is connected to the data signal line 72b, and the signal input terminal of the demultiplexing transistor is connected to the data driver chip 80.

[0066] Demultiplexing transistors all employ the following methods: Figure 4 The transistor shown, at this time, as Figure 7 As shown, demultiplexing transistor 71a includes sub-transistors 71a1, 71a2, and 71a3 connected in series, and demultiplexing transistor 71b includes sub-transistors 71b1, 71b2, and 71b3 connected in series. The gates (control terminals) of sub-transistors 71a1 and 71a3 receive the same gate signal Vga, the gates (control terminals) of sub-transistors 71b1 and 71b3 receive the same gate signal Vgb, the gate (control terminal) of sub-transistor 71a2 receives the gate signal ENa, and the gate (control terminal) of sub-transistor 71b2 receives the gate signal ENb.

[0067] like Figure 8 As shown, at time t1, the gate signal Vga is at a low potential (e.g., -20V), the gate signal Vgb is at 0 potential, the gate signal ENa is at a high potential (e.g., +20V), and the gate signal ENb is at 0. At this time, the demultiplexing transistor 71a is turned on, the demultiplexing transistor 71b is not turned on, and the data signal Data is written to the data signal line 72a. At time t2, the gate signal Vga is at 0 potential, the gate signal Vgb is at a low potential (e.g., -20V), the gate signal ENa is at 0, and the gate signal ENb is at a high potential (e.g., +20V). At this time, the demultiplexing transistor 71a is not turned on, the demultiplexing transistor 71b is turned on, and the data signal Data is written to the data signal line 72b. This step is repeated alternately to complete the data demultiplexing process.

[0068] Accordingly, embodiments of the present invention also provide a display device, which includes the display panel provided by the present invention. The display panel includes, but is not limited to, devices such as liquid crystal displays, liquid crystal televisions, and liquid crystal screens.

[0069] As can be seen from the above embodiments:

[0070] This invention provides a display panel and a display device. The demultiplexing transistor in the display panel includes a source, a drain, an active pattern, a first gate, and a second gate. The source and drain are located on one side of the active pattern, the first gate is located on one side of the active pattern, and the second gate is located on one side of the active pattern. The active pattern is electrically connected to the source and drain through vias within a via region. In the same demultiplexing transistor, the first gate and the second gate are spaced apart, and the first gate and the second gate are loaded with operating voltages of different polarities. Based on the fact that the threshold voltage Vth offset of a transistor is related to the sign and magnitude of the operating voltage, when the demultiplexing transistor is working, the first gate and the second gate are loaded with operating voltages of different polarities. This allows for adjustment and control of the threshold voltage of the entire demultiplexing transistor, effectively alleviating the technical problem of poor stability in existing demultiplexing transistors and improving circuit stability.

[0071] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A display panel, characterized by, The display panel comprises a demultiplexing circuit, the demultiplexing circuit comprising a demultiplexing transistor; wherein: The demultiplexing transistor comprises a source, a drain, an active pattern, a first gate, and a second gate, the source and the drain being located on one side of the active pattern, the first gate being located on one side of the active pattern, and the second gate being located on one side of the active pattern, the active pattern being electrically connected to the source and the drain through a via in a via region; In the same demultiplexing transistor, the first gate and the second gate are arranged at intervals, the second gate being located between a second region where a normal projection of the active pattern on the second gate is located and the via region; The first gate and the second gate are loaded with working voltages of different polarities.

2. The display panel of claim 1, wherein, The first gate and the second gate are arranged in the same layer.

3. The display panel of claim 2, wherein, The second gate comprises a first sub-gate and a second sub-gate, and the first gate is located between the first sub-gate and the second sub-gate.

4. The display panel of claim 3, wherein, The first sub-gate and the second sub-gate have the same normal projection on the active pattern.

5. The display panel of claim 1, wherein, The first gate and the second gate are loaded with working voltages of different polarities.

6. The display panel of claim 5, wherein, The polarity of the working voltage loaded by the first gate is positive, and the polarity of the working voltage loaded by the second gate is negative.

7. The display panel of claim 6, wherein, The working voltage range loaded by the first gate is 0 to 30 volts, and the working voltage range loaded by the second gate is -30 volts to -1 volt.

8. The display panel of claim 1, wherein, The display panel comprises a compensation driving circuit, the compensation driving circuit being used to adjust the working voltage loaded by the second gate according to the threshold voltage of the demultiplexing transistor.

9. A display device, characterized by comprising: The display panel comprises a compensation driving circuit, the compensation driving circuit being used to adjust the working voltage loaded by the second gate according to the threshold voltage of the demultiplexing transistor. The display panel comprises a compensation driving circuit, the compensation driving circuit being used to adjust the working voltage loaded by the second gate according to the threshold voltage of the demultiplexing transistor.

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