T-type three-level inverter with fault-tolerant function and fault-tolerant control method thereof

Abstract

The application discloses a T-type three-level inverter with a fault-tolerant function and a fault-tolerant control method thereof, four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors are additionally arranged; twelve power switching devices in a-phase bridge arm circuit, b-phase bridge arm circuit and c-phase bridge arm circuit are divided into two categories, namely, half-bridge switching devices and neutral-point switching devices; a T-type three-level inverter fault diagnosis method is adopted to diagnose the T-type three-level inverter with the fault-tolerant function, whether an open-circuit fault occurs is diagnosed, the type of the open-circuit fault is identified when the open-circuit fault occurs, if the open-circuit fault occurs, the power switching device with the open-circuit fault is controlled to be turned off, the corresponding fault-tolerant power switching device and the fault-tolerant bidirectional thyristor are controlled to be turned on, and the circuit topology is reconstructed; the T-type three-level inverter has the advantages of low cost, normal operation in the case of the open-circuit fault and improved reliability.

Description

Technical Field

[0001] This invention relates to an inverter, and more particularly to a T-type three-level inverter with fault-tolerant function and its fault-tolerant control method. Background Technology

[0002] The T-type three-level inverter, also known as a T-type neutral-point-clamped three-level inverter (TNPC), is widely used in many industrial applications, such as renewable energy systems, grid-connected systems, traction inverters, and induction motor control systems. Its main circuit topology is as follows: Figure 1 As shown, it includes the first power switching device S of phase a. a1 The second power switching device S of phase a a2 The third power switching device S of phase a a3 The fourth power switching device S of phase a a4 The first power switching device S of phase b b1 The second power switching device S of phase b b2 The third power switching device S of phase b b3 The fourth power switching device S of phase b b4 The first power switching device S of phase c c1 The second power switching device S of phase c c2 The third power switching device S of phase c c3 The fourth power switching device S in phase c c4 All 12 power switching devices mentioned above are insulated-gate bipolar transistors (IGBTs). The T-type three-level inverter is derived from a diode-neutral-point-clamped (NPC) inverter. Compared to NPC inverters, it has advantages such as lower conduction losses and higher efficiency. Compared to traditional two-level inverters, it has advantages such as lower total harmonic distortion of output voltage, higher power density, and lower voltage stress on power switching devices. However, like other multilevel inverters, the increased number of power switching devices and the increased system complexity lead to a higher probability of various faults in the T-type three-level inverter during operation due to overload, temperature rise, and improper operation. Failure of power switching devices is the most common type. Since the failure of even one of these power switching devices can cause the entire T-type three-level inverter to fail or even lead to serious consequences, fault diagnosis and fault-tolerant control become increasingly important to ensure the reliability of the T-type three-level inverter.

[0003] Currently, some research has been conducted both domestically and internationally on the fault-tolerant control problem of T-type three-level inverters. For example, Choi U, Blaabjerg F, Lee K, and others proposed "Reliability improvement of a T-type three-level inverter with fault-tolerant control strategy" in IEEE Transactions on Power Electronics (2015, 30(5), 2660-2673). They classified the fault types of T-type three-level inverters into two cases: half-bridge switch faults and neutral point switch faults, and proposed a fault-tolerant control strategy based on changing the switch state or changing the duration of the switch state. The advantage of this fault-tolerant control method is that it does not require changing the topology of the main circuit of the original T-type three-level inverter. Only the control strategy needs to be changed to allow the T-type three-level inverter to continue to work under the fault state of the power switching device. However, the disadvantage of this fault-tolerant control method is also very obvious. The main circuit of the T-type three-level inverter cannot maintain the maximum power output under non-fault conditions and can only operate at reduced rated power.

[0004] For example, the fault-tolerant control strategy for a T-type three-level inverter with neutral-point voltage balancing (2017, 3420-3425) proposed by Chen J, Chen A, Xing X, Zhang C, et al. at the 2017 IEEE Applied Power Electronics Conference and Exposition, addresses the issue of capacitor neutral-point voltage balancing. When a fault is detected in the power switching devices of a T-type three-level inverter, some voltage vectors are unavailable due to the fault. This strategy recombines the available voltage vectors to prevent distortion of the output waveform. Furthermore, it considers the issue of capacitor neutral-point voltage balance during voltage vector recombining. The drawback of this fault-tolerant control method is that the number of voltage levels in the output waveform decreases after fault tolerance; the line voltage changes from five levels to three levels, leading to an increase in harmonics in the output voltage.

[0005] For example, Xu S, Zhang J, Hang J, et al., in their paper "Investigation of a fault-tolerant three-level T-type inverter system" published in IEEE Transactions on Industry Applications (2017, 53(5), 4613-4623), added an extra half-bridge to the original three half-bridge arms of the T-type three-level inverter. When a power switching device failure is detected in one half-bridge arm, the extra half-bridge is used to replace the faulty half-bridge arm. At the same time, some fast-acting fuses are also added to the main circuit to block the faulty half-bridge arm. The advantage of this fault-tolerant control method is that it can output the original rated power at full capacity under fault-tolerant conditions. However, this fault-tolerant control method uses a large number of extra devices, including 6 thyristors, 2 insulated-gate bipolar transistors (IGBTs), and 8 fast-acting fuses. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a T-type three-level inverter with fault tolerance function and its fault tolerance control method, which is low in cost and can still work normally under open circuit fault, thereby improving the reliability of the T-type three-level inverter.

[0007] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a T-type three-level inverter with fault-tolerant function, including an a-phase bridge arm circuit, a b-phase bridge arm circuit, a c-phase bridge arm circuit, and two voltage dividing capacitors. Each phase's bridge arm circuit consists of four power switching devices, one resistor, and one inductor. All twelve power switching devices are insulated-gate bipolar transistors with built-in anti-parallel diodes. The invention is characterized by further including a fault-tolerant unit, which consists of four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors. The fault-tolerant power switching devices are insulated-gate bipolar transistors with built-in anti-parallel diodes. The collector of the first fault-tolerant power switching device is connected to the positive terminal of the first voltage dividing capacitor. The emitter of the first fault-tolerant power switching device is connected to the second anode of the first fault-tolerant bidirectional thyristor, the second anode of the second fault-tolerant bidirectional thyristor, and the third voltage dividing capacitor. The second anode of the fault-tolerant bidirectional thyristor, the collector of the third fault-tolerant power switch, and the collector of the fourth fault-tolerant power switch are connected. The first anode of the first fault-tolerant bidirectional thyristor is connected to the midpoint of the bridge arm of phase a. The first anode of the second fault-tolerant bidirectional thyristor is connected to the midpoint of the bridge arm of phase b. The first anode of the third fault-tolerant bidirectional thyristor is connected to the midpoint of the bridge arm of phase c. The collector of the second fault-tolerant power switch is connected to the midpoint of the DC voltage of the two voltage-dividing capacitors. The emitter of the second fault-tolerant power switch is connected to the emitter of the third fault-tolerant power switch. The emitter of the fourth fault-tolerant power switch is connected to the negative terminal of the second voltage-dividing capacitor. The gates of the four fault-tolerant power switches and the gates of the three fault-tolerant bidirectional thyristors are used to receive the drive signal.

[0008] The collector of the first power switch in each phase's bridge arm circuit is connected to the positive terminal of the first voltage divider capacitor. The emitter of the first power switch in each phase's bridge arm circuit is connected to the collectors of the third and fourth power switches in the corresponding phase's bridge arm circuit, and one end of the resistor, with the common connection point being the midpoint of the corresponding phase's bridge arm. The collector of the second power switch in each phase's bridge arm circuit is connected to the negative terminal of the first voltage divider capacitor and the positive terminal of the second voltage divider capacitor, respectively. The negative terminal of the first voltage divider capacitor and the positive terminal of the second voltage divider capacitor are connected... The common connection terminal is the midpoint of the DC voltage of the two voltage divider capacitors. The emitter of the second power switch in each phase of the bridge arm circuit is connected to the emitter of the third power switch in the corresponding phase of the bridge arm circuit. The emitter of the fourth power switch in each phase of the bridge arm circuit is connected to the negative terminal of the second voltage divider capacitor. The other end of the resistor in each phase of the bridge arm circuit is connected to one end of the inductor in the corresponding phase of the bridge arm circuit. The other ends of the inductors in each of the three phases of the bridge arm circuit are connected together. The gate of each of the four power switches in each phase of the bridge arm circuit is used to receive the drive signal.

[0009] A fault-tolerant control method for a T-type three-level inverter with fault-tolerant function, characterized by the following steps:

[0010] Step 1: Construct a fault-tolerant T-type three-level inverter, including phase a bridge arm circuit, phase b bridge arm circuit, phase c bridge arm circuit, two voltage divider capacitors, and a fault-tolerant unit. Each phase bridge arm circuit consists of four power switching devices, one resistor, and one inductor. All four power switching devices are insulated-gate bipolar transistors with built-in anti-parallel diodes. The collector of the first power switching device in each phase bridge arm circuit is connected to the positive terminal of the first voltage divider capacitor. The emitter of the first power switching device in each phase bridge arm circuit is connected to the collectors of the third and fourth power switching devices in the corresponding phase bridge arm circuit, as well as one end of the resistor. The common connection terminal is... At the midpoint of one phase bridge arm, the collector of the second power switch in each phase bridge arm circuit is connected to the negative terminal of the first voltage divider capacitor and the positive terminal of the second voltage divider capacitor, respectively. The common connection terminal connecting the negative terminal of the first voltage divider capacitor and the positive terminal of the second voltage divider capacitor is the midpoint of the DC voltage of the two voltage divider capacitors. The emitter of the second power switch in each phase bridge arm circuit is connected to the emitter of the third power switch in the corresponding phase bridge arm circuit. The emitter of the fourth power switch in each phase bridge arm circuit is connected to the negative terminal of the second voltage divider capacitor. The other end of the resistor in each phase bridge arm circuit is connected to one end of the inductor in the corresponding phase bridge arm circuit. The current in each of the three phase bridge arm circuits... The other end of the circuit is connected together. The gate of each of the four power switching devices in each phase bridge arm circuit is used to receive the drive signal. The fault-tolerant unit consists of four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors. The fault-tolerant power switching devices are insulated-gate bipolar transistors with built-in anti-parallel diodes. The collector of the first fault-tolerant power switching device is connected to the positive terminal of the first voltage divider capacitor. The emitter of the first fault-tolerant power switching device is connected to the second anode of the first fault-tolerant bidirectional thyristor, the second anode of the second fault-tolerant bidirectional thyristor, the second anode of the third fault-tolerant bidirectional thyristor, the collector of the third fault-tolerant power switching device, and the fourth fault-tolerant power switching device. The collectors of the devices are connected as follows: the first anode of the first fault-tolerant bidirectional thyristor is connected to the midpoint of the bridge arm of phase a; the first anode of the second fault-tolerant bidirectional thyristor is connected to the midpoint of the bridge arm of phase b; the first anode of the third fault-tolerant bidirectional thyristor is connected to the midpoint of the bridge arm of phase c; the collector of the second fault-tolerant power switch is connected to the midpoint of the DC voltage of the two voltage divider capacitors; the emitter of the second fault-tolerant power switch is connected to the emitter of the third fault-tolerant power switch; the emitter of the fourth fault-tolerant power switch is connected to the negative terminal of the second voltage divider capacitor; the gates of the four fault-tolerant power switches and the gates of the three fault-tolerant bidirectional thyristors are used to input the drive signal.

[0011] Step 2: In a fault-tolerant T-type three-level inverter, the twelve power switching devices in the a-phase bridge arm circuit, b-phase bridge arm circuit, and c-phase bridge arm circuit are divided into two main categories: half-bridge switching devices and neutral point switching devices. The half-bridge switching devices include the first and fourth power switching devices in the a-phase bridge arm circuit, the first and fourth power switching devices in the b-phase bridge arm circuit, and the first and fourth power switching devices in the c-phase bridge arm circuit. The neutral point switching devices include the second power switching device in the a-phase bridge arm circuit. The device and the third power switch device, the second and third power switch devices in the b-phase bridge arm circuit, and the second and third power switch devices in the c-phase bridge arm circuit; and set the fault-tolerant T-type three-level inverter to be able to work normally or to have a single half-bridge switch device open circuit fault or a single neutral point switch device open circuit fault or all four power switch devices in the a-phase bridge arm circuit open circuit fault or all four power switch devices in the b-phase bridge arm circuit open circuit fault or all four power switch devices in the c-phase bridge arm circuit open circuit fault;

[0012] Step 3: Control the twelve power switching devices in the phase a, phase b, and phase c bridge arm circuits to operate according to their original control strategies, while turning them on and off. All four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors in the fault-tolerant unit are turned off. Then, using the T-type three-level inverter fault diagnosis method, fault diagnosis is performed on the fault-tolerant T-type three-level inverter to determine if an open-circuit fault has occurred. If an open-circuit fault occurs, the type of open-circuit fault is identified. The types of open-circuit faults include: single half-bridge switching device open-circuit fault, single neutral point switching device open-circuit fault, all four power switching devices in the phase a bridge arm circuit open-circuit fault, all four power switching devices in the phase b bridge arm circuit open-circuit fault, and all four power switching devices in the phase c bridge arm circuit open-circuit fault.

[0013] Step 4: If no open circuit fault is diagnosed, the twelve power switching devices in the phase a bridge arm circuit, phase b bridge arm circuit, and phase c bridge arm circuit shall be kept in operation according to the original control strategies of the phase a bridge arm circuit, phase b bridge arm circuit, and phase c bridge arm circuit, while the four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors in the fault-tolerant unit shall be turned off.

[0014] If an open-circuit fault is diagnosed and identified as a single half-bridge switch open-circuit fault, then when the first or fourth power switch in the phase a bridge arm circuit experiences an open-circuit fault, the first and fourth power switches in the phase a bridge arm circuit are simultaneously turned off, the first fault-tolerant bidirectional thyristor is turned on, and the first and fourth fault-tolerant power switches are turned on. This causes the gate previously applied to the first power switch in the phase a bridge arm circuit to... The drive signal for the first fault-tolerant power switch is transferred to the gate of the first fault-tolerant power switch, causing the drive signal originally applied to the gate of the fourth power switch in the a-phase bridge arm circuit to be transferred to the gate of the fourth fault-tolerant power switch. When the first or fourth power switch in the b-phase bridge arm circuit experiences an open-circuit fault, the first and fourth power switches in the b-phase bridge arm circuit are simultaneously turned off, the second fault-tolerant bidirectional thyristor is turned on, and the first fault-tolerant power switch... When the first power switch and the fourth fault-tolerant power switch are turned on, the drive signal originally applied to the gate of the first power switch in the b-phase bridge arm circuit is transferred to the gate of the first fault-tolerant power switch, and the drive signal originally applied to the gate of the fourth power switch in the b-phase bridge arm circuit is transferred to the gate of the fourth fault-tolerant power switch. When the first or fourth power switch in the c-phase bridge arm circuit experiences an open-circuit fault, the control signal in the c-phase bridge arm circuit is activated. The first and fourth power switches are turned off simultaneously, the third fault-tolerant bidirectional thyristor is turned on, and the first and fourth fault-tolerant power switches are turned on. This causes the drive signal originally applied to the gate of the first power switch in the c-phase bridge arm circuit to be applied to the gate of the first fault-tolerant power switch, and the drive signal originally applied to the gate of the fourth power switch in the c-phase bridge arm circuit to be applied to the gate of the fourth fault-tolerant power switch.

[0015] If an open-circuit fault is diagnosed and identified as a single neutral point switching device open-circuit fault, then when the second or third power switching device in the phase a bridge arm circuit experiences an open-circuit fault, the second and third power switching devices in the phase a bridge arm circuit are simultaneously turned off, the first fault-tolerant bidirectional thyristor is turned on, and the second and third fault-tolerant power switching devices are turned on. This causes the power originally applied to the second power switching device in the phase a bridge arm circuit to... The gate drive signal is transferred to the gate of the second fault-tolerant power switch, causing the drive signal originally applied to the gate of the third power switch in phase a bridge arm circuit to be transferred to the gate of the third fault-tolerant power switch; when the second or third power switch in phase b bridge arm circuit experiences an open-circuit fault, the second and third power switches in phase b bridge arm circuit are simultaneously turned off, the second fault-tolerant bidirectional thyristor is turned on, and the second fault-tolerant power switch... When the first and third fault-tolerant power switches are turned on, the drive signal originally applied to the gate of the second power switch in the b-phase bridge arm circuit is transferred to the gate of the second fault-tolerant power switch, and the drive signal originally applied to the gate of the third power switch in the b-phase bridge arm circuit is transferred to the gate of the third fault-tolerant power switch. When the second or third power switch in the c-phase bridge arm circuit experiences an open-circuit fault, the control signal in the c-phase bridge arm circuit is activated. The second and third power switches are simultaneously turned off, the third fault-tolerant bidirectional thyristor is turned on, and the second and third fault-tolerant power switches are turned on. This causes the drive signal originally applied to the gate of the second power switch in the c-phase bridge arm circuit to be applied to the gate of the second fault-tolerant power switch, and the drive signal originally applied to the gate of the third power switch in the c-phase bridge arm circuit to be applied to the gate of the third fault-tolerant power switch.

[0016] If an open-circuit fault is diagnosed and identified as an open-circuit fault in all four power switching devices in phase a bridge arm circuit, then all four power switching devices in phase a bridge arm circuit are simultaneously turned off, the first fault-tolerant bidirectional thyristor is turned on, and all four fault-tolerant power switching devices are turned on. This causes the drive signal originally applied to the gate of the first power switching device in phase a bridge arm circuit to be applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in phase a bridge arm circuit to be applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in phase a bridge arm circuit to be applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in phase a bridge arm circuit to be applied to the gate of the fourth fault-tolerant power switching device.

[0017] If an open-circuit fault is diagnosed and identified as an open-circuit fault in all four power switching devices in the b-phase bridge arm circuit, then all four power switching devices in the b-phase bridge arm circuit are simultaneously turned off, the second fault-tolerant bidirectional thyristor is turned on, and all four fault-tolerant power switching devices are turned on. This causes the drive signal originally applied to the gate of the first power switching device in the b-phase bridge arm circuit to be applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in the b-phase bridge arm circuit to be applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in the b-phase bridge arm circuit to be applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the b-phase bridge arm circuit to be applied to the gate of the fourth fault-tolerant power switching device.

[0018] If an open-circuit fault is diagnosed and identified as an open-circuit fault in all four power switching devices in the C-phase bridge arm circuit, then all four power switching devices in the C-phase bridge arm circuit are simultaneously turned off, the third fault-tolerant bidirectional thyristor is turned on, and all four fault-tolerant power switching devices are turned on. This causes the drive signal originally applied to the gate of the first power switching device in the C-phase bridge arm circuit to be applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in the C-phase bridge arm circuit to be applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in the C-phase bridge arm circuit to be applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the C-phase bridge arm circuit to be applied to the gate of the fourth fault-tolerant power switching device.

[0019] Compared with the prior art, the advantages of the present invention are as follows:

[0020] 1) This invention adds four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors to the original T-type three-level inverter. When an open-circuit fault occurs in a power switching device or all power switching devices in a phase of the original T-type three-level inverter, the circuit topology is reconstructed by turning off the power switching device with the open-circuit fault and turning on the corresponding fault-tolerant power switching device and fault-tolerant bidirectional thyristor. This allows the T-type three-level inverter to still operate normally under open-circuit fault conditions, thus improving the reliability of the T-type three-level inverter.

[0021] 2) The present invention achieves fault-tolerant control by adding only four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors, that is, the number of additional devices is small, resulting in lower cost.

[0022] 3) The fault-tolerant control method of the present invention is simple to implement and can control the T-type three-level inverter to output the same level and power as the original T-type three-level inverter during fault-tolerant operation, that is, it does not need to reduce the rated power to work. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the main circuit topology of an existing T-type three-level inverter.

[0024] Figure 2 This is a schematic diagram of the topology of the main circuit of the fault-tolerant T-type three-level inverter of the present invention.

[0025] Figure 3 This is a schematic diagram of the a-phase topology after fault-tolerant control is applied when the first or fourth power switch device in the a-phase bridge arm circuit experiences an open-circuit fault.

[0026] Figure 4 This is a schematic diagram of the a-phase topology after fault-tolerant control is applied when the second or third power switch device in the a-phase bridge arm circuit experiences an open-circuit fault.

[0027] Figure 5 This is a schematic diagram of the a-phase topology after fault-tolerant control is applied when all four power switching devices in the a-phase bridge arm circuit experience open-circuit faults.

[0028] Figure 6a For existing T-type three-level inverters without open-circuit faults and S a1 Experimental results when an open-circuit fault occurs;

[0029] Figure 6b For existing T-type three-level inverters without open-circuit faults and S a2 Experimental results when an open-circuit fault occurs;

[0030] Figure 6c The results are experimental findings for an existing T-type three-level inverter under conditions of no open-circuit fault and under conditions of an overall open-circuit fault in all four power switching devices of phase a.

[0031] Figure 7a For a fault-tolerant T-type three-level inverter without an open-circuit fault, S a1 Experimental results under open-circuit fault conditions and after fault-tolerant control;

[0032] Figure 7b For a fault-tolerant T-type three-level inverter without an open-circuit fault, S a2 Experimental results under open-circuit fault conditions and after fault-tolerant control;

[0033] Figure 7cThe results are experimental findings for a fault-tolerant T-type three-level inverter under the following conditions: no open-circuit fault, all four power switching devices of phase a experiencing an open-circuit fault, and after fault-tolerant control. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0035] This invention proposes a fault-tolerant T-type three-level inverter, such as... Figure 2 As shown, it includes phase a bridge arm circuit, phase b bridge arm circuit, phase c bridge arm circuit, two voltage dividing capacitors, and a fault-tolerant unit. Each phase bridge arm circuit consists of four power switching devices, one resistor, and one inductor. The phase a bridge arm circuit is composed of the first power switching device S of phase a. a1 The second power switching device S of phase a a2 The third power switching device S of phase a a3 The fourth power switching device S of phase a a4 The resistance R of phase a a and the inductance L of phase a a The b-phase bridge arm circuit is composed of the first power switching device S of phase b. b1 The second power switching device S of phase b b2 The third power switching device S of phase b b3 The fourth power switching device S of phase b b4 The resistance R of phase b b and the inductance L of phase b b The c-phase bridge arm circuit is composed of the first power switching device S of the c-phase. c1 The second power switching device S of phase c c2 The third power switching device S of phase c c3 The fourth power switching device S in phase c c4 The resistance R of phase c c and the inductance L of phase c c The system consists of twelve power switching devices, all of which are Insulated Gate Bipolar Transistors (IGBTs) with built-in anti-parallel diodes. a1 The built-in anti-parallel diode is D. a1 S a2 The built-in anti-parallel diode is D. a2 S a3 The built-in anti-parallel diode is D. a3 S a4 The built-in anti-parallel diode is D. a4 S b1 The built-in anti-parallel diode is D. b1 S b2 The built-in anti-parallel diode is D. b2 Sb3 The built-in anti-parallel diode is D. b3 S b4 The built-in anti-parallel diode is D. b4 S c1 The built-in anti-parallel diode is D. c1 S c2 The built-in anti-parallel diode is D. c2 S c3 The built-in anti-parallel diode is D. c3 S c4 The built-in anti-parallel diode is D. c4 The fault-tolerant unit consists of four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors. The first to fourth fault-tolerant power switching devices are S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19 ... t1 S t2 S t3 S t4 The first fault-tolerant bidirectional thyristor to the third fault-tolerant bidirectional thyristor T a T b T c The fault-tolerant power switching device is an insulated-gate bipolar transistor (IGBT) with a built-in anti-parallel diode, S t1 The built-in anti-parallel diode is D. t1 S t2 The built-in anti-parallel diode is D. t2 S t3 The built-in anti-parallel diode is D. t3 S t4 The built-in anti-parallel diode is D. t4 The first fault-tolerant power switching device S t1 The collector of is connected to the positive terminal of the first voltage divider capacitor C1, and the first fault-tolerant power switch S... t1 The emitters are respectively connected to the first fault-tolerant bidirectional thyristor T. a The second anode and the second fault-tolerant bidirectional thyristor T b The second anode and the third fault-tolerant bidirectional thyristor T c The second anode and the third fault-tolerant power switching device S t3 The collector, the fourth fault-tolerant power switch S t4 The collector connection, the first fault-tolerant one uses a bidirectional thyristor T a The midpoint of the bridge arm between the first anode and phase a is... Figure 2 The connection at point a is used for the second fault-tolerant transistor, T. b The midpoint between the first anode and the bridge arm of phase b is... Figure 2 The connection at point b in the diagram, and the third fault-tolerant transistor T is a bidirectional thyristor. c The midpoint between the first anode and the bridge arm of phase c is... Figure 2 The connection at point c in the diagram, and the second fault-tolerant power switch device S. t2 The midpoint between the collector and the DC voltage of the two voltage-dividing capacitors is... Figure 2 The connection at point O in the diagram, and the second fault-tolerant power switching device S. t2 The emitter and the third fault-tolerant power switch S t3 The emitter connection, the fourth fault-tolerant power switch device S t4 The emitter of the first capacitor is connected to the negative terminal of the second voltage divider capacitor C2. The gates of the four fault-tolerant power switching devices and the gates of the three fault-tolerant bidirectional thyristors are used to input the drive signal.

[0036] In this embodiment, the collector (i.e., S) of the first power switching device in each phase arm circuit a1 S b1 S c1 The collector of the first phase is connected to the positive terminal of the first voltage-dividing capacitor C1, and the emitter of the first power switching device in each phase arm circuit (i.e., S) is connected to the positive terminal of the first voltage-dividing capacitor C1. a1 S b1 S c1 The emitter of the device is connected to the collector of the third power switch in the corresponding phase arm circuit (i.e., S). a3 S b3 S c3 The collector of the fourth power switch device (i.e., S) a4 S b4 S c4 The collector and resistor (i.e., R) a R b R c One end of the bridge arm is connected, and the common connection end is the midpoint of the corresponding phase arm (i.e., the midpoint of the bridge arm of phase a is...). Figure 2 Point a in the diagram, the midpoint of the bridge arm in phase b is... Figure 2 Point b in the middle, the midpoint of the bridge arm of phase c is Figure 2 Point c in the diagram), the collector (i.e., S) of the second power switching device in each phase arm circuit. a2 S b2 S c2 The collectors of the capacitors are connected to the negative terminal of the first voltage divider capacitor C1 and the positive terminal of the second voltage divider capacitor C2, respectively. The common connection point between the negative terminal of the first voltage divider capacitor C1 and the positive terminal of the second voltage divider capacitor C2 is the midpoint of the DC voltage of the two voltage divider capacitors. Figure 2 Point O in the circuit refers to the emitter (i.e., S) of the second power switching device in each phase arm circuit. a2 S b2 S c2 The emitter of the third power switch in the corresponding phase arm circuit (i.e., S) a3S b3 S c3 The emitter of the fourth power switching device in each phase arm circuit is connected to the emitter of the fourth power switching device (i.e., S). a4 S b4 S c4 The emitter of the first phase is connected to the negative terminal of the second voltage-dividing capacitor C2, and the resistor (i.e., R) in each phase bridge arm circuit is connected to the negative terminal of the second voltage-dividing capacitor C2. a R b R c The other end of the circuit is connected to the inductor (i.e., L) in the corresponding phase arm of the bridge circuit. a L b L c One end of the bridge arm circuit is connected to the inductor (i.e., L) in each of the three phase bridge arm circuits. a L b L c The other ends of the circuit are connected together, and the gates of the four power switching devices in each phase arm circuit are used to receive the drive signal. Here, the resistor and inductor are the load parts in the bridge arm circuit.

[0037] This invention also proposes a fault-tolerant control method for a T-type three-level inverter with fault-tolerant function, which includes the following steps:

[0038] Step 1: As Figure 2As shown, a fault-tolerant T-type three-level inverter is constructed, comprising phase a, phase b, and phase c bridge arm circuits, two voltage divider capacitors, and a fault-tolerant unit. Each phase bridge arm circuit consists of four power switching devices, one resistor, and one inductor. All four power switching devices are insulated-gate bipolar transistors with integrated anti-parallel diodes. The collector of the first power switching device in each phase bridge arm circuit is connected to the positive terminal of the first voltage divider capacitor. The emitter of the first power switching device in each phase bridge arm circuit is connected to the collectors of the third and fourth power switching devices in the corresponding phase bridge arm circuit, as well as one end of the resistor. The common connection terminal is the corresponding... At the midpoint of one phase bridge arm, the collector of the second power switch in each phase bridge arm circuit is connected to the negative terminal of the first voltage divider capacitor and the positive terminal of the second voltage divider capacitor, respectively. The common connection terminal connecting the negative terminal of the first voltage divider capacitor and the positive terminal of the second voltage divider capacitor is the midpoint of the DC voltage of the two voltage divider capacitors. The emitter of the second power switch in each phase bridge arm circuit is connected to the emitter of the third power switch in the corresponding phase bridge arm circuit. The emitter of the fourth power switch in each phase bridge arm circuit is connected to the negative terminal of the second voltage divider capacitor. The other end of the resistor in each phase bridge arm circuit is connected to one end of the inductor in the corresponding phase bridge arm circuit. The inductors in each of the three phase bridge arm circuits... The other ends are connected together. The gates of the four power switching devices in each phase bridge arm circuit are used to receive the drive signal. The fault-tolerant unit consists of four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors. The fault-tolerant power switching devices are insulated-gate bipolar transistors with built-in anti-parallel diodes. The collector of the first fault-tolerant power switching device is connected to the positive terminal of the first voltage divider capacitor. The emitter of the first fault-tolerant power switching device is connected to the second anode of the first fault-tolerant bidirectional thyristor, the second anode of the second fault-tolerant bidirectional thyristor, the second anode of the third fault-tolerant bidirectional thyristor, the collector of the third fault-tolerant power switching device, and the fourth fault-tolerant power switching device. The collectors of the first fault-tolerant bidirectional thyristor are connected to the midpoint of the bridge arm of phase a, the first anode of the second fault-tolerant bidirectional thyristor is connected to the midpoint of the bridge arm of phase b, the first anode of the third fault-tolerant bidirectional thyristor is connected to the midpoint of the bridge arm of phase c, the collector of the second fault-tolerant power switch is connected to the midpoint of the DC voltage of the two voltage divider capacitors, the emitter of the second fault-tolerant power switch is connected to the emitter of the third fault-tolerant power switch, and the emitter of the fourth fault-tolerant power switch is connected to the negative terminal of the second voltage divider capacitor. The gates of the four fault-tolerant power switches and the gates of the three fault-tolerant bidirectional thyristors are used to input the drive signal.

[0039] exist Figure 2 In the middle, S a1 S a2 S a3 Sa4 These correspond to the first, second, third, and fourth power switching devices in the a-phase bridge arm circuit, R. a Let L be the resistance of phase a. a S is the inductance of phase a. b1 S b2 S b3 S b4 This corresponds to the first, second, third, and fourth power switching devices in the b-phase bridge arm circuit, R. b Let L be the resistance of phase b. b For phase b, S c1 S c2 S c3 S c4 These correspond to the first, second, third, and fourth power switching devices in the c-phase bridge arm circuit, R. c L is the resistance of phase c. c For the inductance of phase c, S a1 The built-in anti-parallel diode is D. a1 S a2 The built-in anti-parallel diode is D. a2 S a3 The built-in anti-parallel diode is D. a3 S a4 The built-in anti-parallel diode is D. a4 S b1 The built-in anti-parallel diode is D. b1 S b2 The built-in anti-parallel diode is D. b2 S b3 The built-in anti-parallel diode is D. b3 S b4 The built-in anti-parallel diode is D. b4 S c1 The built-in anti-parallel diode is D. c1 S c2 The built-in anti-parallel diode is D. c2 S c3 The built-in anti-parallel diode is D. c3 S c4 The built-in anti-parallel diode is D. c4 The first to fourth fault-tolerant power switching devices are S... t1 S t2 S t3 S t4 The first fault-tolerant bidirectional thyristor to the third fault-tolerant bidirectional thyristor T aT b T c S t1 The built-in anti-parallel diode is D. t1 S t2 The built-in anti-parallel diode is D. t2 S t3 The built-in anti-parallel diode is D. t3 S t4 The built-in anti-parallel diode is D. t4 C1 is the first voltage divider capacitor, and C2 is the second voltage divider capacitor.

[0040] Step 2: In a fault-tolerant T-type three-level inverter, the twelve power switching devices in the a-phase bridge arm circuit, b-phase bridge arm circuit, and c-phase bridge arm circuit are divided into two main categories: half-bridge switching devices and neutral point switching devices. The half-bridge switching devices include the first and fourth power switching devices in the a-phase bridge arm circuit, the first and fourth power switching devices in the b-phase bridge arm circuit, and the first and fourth power switching devices in the c-phase bridge arm circuit. The neutral point switching devices include the second power switching device in the a-phase bridge arm circuit. The device and the third power switch device, the second and third power switch devices in the b-phase bridge arm circuit, and the second and third power switch devices in the c-phase bridge arm circuit; and set the fault-tolerant T-type three-level inverter to be able to work normally or to have a single half-bridge switch device open circuit fault or a single neutral point switch device open circuit fault or all four power switch devices in the a-phase bridge arm circuit open circuit fault or all four power switch devices in the b-phase bridge arm circuit open circuit fault or all four power switch devices in the c-phase bridge arm circuit open circuit fault.

[0041] Step 3: The DSP (Digital Signal Processing) or microcontroller controls the twelve power switching devices in the A-phase, B-phase, and C-phase bridge arm circuits to operate according to their original control strategies, while all four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors in the fault-tolerant unit are turned off. Then, the existing fault diagnosis method for T-type three-level inverters is used to diagnose the fault in the fault-tolerant T-type three-level inverter, determining whether an open-circuit fault has occurred, and identifying the type of open-circuit fault when it occurs. The types of open-circuit faults include: a single half-bridge switching device open-circuit fault, a single neutral point switching device open-circuit fault, all four power switching devices in the A-phase bridge arm circuit, all four power switching devices in the B-phase bridge arm circuit, and all four power switching devices in the C-phase bridge arm circuit.

[0042] Step 4: If no open circuit fault is diagnosed, the twelve power switching devices in the phase a, phase b, and phase c bridge arm circuits shall continue to operate according to the original control strategies of the phase a, phase b, and phase c bridge arm circuits, while the four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors in the fault-tolerant unit shall be turned off.

[0043] If an open-circuit fault is diagnosed and identified as a single half-bridge switch open-circuit fault, then when the first or fourth power switch in the phase a bridge arm circuit experiences an open-circuit fault, the first and fourth power switches in the phase a bridge arm circuit are simultaneously turned off, the first fault-tolerant bidirectional thyristor is turned on, and the first and fourth fault-tolerant power switches are turned on. This causes the gate previously applied to the first power switch in the phase a bridge arm circuit to... The drive signal for the first fault-tolerant power switch is transferred to the gate of the first fault-tolerant power switch, causing the drive signal originally applied to the gate of the fourth power switch in the a-phase bridge arm circuit to be transferred to the gate of the fourth fault-tolerant power switch. When the first or fourth power switch in the b-phase bridge arm circuit experiences an open-circuit fault, the first and fourth power switches in the b-phase bridge arm circuit are simultaneously turned off, the second fault-tolerant bidirectional thyristor is turned on, and the first fault-tolerant power switch... When the first power switch and the fourth fault-tolerant power switch are turned on, the drive signal originally applied to the gate of the first power switch in the b-phase bridge arm circuit is transferred to the gate of the first fault-tolerant power switch, and the drive signal originally applied to the gate of the fourth power switch in the b-phase bridge arm circuit is transferred to the gate of the fourth fault-tolerant power switch. When the first or fourth power switch in the c-phase bridge arm circuit experiences an open-circuit fault, the control signal in the c-phase bridge arm circuit is activated. The first and fourth power switches are simultaneously turned off, the third fault-tolerant bidirectional thyristor is turned on, and the first and fourth fault-tolerant power switches are turned on. This causes the drive signal originally applied to the gate of the first power switch in the c-phase bridge arm circuit to be applied to the gate of the first fault-tolerant power switch, and the drive signal originally applied to the gate of the fourth power switch in the c-phase bridge arm circuit to be applied to the gate of the fourth fault-tolerant power switch.

[0044] Figure 3The paper presents the a-phase topology after fault-tolerant control following an open-circuit fault in the first or fourth power switch device in the a-phase bridge arm circuit. When an open-circuit fault occurs in the first or fourth power switch device in the a-phase bridge arm circuit, both the first and fourth power switches in that phase bridge arm circuit are simultaneously turned off, while maintaining the b-phase and c-phase topologies unchanged. The first fault-tolerant device is turned on using a bidirectional thyristor, and the first and fourth fault-tolerant power switches are also turned on. The gate voltage of the second power switch device in the a-phase bridge arm circuit is applied to the... The drive signals for the gates of the three power switching devices remain unchanged. However, the drive signals for the gates of the first and fourth power switching devices in the phase a bridge arm circuit are applied to the gates of the first and fourth fault-tolerant power switching devices, respectively. Therefore, the first fault-tolerant power switching device replaces the first power switching device in the phase a bridge arm circuit, and the fourth fault-tolerant power switching device replaces the fourth power switching device in the phase a bridge arm circuit. This allows the fault-tolerant T-type three-level inverter to still operate normally in the event of an open-circuit fault.

[0045] If an open-circuit fault is diagnosed and identified as a single neutral point switching device open-circuit fault, then when the second or third power switching device in the phase a bridge arm circuit experiences an open-circuit fault, the second and third power switching devices in the phase a bridge arm circuit are simultaneously turned off, the first fault-tolerant bidirectional thyristor is turned on, and the second and third fault-tolerant power switching devices are turned on. This causes the power originally applied to the second power switching device in the phase a bridge arm circuit to... The gate drive signal is transferred to the gate of the second fault-tolerant power switch, causing the drive signal originally applied to the gate of the third power switch in phase a bridge arm circuit to be transferred to the gate of the third fault-tolerant power switch; when the second or third power switch in phase b bridge arm circuit experiences an open-circuit fault, the second and third power switches in phase b bridge arm circuit are simultaneously turned off, the second fault-tolerant bidirectional thyristor is turned on, and the second fault-tolerant power switch... When the first and third fault-tolerant power switches are turned on, the drive signal originally applied to the gate of the second power switch in the b-phase bridge arm circuit is transferred to the gate of the second fault-tolerant power switch, and the drive signal originally applied to the gate of the third power switch in the b-phase bridge arm circuit is transferred to the gate of the third fault-tolerant power switch. When the second or third power switch in the c-phase bridge arm circuit experiences an open-circuit fault, the control signal in the c-phase bridge arm circuit is activated. The second and third power switches are simultaneously turned off, the third fault-tolerant bidirectional thyristor is turned on, and the second and third fault-tolerant power switches are turned on. This causes the drive signal originally applied to the gate of the second power switch in the c-phase bridge arm circuit to be applied to the gate of the second fault-tolerant power switch, and the drive signal originally applied to the gate of the third power switch in the c-phase bridge arm circuit to be applied to the gate of the third fault-tolerant power switch.

[0046] Figure 4The paper presents the a-phase topology after fault-tolerant control following an open-circuit fault in the second or third power switch device in the a-phase bridge arm circuit. When an open-circuit fault occurs in the second or third power switch device in the a-phase bridge arm circuit, both the second and third power switches in that phase bridge arm circuit are simultaneously turned off, while maintaining the b-phase and c-phase topologies unchanged. The first fault-tolerant device is turned on using a bidirectional thyristor, and the second and third fault-tolerant power switches are turned on. The gate voltage of the first power switch device in the a-phase bridge arm circuit and the second fault-tolerant device are then applied to the... The drive signals for the gates of the four power switching devices remain unchanged. However, the drive signals for the gates of the second and third power switching devices in the a-phase bridge arm circuit are applied to the gates of the second and third fault-tolerant power switching devices, respectively. Therefore, the second fault-tolerant power switching device replaces the second power switching device in the a-phase bridge arm circuit, and the third fault-tolerant power switching device replaces the third power switching device in the a-phase bridge arm circuit. This allows the fault-tolerant T-type three-level inverter to still operate normally in the event of an open-circuit fault.

[0047] If an open-circuit fault is diagnosed and identified as an open-circuit fault in all four power switching devices in phase a bridge arm circuit, then all four power switching devices in phase a bridge arm circuit are simultaneously turned off, the first fault-tolerant bidirectional thyristor is turned on, and all four fault-tolerant power switching devices are turned on. This causes the drive signal originally applied to the gate of the first power switching device in phase a bridge arm circuit to be applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in phase a bridge arm circuit to be applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in phase a bridge arm circuit to be applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in phase a bridge arm circuit to be applied to the gate of the fourth fault-tolerant power switching device.

[0048] If an open-circuit fault is diagnosed and identified as an open-circuit fault in all four power switching devices in the b-phase bridge arm circuit, then all four power switching devices in the b-phase bridge arm circuit are simultaneously turned off, the second fault-tolerant bidirectional thyristor is turned on, and all four fault-tolerant power switching devices are turned on. This causes the drive signal originally applied to the gate of the first power switching device in the b-phase bridge arm circuit to be applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in the b-phase bridge arm circuit to be applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in the b-phase bridge arm circuit to be applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the b-phase bridge arm circuit to be applied to the gate of the fourth fault-tolerant power switching device.

[0049] If an open-circuit fault is diagnosed and identified as an open-circuit fault in all four power switching devices in the C-phase bridge arm circuit, then all four power switching devices in the C-phase bridge arm circuit are simultaneously turned off, the third fault-tolerant bidirectional thyristor is turned on, and all four fault-tolerant power switching devices are turned on. This causes the drive signal originally applied to the gate of the first power switching device in the C-phase bridge arm circuit to be applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in the C-phase bridge arm circuit to be applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in the C-phase bridge arm circuit to be applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the C-phase bridge arm circuit to be applied to the gate of the fourth fault-tolerant power switching device.

[0050] Figure 5 The topology of phase a is given after all four power switching devices in phase a bridge arm circuit have experienced open-circuit faults and are subjected to fault-tolerant control. When all four power switching devices in phase a bridge arm circuit have experienced open-circuit faults, only the topology of phase a is changed. The drive signals applied to the gates of the first to fourth power switching devices in phase a bridge arm circuit are respectively applied to the gates of the first to fourth fault-tolerant power switching devices. Therefore, the first to fourth fault-tolerant power switching devices, the first fault-tolerant bidirectional thyristor, and the corresponding resistors and inductors constitute the new phase a bridge arm circuit.

[0051] Considering the entire fault-tolerant T-type three-level inverter, under different open-circuit fault types, the power switching devices controlled by the method of the present invention to turn on and off are shown in Table 1. Table 1 also lists the bidirectional thyristors that are turned on in the event of an open-circuit fault.

[0052] Table 1. Fault-tolerant control scheme for a fault-tolerant T-type three-level inverter.

[0053]

[0054] To verify the feasibility and effectiveness of the method of the present invention, experiments were conducted on the method of the present invention.

[0055] An experimental circuit was built for verification, in which the DC input voltage of the T-type three-level inverter was 100V, i.e. Figure 2 V in dc =100V. In the experiment, an open-circuit fault of a single power switching device was simulated by setting the drive signal of the IGBT gate to the off signal, controlled by the DSP main control board. An overall open-circuit fault of the power switching devices in a certain phase was achieved by setting the drive signals of all IGBTs in that phase to the off signal. Here, S is used as an example. a1 An open-circuit fault is simulated to represent an open-circuit fault in a single half-bridge switching device, with S a2 An open-circuit fault is used to simulate an open-circuit fault in a single neutral point switching device, and an overall open-circuit fault in phase a is used to simulate an overall open-circuit fault in a power switching device of a certain phase.

[0056] Figure 1 In the existing T-type three-level inverter shown, when there is no open-circuit fault and S a1 The experimental results when an open circuit fault occurs are as follows: Figure 6a As shown, when there is no open circuit fault and S a2 The experimental results when an open circuit fault occurs are as follows: Figure 6b As shown, the experimental results are as follows: no open-circuit fault and the overall open-circuit fault of all four power switching devices in phase a. Figure 6c As shown. In Figure 6a , Figure 6b and Figure 6c In the diagram, the waveform to the left of the dashed line is the experimental waveform when there is no open circuit fault, and the waveform to the right of the dashed line is the experimental waveform when an open circuit fault occurs. The three waveforms from top to bottom are: 1) V ao : Figure 1 The voltage between points a and o is called the bridge arm voltage; 2) V ao_rec Bridge arm voltage V ao Voltage after full-wave rectification; 3)i a : Figure 1 The phase a current in the middle. From Figure 6a , Figure 6b and Figure 6c As can be seen, the voltage and current waveforms changed differently after an open circuit fault occurred.

[0057] Figure 2In the fault-tolerant T-type three-level inverter shown, when there is no open-circuit fault, S a1 Experimental results under open-circuit fault and after fault-tolerant control are as follows: Figure 7a As shown, when there is no open circuit fault, S a2 Experimental results under open-circuit fault and after fault-tolerant control are as follows: Figure 7b As shown, the experimental results are as follows: no open-circuit fault, all four power switching devices of phase a experiencing an open-circuit fault, and after fault-tolerant control. Figure 7c As shown. In Figure 7a , Figure 7b and Figure 7c The waveform is divided into three parts from left to right by dashed lines. The left side shows the experimental waveform without an open-circuit fault, the middle side shows the experimental waveform with an open-circuit fault, and the right side shows the experimental waveform after fault-tolerant control. The four waveforms from top to bottom are: 1) V ao_rec Bridge arm voltage V ao Voltage after full-wave rectification; 2)i a : Figure 2 The current in phase a; 3) the moment an open-circuit fault occurs (low level to high level transition); 4) the moment fault-tolerant control is implemented (low level to high level transition). From Figure 7a , Figure 7b and Figure 7c As can be seen from this, when fault-tolerant control is adopted, V ao_rec and i a The waveforms in these two experiments returned to the same waveforms as under the condition of no open circuit fault, indicating that the fault-tolerant T-type three-level inverter has returned to normal operation, verifying the effectiveness of the fault-tolerant T-type three-level inverter and its control method proposed in this invention.

Claims

1. A T-type three-level inverter with fault-tolerant function, comprising a-phase bridge arm circuit, b-phase bridge arm circuit, c-phase bridge arm circuit and two voltage dividing capacitors, each of the bridge arm circuits is composed of four power switching devices, a resistor and an inductor, and each of the twelve power switching devices is an insulated gate bipolar transistor with an anti-parallel diode, characterized in that: Further comprising a fault-tolerant unit, the fault-tolerant unit is composed of four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors, the fault-tolerant power switching device is an insulated gate bipolar transistor with a reverse-parallel diode, the collector of the first fault-tolerant power switching device is connected with the positive terminal of the first voltage dividing capacitor, the emitter of the first fault-tolerant power switching device is connected with the second anode of the first fault-tolerant bidirectional thyristor, the second anode of the second fault-tolerant bidirectional thyristor, the second anode of the third fault-tolerant bidirectional thyristor, the collector of the third fault-tolerant power switching device and the collector of the fourth fault-tolerant power switching device respectively, the first anode of the first fault-tolerant bidirectional thyristor is connected with the midpoint of the bridge arm of phase a, the first anode of the second fault-tolerant bidirectional thyristor is connected with the midpoint of the bridge arm of phase b, the first anode of the third fault-tolerant bidirectional thyristor is connected with the midpoint of the bridge arm of phase c, the collector of the second fault-tolerant power switching device is connected with the DC voltage midpoint of the two voltage dividing capacitors, the emitter of the second fault-tolerant power switching device is connected with the emitter of the third fault-tolerant power switching device, the emitter of the fourth fault-tolerant power switching device is connected with the negative terminal of the second voltage dividing capacitor, the gates of the four fault-tolerant power switching devices and the gates of the three fault-tolerant bidirectional thyristors are used to input driving signals; ​ The collector of the first power switching device in the bridge arm circuit of each phase is connected with the positive terminal of the first voltage dividing capacitor, the emitter of the first power switching device in the bridge arm circuit of each phase is connected with the collector of the third power switching device, the collector of the fourth power switching device and one end of the resistor in the bridge arm circuit of the corresponding phase respectively, and the common connection end is the midpoint of the bridge arm of the corresponding phase, the collector of the second power switching device in the bridge arm circuit of each phase is connected with the negative terminal of the first voltage dividing capacitor and the positive terminal of the second voltage dividing capacitor respectively, the common connection end of the negative terminal of the first voltage dividing capacitor and the positive terminal of the second voltage dividing capacitor is the DC voltage midpoint of the two voltage dividing capacitors, the emitter of the second power switching device in the bridge arm circuit of each phase is connected with the emitter of the third power switching device in the bridge arm circuit of the corresponding phase, the emitter of the fourth power switching device in the bridge arm circuit of each phase is connected with the negative terminal of the second voltage dividing capacitor, the other end of the resistor in the bridge arm circuit of each phase is connected with one end of the inductor in the bridge arm circuit of the corresponding phase, the other ends of the inductors in the bridge arm circuits of the three phases are connected together, and the gates of the four power switching devices in the bridge arm circuit of each phase are used to input driving signals.

2. A fault-tolerant control method of a T-type three-level inverter having a fault-tolerant function, characterized by The method comprises the following steps: Step 1: build a T-type three-level inverter with fault-tolerant function, which includes a phase bridge arm circuit, b phase bridge arm circuit, c phase bridge arm circuit, two voltage dividing capacitors and fault-tolerant unit, each phase bridge arm circuit is composed of four power switching devices, a resistor and an inductor, the four power switching devices are all insulated gate bipolar transistors with anti-parallel diodes, the collector of the first power switching device in each phase bridge arm circuit is connected with the positive terminal of the first voltage dividing capacitor, the emitter of the first power switching device in each phase bridge arm circuit is connected with the collector of the third power switching device, the collector of the fourth power switching device and one end of the resistor in the corresponding one phase bridge arm circuit respectively, and the common connection end is the bridge arm midpoint of the corresponding one phase, the collector of the second power switching device in each phase bridge arm circuit is connected with the negative terminal of the first voltage dividing capacitor and the positive terminal of the second voltage dividing capacitor respectively, the common connection end of the negative terminal of the first voltage dividing capacitor and the positive terminal of the second voltage dividing capacitor is the DC voltage midpoint of the two voltage dividing capacitors, the emitter of the second power switching device in each phase bridge arm circuit is connected with the emitter of the third power switching device in the corresponding one phase bridge arm circuit, the emitter of the fourth power switching device in each phase bridge arm circuit is connected with the negative terminal of the second voltage dividing capacitor, the other end of the resistor in each phase bridge arm circuit is connected with one end of the inductor in the corresponding one phase bridge arm circuit, the other ends of the inductors in the three phase bridge arm circuits are connected together, the gates of the four power switching devices in each phase bridge arm circuit are used to input driving signals, the fault-tolerant unit is composed of four fault-tolerant power switching devices and three fault-tolerant bidirectional thyristors, the fault-tolerant power switching devices are all insulated gate bipolar transistors with anti-parallel diodes, the collector of the first fault-tolerant power switching device is connected with the positive terminal of the first voltage dividing capacitor, the emitter of the first fault-tolerant power switching device is connected with the second anode of the first fault-tolerant bidirectional thyristor, the second anode of the second fault-tolerant bidirectional thyristor, the second anode of the third fault-tolerant bidirectional thyristor, the collector of the third fault-tolerant power switching device and the collector of the fourth fault-tolerant power switching device respectively, the first anode of the first fault-tolerant bidirectional thyristor is connected with the bridge arm midpoint of a phase, the first anode of the second fault-tolerant bidirectional thyristor is connected with the bridge arm midpoint of b phase, the first anode of the third fault-tolerant bidirectional thyristor is connected with the bridge arm midpoint of c phase, the collector of the second fault-tolerant power switching device is connected with the DC voltage midpoint of the two voltage dividing capacitors, the emitter of the second fault-tolerant power switching device is connected with the emitter of the third fault-tolerant power switching device, the emitter of the fourth fault-tolerant power switching device is connected with the negative terminal of the second voltage dividing capacitor, the gates of the four fault-tolerant power switching devices and the gates of the three fault-tolerant bidirectional thyristors are used to input driving signals; Step 2: In the T-type three-level inverter with fault-tolerant function, twelve power switching devices in the a-phase bridge arm circuit, the b-phase bridge arm circuit and the c-phase bridge arm circuit are divided into two categories, i.e., half-bridge switching devices and neutral-point switching devices, the half-bridge switching devices include the first power switching device and the fourth power switching device in the a-phase bridge arm circuit, the first power switching device and the fourth power switching device in the b-phase bridge arm circuit, and the first power switching device and the fourth power switching device in the c-phase bridge arm circuit, and the neutral-point switching devices include the second power switching device and the third power switching device in the a-phase bridge arm circuit, the second power switching device and the third power switching device in the b-phase bridge arm circuit, and the second power switching device and the third power switching device in the c-phase bridge arm circuit; and the T-type three-level inverter with fault-tolerant function is set to be able to normally work or to have a single half-bridge switching device open-circuit fault, a single neutral-point switching device open-circuit fault, all four power switching devices in the a-phase bridge arm circuit open-circuit fault, all four power switching devices in the b-phase bridge arm circuit open-circuit fault, or all four power switching devices in the c-phase bridge arm circuit open-circuit fault; Step 3: The twelve power switching devices in the a-phase bridge arm circuit, the b-phase bridge arm circuit and the c-phase bridge arm circuit are controlled to be turned on and turned off according to the original control strategy of the a-phase bridge arm circuit, the b-phase bridge arm circuit and the c-phase bridge arm circuit, while the four fault-tolerant power switching devices and the three fault-tolerant bidirectional thyristors in the fault-tolerant unit are all turned off; then a T-type three-level inverter fault diagnosis method is used to diagnose the T-type three-level inverter with fault-tolerant function to determine whether an open-circuit fault occurs and identify the type of the open-circuit fault when the open-circuit fault occurs; the type of the open-circuit fault includes a single half-bridge switching device open-circuit fault, a single neutral-point switching device open-circuit fault, all four power switching devices in the a-phase bridge arm circuit open-circuit fault, all four power switching devices in the b-phase bridge arm circuit open-circuit fault, or all four power switching devices in the c-phase bridge arm circuit open-circuit fault; Step 4: If it is diagnosed that no open-circuit fault occurs, the twelve power switching devices in the a-phase bridge arm circuit, the b-phase bridge arm circuit and the c-phase bridge arm circuit are kept to be turned on and turned off according to the original control strategy of the a-phase bridge arm circuit, the b-phase bridge arm circuit and the c-phase bridge arm circuit, while the four fault-tolerant power switching devices and the three fault-tolerant bidirectional thyristors in the fault-tolerant unit are all turned off. If an open-circuit fault is diagnosed and it is identified as an open-circuit fault of a single half-bridge switching device, when the first power switching device or the fourth power switching device in the a-phase bridge arm circuit has an open-circuit fault, the first power switching device and the fourth power switching device in the a-phase bridge arm circuit are controlled to be turned off at the same time, the first fault-tolerant thyristor is turned on, the first fault-tolerant power switching device and the fourth fault-tolerant power switching device are turned on, the drive signal originally applied to the gate of the first power switching device in the a-phase bridge arm circuit is applied to the gate of the first fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the a-phase bridge arm circuit is applied to the gate of the fourth fault-tolerant power switching device; when the first power switching device or the fourth power switching device in the b-phase bridge arm circuit has an open-circuit fault, the first power switching device and the fourth power switching device in the b-phase bridge arm circuit are controlled to be turned off at the same time, the second fault-tolerant thyristor is turned on, the first fault-tolerant power switching device and the fourth fault-tolerant power switching device are turned on, the drive signal originally applied to the gate of the first power switching device in the b-phase bridge arm circuit is applied to the gate of the first fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the b-phase bridge arm circuit is applied to the gate of the fourth fault-tolerant power switching device; when the first power switching device or the fourth power switching device in the c-phase bridge arm circuit has an open-circuit fault, the first power switching device and the fourth power switching device in the c-phase bridge arm circuit are controlled to be turned off at the same time, the third fault-tolerant thyristor is turned on, the first fault-tolerant power switching device and the fourth fault-tolerant power switching device are turned on, the drive signal originally applied to the gate of the first power switching device in the c-phase bridge arm circuit is applied to the gate of the first fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the c-phase bridge arm circuit is applied to the gate of the fourth fault-tolerant power switching device. If it is diagnosed that an open-circuit fault occurs and it is identified that it is an open-circuit fault of a single neutral-point switching device, when the second power switching device or the third power switching device in the a-phase bridge arm circuit has an open-circuit fault, the second power switching device and the third power switching device in the a-phase bridge arm circuit are controlled to be turned off at the same time, the first fault-tolerant bidirectional thyristor is turned on, the second fault-tolerant power switching device and the third fault-tolerant power switching device are turned on, the drive signal originally applied to the gate of the second power switching device in the a-phase bridge arm circuit is applied to the gate of the second fault-tolerant power switching device, and the drive signal originally applied to the gate of the third power switching device in the a-phase bridge arm circuit is applied to the gate of the third fault-tolerant power switching device; when the second power switching device or the third power switching device in the b-phase bridge arm circuit has an open-circuit fault, the second power switching device and the third power switching device in the b-phase bridge arm circuit are controlled to be turned off at the same time, the second fault-tolerant bidirectional thyristor is turned on, the second fault-tolerant power switching device and the third fault-tolerant power switching device are turned on, the drive signal originally applied to the gate of the second power switching device in the b-phase bridge arm circuit is applied to the gate of the second fault-tolerant power switching device, and the drive signal originally applied to the gate of the third power switching device in the b-phase bridge arm circuit is applied to the gate of the third fault-tolerant power switching device; when the second power switching device or the third power switching device in the c-phase bridge arm circuit has an open-circuit fault, the second power switching device and the third power switching device in the c-phase bridge arm circuit are controlled to be turned off at the same time, the third fault-tolerant bidirectional thyristor is turned on, the second fault-tolerant power switching device and the third fault-tolerant power switching device are turned on, the drive signal originally applied to the gate of the second power switching device in the c-phase bridge arm circuit is applied to the gate of the second fault-tolerant power switching device, and the drive signal originally applied to the gate of the third power switching device in the c-phase bridge arm circuit is applied to the gate of the third fault-tolerant power switching device; If it is diagnosed that an open-circuit fault occurs and it is identified that it is an open-circuit fault of all the four power switching devices in the a-phase bridge arm circuit, the four power switching devices in the a-phase bridge arm circuit are controlled to be turned off at the same time, the first fault-tolerant bidirectional thyristor is turned on, and all the four fault-tolerant power switching devices are turned on, the drive signal originally applied to the gate of the first power switching device in the a-phase bridge arm circuit is applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in the a-phase bridge arm circuit is applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in the a-phase bridge arm circuit is applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the a-phase bridge arm circuit is applied to the gate of the fourth fault-tolerant power switching device; If it is diagnosed that open-circuit fault occurs and it is identified that all four power switching devices in the b-phase bridge arm circuit are open-circuit fault, the four power switching devices in the b-phase bridge arm circuit are controlled to be turned off at the same time, the second fault-tolerant bidirectional thyristor is turned on, the four fault-tolerant power switching devices are turned on, the drive signal originally applied to the gate of the first power switching device in the b-phase bridge arm circuit is applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in the b-phase bridge arm circuit is applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in the b-phase bridge arm circuit is applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the b-phase bridge arm circuit is applied to the gate of the fourth fault-tolerant power switching device. If it is diagnosed that open-circuit fault occurs and it is identified that all four power switching devices in the c-phase bridge arm circuit are open-circuit fault, the four power switching devices in the c-phase bridge arm circuit are controlled to be turned off at the same time, the third fault-tolerant bidirectional thyristor is turned on, the four fault-tolerant power switching devices are turned on, the drive signal originally applied to the gate of the first power switching device in the c-phase bridge arm circuit is applied to the gate of the first fault-tolerant power switching device, the drive signal originally applied to the gate of the second power switching device in the c-phase bridge arm circuit is applied to the gate of the second fault-tolerant power switching device, the drive signal originally applied to the gate of the third power switching device in the c-phase bridge arm circuit is applied to the gate of the third fault-tolerant power switching device, and the drive signal originally applied to the gate of the fourth power switching device in the c-phase bridge arm circuit is applied to the gate of the fourth fault-tolerant power switching device.

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