Method and associated device for determining a measurement selection scheme

Abstract

Disclosed is a method for determining a measurement selection scheme, the measurement selection scheme describing a measurement setting for measuring a parameter of interest from a substrate affected by parameter errors caused by etching, the parameter errors caused by etching affecting the measurement of the parameter of interest in a manner depending on the selection scheme. The method includes: obtaining debug data of the parameter of interest related to the measurement of at least one debug substrate, the parameter of interest on the at least one debug substrate having a plurality of first induced adjustment values; and obtaining debug data of the parameter caused by etching related to the measurement of at least one debug substrate, the parameter caused by etching on the at least one debug substrate having a plurality of second induced adjustment values. Determining the selection scheme to minimize the influence of the parameter caused by etching on the measurement of the parameter of interest.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to European Application No. 19218690.6, filed on December 20, 2019, and the entire content of the European application is incorporated herein by reference. Technical field

[0003] The present invention relates to metrology applications in the manufacture of integrated circuits. Background art

[0004] A lithographic apparatus is a machine configured to apply a desired pattern onto a substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A lithographic apparatus can project a pattern (also often referred to as a “design layout” or “design”) present on a patterning device (e.g., a mask) onto a layer of radiation - sensitive material (resist) provided on a substrate (e.g., a wafer).

[0005] In order to project a pattern onto a substrate, a lithographic apparatus can use electromagnetic radiation. The wavelength of this radiation determines the minimum size of the features that can be formed on the substrate. Typical wavelengths currently in use are 365 nm (i - line), 248 nm, 193 nm, and 13.5 nm. Compared to a lithographic apparatus using radiation having a wavelength of, for example, 193 nm, a lithographic apparatus using extreme ultraviolet (EUV) radiation having a wavelength in the range of between 4 nm and 20 nm (e.g., 6.7 nm or 13.5 nm) can be used to form smaller features on a substrate.

[0006] Low k 1 Lithography can be used to process features smaller than the classical resolution limit of a lithographic apparatus. In such a process, the resolution formula can be expressed as CD = k 1 ×λ / NA, where λ is the wavelength of the radiation employed, NA is the numerical aperture of the projection optics in the lithographic apparatus, CD is the “critical dimension” (usually the smallest feature size printed, but in this case the half - pitch) and k 1 is an empirical resolution factor. Typically, k 1The smaller it is, the more difficult it becomes to reproduce on the substrate a pattern that is similar in shape and size to that planned by the circuit designer in order to achieve a specific electrical functionality and performance. To overcome these difficulties, complex fine-tuning steps can be applied to the lithographic projection apparatus and / or the design layout. These steps include, for example but not limited to, optimization of the NA, customized illumination schemes, use of a phase-shifting patterning device, various optimizations of the design layout such as optical proximity correction (OPC, sometimes also referred to as "optical and process correction") in the design layout, or other methods generally defined as "resolution enhancement techniques" (RET). Alternatively, a strict control loop for controlling the stability of the lithographic apparatus can be used to improve the reproduction of the pattern at low k 1 under the pattern.

[0007] Measurement tools are used, for example, as alignment tools for proper positioning of the substrate before exposure and as scatterometry-based tools for inspecting / measuring the exposed and / or etched product in process control in many aspects of the IC manufacturing process; for example, to measure overlay.

[0008] To perform a measurement, a measurement recipe including a number of measurement settings (such as illumination settings) should be selected since these settings generally affect the measurement quality. An improvement in the method for determining the measurement recipe would be desirable. Summary of the Invention

[0009] In a first aspect of the invention, there is provided a method for determining a measurement recipe, the measurement recipe describing measurement settings for measuring a parameter of interest on a substrate subject to etch-induced parameter errors, the etch-induced parameter errors affecting the measurement of the parameter of interest in a manner dependent on the recipe; the method comprising: obtaining setting data of the parameter of interest related to the measurement of at least one set substrate, the parameter of interest on the at least one set substrate having a plurality of first-induced setting values; obtaining setting data of the etch-induced parameter related to the measurement of at least one set substrate, the etch-induced parameter on the at least one set substrate having a plurality of second-induced setting values; and determining the recipe to minimize the effect of the etch-induced parameter on the measurement of the parameter of interest.

[0010] Also disclosed are a computer program, an alignment sensor, and a lithographic apparatus capable of operating to perform the method described in the first aspect.

[0011] The above and other aspects of the invention will be understood from the consideration of the examples described below. Brief Description of the Drawings

[0012] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which:

[0013] - Figure 1 Schematic overview of a lithographic apparatus;

[0014] - Figure 2 Schematic overview of a lithographic cell;

[0015] - Figure 3 Schematic representation of overall lithography, showing the cooperation between three key technologies for optimizing semiconductor manufacturing;

[0016] - Figure 4 Schematic overview of a scatterometry apparatus used as a metrology device for a method according to an embodiment of the invention;

[0017] - Figure 5 Comprising Figure 5 (a) Schematic of a pupil and dark field scatterometer for a method according to an embodiment of the invention using a first reference aperture, and Figure 5 (b) Details of the diffraction spectrum of a target grating for a given illumination direction;

[0018] - Figure 6 Schematic of a flow chart depicting a method according to an embodiment of the invention; and - Figure 7 Depicting an expected pattern or feature signature that can be observed due to etch-induced tilt. DETAILED DESCRIPTION

[0019] In this document, the terms "radiation" and "beam" are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. having a wavelength of 365 nm, 248 nm, 193 nm, 157 nm or 126 nm) and extreme ultraviolet radiation (EUV, e.g. having a wavelength in the range of about 5 nm to 100 nm).

[0020] As used herein, the terms "reticle", "mask" or "patterning device" can be broadly interpreted to mean a general patterning device that can be used to impart a patterned cross-section to an incident radiation beam, the patterned cross-section corresponding to a pattern to be created in a target portion of a substrate. In such a context, the term "light valve" can also be used. Examples of other such patterning devices include programmable mirror arrays and programmable LCD arrays, in addition to classical masks (transmission or reflection, binary, phase-shift, hybrid, etc.).

[0021] Figure 1Schematically depicts a lithographic apparatus LA or scanner (the two terms are used synonymously, but the concepts herein can also apply to stepper arrangements). The lithographic apparatus LA includes: an illumination system (also referred to as an illuminator) IL configured to condition a radiation beam B (e.g., UV radiation, DUV radiation, or EUV radiation); a mask support (e.g., a mask table) MT configured to support a patterning device (e.g., a mask) MA and connected to a first positioner PM configured to accurately position the patterning device MA according to certain parameters; a substrate support (e.g., a wafer table) WT configured to hold a substrate (e.g., a wafer coated with resist) W and connected to a second positioner PW configured to accurately position the substrate support according to certain parameters; and a projection system (e.g., a refractive projection lens system) PS configured to project the pattern imparted to the radiation beam B by the patterning device MA onto a target portion C (e.g., including one or more dies) of the substrate W.

[0022] In operation, the illumination system IL receives the radiation beam from a radiation source SO, e.g., via a beam delivery system BD. The illumination system IL can include various types of optical components for guiding, shaping, and / or controlling the radiation, such as refractive, reflective, magnetic, electromagnetic, electrostatic, and / or other types of optical components, or any combination thereof. The illuminator IL can be used to condition the radiation beam B to have a desired spatial and angular intensity distribution in a cross-section at the plane of the patterning device MA.

[0023] The term "projection system" PS as used herein should be broadly interpreted to cover various types of projection systems suitable for the exposure radiation used and / or for other factors such as the use of an immersion liquid or the use of a vacuum, including refractive, reflective, catadioptric, anamorphic, magnetic, electromagnetic, and / or electrostatic optical systems or any combination thereof. Any use of the term "projection lens" herein can be considered synonymous with the more general term "projection system" PS.

[0024] The lithographic apparatus LA can be of a type in which at least a portion of the substrate can be covered by a liquid, e.g., water, having a relatively high refractive index to fill the space between the projection system PS and the substrate W - this is also known as immersion lithography. More information on immersion techniques is given in US6952253, which is incorporated herein by reference.

[0025] The lithographic apparatus LA can also be of the type having two or more substrate supports WT (also known as “dual stage”). In such a “multi-stage” machine, the substrate supports WT can be used in parallel, and / or steps of preparing a substrate W for a subsequent exposure of the substrate W located on one of the substrate supports WT can be carried out while another substrate W on another substrate support WT is used for exposing a pattern on another substrate W.

[0026] In addition to the substrate support WT, the lithographic apparatus LA can also include a metrology stage. The metrology stage is arranged to hold sensors and / or cleaning devices. The sensors can be arranged to measure properties of the projection system PS or of the radiation beam B. The metrology stage can hold a plurality of sensors. The cleaning devices can be arranged to clean parts of the lithographic apparatus, for example parts of the projection system PS or parts of the system providing the immersion liquid. The metrology stage can move under the projection system PS when the substrate support WT is away from the projection system PS.

[0027] In operation, the radiation beam B is incident on a patterning device (e.g., a mask) MA held on a mask support MT and is patterned by the pattern (design layout) present on the patterning device MA. After traversing the mask MA, the radiation beam B passes through the projection system PS, which focuses the beam onto a target portion C of the substrate W. By means of a second positioning device PW and a position measurement system IF, the substrate support WT can be accurately moved, for example, in order to position different target portions C in the path of the radiation beam B at a focus and alignment position. Similarly, a first positioning device PM and possibly another position sensor (which is not explicitly depicted in Figure 1 ) can be used to accurately position the patterning device MA relative to the path of the radiation beam B. Mask alignment marks M1, M2 and substrate alignment marks P1, P2 can be used to align the patterning device MA with the substrate W. Although as illustrated the substrate alignment marks P1, P2 occupy dedicated target portions, they can be located in the space between the target portions. When the substrate alignment marks P1, P2 are located between the target portions C, these substrate alignment marks are called scribe alignment marks.

[0028] As Figure 2As shown, a lithographic apparatus LA can form part of a lithographic cell LC (sometimes also referred to as a lithographic cell or (lithographic) cluster), which often also includes equipment for performing pre-exposure processes and post-exposure processes on a substrate W. Conventionally, these include a spin coater SC for depositing a resist layer, a developer DE for developing the exposed resist, a chill plate CH and a bake plate BK for regulating the temperature of the substrate W (e.g., for regulating the solvent in the resist layer). A substrate transfer device or robot RO picks up the substrate W from the input / output ports I / O1, I / O2, moves the substrate W between different process devices and transfers the substrate W to the feed table LB of the lithographic apparatus LA. Devices typically collectively referred to as a track in the lithographic cell are typically under the control of a track control unit TCU, which itself can be controlled by a management control system SCS, which can also control the lithographic apparatus LA via, for example, a lithographic control unit LACU.

[0029] To correctly and consistently expose the substrate W exposed by the lithographic apparatus LA, it is desirable to inspect the substrate to measure the properties of the patterned structures, such as overlay errors between subsequent layers, line thickness, critical dimension (CD), etc. For this purpose, an inspection tool (not shown) can be included in the lithographic cell LC. If an error is detected, adjustments can be made, for example, to the exposure of subsequent substrates or to other processing steps to be performed on the substrate W, especially in cases where inspections are carried out before other substrates W in the same batch or lot are still to be exposed or processed.

[0030] An inspection device, which can also be referred to as a metrology device, is used to determine the properties of the substrate W, and specifically, how the properties of different substrates W vary or how the properties related to different layers of the same substrate W vary from layer to layer. The inspection device is alternatively configured to identify defects on the substrate W and can be, for example, part of the lithographic cell LC, or can be integrated into the lithographic apparatus LA, or can even be a separate device. The inspection device can measure the properties of a latent image (the image in the resist layer after exposure), or a semi-latent image (the image in the resist layer after a post-exposure bake step PEB), or a developed resist image (where the exposed or unexposed portions of the resist have been removed), or even an etched image (after a pattern transfer step such as etching).

[0031] Typically, the patterning process in the lithographic apparatus LA is one of the most important steps in the process, which requires a high degree of accuracy in the sizing and placement of the structures on the substrate W. To ensure this high degree of accuracy, three systems can be combined in a so-called "integrated" control environment, as Figure 3Schematically depicted. One of these systems is a lithographic apparatus LA, which is (in fact) connected to a metrology tool MT (second system) and to a computer system CL (third system). The key to such an "integrated" environment is to optimize the collaboration between these three systems to enhance the overall process window and provide a tight control loop, thus ensuring that the patterning performed by the lithographic apparatus LA remains within the process window. The process window defines a range of process parameters (such as dose, focus, overlay), within which a particular manufacturing process yields a defined result (such as a functional semiconductor device) - typically within which variations in the process parameters during the lithography process or patterning process are allowed.

[0032] The computer system CL can use (parts of) the design layout to be patterned to predict which resolution enhancement techniques to use, and perform computational lithography simulations and calculations to determine which mask layout and lithographic apparatus settings achieve the maximum overall process window for the patterning process (depicted by the double arrow in the first scale SC1 in Figure 3 . Typically, the resolution enhancement techniques are arranged to match the patterning capabilities of the lithographic apparatus LA. The computer system CL can also be used to detect where within the process window the lithographic apparatus LA is currently operating (e.g., using input from the metrology tool MT) to predict whether defects may be present due to, for example, sub-optimal processing (depicted by the arrow pointing to "0" in the second scale SC2 in Figure 3 .

[0033] The metrology tool MT can provide input to the computer system CL to enable accurate simulations and predictions, and can provide feedback to the lithographic apparatus LA to identify possible drifts, for example, in the calibration state of the lithographic apparatus LA (depicted by the multiple arrows in the third scale SC3 in Figure 3 .

[0034] During the lithography process, it is desirable to frequently measure the structures produced, e.g., for process control and verification. Tools used to make such measurements are typically referred to as metrology tools MT. Different types of metrology tools MT for making such measurements are well known and include scanning electron microscopes or various forms of scatterometer metrology tools MT. A scatterometer is a versatile instrument that allows for the measurement of lithography process parameters by having a sensor in the pupil or a plane conjugate to the pupil of the scatterometer's objective lens, and the measurement is typically referred to as pupil-based measurement, or allows for the measurement of lithography process parameters by having a sensor in the image plane or a plane conjugate to the image plane, in which case the measurement is typically referred to as image- or field-based measurement. Patent applications US20100328655, US2011102753A1, US20120044470A, US20110249244, US20110026032 or EP1,628,164A, which are incorporated herein by reference in their entirety, further describe such scatterometers and related measurement techniques. The aforementioned scatterometers can use radiation from soft x-rays and light visible in the near-IR wavelength range to measure gratings.

[0035] In a first embodiment, the scatterometer MT is an angular-resolved scatterometer. In such a scatterometer, a reconstruction method can be applied to the measured signal to reconstruct or calculate the properties of the grating. Such a reconstruction can be caused, for example, by simulating the interaction of the scattered radiation with a mathematical model of the target arrangement and comparing the simulated results with those measured. The parameters of the mathematical model are adjusted until the simulated interaction produces a diffraction pattern similar to the diffraction pattern observed from the real target.

[0036] In a second embodiment, the scatterometer MT is a spectroscopic scatterometer MT. In such a spectroscopic scatterometer MT, radiation emitted by a radiation source is directed onto a target and the reflected or scattered radiation from the target is directed to a spectrometer detector that measures the spectrum of the specularly reflected radiation (i.e., the measurement of intensity as a function of wavelength). From this data, the structure or profile of the target that produced the detected spectrum can be reconstructed, for example, by rigorous coupled-wave analysis and non-linear regression or by comparison with a simulated spectral library.

[0037] In a third embodiment, the scatterometer MT is an ellipsometric scatterometer. An ellipsometric scatterometer allows determination of parameters of a lithography process by measuring scattered radiation for each polarization state. Such metrology equipment emits polarized light (such as linear, circular or elliptical) by using, for example, a suitable polarization filter in the illumination section of the metrology equipment. A source suitable for the metrology equipment can also provide polarized radiation. U.S. Patent Applications 11 / 451,599, 11 / 708,678, 12 / 256,780, 12 / 486,449, 12 / 920,968, 12 / 922,587, 13 / 000,229, 13 / 033,135, 13 / 533,110 and 13 / 891,410, which are incorporated herein by reference in their entirety, describe various embodiments of existing ellipsometric scatterometers.

[0038] Figure 4 depicts a metrology equipment, such as a scatterometer. The scatterometer includes a broadband (white light) radiation projector 2 that projects radiation onto a substrate W. The reflected or scattered radiation is transmitted to a spectrometer detector 4, which measures the spectrum 6 of the specularly reflected radiation (i.e., the measurement of the intensity as a function of wavelength). From such data, the processing unit PU can reconstruct the structure or profile 8 that gives rise to the detected spectrum, for example, by rigorous coupled-wave analysis and non-linear regression, or by comparison with a Figure 3 simulated spectral library shown at the bottom of. Generally, for reconstruction, the general form of the structure is known, and some parameters are assumed from knowledge of the process used to fabricate the structure, leaving only a few parameters of the structure to be determined from the scatterometry measurement data. Such a scatterometer can be configured as a normal incidence scatterometer or an oblique incidence scatterometer.

[0039] Figure 5 (a) presents an embodiment of a metrology equipment and more particularly a dark field scatterometer. Figure 5 (b) more particularly illustrates the target T and the diffracted rays of the measurement radiation used to irradiate the target. The illustrated metrology equipment belongs to the type known as a dark field metrology equipment. The metrology equipment can be a stand-alone device, or incorporated into a lithography apparatus LA (e.g., at a measurement station) or a lithography cell LC. The optical axis with several branches throughout the equipment is represented by the dashed line O. In such an equipment, the light emitted by a source 11 (e.g., a xenon lamp) is guided to the substrate W via a beam splitter 15 by an optical system including lenses 12, 14 and an objective lens 16. These lenses are arranged in a double sequence in a 4F arrangement. Different lens arrangements can be used as long as the lens arrangement still provides an image of the substrate onto the detector and at the same time allows access to the intermediate pupil plane for spatial frequency filtering. Thus, the illumination angle can be designed or adjusted such that the first-order rays entering the objective lens are closely aligned with the central optical axis. Figure 5 (a) and Figure 3(b) The rays illustrated are shown slightly off-axis only to enable them to be more easily distinguished in the figure.

[0040] At least the 0th and +1st orders diffracted by the target T on the substrate W are collected by the objective lens 16 and are guided back through the beam splitter 15. Returning to Figure 5 (a), both the first illumination mode and the second illumination mode are illustrated by specifying diametrically opposed holes labeled North (N) and South (S). When the incident ray I of the radiation being measured comes from the north side of the optical axis, i.e., when the first illumination mode is applied using the aperture plate 13N, the +1 diffracted ray labeled +1(N) enters the objective lens 16. In contrast, when the second illumination mode is applied using the aperture plate 13S, the -1 diffracted ray (labeled 1(S)) is the diffracted ray entering the lens 16.

[0041] The second beam splitter 17 divides the diffracted beam into two measurement branches. In the first measurement branch, the optical system 18 uses the 0th order diffracted beam and the 1st order diffracted beam to form a diffraction spectrum (pupil plane image) of the target on the first sensor 19 (e.g., a CCD or CMOS sensor). Each diffracted order hits, i.e., strikes, a different point on the sensor, such that image processing can compare and contrast multiple orders. The pupil plane image captured by the sensor 19 can be used to focus the metrology device and / or normalize the intensity measurement results of the 1st order beam. The pupil plane image can also be used for many measurement purposes such as reconstruction. The concepts disclosed herein relate to using such branched pupil measurements.

[0042] In the second measurement branch, the optical systems 20, 22 form an image of the target T on the sensor 23 (e.g., a CCD or CMOS sensor). In the second measurement branch, an aperture stop 21 is disposed in a plane conjugate to the pupil plane. The aperture stop 21 is used to block the 0th order diffracted beam such that the image of the target formed on the sensor 23 is formed only by the -1 or +1 order beam. The images captured by the sensors 19 and 23 are output to a processor PU that processes the images, and the function of the processor PU will depend on the specific type of measurement being performed. It should be noted that the term "image" is used herein in a broad sense. Thus, if only one of the -1 and +1 orders exists, an image of the grating lines will not be formed. Figure 5 The specific forms of the aperture plate 13 and the field stop 21 shown in are merely examples.

[0043] The metrology tool described above can be used to measure overlay in a device using a zero - order response (pupil) after etching. This method is currently referred to as metrology OV in device (IDM OV). The main functional requirement of IDM is that the target being measured includes asymmetry when there is an overlay error. By monitoring the asymmetry induced in the zero - order pupil, IDM can measure the existing overlay.

[0044] To measure overlay, an alignment pattern needs to be generated, which should be sensitive only to the overlay of interest and robust (i.e., insensitive) to process variations and other asymmetries. Due to cross - polarization, many acquisition settings (wavelength, grating - to - sensor rotation, and polarization) can generate alignment patterns that show sensitivity to the OV of interest. Unfortunately, many of these alignment patterns can measure different die maps for the same wafer in the presence of large point - to - point differences. Specifically, this phenomenon is observed for more complex structures such as bit - line placement (GBL), storage - node placement (SN), and 3D NAND in DRAM. Therefore, it is expected that, in addition to the overlay of interest, the main cause of the large diversity in die maps is due to asymmetries in the structure, such as those known to exist in these structures. Additionally, the sensor also induces die maps, which can also depend on the acquisition strategy. One of the key performance indicators (KPIs) in the formation of IDM alignment patterns is the quantification of crosstalk in the IDM alignment pattern. Crosstalk indicates the degree to which the alignment pattern is vulnerable to changes in different layers. For example, an alignment pattern used to measure bit - line OV may be vulnerable to other overlays (e.g., bit - line contact OV, DRAM OV, etc.).

[0045] The two main contributing factors to the asymmetry in the pupil are overlay (e.g., the overlay of interest or the parameter of interest) and etch - induced tilt. Certain etch techniques, such as deep silicon etching, may cause a radial mismatch between the front and back sides of the wafer, which is inherently coupled to the plasma - etching process itself (rather than the exposure process) and is referred to as tilt error or just tilt.

[0046] Although there are KPIs for quantifying the amount of crosstalk in the presence of tilt for a given alignment pattern, no method has been identified for suppressing crosstalk other than using different acquisition settings (WL / polarization / wafer rotation). Since this crosstalk degrades the alignment - pattern accuracy, a method for suppressing such crosstalk is desired. This crosstalk will mainly manifest at the edges of the wafer; a substantial IDM accuracy penalty (i.e., substantial IDM accuracy loss) has been observed for overlay measurements; for example, an error of approximately 10 nm or greater at the edges of the wafer, which is believed to be due to crosstalk in the presence of tilt.

[0047] To reduce the crosstalk between the two main contributing factors, i.e., the enabling factors, of the asymmetry in the pupil, it is proposed to use tilt analysis to expand the IDM matching scheme settings in order to address any measured asymmetry caused by the tilt resulting from the measurement of the parameter of interest (e.g., overlap; more specifically, the overlap of interest, such as the overlap of a particular layer or structure). The proposed IDM matching scheme settings can also address such overlap of interest from other sources of pupil asymmetry, such as other overlaps (e.g., the overlap of other layers or structures).

[0048] The proposed method may include: during the setup phase, introducing a setup error (e.g., tilt error) for the etch-induced parameter on the matching scheme setup wafer (or design of experiments wafer), in addition to introducing a setup overlap error in the scanner on the same or another matching scheme setup wafer (or design of experiments wafer). By having two controllable input parameters for design of experiments (DoE) in the IDM matching scheme, it is possible to significantly reduce the crosstalk between overlap and tilt.

[0049] Figure 6 Conceptually illustrate such a matching scheme formation method. Scanner LA is used to form (at least) one DoE wafer DoE with one or more scanner-induced OVs OV This may include only inducing overlap for the overlap of interest (e.g., variations in such overlap across the entire wafer). Alternatively, such a step may include inducing overlap of other overlap parameters related to other layers or structures (on the same wafer or multiple different wafers in such a set of wafer DoE OV ), thereby enabling the addressing of the overlap of interest originating from other overlaps other than tilt.

[0050] Etcher EH is used to form (at least) one DoE wafer DoE with etcher-induced tilt TI ; (e.g., variations in tilt across the entire wafer). It should be understood that these scanner and etcher steps can be combined to the extent that they are performed on one wafer or a set of wafers. Thus, instead of separate DoE wafer DoE OV and DoE wafer DoE TI (or in addition to separate DoE wafer DoE OV and DoE wafer DoE TI ), a single DoE wafer or a set of wafers can be set up to have etcher-induced tilt at the edge or peripheral region of the wafer and one or more scanner-induced OVs in the central region of the wafer.

[0051] Measurement device MET is used to measure wafer DoE OV 、DoE TI, in order to obtain training data comprising (at least) the DoE of the wafers with the overlay changes of interest OV Related overlapping data DAT OV , and DoE of wafers with changed tilt TI Related tilt data DAT TI The latter may relate to measurement results only or predominantly at the edge of the wafer where significant tilt errors are present. OV and the tilt data DAT TI Known settings for scan-induced overlap, and etch-induced tilt will also be included.

[0052] For tilted data DAT TI A component analysis step is performed. For example, such a step may include applying principal component analysis, PCA, to such data, for example, related to a target with etcher-induced tilt, in order to estimate the pupil response to the tilt. PCA is a statistical technique for identifying the directions of the highest variance (principal components) in a high-dimensional data set. Such a step may include using tilted wafer map data WM describing an expected tilted wafer map (e.g., based on knowledge and / or from experiments as described below) TI The method of claim 1 further comprising selecting one or more components of the invention that are similar to a known / expected pattern (wafer mapping) and selecting one or more components of the invention that are similar to a known / expected pattern (wafer mapping) may include selecting a principal component whose similarity to the known pattern is above a threshold similarity metric; and / or selecting one or more components having the highest similarity among all principal components according to the metric.

[0053] It should be noted that PCA is only one example of a data analysis method that can be used; any other suitable data analysis method capable of determining a tilted wafer map may be used instead. For example, independent component analysis (ICA), or more generally other blind signal separation techniques may be used. There are many of these algorithms available, as those skilled in the art will appreciate, and will know how to use any of these algorithms to estimate tilt.

[0054] Alternatively or in addition, the tilt data may be measured by SEM (e.g. from a 3D NAND structure). Thus, it is possible to obtain the tilt data from another reference source. Therefore, in an embodiment, it is proposed to use such a reference for the tilt if such a reference is available; if not, any of the aforementioned blind signal separation techniques may be used to estimate the tilt. In the first case, the cost function changes a lot (to be added below), but the idea remains the same, i.e., use the tilt information to make the matching scheme robust to the tilt.

[0055] In the matching solution formation step RC, the selected main component PC and / or the pupil response for tilt are used to determine an overlapping matching solution REC that is robust (has low sensitivity or is insensitive) to tilt; for example, the matching solution includes weights that are robust, i.e., insensitive, to the tilt response.

[0056] To make the matching solution robust, i.e., insensitive, to tilt in the final step, an additional penalty, i.e., an additional loss, can be added to the cost function used when determining the weights of the matching solution:

[0057]

[0058] where P is a matrix that includes the pupils of the targets within each row (i.e., the measured pupils); P T w corresponds to a vector that includes the "obtained values" (OV values obtained by the matching solution), s is the set value (e.g., from a scanner or an etcher, or measured using, for example, an SEM). The second term is a penalty term, i.e., a loss term, that penalizes the crosstalk between the overlap of interest and tilt: E is a matrix that includes one or more main components of the tilt data obtained in step PCA (e.g., those that most closely correspond to the expected pattern). The parameter α controls the penalty.

[0059] If SEM data is available, the cost function changes slightly:

[0060] w opt = argmin w ||P T w - s|| 2 + β||(w T P)t|| 2 ,

[0061] where t is a vector that contains the tilt obtained by reference. Basically, the cost function tries to ensure that the "obtained values" are not similar to the tilt (which tries to make the "obtained values" orthogonal to the tilt measurement, controlled by the parameter β).

[0062] Thus, the cost function determines the weights for the measured values that match well with the set value (first term) while being robust, i.e., insensitive, to tilt (second penalty term). More specifically, the cost function determines the weighting for the measured values of the parameter of interest (e.g., the vector that describes the measured values) in order to minimize the difference between the set value and the measured values induced for the parameter of interest, while including a penalty term that penalizes the crosstalk between the parameter of interest and the tilt parameter; for example, penalizing a solution that has the potential to produce a significant tilt effect (e.g., the solution corresponds to an expected tilt pattern or fingerprint).

[0063] The above simple linear regression is used as an example of making the matching solution robust to tilt. However, the method can be easily generalized to more complex regression techniques, such as neural networks (deep learning), i.e., the cost function can be easily adjusted to penalize tilt during the training of the neural network. Since neural networks are well known in the art, neural networks will not be described in detail here.

[0064] In this way, the following method is described: suppressing the crosstalk of overlaps in the case of tilt in order to increase the number of targets within specifications (e.g., at the edge of the wafer) and thus improve the yield.

[0065] As stated, the method includes selecting the principal components corresponding to the expected tilt pattern. Figure 7 Illustrate how such an expected tilt pattern might look. Etcher tilt is a radially symmetric phenomenon. The effect of etcher tilt on overlaps can be different for top and bottom structures; the effect of etcher tilt on the pattern shift of lines is perpendicular to the lines. This results in the resulting overlap shape having a sinusoidal behavior across the wafer circumference.

[0066] In Figure 7 (a), a specific (e.g., memory) structure is shown, which includes a periodic tilt (skew) active region AA in layer L1, and a cut hole CH defining the cut portion of the active region, and a word line WL in layer L2 corresponding to the cut portion. Arrows indicate the direction of the tilt error for each layer (e.g., perpendicular to the periodicity of the layer). Figure 7 (b) is a plot of the tilt error magnitude (y-axis) versus the peripheral angle (x-axis - 0 to 360 degrees) on the wafer for these two layers. The sinusoidal behavior of the tilt error is evident; for this particular layer pair, the tilt amplitude of the bottom grating is sin(22°) * the amplitude of the top grating. A shift occurs at the tilt-induced pattern. Figure 7 (c) shows the tangential behavior of the tilt with respect to the overlap for layers L1 and L2, and the combined effect. These two effects can enhance each other (same sign) or cancel each other out (opposite sign). Other layer combinations or tilt errors for cut etching will show a similar sinusoidal pattern of tilt error, but the actual shape will change (in a generally predictable way) for different angles of different layers.

[0067] Additional embodiments are disclosed in the aspects numbered subsequently:

[0068] 1. A method for determining a measurement selection scheme, the measurement selection scheme describing a measurement setting for measuring a parameter of interest from a substrate subject to parameter errors caused by etching, the parameter errors caused by etching affecting the measurement of the parameter of interest in a manner depending on the selection scheme; the method includes:

[0069] Obtaining setup data or called setup data of the parameter of interest related to the measurement of at least one setup substrate, i.e., a debug substrate, where the parameter of interest on the at least one debug substrate has multiple first induced setup values or first induced adjustment values;

[0070] Obtaining setup data of the parameter caused by etching related to the measurement of at least one debug substrate, where the parameter caused by etching on the at least one debug substrate has multiple second induced setup values or second induced adjustment values; and

[0071] Determining the selection scheme to minimize the influence of the parameter caused by etching on the measurement of the parameter of interest.

[0072] 2. The method according to aspect 1, wherein the step of determining the selection scheme includes penalizing the scheme for the selection scheme according to the similarity of the parameter error caused by etching to a known pattern.

[0073] 3. The method according to aspect 2, wherein the method includes: performing blind source separation analysis on the setup data of the parameter caused by etching to obtain components of the setup data of the parameter caused by etching; and

[0074] Penalizing the scheme for the selection scheme corresponding to the component having a high similarity to the known pattern.

[0075] 4. The method according to aspect 3, including selecting one or more components having high similarity for the penalizing step by one or both of the following:

[0076] Selecting one or more components whose similarity of the components is higher than a threshold similarity metric; and

[0077] Selecting one or more components having the highest similarity among all components according to a metric.

[0078] 5. The method according to aspect 3 or 4, wherein the blind source separation analysis includes principal component analysis or independent component analysis, and the components include principal components or independent components as the case may be.

[0079] 6. The method according to any one of aspects 3 to 5, wherein the blind signal separation analysis is applied to the setting data of the etch-induced parameters measured at the peripheral region of the at least one debug substrate.

[0080] 7. The method according to aspect 2, wherein the method includes obtaining the setting data of the etch-induced parameters from a reference measurement source, optionally a scanning electron microscope.

[0081] 8. The method according to any one of aspects 2 to 7, wherein the determining step further includes determining a weight affected by the penalty such that the difference between the setting data value of the parameter of interest and the first trigger adjustment value is minimized.

[0082] 9. The method according to any one of the preceding aspects, wherein the at least one debug substrate having a plurality of first trigger adjustment values for the parameter of interest and the at least one debug substrate having a plurality of second trigger adjustment values for the etch-induced parameters include different at least one debug substrates.

[0083] 10. The method according to any one of aspects 1 to 8, wherein the at least one debug substrate having a plurality of first trigger adjustment values for the parameter of interest and the at least one debug substrate having a plurality of second trigger adjustment values for the etch-induced parameters include the same at least one debug substrate; the first trigger adjustment value is triggered in the central region of the at least one debug substrate, and the second trigger adjustment value is triggered in the peripheral region of the at least one debug substrate.

[0084] 11. The method according to any one of the preceding aspects, wherein the parameter of interest includes an overlapping parameter of interest.

[0085] 12. The method according to any one of the preceding aspects, wherein the etch-induced parameter includes an etch-induced tilt.

[0086] 13. The method according to any one of the preceding aspects includes the following steps:

[0087] Generating at least one debug substrate having a plurality of first trigger adjustment values for the parameter of interest, the first trigger adjustment value being triggered via a lithographic exposure device; and

[0088] Generating at least one debug substrate having a plurality of second trigger adjustment values for the etch-induced parameters, the second trigger adjustment value being triggered via an etching device.

[0089] 14. The method according to any one of the preceding aspects, wherein the method uses the measurement selection scheme to measure the parameter of interest on a product substrate.

[0090] 15. The method according to aspect 14, wherein each of the debug substrate and the product substrate includes a functional circuit structure, and the measurement is performed on the functional circuit structure.

[0091] 16. A debug substrate configured to be used in the method according to aspects 1 to 12, wherein the etch initiation parameters have a plurality of second initiation adjustment values.

[0092] 17. The debug substrate according to aspect 16, wherein the etch initiation parameter includes an etch initiation tilt.

[0093] 18. The debug substrate according to aspect 16 or 17, wherein the second initiation adjustment values are initiated in a peripheral region of the debug substrate.

[0094] 19. The debug substrate according to aspects 16 to 18, wherein the parameter of interest has a plurality of first initiation adjustment values, and wherein the first initiation adjustment values are initiated in a central region of the debug substrate.

[0095] 20. A computer program comprising program instructions operable to perform the method according to any one of aspects 1 to 12 when run on a suitable device.

[0096] 21. A non - transitory computer program carrier containing the computer program according to aspect 20.

[0097] 22. A processing system comprising: a processor, and a storage device containing the computer program according to aspect 21.

[0098] 23. A metrology device comprising the processing system according to aspect 22, and the metrology device is further operable to perform the method according to aspects 14 and 15.

[0099] Although specific reference may be made herein to the use of a lithographic apparatus in IC manufacture, it should be understood that the lithographic apparatus described herein may have other applications. Possible other applications include the manufacture of integrated optical systems, the guidance and detection for magnetic domain memories, flat panel displays, liquid crystal displays (LCDs), thin film magnetic heads, and the like.

[0100] Although embodiments of the invention may be specifically referred to herein in the context of a lithographic apparatus, embodiments of the invention may be used in other apparatuses. Embodiments of the invention may form part of a mask inspection apparatus, a metrology apparatus, or any apparatus for measuring or processing an object such as a wafer (or other substrate) or a mask (or other patterning device). These apparatuses may generally be referred to as lithographic tools. Such lithographic tools may operate under vacuum conditions or ambient (non - vacuum) conditions.

[0101] Although the foregoing may have specifically referenced the use of embodiments of the present invention in the context of optical lithography, it should be understood that the present invention is not limited to optical lithography and can be used in other applications (such as imprint lithography) where the context permits.

[0102] Although specific embodiments of the present invention have been described above, it will be understood that the present invention can be practiced in other ways different from the described manner. The foregoing description is intended to be illustrative, not restrictive. Thus, those skilled in the art will appreciate that the described present invention can be modified without departing from the scope of the claims set forth below.

Claims

1. A method for determining a measurement selection scheme, the measurement selection scheme describing a measurement setting for measuring a parameter of interest from a substrate subject to parameter errors caused by etching, the parameter errors caused by etching affecting the measurement of the parameter of interest in a manner depending on the selection scheme; the method comprises: obtaining debug data of the parameter of interest related to the measurement of at least one debug substrate, the parameter of interest on the at least one debug substrate having a plurality of first induced adjustment values; obtaining debug data of the parameter caused by etching related to the measurement of at least one debug substrate, the parameter caused by etching on the at least one debug substrate having a plurality of second induced adjustment values; and determining the selection scheme to minimize the influence of the parameter caused by etching on the measurement of the parameter of interest.

2. The method according to claim 1, wherein, the step of determining the selection scheme includes penalizing the scheme for the selection scheme according to the similarity of the parameter error caused by etching to a known pattern.

3. The method according to claim 2, wherein, the method comprises: performing blind source separation analysis on the debug data of the parameter caused by etching to obtain components of the debug data of the parameter caused by etching; and penalizing the scheme for the selection scheme corresponding to the components having high similarity to the known pattern.

4. The method according to claim 3, including selecting one or more components having high similarity for the penalizing step by one or both of the following: selecting one or more components whose similarity of the components is higher than a threshold similarity metric; and selecting one or more components having the highest similarity among all components according to a metric.

5. The method according to any one of claims 1 to 4, wherein, the at least one debug substrate on which the parameter of interest has a plurality of first induced adjustment values and the at least one debug substrate on which the parameter caused by etching has a plurality of second induced adjustment values include the same at least one debug substrate; the first induced adjustment values are induced in a central region of the at least one debug substrate, and the second induced adjustment values are induced in a peripheral region of the at least one debug substrate.

6. The method according to any one of the preceding claims, comprising the steps of: producing at least one debug substrate on which the parameter of interest has a plurality of first induced adjustment values, the first induced adjustment values being induced via a lithography exposure device; and producing at least one debug substrate on which the parameter caused by etching has a plurality of second induced adjustment values, the second induced adjustment values being induced via an etching device.

7. The method according to any one of the preceding claims, the method using the measurement selection scheme to measure the parameter of interest on a product substrate.

8. The method according to claim 7, wherein, each of the debug substrate and the product substrate includes a functional circuit structure, and the measurement is performed on the functional circuit structure.

9. A non - transitory computer program carrier, comprising a computer program stored therein, the computer program including program instructions capable of operating to execute the method according to any one of claims 1 to 5 when run on a suitable device.

10. A processing system, comprising: a processor and a storage device, the storage device including a computer program stored therein, the computer program including program instructions capable of operating to execute the method according to any one of claims 1 to 5 when run on the processor.

11. A measuring device, comprising the processing system according to claim 10, and the measuring device is further capable of operating to execute the methods according to claims 7 and 8.

12. A debugging substrate for use in the method according to any one of claims 1 to 8, wherein on the debugging substrate, the parameters for etch initiation have a plurality of second initiation adjustment values.

13. The debugging substrate according to claim 12, wherein, the second initiation adjustment values are initiated in the peripheral region of the debugging substrate.

14. The debugging substrate according to claim 12 or 13, wherein on the debugging substrate, the parameters of interest have a plurality of first initiation adjustment values, and wherein, the first initiation adjustment values are initiated in the central region of the debugging substrate.

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