automated memory overclocking

Abstract

Automated memory overclocking, including: increasing a memory frequency setting of a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting that passes the memory stability test; and generating a configuration file including the overclocked memory frequency setting.

Description

Background Technology

[0001] Memory module settings can be configured based on vendor profiles or user-input specifications. These profiles are typically generated and tested using system configurations different from those of the user's system. Furthermore, the boundaries determined and tested using these different system configurations may limit the scope of the user-input specifications. Attached Figure Description

[0002] Figure 1 This is a block diagram of an example processor for automatic memory overclocking, based on some implementation schemes.

[0003] Figure 2 This is a flowchart of an example method for automatic memory overclocking based on some implementation schemes.

[0004] Figure 3 This is a flowchart of an example method for automatic memory overclocking based on some implementation schemes.

[0005] Figure 4 This is a flowchart of an example method for automatic memory overclocking based on some implementation schemes.

[0006] Figure 5 This is a flowchart of an example method for automatic memory overclocking based on some implementation schemes. Detailed Implementation

[0007] In some implementations, the method for automatic memory overclocking includes: increasing the memory frequency setting of the memory module until the memory stability test fails; determining the overclocked memory frequency setting, including the highest memory frequency setting that passed the memory stability test; and generating a configuration file that includes the overclocked memory frequency setting.

[0008] In some embodiments, increasing the memory frequency setting of the memory module until the memory stability test fails includes determining one or more memory timing settings, and the method further includes: determining one or more overclocked memory timing settings, including one or more memory timing settings corresponding to the overclocked memory frequency setting; and wherein generating a configuration file includes generating a configuration file including one or more overclocked memory timing settings. In some embodiments, the one or more memory timing settings include one or more of the following: column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) latency (write), row address strobe (RAS) to column address strobe (CAS) latency (read), row precharge time, and / or row activity time. In some embodiments, the method further includes: determining one or more sub-timing settings based on the overclocked memory frequency setting and / or one or more overclocked memory timing settings; and wherein generating a configuration file includes generating a configuration file including one or more sub-timing settings. In some embodiments, the one or more sub-timing settings are based on one or more rules applied to the overclocked memory frequency setting and / or one or more memory timing settings. In some embodiments, the method further includes storing the configuration file in a storage location. In some implementations, the method further includes: loading a configuration file from a storage location; and applying the configuration file to a memory module.

[0009] In some implementations, the apparatus for automatic memory overclocking performs the following steps: increasing the memory frequency setting of the memory module until a memory stability test fails; determining an overclocked memory frequency setting that includes the highest memory frequency setting that passed the memory stability test; and generating a configuration file that includes the overclocked memory frequency setting.

[0010] In some implementations, increasing the memory frequency setting of the memory module until the memory stability test fails includes determining one or more memory timing settings, and the step further includes: determining one or more overclocked memory timing settings, including one or more memory timing settings corresponding to the overclocked memory frequency setting; and wherein generating a configuration file includes generating a configuration file including one or more overclocked memory timing settings. In some implementations, the one or more memory timing settings include one or more of the following: column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) latency (write), row address strobe (RAS) to column address strobe (CAS) latency (read), row precharge time, and / or row activity time. In some implementations, the step further includes: determining one or more sub-timing settings based on the overclocked memory frequency setting and / or one or more overclocked memory timing settings; and wherein generating a configuration file includes generating a configuration file including one or more sub-timing settings. In some implementations, the one or more sub-timing settings are based on one or more rules applied to the overclocked memory frequency setting and / or one or more memory timing settings. In some implementations, the step further includes storing the configuration file in a storage location. In some implementations, the steps further include: loading a configuration file from a storage location; and applying the configuration file to the memory module.

[0011] In some embodiments, a computer program product disposed on a non-transitory computer-readable medium includes computer program instructions for automatic memory overclocking, which, when executed, cause a computer to perform steps including: increasing the memory frequency setting of a memory module until a memory stability test fails; determining an overclocked memory frequency setting including the highest memory frequency setting that passed the memory stability test; and generating a configuration file including the overclocked memory frequency setting.

[0012] In some implementations, increasing the memory frequency setting of the memory module until the memory stability test fails includes determining one or more memory timing settings, and the step further includes: determining one or more overclocked memory timing settings, including one or more memory timing settings corresponding to the overclocked memory frequency setting; and wherein generating a configuration file includes generating a configuration file including one or more overclocked memory timing settings. In some implementations, the one or more memory timing settings include one or more of the following: column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) latency (write), row address strobe (RAS) to column address strobe (CAS) latency (read), row precharge time, and / or row activity time. In some implementations, the step further includes: determining one or more sub-timing settings based on the overclocked memory frequency setting and / or one or more overclocked memory timing settings; and wherein generating a configuration file includes generating a configuration file including one or more sub-timing settings. In some implementations, the one or more sub-timing settings are based on one or more rules applied to the overclocked memory frequency setting and / or one or more memory timing settings. In some implementations, the step further includes storing the configuration file in a storage location. In some implementations, the steps further include: loading a configuration file from a storage location; and applying the configuration file to the memory module.

[0013] Automatic memory overclocking as described in this disclosure is typically implemented using a computer, that is, using an automated computing machine. Therefore, for further explanation, Figure 1 A block diagram is illustrated of an automated computing machine including an exemplary computer 100 configured for automatic memory overclocking. Figure 1 The computer 100 includes at least one computer processor 102 or 'CPU' and random access memory 104 ('RAM') connected to the processor 102 and other components of the computer 100 via a high-speed memory bus 106 and a bus adapter 108.

[0014] Storing in RAM 104 is the operating system 110. Operating systems useful in computers configured for automatic memory overclocking include UNIX. TM Linux TM Microsoft Windows TM And other operating systems that those skilled in the art would think of. Figure 1 In the example, the operating system 110 is shown in RAM 104, but many components of such software are also typically stored in non-volatile memory, such as data storage devices 112 on a disk drive. Also stored in RAM is a configuration module 114, which is a module for automatic memory overclocking.

[0015] Figure 1 Computer 100 includes a disk drive adapter 116 coupled to processor 102 and other components of computer 100 via an expansion bus 118 and a bus adapter 108. Disk drive adapter 116 connects a non-volatile data storage device to computer 100 in the form of a data storage device 112. Disk drive adapters useful in computers configured for automatic memory overclocking include Integrated Drive Electronics ('IDE') adapters, Small Computer System Interface ('SCSI') adapters, and other adapters that will be apparent to those skilled in the art. In some embodiments, as will be apparent to those skilled in the art, the non-volatile computer memory is implemented as an optical disc drive, electrically erasable programmable read-only memory (so-called 'EEPROM' or 'flash memory'), RAM drive, etc.

[0016] Figure 1 Example computer 100 includes one or more input / output ('I / O') adapters 120. The I / O adapters implement user-oriented input / output through, for example, software drivers and computer hardware, to control output to display devices such as computer displays, and user input from user input devices 122 such as keyboards and mice. Figure 1 Example computer 100 includes a video adapter 124, which is an example of an I / O adapter specifically designed to output graphics to a display device 126, such as a display screen or computer monitor. Video adapter 124 is connected to processor 102 via a high-speed video bus 128, a bus adapter 108, and a front-side bus 130, which is also a high-speed bus.

[0017] Figure 1 An exemplary computer 100 includes a communication adapter 132 for data communication with other computers and for data communication with a data communication network. Such data communication is performed serially via an RS-232 connection, via an external bus such as a Universal Serial Bus ('USB'), via a data communication network such as an IP data communication network, and / or via other means that will be conceived by those skilled in the art. The communication adapter implements the hardware level of data communication, through which one computer transmits data communication directly or via a data communication network to another computer. Examples of communication adapters useful in computers configured for automatic memory overclocking include modems for wired dial-up communication, Ethernet (IEEE 802.3) adapters for wired data communication, and 802.11 adapters for wireless data communication.

[0018] To further explain, Figure 2A flowchart illustrating an exemplary method for automatic memory overclocking is provided, the method comprising increasing the memory frequency setting of a memory module 202 (e.g., via configuration module 114) until a memory stability test fails. The memory module is a group of one or more random access memory chips within the same circuit board (e.g., the same dual in-line memory module (DIMM)). The memory frequency setting is the clock speed of the memory module (e.g., 1000 MHz, 3000 MHz, etc.).

[0019] For example, configuration module 114 starts from a baseline memory frequency setting (e.g., the current memory frequency setting of the memory module, a predefined minimum frequency setting, etc.) and increases the memory frequency setting at predefined time intervals (e.g., 100 MHz or other time intervals). After increasing the memory frequency setting, configuration module 114 performs one or more memory stability tests on the memory module. The memory stability tests are based on one or more data integrity checks, including error correction code checks or other methods that can be understood for detecting bit errors. For example, configuration module 114 may perform one or more data reads and / or writes on the memory module and determine whether errors are found in the data read and / or written.

[0020] If the memory module passes one or more memory stability tests, the configuration module 114 increases the memory frequency setting and performs one or more memory stability tests. This process is repeated until a memory stability test fails. In some embodiments, in response to a memory stability test failure, the configuration module 114 lowers the memory frequency setting to a value greater than the last memory frequency setting that passed the memory stability test but less than the memory frequency setting that failed the memory stability test. For example, suppose the memory module passes the 2800 MHz memory stability test. After increasing the memory frequency setting by a predefined interval of 200 MHz, the memory module fails the 3000 MHz memory stability test. The configuration module 114 then lowers the memory frequency setting to 2900 MHz and performs the memory stability test. Those skilled in the art will understand that such a method can be repeated to efficiently search for the highest memory frequency setting that will pass the memory stability test.

[0021] Figure 2 The method also includes determining, 204 (e.g., via configuration module 114), the highest memory frequency setting that has passed the memory stability test. For example, assuming configuration module 114 increments the memory frequency setting of the memory module in 100 MHz increments, a memory frequency setting of 2900 MHz passes the memory stability test, while a setting of 3000 MHz fails. The overclocked memory frequency setting will then be determined by 204 to be 2900 MHz.

[0022] Figure 2The method also includes generating 206 (e.g., via configuration module 114) a configuration file 208 that includes overclocking memory frequency settings. For example, configuration file 208 is generated 206 as data indicating one or more settings of the memory module, including overclocking memory frequency settings. Those skilled in the art will understand that... Figure 2 The method can be repeated for each memory module in the computing system, thereby generating a configuration file 208 for each memory module, or generating a configuration file 208 for indicative of settings for each memory module. Configuration module 114 is described as a software-based process (e.g., implemented in random access memory 104). Those skilled in the art will understand that, in alternative embodiments, configuration module 114 is at least partially implemented in a storage controller or other hardware component.

[0023] To further explain, Figure 3 A flowchart illustrating an exemplary method for automatic memory overclocking is provided, the method comprising: increasing 202 (e.g., via configuration module 114) the memory frequency setting of a memory module until a memory stability test fails; determining 204 an overclocked memory frequency setting including the highest memory frequency setting that passed the memory stability test; and generating 206 a configuration file 208 including the overclocked memory frequency setting.

[0024] Figure 3 Methods and Figure 2 The difference lies in the addition of memory frequency settings for memory modules 202 until memory stability testing fails, which also includes determining one or more memory timing settings 302. Memory timing settings include, for example, one or more of the following: Column Access Strobe (CAS) latency, Row Address Strobe (RAS) to Column Address Strobe (CAS) latency (write), Row Address Strobe (RAS) to Column Address Strobe (CAS) latency (read), Row Precharge Time, and / or Row Activity Time.

[0025] In one implementation, determining 302 one or more memory timing settings includes determining one or more memory timing settings as one or more minimum timing settings. For example, the memory module includes a default minimum threshold for one or more memory timing settings. The one or more memory timing settings are then determined as the minimum threshold. In one implementation, determining 302 one or more memory timing settings includes determining 302 one or more memory timing settings based on one or more other minimum timing settings. For example, a first memory timing setting is determined as the minimum timing setting, and a second memory timing setting is determined based on the first memory timing setting (e.g., using a formula or other rule). After determining 302 one or more minimum timing settings, the memory timing settings are applied to the memory module before executing the one or more memory timing settings.

[0026] In one implementation, after a memory stability test at a given frequency fails, configuration module 114 increases one or more memory timing settings until a threshold for the memory timing settings is reached, or until the memory stability test is passed. Therefore, the memory frequency setting passes the memory stability test using the increased memory timing settings.

[0027] Figure 3 The method also includes determining one or more overclocked memory timing settings, including one or more memory timing settings corresponding to the overclocked memory frequency setting. In other words, the one or more overclocked memory timing settings are the minimum memory timing settings applied to the memory modules when the overclocked memory frequency setting passes the memory stability test.

[0028] Figure 3 Methods and Figure 2 A further difference is that configuration file 208, which generates 206 including overclocked memory frequency settings, also includes configuration file 208, which generates 306 including one or more overclocked memory timing settings. Therefore, configuration file 208 generated in 206 indicates the overclocked memory frequency settings and one or more overclocked memory timing settings for the memory module.

[0029] To further explain, Figure 4 A flowchart illustrating an exemplary method for automatic memory overclocking is provided, the method comprising: increasing 202 (e.g., via configuration module 114) the memory frequency setting of a memory module until a memory stability test fails, including 302 determining one or more memory timing settings; determining 204 an overclocked memory frequency setting including the highest memory frequency setting that passed the memory stability test; determining 304 one or more overclocked memory timing settings, including one or more memory timing settings corresponding to the overclocked memory frequency setting; and generating 208 a configuration file 206 including the overclocked memory frequency setting by generating 306 a configuration file including one or more overclocked memory timing settings.

[0030] Figure 4 Methods and Figure 3 The difference is Figure 4The method also includes determining one or more sub-timing settings based on overclocked memory frequency settings and / or one or more overclocking timing settings. Examples of sub-timing settings include page timeline period settings; RAS-to-RAS latency, different bank group settings (e.g., latency between two active rows across different bank groups), RAS-to-RAS latency, same bank group settings (e.g., latency between two active rows within the same bank group); four-active window settings (e.g., the amount of time during which four active rows can occur in the same phase); write-to-read latency, different bank group settings (e.g., latency between a successful write command and a read command across different bank groups); write-to-read latency, same bank group settings (e.g., latency between a successful write command and a read command within the same bank group); write recovery time settings (e.g., latency between a successful write command and a precharged active bank), and other settings that may be understood.

[0031] In one implementation, one or more sub-timing settings are determined based on one or more overclocked memory timing settings. For example, the row cycle time setting is determined as the sum of the row precharge time setting and the row address strobe (RAS) activity time setting in the overclocked memory frequency settings. In one implementation, one or more sub-timing settings are determined based on one or more thresholds. For example, a setting below a threshold determined by a formula can instead be determined as a threshold amount. In one implementation, one or more sub-timing settings are determined based on one or more other sub-timing settings. For example, a four-activation window setting is determined as four times the RAS-to-RAS latency of different bank group settings. In other words, one or more sub-timing settings are determined based on one or more rules.

[0032] Figure 4 Methods and Figure 3 A further difference is that configuration file 208, which generates 206 including overclocked memory frequency settings, also includes configuration file 208, which generates 404 including one or more sub-timing settings. Therefore, configuration file 208, generated 206, indicates the overclocked memory frequency settings, one or more overclocked memory timing settings, and one or more sub-timing settings for the memory module.

[0033] To further explain, Figure 5 A flowchart illustrating an exemplary method for automatic memory overclocking is provided, the method comprising: increasing 202 (e.g., via configuration module 114) the memory frequency setting of a memory module until a memory stability test fails; determining 204 an overclocked memory frequency setting including the highest memory frequency setting that passed the memory stability test; and generating 206 a configuration file 208 including the overclocked memory frequency setting.

[0034] Figure 5 Methods and Figure 2 The difference is Figure 5 The method also includes storing the configuration file 502 in storage location 504. In one embodiment, storage location 504 includes non-volatile memory of a computing system including memory modules (e.g., disk storage devices, basic input / output system temporary tables, etc.). In another embodiment, storage location 504 includes non-volatile storage on the memory module itself, such as a serial presence detection (SPD) electrically erasable programmable read-only memory (EEPROM) on the module (e.g., on a dual in-line memory module (DIMM)).

[0035] Figure 5 The method also includes loading the 506 configuration file from storage location 504. For example, as part of the startup process of a computing system including memory modules, the 506 configuration file 208 is loaded from storage location 504. Figure 5 The method also includes applying configuration file 208 to the memory module. Applying configuration file 208 to the memory module includes configuring the memory module to operate using settings indicated in configuration file 208 (e.g., overclocking memory frequency settings, overclocking memory timing settings, and / or sub-timing settings).

[0036] In existing solutions, memory modules are configured using profiles provided by the memory module manufacturer or supplier. These profiles are tested with configuration settings that may differ from those of the end user (e.g., different chip or motherboard manufacturers or designers). Although users can modify the settings in these profiles, they are constrained by boundaries based on these different configuration settings. Using the method described above, the configuration settings of the memory module are determined and optimized based on the actual capabilities of the computing system implementing the memory module.

[0037] Based on the above explanation, readers will recognize that the benefits of automatic memory overclocking include:

[0038] • By optimizing memory overclocking settings to reflect the current user system configuration and operating environment, the performance of the computing system is improved.

[0039] Exemplary embodiments of this disclosure are described primarily in the context of a full-featured computer system for automatic memory overclocking. However, those skilled in the art will recognize that this disclosure can also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium can be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include disks in hard disk drives or floppy disks, optical discs for optical drives, magnetic tapes, and other media that will conceive of those skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means will be able to perform the steps of the methods of this disclosure as embodied in a computer program product. Those skilled in the art will also recognize that while some of the exemplary embodiments described in this specification are directed to software installed on and executed on computer hardware, alternative embodiments implemented as firmware or hardware are also fully within the scope of this disclosure.

[0040] This disclosure can be a system, method, and / or computer program product. A computer program product may include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform aspects of this disclosure.

[0041] A computer-readable storage medium can be a tangible means capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanical encoding devices (e.g., punched cards or raised structures in slots on which instructions are recorded), and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transient signal, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0042] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0043] Computer-readable program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. As a standalone software package, the computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be (e.g., via the Internet using an Internet service provider) to an external computer. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by personalizing the electronic circuitry with status information from the computer-readable program instructions in order to perform various aspects of this disclosure.

[0044] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0045] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, establish means for implementing the functions / actions specified in one or more boxes of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other means to function in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions that implement aspects of the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0046] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0047] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this respect, each block in a flowchart or block diagram may represent a module, segment, or portion comprising one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions mentioned in the blocks may occur in a different order than those shown in the drawings. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a system based on dedicated hardware that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0048] As will be understood from the foregoing description, modifications and changes can be made to various embodiments of this disclosure. The descriptions in this specification are for illustrative purposes only and should not be construed as limiting. The scope of this disclosure is limited only by the language of the appended claims.

Claims

1. An apparatus for automatic memory overclocking, the apparatus comprising a processor and a memory, the memory storing computer program instructions configured, when executed by the processor, to: Increase the memory frequency setting of the memory module until the memory stability test fails; Determine the overclocked memory frequency setting, including the highest memory frequency setting that passed the memory stability test; as well as Generate a configuration file that includes the overclocked memory frequency settings and one or more memory timing settings corresponding to the overclocked memory frequency settings.

2. The apparatus of claim 1, wherein increasing the memory frequency setting of the memory module until the memory stability test fails includes determining the one or more memory timing settings, and wherein the apparatus is further configured to: Determine one or more overclocked memory timing settings, including the one or more memory timing settings corresponding to the overclocked memory frequency settings; and Generating the configuration file includes generating the configuration file that includes the one or more overclocked memory timing settings, and wherein the configuration file is dedicated to the memory module.

3. The apparatus of claim 2, wherein the one or more memory timing settings include one or more of the following: column access strobe (CAS) latency, row address strobe (RAS) to column address strobe (CAS) latency (write), row address strobe (RAS) to column address strobe (CAS) latency (read), row precharge time and / or row activity time.

4. The apparatus of claim 2, further comprising computer program instructions configured, when executed by the processor, to: One or more sub-timing settings are determined based on the overclocked memory frequency settings and the one or more overclocked memory timing settings; and Generating the configuration file includes generating the configuration file that includes the one or more sub-timing settings.

5. The apparatus of claim 4, wherein the one or more sub-timing settings are based on one or more rules applied to the overclocked memory frequency settings and / or the one or more memory timing settings.

6. The apparatus of claim 1, further comprising computer program instructions configured, when executed by the processor, to store the configuration file in a storage location.

7. The apparatus of claim 6, further comprising computer program instructions configured, when executed by the processor, to: Load the configuration file from the storage location; and Apply the configuration file to the memory module.

8. A computer program product disposed on a non-transitory computer-readable medium, the computer program product comprising computer program instructions for automatic memory overclocking, the computer program instructions, when executed, causing a computer to perform steps including: Increase the memory frequency setting of the memory module until the memory stability test fails; Determine the overclocked memory frequency setting, including the highest memory frequency setting that passed the memory stability test; as well as Generate a configuration file that includes the overclocked memory frequency settings and one or more memory timing settings corresponding to the overclocked memory frequency settings.

9. The computer program product of claim 8, wherein increasing the memory frequency setting of the memory module until the memory stability test fails includes determining the one or more memory timing settings, and the step further includes: Determine one or more overclocked memory timing settings, including the one or more memory timing settings corresponding to the overclocked memory frequency settings; and Generating the configuration file includes generating the configuration file that includes the one or more overclocked memory timing settings, and wherein the configuration file is dedicated to the memory module.

10. The computer program product of claim 9, wherein the one or more memory timing settings include one or more of the following: column access strobe (CAS) delay, row address strobe (RAS) to column address strobe (CAS) delay (write), row address strobe (RAS) to column address strobe (CAS) delay (read), row precharge time and / or row activity time.

11. The computer program product according to claim 9, wherein the step further comprises: One or more sub-timing settings are determined based on the overclocked memory frequency settings and the one or more overclocked memory timing settings; and Generating the configuration file includes generating the configuration file that includes the one or more sub-timing settings.

12. The computer program product of claim 11, wherein the one or more sub-timing settings are based on one or more rules applied to the overclocked memory frequency settings and / or the one or more memory timing settings.

13. The computer program product of claim 8, wherein the step further includes storing the configuration file in a storage location.

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