Semiconductor circuit control method and power converter applying the same

Abstract

The carrier concentration of the drift region (87) is controlled in the semiconductor substrate in response to a voltage applied to the gate electrode (81) of the gate-controlled diode (203). In the reverse recovery state, a voltage signal of zero bias or positive bias that causes an electron layer at the interface of the gate electrode (81) is applied between the gate electrode (81) and the anode electrode (86). In the forward recovery state, a voltage signal of negative bias that causes a hole layer at the interface of the gate electrode (81) is applied between the gate electrode (81) and the anode electrode (86). After the forward recovery state, the voltage signal of zero bias or positive bias is switched from the negative bias. The gate-controlled diode (203) variably controls the period during which the voltage signal of zero bias or positive bias is applied in accordance with the non-conduction period of the IGBT connected in series therewith.

Description

Technical Field

[0001] This invention relates to a semiconductor circuit control method and a power conversion device using the same, and particularly to a semiconductor circuit control method applicable to a wide range of machines from low-power machines such as air conditioners and microwave ovens to high-power machines such as inverters in motor vehicles, railways and steel plants, as well as a power conversion device using the same. Background Technology

[0002] Global warming has become a critical and urgent global issue, and the potential contribution of power electronics technology as a countermeasure is increasingly anticipated. In particular, to increase the efficiency of inverters responsible for power conversion, it is necessary to reduce the power consumption of the IGBTs (Insulated Gate Bipolar Transistors) that constitute them for power switching and the diodes that perform rectification.

[0003] As a key technology for reducing reverse recovery losses in diodes, the gate-controlled diode described in Patent Document 1 is known. It comprises a structure with a gate electrode disposed on the surface of the anode region, capable of controlling the concentration of carriers injected into the drift region, and a control technique thereof.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent document 1: Japanese Patent Application Publication No. 2018-117044. Summary of the Invention

[0007] The problem the invention aims to solve

[0008] However, in the diodes of the dual-bridge arm, the diodes become current-carrying during various non-conducting commands for the IGBT. Therefore, considering the operation during various conduction periods and switching modes, just like the IGBT, a technique is required that minimizes conduction losses, reverse recovery losses, and forward recovery losses. Therefore, using the diode technique shown in Patent Document 1, it is difficult to reduce the forward recovery losses in the inverter's PWM (Pulse Width Modulation) operation.

[0009] The present invention addresses the aforementioned problems by providing a semiconductor circuit control method that, compared to existing gate-controlled diode control methods, achieves low power consumption and miniaturization by reducing conduction losses and forward recovery losses generated in the diode under various pulse conditions during the PWM operation of the inverter.

[0010] Technical means for solving problems

[0011] The present invention, which solves the above-mentioned problems, is a semiconductor circuit control method for controlling a semiconductor circuit. This semiconductor circuit is composed of a double-bridge arm formed by connecting bridge arms in series. The bridge arm is constructed by connecting a gate-controlled diode to an IGBT. In the semiconductor circuit being controlled, the conduction directions of the IGBT's collector and emitter are opposite to the conduction directions of the gate-controlled diode's anode and cathode, connected in parallel within the bridge arm. The double-bridge arm connects the gate-controlled diode and the IGBT in series from one bridge arm to the other. The gate-controlled diode has an anode electrode, a cathode electrode, and a gate electrode disposed in an insulated manner on a semiconductor substrate. In this semiconductor circuit control method, in response to the voltage applied to the gate electrode, the carrier concentration in the drift region within the semiconductor substrate is controlled. In the forward recovery state, a negative bias voltage signal is applied between the gate electrode and the anode electrode to generate a hole layer at the interface of the gate electrode. In the reverse recovery state, a zero bias or positive bias voltage signal is applied between the gate electrode and the anode electrode to generate an electron layer at the interface of the gate electrode. After the forward recovery state, the application of the zero bias or positive bias voltage signal is switched from negative bias to zero bias or positive bias. The pulse width of the other bridge arm is determined in a manner corresponding to the pulse width of one bridge arm in the dual-bridge arm. The period of zero bias or positive bias is variably controlled according to the non-conducting period of the series-connected IGBTs.

[0012] The effects of the invention

[0013] According to the present invention, a semiconductor circuit control method can be provided that, under various pulse conditions in the PWM operation of an inverter, achieves low power consumption and miniaturization by reducing the conduction losses and forward recovery losses generated in the diodes. Other problems, structures, and effects beyond those described above will be explained through the following description of embodiments. Attached Figure Description

[0014] Figure 1A This is a timing diagram illustrating a control method (hereinafter also referred to as "semiconductor circuit control method" or "control method" or simply "method") for a gate-controlled diode according to an embodiment of the present invention, showing the non-conduction period t. off The longer case is a.

[0015] Figure 1B Is with Figure 1A In comparison, t represents the non-conduction period. off The timing diagram for the shorter case c.

[0016] Figure 2 This is a circuit diagram of a PWM inverter using the method shown in Figure 1.

[0017] Figure 3A Is with Figure 1A The same content indicates the non-conduction period t.off The timeline diagram for the longer case a.

[0018] Figure 3B It is used with Figure 3A The comparison represents the non-conduction period t. off The timing diagram for the shorter case c.

[0019] Figure 4 It means Figure 1A and Figure 3A Implementation methods and Figure 3B Timing diagrams of the current waveform, voltage waveform, and time integral waveform of the current-voltage product for each method in the comparative examples.

[0020] Figure 5A This is an explanation Figure 2 The timing diagram of the inverter's operation.

[0021] Figure 5B yes Figure 2 Losses and carrier extraction time t in gate-controlled diodes d_rr The relevant graph shows the non-conduction period t. off In a larger case.

[0022] Figure 5C Is with Figure 5B The comparison represents the non-conduction period t. off Related diagrams for smaller cases.

[0023] Figure 6A This is to explain Figure 2 The optimal t with minimum loss among gate-controlled diodes d_rr The timing diagram.

[0024] Figure 6B yes Figure 2 The optimal t in gate-controlled diodes d_rr During the non-conducting period t of the IGBT in the dual bridge arms (upper and lower bridge arms) off Related images.

[0025] Figure 7A It means to use Figure 1A and Figure 1B The diagram illustrates the cross-sectional view of the gate-controlled diode during operation and the schematic diagram of the charge carriers when it is turned on.

[0026] Figure 7B It means to use Figure 1A and Figure 1B The diagram illustrates the cross-sectional view of the gate-controlled diode during operation and the schematic diagram of the charge carriers when it is turned on.

[0027] Figure 8A It is Figure 1A and Figure 1BThis diagram illustrates the corresponding gate bias when the forward recovery voltage is low during the current switching of a gate-controlled diode.

[0028] Figure 8B Is with Figure 8A The corresponding diagrams for gate bias under the condition of larger positive recovery voltage are compared above.

[0029] Figure 9A This is a timing diagram illustrating the method of an embodiment of the present invention, showing the non-conduction period t. off In longer cases.

[0030] Figure 9B Is with Figure 9A In comparison, t represents the non-conduction period. off Timing diagram for the shorter case.

[0031] Figure 10 This indicates that it will be realized. Figure 9A and Figure 9B The circuit diagram of an inverter formed by connecting the gate control circuit and the bridge arm in the control method.

[0032] Figure 11A It means Figure 10 The timing diagram of the sequence of signals in the gate control circuit represents the case where the turn-on command period is relatively long.

[0033] Figure 11B and Figure 11A In comparison, this indicates a shorter period of the conduction command.

[0034] Figure 12 It is an application Figure 9A and Figure 9B The circuit diagram of the inverter with the control method.

[0035] Figure 13 It means Figure 12 Timing diagrams of the gate waveforms and main circuit waveforms of the IGBTs, gate-controlled diodes, and main circuit of the dual-bridge arms (upper and lower bridge arms) of the inverter during regenerative operation.

[0036] Figure 14 It means Figure 12 The diagram shows the gate waveforms and main circuit waveforms of the IGBTs and gate-controlled diodes in the dual-bridge arms (upper and lower bridge arms) of the inverter during power operation.

[0037] Figure 15 This is a circuit diagram showing an inverter formed by connecting a gate control circuit and a bridge arm to implement the method of the present invention.

[0038] Figure 16 It means Figure 15The timing diagram of the sequence of signals in the gate control circuit, especially when the command pulse width is long.

[0039] Figure 17 It means Figure 15 The timing diagram of the sequence of signals in the gate control circuit, especially when the command pulse width is short.

[0040] Figure 18 This is a circuit diagram of a three-phase AC inverter using the method of an embodiment of the present invention.

[0041] Figure 19 Is as with Figure 18 A contrasting example is the circuit diagram of a three-phase AC inverter using dual-gate IGBTs.

[0042] Figure 20 This is a circuit diagram of a three-phase inverter with a double-bridge arm structure.

[0043] Figure 21 This is a diagram of an evaluation circuit used to evaluate the recovery characteristics of a diode in a power conversion device designed to generate AC output from DC power.

[0044] Figure 22 It means to use Figure 21 The timing diagram of the recovery characteristics obtained from the evaluation circuit. Detailed Implementation

[0045] The following description, with reference to the accompanying drawings, outlines embodiments 1 to 4 of the present invention and their basic techniques. Figures 1A to 8B Example 1 is described below. Figures 9A to 14 Example 2 is described below, using Figures 15-17 Example 3 is described below. Figure 18 Example 4 is described below. Figure 19 A variation of Example 4 will be described. Additionally, using... Figures 20-22 The basic technology of the present invention and comparative examples are explained.

[0046] Furthermore, in the circuit diagrams of each figure, the gate terminal is simply represented by a single line as the conductive line for transmitting the gate signal. In reality, there is also a reference conductive line used to reference the emitter potential, and a voltage relative to this reference potential is input. Additionally, the reference conductive line that conducts to the emitter of the dual-gate IGBT is omitted from the circuit diagrams of each figure.

[0047] Example 1

[0048] The control method (semiconductor circuit control method) for the gate-controlled diode in Embodiment 1 of the present invention is as follows: Figure 1A and Figure 1BAs specified in timing diagrams 200 and 200'. That is, ... Figure 1A and Figure 1B The method shown in timing diagrams 200 and 200' is the method of Example 1. Figure 1A Indicates the non-conduction period t off 19 is a longer case. Below, Figure 1A The horizontal axis of the isochronous sequence diagram represents the common time T.

[0049] Figure 1B and Figure 1A In comparison, t represents the non-conduction period. off 19. The shorter case is c. Figure 1A and Figure 1B Timing diagram 200 shows gate-controlled diode 93 ( Figure 2 ), 203 Figure 7A , Figure 7B The gate control signal waveforms 1 and 2, and the cathode / anode voltage V are shown. KA 3. Current waveform I K 4.

[0050] Figure 2 This is the circuit diagram of the PWM inverter 130 applying the method shown in Figure 1. Figure 2 As shown, the PWM inverter 130 (hereinafter also referred to as "inverter 130") has two IGBTs 91 connected in series and gate-controlled diodes 93 connected in reverse parallel to its DC power supply 169, forming a double bridge arm 92, 94 composed of bridge arm 92 and bridge arm 94.

[0051] An inductive load 95 is connected to the neutral point 90 of each of the IGBTs 91 connected in series in the dual bridge arms 92 and 94. The two IGBTs 91 configured in the dual bridge arms 92 and 94 (hereinafter also referred to as "dual-bridge IGBTs") are controlled by PWM command signals 63 and 64 having a sequence that enables them to conduct complementaryly, thus performing switching operations. As a result, DC power 169 is converted into AC power in the inductive load 95. Furthermore, the term "dual-bridge IGBT" as viewed from this bridge arm refers to an IGBT belonging to the other bridge arm when viewed from the perspective of one of the two bridge arms.

[0052] The method in Example 1 is, in other words, a control method for applying a bias voltage to the gate of a gate-controlled diode that has the function of controlling the carrier concentration in the drift region. An inverter applying this method is illustrated as an example. Figure 2 The single-phase PWM inverter 130 is shown. The inverter 130 consists of IGBT 91 respectively configured in the dual bridge arms 92 and 94, and diodes 93 connected in reverse parallel with them respectively.

[0053] Reverse parallel connection refers to, in Figure 2 In the bridge arms 92 and 94 shown, the conduction directions of the collector and emitter of the IGBT 91 and the conduction directions of the anode 86 and cathode 89 of the gate-controlled diode (hereinafter also referred to as "diode") 93 are aligned. Figure 7A , Figure 7B , Figure 8A , Figure 8B This is a circuit configuration where the electrodes are connected in parallel in opposite directions. Additionally, "anode" and "cathode" are referred to as "anode electrode" and "cathode electrode" respectively, depending on the described situation.

[0054] Furthermore, the gate terminals of the IGBT 91 respectively configured in the dual bridge arms 92 and 94 are collectively referred to as gate terminal 67. Additionally, if it is necessary to distinguish which bridge arm is being used, the gate terminal 67A of the IGBT 91 configured in the upper bridge arm 92 and the gate terminal 67B of the IGBT 91 configured in the lower bridge arm 94 are distinguished by the corresponding symbols.

[0055] In inverter 130, due to the circuit breaker command of IGBT 91 configured in one bridge arm 92, current is diverted to diode 93 configured in the same bridge arm 92, so diode 93 becomes conductive. Conversely, due to the circuit breaker command of IGBT 91, IGBT 91 becomes conductive, and diode 93 configured in the same bridge arm becomes deconductive.

[0056] Figure 1A and Figure 1B In the middle, when the gate control signal 1 of each IGBT 91 (dual-bridge IGBT) of the dual bridge arms 92 and 94 is turned off, the current is transferred to diode 93, V KA 3 decreases, I K 4. Rise. Generally, the inductive load of the inverter functions by continuously flowing a certain current, so the same load current flows through diode 93 as the current flowing through IGBT 91. Therefore, in diode 93, the carriers that allow the load current 15 to flow through it are in the drift region 87 ( Figure 7A and Figure 7B The current flows through the middle, thus transiently generating a relatively high negative polarity positive recovery voltage V. KA twenty one.

[0057] This state is called the positive recovery state 23. A positive recovery period t is required until a stable conduction state is reached. fr 36. Then, during this positive recovery period t fr 36 due to transitional V KA Changes and I KThe positive recovery loss is generated by the product of the changes. In the gate-controlled diode 93, by biasing the gate control signal 2 to a negative voltage 12 below the threshold voltage in the positive recovery state 23, the injected carrier concentration can be increased, which can suppress V KA The rise.

[0058] Therefore, performance with reduced positive recovery losses can be achieved. Next, diode 93 becomes in the conducting state 28, but lower conduction losses can be obtained by maintaining the negative bias 12. Then, when the gate control signal 1 of IGBT 91 in the same bridge arm 92 is turned on 18, the current I of diode 93... K 4. Attenuation, current is transferred to IGBT91 in the same bridge arm 92. Then, V KA 3 rises to the power supply voltage 13 of inverter 130 and reaches the non-conducting state 27.

[0059] Here, in diode 93, the residual charge carriers that participated in conductivity modulation during conduction return to the anode 86, resulting in a reverse current, i.e., the reverse recovery current 22, which continues until the non-conducting state 27 is reached. This requires a reverse recovery period t. rr 37. This state is called the reverse recovery state 24, due to the transitional V. KA Changes and I K The product of the changes generates reverse recovery loss.

[0060] In the gate-controlled diode 93, for the gate control signal 2, during the carrier extraction period t before the reverse recovery state 24... d_rr In step 20, control is performed by applying either a zero bias or a positive bias 11. This control reduces the injected carrier concentration from the anode and allows electron carriers involved in conductivity modulation to be discharged towards the anode. As a result, the carrier concentration in the drift region can be temporarily reduced, and the reverse recovery current 22 can be reduced in the reverse recovery state 24. Therefore, lower reverse recovery losses can be achieved.

[0061] On the other hand, since the inverter 130 generates AC waveforms through PWM operation, the operation of the IGBT 91 and diode 93 during various on and off widths needs to be considered. In particular, diode 93 in inverter 130 conducts during the period when the IGBT 91 in the same bridge arm is off. Therefore, the moments when the IGBT 91 in the same bridge arm is turned off and on generate forward recovery, on, and reverse recovery states in diode 93. Therefore, the gate bias applied to the gate-controlled diode 93 at these moments is important for achieving loss reduction in inverter 130.

[0062] As mentioned above, Figure 1A and Figure 1BThe diagram shows the non-conducting period t of the IGBT91 in the same bridge arm. off In cases a (longer) and c (shorter), the gate control signal 2 of the gate-controlled diode 93 enables a simultaneous reduction in the forward recovery loss, conduction loss, and reverse recovery loss of the diode 93. In the forward recovery state 23, the gate bias is set to a negative bias 12 below the threshold voltage.

[0063] Furthermore, in reverse recovery state 24, for gate bias, the carrier concentration of the gate-controlled diode 93 can be optimized by applying a sequence of zero bias or positive bias 11. Additionally, considering the PWM operation of the inverter 130, for the carrier extraction period t... d_rr 20, during the circuit breaker command period of IGBT91 in the same bridge arm t off 19 Accordingly, to satisfy [t] off ≥t d_rr +t fr The diode 93 is controlled in a variable manner in a way that reduces its losses in the PWM inverter 130.

[0064] The gate terminal 67 of the IGBT91, the gate terminal 68 of the gate-controlled diode, and the emitter sensing terminal (hereinafter also referred to as the "emitter electrode") 69 for reference potential are connected to a gate control circuit board (hereinafter also referred to as the "gate control circuit") 66. In this gate control circuit 66, command signals 63 and 64 are received, and a gate control signal capable of realizing PWM operation of the IGBT91 and low-loss of the diode is generated. The gate control signal of the gate-controlled diode 93 is configured to adjust the voltage based on the off-circuit period of the dual-bridge IGBT. d_rr The signal is used for variable control. As a result, the power loss generated in diode 93 can be minimized during the PWM operation of inverter 130.

[0065] In the non-conducting state, this gate-controlled diode 93 achieves a forward recovery state by applying a circuit-breaking command voltage between the gate electrode 67 and the emitter electrode 69 of the IGBT 91, causing the current flowing through the IGBT 91 to be diverted. Conversely, in the conducting state, the gate-controlled diode 93 achieves a reverse recovery state by applying a circuit-breaking command voltage between the gate electrode 67 and the emitter electrode 69 of the IGBT 91, causing the current flowing through the IGBT 91 to be diverted.

[0066] Figure 3A Is with Figure 1A The same content indicates the non-conduction period t. off Timing diagram for the longer case a. This is a timing diagram illustrating the method of a comparative example of the present invention. Figure 3B It is used with Figure 3AThe comparison represents the non-conduction period t. off The timing diagram for the shorter case c. That is, Figure 3B As a comparative example to the method of Example 1, a method for controlling the gate of a diode is shown. d_rr The control waveform and the obtained V when it becomes a fixed value KA 3. I K Waveform 4. Additionally, in the following description, symbols added to the timing diagrams, etc., are repeated, but sometimes self-evident symbols are omitted from the inverter and its components.

[0067] Figure 3A and Figure 3B The diagram shows the gate control signal 1 of the dual-bridge IGBT, the gate control signal 2 of the gate-controlled diode, and the cathode / anode voltage (V) of the gate-controlled diode. KA Waveform 3, Current (I) of the gate-controlled diode K Waveform 4, V of gate-controlled diode KA ·I K The time integral of the product is the energy E produced. fr 5. On-circuit voltage; 9. Off-circuit voltage; 10. Zero bias or positive bias; 11. Negative bias less than threshold voltage; 12. High voltage (supply voltage); 13. 0V potential; 14. High current (load current); 15. and 0A potential; 16.

[0068] Under the condition a longer open-circuit period of the dual-arm IGBT, a fixed value t can be used to reduce the forward recovery loss, conduction loss, and reverse recovery loss. d_rr The gate control signal 2 is applied to the case where the open-circuit period of the dual-bridge arm IGBT is short, i.e., it does not satisfy [t]. off ≥t d_rr +t fr Under the condition of […], it will lead to an increase in forward recovery loss. This is because when the gate bias of the gate-controlled diode is zero bias or positive bias, current transfer occurs from the dual-arm IGBT to the diode, resulting in poor carrier injection efficiency and a transitionally large negative polarity V. KA 25.

[0069] In the PWM operation of the inverter, due to the various modulations during the non-conducting period of the IGBT with diode dual-bridge arm configuration, the gate bias of the gate-controlled diode is negatively biased to be less than the threshold voltage at the time of its turn-off. If a state with high carrier injection efficiency is not formed, the positive recovery loss will increase.

[0070] Furthermore, in order to reduce reverse recovery losses during reverse recovery, the gate of the gate-controlled diode needs to be zero-biased or forward-biased when the dual-bridge arm IGBT is turned on, which reduces carrier injection efficiency.

[0071] Therefore, the period t for zero bias or positive bias of the gate can be variably controlled based on the non-conducting period of the dual-bridge arm IGBT. d_rr This is necessary in the PWM operation of the inverter to reduce both the forward and reverse recovery losses generated in the diodes.

[0072] Regarding the effects achieved by the method in Example 1, refer to... Figures 4 to 6B Please provide an explanation. Figure 4 It means Figure 1A and Figure 3A Example 1, and Figure 3B Timing diagrams of the current waveform, voltage waveform, and time integral waveform of the current-voltage product for each method in the comparative examples. Figure 4 The control 6 of Example 1, which uses solid lines, and the control 7 of the comparative example, which uses dashed lines, are clearly shown.

[0073] Right now, Figure 4 This shows the I during the forward recovery of the gate-controlled diode. K Waveform 4, V KA Waveform 3 and the generated energy E calculated by time integration of the current-voltage product. fr 5. The comparative example here refers to the t in the gate control signal of a gate-controlled diode. d_rr The period is set to a fixed width, and the circuit breaking period of the dual-arm IGBT is longer than t. d_rr Even shorter cases.

[0074] The Ig of the gate-controlled diodes increases transiently due to the current transfer of the dual-bridge IGBT. K Waveform 4, due to the effect of the inverter's inductive load, and Figure 1A and Figure 3A The control 6 and shown in Embodiment 1 Figure 3B There was no difference in control 7 of the comparative examples shown; no change was observed. On the other hand, regarding V... KA Waveform 3 shows that, compared to control 7 in the comparative example, control 6 in Example 1 can suppress the voltage rise caused by the forward recovery of the diode.

[0075] This effect is achieved by controlling 6 in Example 1, based on the off-circuit period of the dual-bridge arm IGBT, to adjust t. d_rrVariable control can be achieved even when the circuit breaker period is short. That is, this is the effect of improving carrier injection efficiency during the positive recovery 23 of Embodiment 1, because a negative bias below the threshold voltage is applied to the gate of the gate-controlled diode.

[0076] In this way, by suppressing the transient forward recovery voltage, the current-voltage product applied to the gate-controlled diode is reduced. As a result, the energy E generated during forward recovery is reduced. fr From the perspective of 5, compared to the control 7 of the comparative example, the control 6 of the embodiment 1 can achieve smaller and more efficient inverter operation.

[0077] Figure 5A This is an explanation Figure 2 The timing diagram of the operation of inverter 130. Figure 5B yes Figure 2 Loss and carrier extraction time t in gate-controlled diode 93 d_rr The relevant graph shows the non-conduction period t. off In a larger case. Figure 5C Is with Figure 5B Comparison, representing the non-conduction period t off Related diagrams for smaller cases. Figure 5B and Figure 5C In the diagram, the horizontal axis represents the optimal carrier removal time t. d_rr During the non-conduction period t off The associated time axis, with the vertical axis representing diode loss E.

[0078] Figures 5A to 5C This represents the generation sequence of forward recovery loss, conduction loss, and reverse recovery loss in the diodes during inverter operation, and the relationship between losses and the control of gate-controlled diodes. d_rr The correlation. By inputting a circuit breaker command to the gate control signal 1 of the dual-bridge arm IGBT, the IGBT is turned off 17, and the gate-controlled diode reaches the conduction state 28 after the forward recovery state 23.

[0079] Next, by inputting a turn-on command to the gate control signal 1 of the dual-bridge IGBT, the IGBT is turned on 18, and the gate-controlled diode reaches the non-conducting state 27 after passing through the reverse recovery state 24. In this sequence, the current I flowing through the diode is controlled... K 4. Voltage between cathode / anode V KA The product of 3 is integrated over time to calculate the energy produced, 5.

[0080] Here, to make the effect of the method in Embodiment 1 clear, the generated energy 5 is divided into the loss E generated under the conduction state 28 after the positive recovery state. condThe losses E generated under states 29 and 24 are as follows: rrsw Considering point 30. Furthermore, in the gate-controlled diode 92, during the period t during which zero bias or positive bias is applied to the gate to reduce carrier concentration before reverse recovery. d_rr In 20, the increase in losses caused by a temporary rise in forward voltage is also considered and included in E. cond 29.

[0081] like Figure 5B As shown, during the open circuit period t of the dual-bridge arm IGBT off Under relatively long conditions, t d_rr When 20 is used as a control parameter, by increasing t d_rr 20. Improved carrier extraction efficiency before reverse recovery, E rrsw 30 decreases. On the other hand, because t before reverse recovery... d_rr During this period, the conduction loss in 20 increases, E cond 29 rose.

[0082] Therefore, there exists a total loss E generated in the diode. cond 29+E rrsw 30 minimum optimal t d_rr Regarding this point, in t off For a relatively long period, value b is fixed according to the diode's structure, and at this fixed value b, losses can be minimized. Here, the diode's structure refers to the thickness of the drift region and the carrier lifetime.

[0083] On the other hand, such as Figure 5C As shown, at t off For shorter conditions, especially those shorter than a fixed value b, increase t. d_rr 20°C conduction loss E cond The increase in positive recovery loss ΔE in 29 fr It accounts for the majority, with total losses E cond 29+E rrsw A rise of 30. That is, without producing ΔE. fr Under the condition of 8 rising, the diode loss E drops to the minimum relative to the positive recovery period t. fr 36, by t d_rr Control is to have [t off -t fr During the period of variable value of ], the diode loss E can be minimized.

[0084] Figure 6A This is to explain Figure 2 The optimal t with minimum loss among the gate-controlled diodes 93 d_rr The timing diagram. Figure 6B yes Figure 2 The optimal t in the gate-controlled diode 93 d_rr During the non-conducting period t of the dual-arm IGBT off Related images. Figure 6B In the diagram, both the vertical and horizontal axes are time axes.

[0085] use Figure 6A and Figure 6B For the diode current 4 and V KA 3. Define the positive recovery period t fr 36, and the optimal t for minimizing diode losses using the method of Example 1. d_rr Please provide an explanation. Figure 6A and Figure 6B During forward recovery, the current transfer begins, and after the diode current 4 starts to rise, V... KA The voltage applied to inject charge carriers inverts to its maximum value, V, by filling the charge carriers. KA Stabilized at a forward voltage of 32, current I K The load current of the dual-bridge arm IGBT is stabilized at 15.

[0086] The change in forward recovery loss ΔE that can be controlled by the gate bias of a gate-controlled diode. fr It is at the beginning of the current conversion, the negative polarity V KA The change before and after reaching its maximum value is considered, so the period from the start of current switching to the point where the current stabilizes is defined as the positive recovery period t. fr 36, There exists another t to consider fr 36 Optimal control condition t d_rr .

[0087] The circuit breaker period t of the dual-bridge arm IGBT off That is, the conduction period of a gate-controlled diode is a fixed value b+t determined by the diode's structure. fr In the case of a long time, by measuring t d_rr Setting a fixed value 'b' minimizes diode losses. On the other hand, at t... off Less than a fixed value b+t fr In this case, in order to avoid an increase in positive recovery loss, by adjusting t d_rr Set variable value [t] off -t fr This can minimize the losses of the diode.

[0088] As described above, according to the method of Embodiment 1, in a gate-controlled diode, t is adjusted based on the non-conducting period of the dual-bridge arm IGBT, i.e., the conducting period of the diode. d_rrVariable control during the period can minimize diode losses during the inverter's PWM operation.

[0089] According to the method of Embodiment 1, even if the turn-off time of the dual-bridge IGBT varies due to the PWM operation of the inverter, the carrier injection efficiency can always be improved in the forward recovery state caused by the current transfer to the gate-controlled diode. As a result, the transient rise in anode / cathode voltage can be suppressed, thereby reducing the forward recovery loss of the diode.

[0090] Moreover, the carrier concentration can be temporarily reduced by controlling the gate bias just before reaching the reverse recovery state, thus achieving both low conduction loss and low reverse recovery loss.

[0091] Next, regarding the reasons for achieving the effect of Example 1, refer to... Figure 7A Figure 8 provides an explanation. Figure 7A It means to use Figure 1A and Figure 1B The diagram illustrates the cross-sectional view of the gate-controlled diode 203 during operation and the schematic diagram of the charge carriers when it is turned on.

[0092] Figure 7B yes Figure 7A The cross-sectional view of the gate-controlled diode 203 is a schematic diagram of the carriers when a negative voltage 71 less than the threshold voltage is applied to the gate, and when the gate is zero-biased or positive-biased 70, and when current is flowing.

[0093] Figure 7A and Figure 7B The gate-controlled diode 203 shown includes an N-type cathode drift layer 87, a P-type anode layer 84 longitudinally adjacent to the N-type cathode drift layer 87, and an N+ type cathode layer 88 longitudinally adjacent to the N-type cathode drift layer 87 on the opposite side of the P-type anode layer 84. Furthermore, within the scope of what is self-evident to those skilled in the art, even for the same location, expressions such as "layer," "region," or "electrode" are changed or omitted accordingly to the described situation.

[0094] Furthermore, above the P-type anode layer 84, there is an adjacent N-type potential well layer 85, and above that, there is a P-type anode layer 77. Then, the P-type anode layer 84, the N-type potential well layer 85, and the P-type anode layer 77 are in contact with the trench gate insulating gate (also simply referred to as the "gate") 83 having the gate electrode 81, separated by a gate insulating film (gate oxide film) 82.

[0095] That is, the anode region is composed of a P-type anode layer 84, an N-type potential well layer 85, and a P-type anode layer 77 sequentially from the bottom to the top. The anode electrode 86 has a downwardly protruding trench shape. The P-type anode layer 77 is in contact with the N-type potential well layer 85 and electrically separated from the P-type anode layer 84 through the N-type potential well layer 85.

[0096] The anode electrode 86 is electrically connected to the P-type anode layer 77 via a Schottky or ohmic contact (barrier) 78, and the cathode electrode 89 is electrically connected to the N+ type cathode layer 88 via an ohmic contact. Furthermore, the semiconductor layer used here is formed of silicon (Si) or silicon carbide (SiC), and the gate insulating film 82 is formed of silicon dioxide (SiO2).

[0097] That is, the anode electrode 86 has a convex shape from the upper layer to the lower layer, and is formed such that the position in contact with the P-type anode layer 77 is further up the layer than the position in contact with the N-type potential well layer 85. Furthermore, both the N-type potential well layer 85 and the P-type anode layer 77 are electrically connected to the anode electrode 86 and are formed electrically separately from the semiconductor substrate. However, it is also possible to have a low concentration of the N-type potential well layer 85, allowing the anode electrode 86 to partially or completely contact the P-type anode layer 84.

[0098] Figure 7A and Figure 7B In the structure of the gate-controlled diode 203 shown (hereinafter also referred to as the "structure of diode 203"), a hole layer 73 is generated on the interface of the gate oxide film 82 by applying a negative bias 71 below the threshold voltage to the gate electrode 81 to generate an electron layer in the P-type anode layer 84 and the N-type potential well layer 85.

[0099] In this state, when a positive current flows from the external power supply 72 between the anode electrode 86 and the cathode electrode 89, hole carriers 74 are injected at a high concentration into the N-type cathode drift layer 87 from the anode electrode 86 via the hole layer 73, and conductivity modulation occurs due to the electron carriers 75 injected from the cathode electrode 89, resulting in a lower positive voltage performance.

[0100] On the other hand, in the structure of diode 203, an electron layer 76 is generated on the interface of gate oxide film 82 by applying a zero bias or positive bias 70 to the gate electrode 81 to generate an electron layer in the P-type anode layer 84 and the N-type potential well layer 85.

[0101] In this state, when a positive current flows from the external power source 72 between the anode electrode 86 and the cathode electrode 89, the electron carriers of the N-type cathode drift layer 87 are discharged to the anode electrode 86 through the electron layer 76 generated on the interface of the gate oxide film 82, and the carrier concentration of the N-type cathode drift layer 87 decreases.

[0102] Hole carriers injected from the anode electrode 86 are injected at a low concentration into the N-type cathode drift layer 87 in the region directly below the anode electrode 86 and away from the gate oxide film 82. At this time, a high voltage exceeding the injected potential barrier is applied. As a result, the forward voltage applied to the anode electrode 86 and the cathode electrode 89 increases.

[0103] Based on the state change of diode 203 caused by gate bias, refer to Figure 8A and Figure 8B The forward recovery state of the gate-controlled diode during inverter operation is explained. Figure 8A It is Figure 1A and Figure 1B This diagram illustrates the gate bias when the forward recovery voltage (transition voltage) is low during the current switching (arrow) of the gate-controlled diode.

[0104] Figure 8B Is with Figure 8A The diagrams comparing the gate bias under the condition of a larger positive recovery voltage are shown above. Figure 8A and Figure 8B As shown, when a negative bias 71 less than the threshold voltage is applied to the gate electrode 81, the injection efficiency of hole carriers from the anode electrode 86 is high when current flows through the diode. Consequently, the positive recovery voltage applied transiently to induce conductivity modulation in the N-type cathode drift layer 87 is small.

[0105] On the other hand, when the gate electrode 81 is subjected to zero bias or positive bias 70, the injection efficiency of hole carriers from the anode electrode 86 is low when current flows through the diode, and the positive recovery voltage applied transiently to induce conductivity modulation in the N-type cathode drift layer increases.

[0106] Therefore, to reduce forward recovery losses, a control sequence requiring a negative bias 71 with a voltage less than the threshold voltage applied to the gate when switching to the gate-controlled diode is needed. In addition, to balance reducing both conduction and reverse recovery losses in the inverter's PWM operation, t... d_rr The method of Implementation Example 1, which performs variable control, is effective.

[0107] As explained above, the semiconductor circuit control method according to Embodiment 1 of the present invention can minimize the forward recovery loss, conduction loss and reverse recovery loss of the gate-controlled diode during the PWM operation of the inverter.

[0108] Example 2

[0109] For the control method (semiconductor circuit control method) of the gate-controlled diode in Embodiment 2 of the present invention, refer to... Figures 9A to 14 Please provide an explanation. Figure 9A This is a timing diagram 300 illustrating the method of Embodiment 2, representing the non-conduction period t. off In longer cases. Figure 9B Is with Figure 9A In comparison, t represents the non-conduction period. off 19. Timing diagram 300' for the shorter case.

[0110] Figure 9A and Figure 9B The diagram shows the gate control signal waveform 1 of the IGBT with a dual-bridge arm configuration, the gate control signal waveform 33 of the IGBT with this bridge arm configuration, and the gate control signal waveform 2 of the gate-controlled diode with this bridge arm configuration.

[0111] In a PWM inverter, the function is to convert DC power to AC power by complementaryly turning on the two IGBTs configured in the dual-bridge arm. Therefore, gate control signals for turning on are complementaryly applied to the gates of the IGBTs in the dual-bridge arm. Furthermore, to prevent abnormal operation or short circuits caused by simultaneous conduction of both bridge arms, a dead time DT34 is set in the gate control signal.

[0112] In Example 2, the timing of the gate control signal that minimizes the loss of the gate-controlled diode and the gate control circuit 66 that implements it are described using the gate control signal of the local IGBT that is synchronized with the gate control signal of the dual-bridge IGBT. Figure 9A The non-conducting period t of the dual-arm IGBT off The longer case refers to the gate control signal when the conduction period of the diode in this bridge arm is longer. Figure 9B It is the gate control signal in the case of a shorter duration.

[0113] Here, during the period t off The longer case refers to the situation in gate-controlled diodes where, compared to applying zero bias or forward bias to the gate to extract carriers, thus stabilizing the carrier concentration in the drift region and minimizing reverse recovery loss, t... d_rr Period b and positive recovery period t fr The sum, during the period t off Longer-term scenarios.

[0114] First, during the period t off 19 will be explained under longer conditions. Under these conditions, at the moment 35 when the IGBT of this bridge arm is input with a turn-on command, a negative bias 12 less than the threshold voltage is applied to the gate of the gate control diode of this bridge arm. Then, during the diode's conduction period 28, a zero bias or a positive bias 11 is applied to the gate to begin discharging carriers.

[0115] Then, the carrier extraction period td_rr A fixed period 'b' is set, during which a disconnect command is input to the gate of the IGBT in this bridge arm. Then, via DT34, a turn-on command is input to the gate of the dual-bridge arm IGBT, bringing both IGBTs to on (18). That is, the gate-controlled diode reaches the reverse recovery state. Then, after the reverse recovery period 't'... rr 37. After reaching the non-conducting state, a negative bias 12 less than the threshold voltage is applied to the gate again to prepare for the next positive recovery state. This sequence is used.

[0116] Conversely, with period t off 19 during the period b+t fr The explanation is based on the condition of a short time. Under this condition, starting from the state where a negative bias 12 less than the threshold voltage is applied to the gate of the gate-controlled diode, at the moment 35 when the IGBT of this bridge arm is input with the turn-on command, a zero bias or a positive bias 11 is applied to the gate of the gate-controlled diode.

[0117] Then, to make the carrier extraction period t d_rr Control is maintained as the sum of the on-time f of the IGBT in this bridge arm and the dead time f + DT. Therefore, control is performed according to the on-time f of the IGBT in this bridge arm, which is also the off-time t of both bridge arm IGBTs. off 19. A synchronous variable value controls the carrier extraction period t. d_rr Then, a disconnect command is sent to the gate of the IGBT in this bridge arm. Subsequently, after the DT34 sends a turn-on command to the gate of the dual-bridge arm IGBT, the dual-bridge arm IGBTs are turned on (18). That is, the gate-controlled diodes reach the reverse recovery state.

[0118] Then, the gate-controlled diode undergoes reverse recovery period t rr 37. After reaching the non-conducting state 27, a negative bias 12 less than the threshold voltage is applied to the gate again to prepare for the next positive recovery state. If the above control is applied, even if the conduction period of the diode varies due to the inverter's PWM operation, the forward recovery loss, conduction loss, and reverse recovery loss can be minimized by applying a negative bias less than the threshold voltage to the gate during forward recovery and applying a zero bias or positive bias to the gate during reverse recovery.

[0119] Then, according to Embodiment 2, by utilizing the complementary input turn-on command relationship between the gate control signal of the dual-bridge arm IGBT and the gate control signal of the IGBT of this bridge arm, the gate control signal of the IGBT of this bridge arm can be used to generate the gate control signal of the gate-controlled diode.

[0120] In addition, in the above control, the variable time t d_rrThe value f+DT is during the reverse recovery period of the diode. fr In the case where the dead time DT is shorter than that of the dual-bridge arm, at t fr In cases where DT is longer than DT, the time when zero or positive bias is applied to the gate control diode is delayed by a certain time x from the time of the IGBT turn-on command of this bridge arm, i.e., t d_rr Setting it to f+DT–x will achieve the same effect.

[0121] Figure 10 It will be realized Figure 9A and Figure 9B The circuit diagram of the inverter 140, which is formed by connecting the gate control circuit 66 and the bridge arm 96, is shown. Figure 10 As shown, in inverter 140, gate control circuit 66 is a circuit that receives the PWM operation command signal 62 of the inverter and generates gate control signals for IGBT 91 and gate-controlled diode 93. Here, the gate control signal is a voltage signal input to the gate terminal 67 of IGBT and the gate terminal 68 of gate-controlled diode, with the emitter sensing terminal (emitter electrode) 69 of IGBT 91 and gate-controlled diode 93 as the reference potential.

[0122] The gate control circuit 66 receives the PWM operation command signal 62 and uses the trigger signal generation module 58 to generate an IGBT operation trigger signal A and a fixed pulse signal B for the gate-controlled diode. Here, the generation module 58 is preset to have the same on / off period as the command signal 62, and the fixed pulse signal B is turned on a certain time before the input IGBT turn-off command.

[0123] Furthermore, the signal C obtained by delaying A by a certain time through delay module 55 and signal B are passed through logic product module 56, thereby generating the trigger signal D of the gate-controlled diode. Thus, it is possible to generate a signal t that can be variably controlled according to the IGBT's turn-on command period. d_rr The IGBT's activation trigger signal A and the gate-controlled diode's activation trigger signal D are converted into adjusted voltage signals by the output buffer 57, controlling the gate terminals 67 and 68 of the IGBT 91 and the gate-controlled diode 93.

[0124] Figure 11A It means Figure 10 The timing diagram 301 of the sequence of signals in the gate control circuit 66 shows the case where the turn-on command period is relatively long. Figure 11B Is with Figure 11A In comparison, timing diagram 302 shows the case where the turn-on command period is shorter. Figure 11A and Figure 11BThe diagram illustrates the sequence of signals A through B when a command signal with a longer pulse g during the IGBT's turn-on command period is input, and when a command signal with a shorter pulse f is input. Here, the longer pulse refers to the pulse t that can control the gate-controlled diode at a fixed value. d_rr In this case, a shorter pulse refers to the pulse controlled by a variable value t. d_rr The situation.

[0125] In addition, Figure 11A and Figure 11B In the diagram, the on-state level 59 and off-state level 60 are shown on the vertical axis, and the time T is shown on the horizontal axis. When a command signal of a longer pulse g is input, the rise of the fixed pulse signal B generated by the generation module 58 within the gate control circuit 66 serves as a trigger. The trigger signal D of the gate-controlled diode rises, and the dual-bridge IGBT is turned on according to the signal A in the gate control circuit configured for the dual-bridge arms. Before the gate-controlled diode reverses and recovers, the period for setting a fixed value b is taken as the carrier extraction period t. d_rr .

[0126] On the other hand, when a short pulse f is input as a command signal, the rise of signal C, obtained by delaying signal A by a certain time, serves as the trigger. The trigger signal D of the gate-controlled diode rises, and the dual-bridge IGBT is turned on according to signal A in the gate control circuit configured in the dual-bridge configuration. The carrier extraction period t before the gate-controlled diode reverses and recovers is... d_rr It becomes a variable value corresponding to the turn-on command period of signal A.

[0127] Then, in either the longer turn-on command period g or the shorter turn-on command period f, during the period when the dual-bridge IGBT is turned off and the gate-controlled diode is recovering forward, the trigger signal D of the gate of the gate-controlled diode can standby at the off-circuit level, so a negative bias less than the threshold voltage can be applied to the gate of the gate-controlled diode.

[0128] Furthermore, during the period when the dual-bridge arm IGBT is turned on and the gate-controlled diode is in reverse recovery, the gate trigger signal D of the gate-controlled diode can standby at the on-level, so it can make t d_rr Under variable conditions, a zero-bias or positive-bias condition can be applied to the gate of a gate-controlled diode. Additionally, Figure 11A and Figure 11B Q in the text represents from Figure 10 The signal A of the gate control circuit for the dual bridge arms (omitted in the text) is referenced. Figure 10 ).

[0129] In addition, for the falling moment of a fixed pulse signal B or a variable pulse signal C based on signal A, the reverse recovery time t of the gate-controlled diode should be considered. rr37. By setting this time, a negative bias of less than the threshold voltage can be applied to the gate again after the gate-controlled diode has reverse recovered, thus preparing for the next forward recovery state. Therefore, it is possible to provide, through embodiments, a gate control sequence that minimizes the forward recovery loss, conduction loss, and reverse recovery loss of the gate-controlled diode for any instruction signal with an arbitrary conduction command width.

[0130] use Figures 12-14 The circuit diagram and operating waveforms of the inverter using the control method of Example 1 are shown. Figure 12 It is an application Figure 9A and Figure 9B Circuit diagram of inverter 150 with control method. Figure 12 In the circuit of the inverter 150 shown, a gate control circuit 66 capable of deriving the above-mentioned action sequence, an IGBT 91 connected thereto, and a gate control type diode 93 are arranged in the dual bridge arms 92 and 94. An inductive load 95 is provided at the neutral point 90, so that the dual bridge arms are connected to the DC power supply 169.

[0131] and then, Figure 12 The inverter circuit shown inputs signals 63 and 64 to the gate control circuit 66 of the dual-arm bridge, instructing the inverter to perform complementary operations for PWM operation and outputting AC power. Internally, the gate control circuit 66, receiving signals 63 and 64, generates trigger signals for the IGBT 91 and the gate-controlled diode 93. These trigger signals are connected to the gate terminal 67 of the IGBT 91 and the gate terminal 68 of the gate-controlled diode 93, respectively.

[0132] Figure 13 It means Figure 12 Timing diagram 303 shows the gate waveforms of the IGBTs and gate-controlled diodes of the dual-bridge arms and the main circuit waveforms during the regenerative operation of the inverter. Figure 13 The diagram shows the state of current flowing from the inductive load 95 to the neutral point 90 of the dual-arm IGBT, i.e., the gate waveforms 97, 98, 101, 102 and the main circuit waveforms 99, 100, 103, 104 of the dual-arm IGBT during the regenerative operation of drawing current from the load to the inverter.

[0133] in addition, Figure 13 The diagram shows the gate control signal 97 of the upper bridge arm IGBT, the gate control signal 98 of the upper bridge arm gate-controlled diode, and the cathode / anode voltage V of the upper bridge arm gate-controlled diode. KA 99. Cathode current I of the upper bridge arm gate-controlled diode K100. Gate control signal of the lower bridge arm IGBT; 101. Gate control signal of the lower bridge arm gate-controlled diode; 102. Collector / emitter voltage V of the lower bridge arm IGBT. CE 103. The collector current I of the lower bridge arm IGBT C 104.

[0134] Here, the main circuit waveform refers to the voltage V applied between the collector / emitter terminals or the cathode / emitter terminals of the IGBT or the diode connected in reverse parallel. CE or V KA and the current I flowing through the IGBT C Or the current I flowing through the diode K The waveform. Additionally... Figure 13 The diagram illustrates the state transition from the on-time 105 of the lower IGBT, through the on-time 106 of the upper IGBT diode, and back to the on-time 105 of the lower IGBT. First, starting from the on-time state of the lower IGBT, a turn-off command 17 is input to the gate of the lower IGBT, causing current to flow to the gate-controlled diode of the upper IGBT, resulting in a positive recovery state.

[0135] Here, a negative bias 12, less than the threshold voltage, is applied to the gate 98 of the gate-controlled diode of the upper bridge arm using the gate control circuit of the upper bridge arm, resulting in low forward recovery loss. Then, during the conduction period 106 of the upper bridge arm diode, an on-command command 18 is input to the gate of the IGBT of the lower bridge arm, thereby transferring current to the IGBT of the lower bridge arm, and the gate-controlled diode of the upper bridge arm enters the reverse recovery state. Here, during the conduction period 106 of the upper bridge arm diode, a variable-value-controlled t is input. d_rr During the period, the zero bias or positive bias 11 results in low reverse recovery loss.

[0136] Next, use Figure 14 The diagram shows the state of current flowing from the neutral point 90 of the dual-arm IGBT to the inductive load 95, i.e., the gate waveforms 97, 98, 101, 102 and the main circuit waveforms 115, 116, 117, 118 of the dual-arm IGBT during the power operation of the inverter supplying current to the load. Figure 14 It means Figure 12 Timing diagram 304 shows the gate waveforms of the IGBTs and gate-controlled diodes of the dual-bridge arms, as well as the main circuit waveforms, during the power operation of the inverter. Additionally, Figure 14 The image shows the collector / emitter voltage V of the upper bridge arm IGBT. CE 115. Collector current I of the upper arm IGBT C 116. Cathode / anode voltage V of the lower bridge arm gate-controlled diode KA117. The cathode current I of the lower bridge arm gate-controlled diode. K 118.

[0137] This section illustrates the state transition from the conduction period 119 of the lower bridge arm diode, through the conduction period 120 of the upper bridge arm IGBT, and back to the conduction period 119 of the lower bridge arm diode. First, starting from the conduction state 119 of the lower bridge arm diode, a turn-on command 18 is input to the gate of the upper bridge arm IGBT, current flows to the upper bridge arm IGBT, and the lower bridge arm diode enters a reverse recovery state. Here, during the conduction period 119 of the lower bridge arm diode, a variable-value-controlled t is input. d_rr During the period, the zero bias or positive bias 11 results in low reverse recovery loss.

[0138] Next, during the conduction period 120 of the upper IGBT, a turn-off command 17 is input to the gate of the upper IGBT, thereby diverting current to the diode of the lower IGBT, which then enters a forward recovery state. Here, a negative bias 12, less than the threshold voltage, is applied to the gate of the gate-controlled diode of the lower IGBT using the gate control circuit of the lower IGBT, resulting in low forward recovery losses.

[0139] That is, by configuring a gate control circuit that applies the control method of the embodiment in the dual bridge arms, the power loss generated by the diodes in the forward recovery state, conduction state and reverse recovery state of the dual bridge arms can be minimized during the power operation and regeneration operation of the inverter, thereby achieving miniaturization and high efficiency of the inverter.

[0140] In addition, Figure 9A , Figure 9B , Figure 11A , Figure 11B , Figure 13 and Figure 14 The method shown in timing diagrams 300-304 is the method of Embodiment 2. As explained above, in the PWM operation of the inverter using the method of Embodiment 2 of the present invention, the gate-controlled diode (semiconductor circuit) 93 can minimize the losses consisting of forward recovery loss, conduction loss, and reverse recovery loss.

[0141] Example 3

[0142] For the control method of the gate-controlled diode in Embodiment 3 of the present invention, refer to... Figures 15-17 Please provide an explanation. Figure 15 This is a circuit diagram showing an inverter 160 formed by connecting the gate control circuit 66, which implements the method of Embodiment 3, with the bridge arm 96. (See diagram below.) Figure 15As shown, inverter 160 represents gate control circuit 66, IGBT 91 connected thereto, and gate-controlled diode 93. Gate control circuit 66 is a circuit that receives PWM operation command signal 62 from the inverter and generates gate control signals for IGBT 91 and gate-controlled diode 63.

[0143] Here, regarding the gate control signal, the gate control circuit 66, which is related to the voltage signal input to the gate terminal 67 of the IGBT and the gate terminal 68 of the gate control diode, with the emitter sensing terminal 69 of the IGBT 91 and the gate control diode as the reference potential, receives the PWM operation command signal 62, and uses the trigger signal generation module 58 to generate the IGBT operation trigger signal E and the fixed pulse signal F for the gate control diode.

[0144] Here, the trigger signal generation module 58 consists of a delay circuit 53 that delays the on / off moment by a certain period while maintaining the same on command period as the command signal 62, and a circuit 54 that generates a fixed pulse of a certain period triggered by the off command of the command signal 62. Then, the signals G and F, which further delay the IGBT operation trigger signal E by a certain period, are passed through the logic product module 56, thereby generating the trigger signal H of the gate-controlled diode.

[0145] Therefore, it is possible to generate variable control t during the IGBT turn-on command. d_rr The IGBT's activation trigger signal E and the gate-controlled diode's activation trigger signal H are converted into adjusted voltage signals by the output buffer 57, controlling the gate terminals 67 and 68 of the IGBT 91 and the gate-controlled diode 93. Additionally, if... Figure 15 Bridge arm 96 serves as the upper bridge arm, and there exists a paired (not shown) double bridge arm structure. The command signal 62' and action trigger signal E of the double bridge arm IGBT 91 are as follows: Figure 16 and Figure 17 As shown below.

[0146] Figure 16 It means Figure 15 The timing diagram 400 shows the sequence of signals in the gate control circuit, especially when the command pulse width is long. Figure 16 The diagram illustrates the sequence of signals E to H when a relatively long pulse g is input during the IGBT's turn-on command period, and the command signals and their sequence E for the dual-bridge arms with a set dead time DT34 and complementary input of the turn-on command. Here, a relatively long pulse refers to a pulse that can control t by a fixed value. d_rr In this case, when the input command signal 62 is received, a signal E with the same pulse width g and a certain delay a is generated.

[0147] The certain period 'a' here is a fixed t that is effective in reducing the reverse recovery loss of gate-controlled diodes. d_rr The value b – DT is obtained by subtracting the dead time DT34, the turn-on command interval of the dual bridge arms, from b. Then, signal F rises triggered by the fall of command signal 62, and conducts for a certain period.

[0148] The specific period here refers to the period between b and the reverse recovery period t. rr 37 and b+t rr Furthermore, signal G is generated by delaying the forward and reverse recovery times of the gate-controlled diode based on signal E. Signal H is generated by the logical product of signal F and signal G. In this case, signal H rises triggered by the rise of a fixed pulse signal F. A fixed value b is set as the carrier extraction period t before the dual-arm IGBT is turned on by the dual-arm signal E and before the gate-controlled diode reverse recovers. d_rr .

[0149] then, Figure 17 It means Figure 15 In the gate control circuit 66, a timing diagram 401 shows the sequence of signals, particularly when the command pulse width is short. That is, Figure 17 This indicates the case where a command signal 62 with a short conduction time pulse f is input to the gate control circuit 66. Additionally, [the following text is incomplete and likely refers to a different context:] ... Figure 16 and Figure 17 The method shown in timing diagrams 400 and 401 is the method of Example 3.

[0150] When the pulse is shorter than b–DT, compared to the signal F with a fixed width that turns on when the command signal 62 falls, it becomes a sequence of signals G that turn on with a variable width corresponding to the turn-on command width of the command signal 62, delayed by a certain period from the command signal 62. Therefore, the signal H rises triggered by the rise of the signal G. Before the dual-bridge IGBT is turned on by the dual-bridge signal E and the gate-controlled diode reverse recovers, the period of setting the variable value f+DT is taken as the carrier extraction period t. d_rr .

[0151] Thus, the generation module 58 in the gate control circuit 66 of Embodiment 3 consists of a delay circuit 53 that maintains the same turn-on command period as the command signal 62 and delays the turn-on / turn-off timing by a certain period, and a circuit 54 that generates a fixed pulse of a certain period triggered by the turn-off command of the command signal 62. Such a gate control circuit 66 can generate pulses for various command widths with different turn-on widths. d_rr A signal that enables variable control and always minimizes the loss of diode 93.

[0152] As explained above, in the PWM operation of the inverter 501 using the method of Embodiment 3, the losses of the diode 93, which consists of forward recovery losses, conduction losses, and reverse recovery losses, can be minimized.

[0153] Example 4

[0154] For a three-phase AC inverter of a power converter that uses the gate-controlled diode control method of Embodiment 4 of the present invention, refer to Figure 18 and Figure 19 Please provide an explanation. Figure 18 This is a circuit diagram of a three-phase AC inverter 500 using the method of Embodiment 4, showing a total of 6 sets of control circuits 66 configured in a three-phase double-bridge configuration, and the circuits of IGBT 91 and gate-controlled diodes 93 connected thereto.

[0155] Motors 950, which serve as inductive loads, are configured at neutral points 121, 122, and 123 of the dual-bridge arms, connecting the dual-bridge arms to a DC power supply 169. For the gate control circuit 66 of the dual-bridge arms, a signal is input from the instruction unit 951 to indicate the complementary operation of each phase for the inverter 501 to perform PWM operation and output AC power, and for the motor to perform rotational operation.

[0156] Upon receiving the command signal, the gate control circuit 66 configured in each phase and each bridge arm generates trigger signals for the IGBT and the gate-controlled diode, respectively, and connects them to the gate terminals of the IGBT 91 and the gate-controlled diode 93. The gate-controlled diode operates according to the signal generated by the gate control circuit 66, as shown in Embodiment 4, thereby minimizing power losses generated in the forward recovery state, the on state, and the reverse recovery state.

[0157] Figure 19 Is with Figure 18 The corresponding modified examples utilize the control method of gate-controlled diodes and the circuit diagram of a three-phase AC inverter 501 with dual-gate IGBTs. For example... Figure 19 As shown, the dual-gate IGBT 901 has two insulated gate terminals. By controlling it with two signals that are set during a timing delay period that can control the carrier concentration during conduction and switching, the switching loss and conduction loss of the IGBT can be reduced.

[0158] In the gate control circuit 902, in addition to the common emitter sensing, three gate signals are generated in each phase and each bridge arm according to the command signal. These signals consist of the gate of the gate-controlled diode 93 and the two gates of the dual-gate IGBT 901. Therefore, in addition to reducing the losses of the gate-controlled diode 93, the losses of the IGBT 901 are also reduced. As a result, the efficiency of the three-phase AC inverter 501 is improved and its size is reduced.

[0159] As explained above, the method according to Embodiment 3 can minimize the losses of the diode 93, which consists of forward recovery loss, conduction loss, and reverse recovery loss, thereby achieving a high-efficiency inverter (power converter) 501.

[0160] [Basic Techniques]

[0161] Here, for the basic technology of the present invention, refer to Figure 20 Please provide an explanation. Figure 20 This is a circuit diagram of a three-phase inverter 600 having a double-bridge arm structure, which is the basic technology of this invention. (See diagram below.) Figure 20 As shown, in the three-phase inverter 600, for the IGBT 170 with an insulated gate terminal (referred to as "gate") 171, a diode 172 is connected in reverse parallel with the IGBT 170.

[0162] The inverter 600 is a structure that supplies power from the voltage source 169, applies voltage to the gate 171 of the IGBT 170, and repeatedly turns it on and off at high speed, thereby controlling the power supplied to the connected inductive load 168. The inductive load 168 is, for example, a motor.

[0163] IGBT170 and diode 172 generate conduction losses when turned on and switching losses when switched on, and their temperature rises due to the thermal resistance of the components and their surroundings. Therefore, the current density that can flow through IGBTs and diodes is limited by their maximum allowable temperature, thus requiring parallel connections to form a specified volume in order to meet the required inverter rated current.

[0164] To achieve miniaturization and increased efficiency in inverters, reducing thermal resistance and minimizing losses in the IGBT and diodes are effective methods. Losses can be broadly categorized into conduction losses generated when the IGBT and diode are turned on separately, and switching losses generated in the IGBT and diode during IGBT switching.

[0165] Furthermore, the switching losses can be divided into four parts: the turn-on loss generated when the IGBT is turned on, the reverse recovery loss in the diodes of the dual-bridge arm, the turn-off loss generated when the IGBT is turned off, and the forward recovery loss in the diodes of the dual-bridge arm.

[0166] By reducing these losses, the temperature rise of components can be suppressed, thus enabling an increase in allowable current density. This means that the inverter can be miniaturized and made more efficient by reducing the number of parallel connections and the area of ​​components.

[0167] [Comparative Example]

[0168] Here, for the gate-controlled diode that serves as a comparative example of the present invention, reference is made to... Figure 21 and Figure 22 A detailed explanation follows. This gate-controlled diode is a technique for reducing the reverse recovery loss of a diode. It consists of a structure in which a gate electrode is disposed on the surface of the anode region, which can control the concentration of injected carriers in the drift region, and the control technology thereof.

[0169] Figure 21 This is a diagram of an evaluation circuit 700 designed to evaluate the recovery characteristics of diodes in the operation of a power conversion device that generates AC output from DC power. (See diagram for example.) Figure 21 As shown, the evaluation circuit 700 is configured by connecting a gate-controlled diode 45 and a dual-bridge IGBT 44 in series with respect to the DC power supply 47, and by connecting an inductive load 48 in parallel with respect to the diode 45. In this evaluation circuit 700, an AC output voltage is generated across the inductive load 48 in response to the input signal 42 at the gate of the IGBT 44.

[0170] Figure 22 It means to use Figure 21 The timing diagram of the recovery characteristics obtained from the evaluation circuit 700 is shown. This represents... Figure 21 The timing diagram of the recovery characteristics obtained by the evaluation circuit 700 is shown. As the recovery characteristics, the following is illustrated: Figure 21 The gate control signal 43, the corresponding current waveform 107 with switching characteristics, and the cathode / anode voltage waveform 108 with the same characteristics.

[0171] During the conduction period 109, the gate-controlled diode 45 increases the injected carrier concentration in the drift region and decreases the forward voltage by applying a negative bias 112 to the gate, which is less than the threshold voltage, thereby reducing conduction losses. Then, as the IGBTs of the dual bridge arms turn on, the current 107 of diode 45 decays. Subsequently, a reverse recovery current 49 is transiently generated in the opposite direction due to the return of residual carriers, during the reverse recovery period 110 when the cathode / anode voltage 108 rises.

[0172] This is like Figure 22 As shown by the dashed line, the existing pn diode has a relatively large reverse recovery current 50, which can be reduced to the reverse recovery current 49 shown by the solid line. Afterwards, during the non-conducting period 09, the cathode / anode voltage 51 reaches the supply voltage and stabilizes. Here, as... Figure 22 As shown by the dashed line, the existing pn diode has a relatively large cathode / anode voltage 52, which can be reduced to the cathode / anode voltage 51 shown by the solid line.

[0173] Figure 21 In the evaluation circuit 700, before the reverse recovery period 1, a positive bias 113 above the threshold voltage is applied to the gate to reduce the injected carrier concentration from the anode. Furthermore, carriers in the drift region are discharged to the anode via an electron reversal layer generated at the oxide film interface, thus temporarily reducing the carrier concentration in the drift region. Consequently, the reverse recovery current during the reverse recovery period 110 decreases, and the rise rate of the cathode / anode voltage 51 increases, reducing reverse recovery losses.

[0174] Right now, Figure 21 In the gate-controlled diode 45 of the evaluation circuit 700, its structure and gate control method can reduce both conduction loss and reverse recovery loss. On the other hand, since this diode 45 also generates losses in the forward recovery state, it is also important to reduce these losses. The forward recovery state is the state in which current is transferred to the diode when the IGBT of the dual bridge arm is turned off, but this transfer results in a transient anode / cathode voltage rise caused by the filling of carriers in the drift region of the diode 45.

[0175] The product of the current and voltage rise caused by this commutation results in forward recovery loss. Furthermore, during the period when a forward bias control above a threshold voltage is applied to the gate (previously introduced to reduce reverse recovery loss) is implemented, if this overlaps with the IGBT turn-off state of the dual-bridge arm diodes and the forward recovery state, it can lead to an increase in forward recovery loss as a side effect.

[0176] This is because by applying a positive bias above the threshold voltage to the gate, the concentration of injected carriers from the anode decreases, thus increasing the cathode / anode voltage required to fill the required amount of carriers for the current transfer.

[0177] An inverter is a device that converts DC to AC by pulse width modulation (PWM) of the dual bridge arms, which serves as the turn-on command for the IGBTs. To maintain the quality of the AC waveform, various pulse width controls need to be considered. That is, because... Figure 21 The gate-controlled diode 45 of the evaluation circuit 700 also generates losses in the forward recovery state, so reducing these losses is the subject of this invention.

[0178] The semiconductor circuit control method of Embodiments 1 to 4 of the present invention, and the power converter using it, can be summarized as follows.

[0179] [1] The semiconductor circuit controlled by this method is a semiconductor circuit consisting of two bridge arms, formed by connecting bridge arms 92 and 94, which are connected in series with gate control diodes 93 and 203 for IGBTs 91 and 901. More specifically, it is... Figure 2 (Example 1) Figure 12 The single-phase PWM inverters 130 and 150 shown in (Example 2) are also applicable to other applications. Figure 18 (Example 4) Figure 19 The three-phase inverters 500 and 501 shown in the (modified example of Example 4) are as follows.

[0180] In the bridge arms 92 and 94 of this semiconductor circuit, the collectors and emitters of BT91 and 901 are connected in reverse parallel with the anodes 86 and cathodes 89 of the gate-controlled diodes 93 and 203, forming a circuit. In the dual-bridge arm, the gate-controlled diodes 93 and 203 and IGBTs 91 and 901 are connected in series from one bridge arm 92 (94) to the other bridge arm 94 (92) to form a circuit.

[0181] Gate-controlled diodes 93 and 203 have an anode electrode 86, a cathode electrode 89, and a gate electrode 81 disposed in an insulating manner on a semiconductor substrate. In particular, these gate-controlled diodes 93 and 203 possess the following characteristics: Carrier concentration is controlled in a drift region 87 within the semiconductor substrate in response to a voltage applied to the gate electrode 81. The gate-controlled diodes 93 and 203 operate by controlling the carrier concentration as described below.

[0182] In the reverse recovery state, a voltage signal that generates an electron layer at the interface of gate electrode 81 (zero bias or positive bias 70) is applied between gate electrode 81 and anode electrode 86. Conversely, in the forward recovery state, a voltage signal that generates a hole layer at the interface of gate electrode 81 (negative bias) is applied between gate electrode 81 and anode electrode 86. After the forward recovery state, the voltage signal is switched from negative bias 71 to zero bias or positive bias 70.

[0183] This method controls the circuit by determining the pulse width of the other arm 94(92) in accordance with the pulse width of one arm 92(94) in the dual-arm circuit. More specifically, the gate-controlled diodes 93 and 203 are variably controlled for the period during which a zero bias or a positive bias 70 is applied, depending on the non-conducting period of the IGBTs 91 and 901 connected in series with them. According to this semiconductor circuit control method, it is possible to reduce power consumption and miniaturization by improving the transition response characteristics corresponding to various pulse conditions in the inverter's PWM operation, i.e., the ON / OFF transition state.

[0184] [2] Furthermore, in the methods of Embodiments 1 to 4 of the present invention, in addition to the methods described in [1] above, also as... Figure 1A and Figure 1B As shown, control is performed based on the following definition. First, the non-conducting period of the series-connected IGBTs 91 and 901 is defined as t. off Furthermore, the states of gate-controlled diodes 93 and 203 are defined as follows: The period from applying a zero bias or positive bias 70 between the gate electrode 81 and the anode electrode 86 until the reverse recovery state is reached is defined as t. d_rr Furthermore, the duration of the positive recovery state is defined as t. fr .

[0185] Additionally, relative to the non-conduction period t off The period t during which the reverse recovery state will be reached d_rr The period t of the positive recovery state fr The total period t obtained d_rr +t fr The relation satisfies t off ≥t d_rr +t fr Control is achieved through this method. Additionally, based on the non-conduction period t... off The length of t during which the reverse recovery state is reached. d_rr Variable control is implemented. This allows for better transient response characteristics and reduces heat loss during ON / OFF switching.

[0186] [3] Furthermore, in the methods of Embodiments 1 to 4 of the present invention, in addition to the methods described in [2] above, control is also performed based on the following definition. First, control is performed without relying on the non-conduction period t. off The fixed period is set as b. For example... Figure 9A As shown, during the non-conduction period t off Satisfy t off >b+t fr In the case of the relationship, the period t during which the recovery state will be reached.d_rr Set as a fixed period b. Based on the non-conduction period t... off For the period t during which the recovery state is reached d_rr Variable control is implemented. This allows for better transient response characteristics and reduces heat loss during ON / OFF switching.

[0187] [4] In addition to the method described in [3] above, the objects controlled by the methods of Embodiments 1 to 4 of the present invention can be semiconductor circuits, exemplified by three-phase inverters 500 and 501, in addition to single-phase PWM inverters 130 and 150. These semiconductor circuits include: first IGBTs 91 and 901 disposed in one bridge arm 92; second IGBTs 91 and 901 disposed in another bridge arm 94; and gate-controlled diodes 93 and 203 connected in series with the first IGBTs 91 and 901, thereby forming a circuit. Furthermore, the terminal that can apply voltage between the gate electrode of the first IGBTs 91 and 901 and the emitter sensing terminal (emitter electrode) 69 is designated as the first gate terminal 67A. Furthermore, the terminal that can apply voltage between the gate electrode 67A and the emitter electrode 69 of the second IGBTs 91 and 901 is designated as the second gate terminal 67B.

[0188] For the first gate terminal and the second gate terminal, a voltage signal is input to control the first IGBT 91, 901 and the second IGBT 91, 901 to be complementaryly turned on or off at certain intervals. This voltage signal is obtained based on the first PWM command signal 63 and the second PWM command signal 64 modulated with pulse widths. Figure 2 , Figure 12 , Figure 18 and Figure 19 Additionally, regarding... Figure 7A , Figure 7B The voltage signal applied between the gate electrode 81 and the anode electrode 86 of the gate-controlled diode 203 illustrated in Figure 8 is generated based on the second PWM command signal 64. This improves the aforementioned transient response characteristics.

[0189] [5] Furthermore, in addition to the method described in [4] above, the method of embodiments 1 to 4 of the present invention applies a voltage signal between the gate electrode 81 and the anode electrode 86 of the gate-controlled diodes 93 and 203, which is a voltage signal applied to the second gate terminal 67B and a second PWM command signal 64, on the same gate control circuit board 66, 902 ( Figure 2 , Figure 12 , Figure 18 and Figure 19 This is generated in ( ). Thus, the present invention can be easily implemented.

[0190] [6] Furthermore, in addition to the method described in [5] above, the method of Embodiment 2 of the present invention applies a voltage signal between the gate electrode 81 and the anode electrode 86 of the gate-controlled diodes 93 and 203. Figure 12 In the gate control circuit board 66 shown, the second PWM command signal 64 is delayed for a certain period, and the timing of the switching voltage signal is generated by calculating the logical product of a PWM trigger signal synchronized with the pulse width of the second PWM command signal 64 and a fixed trigger signal having a conduction command period longer than the fixed period b. Thus, the present invention can be reliably implemented.

[0191] [7] Furthermore, the method of Embodiment 3 of the present invention differs from the method described in [6] above. Figure 15 and Figure 16 The signal G shown is generated by delaying the forward and reverse recovery times of the gate-controlled diodes based on signal E. That is, in the pulses of the PWM trigger signal and the fixed trigger signal, the pulse drop time is delayed until the reverse recovery state of the gate-controlled diodes 93 and 203 has passed. Therefore, the present invention can be implemented more reliably.

[0192] [8] Furthermore, the method of Embodiment 2 of the present invention, in addition to the method described in [7] above, such as Figure 11A and Figure 11B As shown, voltage signals delayed by the same fixed period 'a' from the first PWM command signal 63 and the second PWM command signal 64 are input to the first gate terminal 67A and the second gate terminal 67B, respectively. Furthermore, when the interval between the conduction command signals in the first PWM command signal 63 and the second PWM command signal 64 is set to DT34, the first and second gate terminals 67B are controlled as follows: First, the relationship between the fixed period 'b', the fixed period 'a', and the interval period DT is set to b = a + DT. Then, a fixed trigger signal having a conduction command period longer than the fixed period 'b' is controlled to input the conduction command at the moment the pulse of the second PWM command signal 64 falls.

[0193] [9] Furthermore, the power converters of embodiments 1 to 4 of the present invention are power converters that apply one of the methods described in [1] to [8] above, for example, Figure 2 , Figure 12 , Figure 18 and Figure 19 Inverters 130, 150, 500, and 501 are shown. The following examples primarily illustrate that the first conductivity type is N-type and the second conductivity type is P-type, but the overall configuration can be reversed. The gate-controlled diodes 93 and 203 in inverters 130, 150, 500, and 501 have the following characteristics: Figure 7A and Figure 7BThe features shown are as follows. That is, the gate-controlled diodes 93 and 203 have a semiconductor substrate of a first conductivity type (N-type), a cathode region of a first conductivity type (N+ type cathode layer 88 and cathode electrode 89), an anode region of a second conductivity type (P-type) (P-type anode layer 84 and anode electrode 86), and a gate electrode 81.

[0194] A cathode region of the first conductivity type (N-type) (N+ type cathode layer 88 and cathode electrode 89) is disposed on the first surface side of the semiconductor substrate. An anode region of the second conductivity type (P-type) (P-type anode layer 84 and anode electrode 86) is disposed on the second surface side of the semiconductor substrate opposite to the first surface side. The anode electrode 86 is disposed on the second surface side of the anode region (P-type anode layer 84 and anode electrode 86). A gate electrode 81 is adjacent to the anode region 86 via a gate insulating film 82.

[0195] In the gate electrode 81, the interior of the trench extending from the second surface side through the anode region (P-type anode layer 84 and anode electrode 86) to the cathode region (N+ type cathode layer 88) is surrounded by a gate insulating film 82. The anode regions (77, 84) and a first conductivity type potential well region (N-type potential well layer 85) in contact with the gate insulating film 82 are in contact. The potential well region 85 and a first conductivity type drift region (N-type cathode drift layer 87) in contact with the cathode region (N+ type cathode layer 88) are adjacent.

[0196] When a negative bias is applied to the gate electrode 81 relative to the anode electrode 86, a hole layer is formed in the portion of the potential well region (N-type potential well layer 85) that contacts the gate insulating film 82. During the forward recovery state, holes are injected from the hole layer formed in the potential well region (N-type potential well layer 85) into the drift region (N-type cathode drift layer 87). Therefore, under the pulse conditions of PWM operation, the conduction losses and forward recovery losses generated in the diodes can be reduced, providing inverters 500 and 501 that are energy-efficient and miniaturized.

[0197]

[10] Furthermore, in the power converter of Embodiment 4 of the present invention, the IGBT901 in [9] above is as follows Figure 19 The diagram shows a dual-gate IGBT 901 with a first gate terminal and a second gate terminal, which has the following control functions. In this dual-gate IGBT 901, when a voltage above a threshold is applied to at least one gate terminal, it transitions from a non-conducting state to a conducting state. Furthermore, in this dual-gate IGBT 901, when the voltage applied to both gate terminals is below the threshold, it transitions from a conducting state to a non-conducting state. Therefore, under the pulse conditions of PWM operation, the conduction loss and forward recovery loss generated in the diode can be reduced, providing energy-saving and miniaturized inverters 130, 150, 500, and 501.

[0198]

[11] Furthermore, the power converters in Embodiments 1, 2, and 4 of the present invention are power converters configured in the manner described in [9] or

[10] above, which convert DC to single-phase or three-phase AC to supply power to the load 950, for example, are Figure 2 and Figure 12 The single-phase inverter shown, and Figure 18 and Figure 19 The three-phase inverter shown is a power converter whose circuitry consists of a number of dual-bridge arms corresponding to the number of AC phases being converted. One end of each of these dual-bridge arms serves as a DC input terminal connected to the positive and negative terminals, respectively. Furthermore, for each dual-bridge arm corresponding to the number of phases, the neutral point connecting each arm 92, 94 is used as AC terminals 121-123 connected to the load 950. This provides a highly practical single-phase or three-phase inverter that is energy-efficient and compact.

[0199] Symbol Explanation

[0200] 1…Gate control signal of dual-bridge arm IGBT

[0201] 2…Gate control signal of gate-controlled diode

[0202] 3…Cathode / anode voltage V of a gate-controlled diode KA

[0203] 4… Current I of the gate-controlled diode K

[0204] 5…V of gate-controlled diodes KA ·I K Time integral of product, energy E produced fr

[0205] 6…Control of the present invention

[0206] 7…Control of comparative examples

[0207] 8… The increase in positive recovery loss ΔE fr

[0208] 9… On-state voltage

[0209] 10…Break-off voltage

[0210] 11…Zero bias or positive bias

[0211] 12… Negative bias less than the threshold voltage

[0212] 13…High voltage (power supply voltage)

[0213] 14…0V potential

[0214] 15…High current (load current)

[0215] 16…0A potential

[0216] 17…Connection of dual-arm IGBTs

[0217] 18…Switch-off of dual-bridge IGBTs

[0218] 19… Non-conducting period t of the dual-arm IGBT off

[0219] 20…Carrier extraction period t of a gate-controlled diode d_rr

[0220] 21…Forward recovery voltage

[0221] 22…Reverse recovery current

[0222] 23…Positive recovery state

[0223] 24…Reverse recovery state

[0224] 25…The positive recovery voltage and larger negative polarity V in the comparative example KA The generation

[0225] 26…Zero (Baseline)

[0226] 27…The non-conducting period of a gate-controlled diode

[0227] 28… On-time of gate-controlled diodes

[0228] 29…Loss E generated in the on state cond

[0229] 30…Loss E generated in reverse recovery state rrsw

[0230] 32… Forward voltage when conducting

[0231] 33… Gate control signal of the IGBT in this bridge arm

[0232] 34…Dead Zone Time DT

[0233] 35… Timing of inputting the turn-on command to the IGBT of this bridge arm

[0234] 36… During the positive recovery period t fr

[0235] 37…Reverse recovery period t rr

[0236] 42… Control Signal

[0237] 43…Gate control signal of a gate-controlled diode

[0238] 44…IGBT

[0239] 45…Gate-controlled diode

[0240] 47…DC power supply

[0241] 48…Inductive load

[0242] 49…Reverse recovery current of existing gate-controlled diodes

[0243] 50… Reverse recovery current of existing pn diodes

[0244] 51…Patent Document 1 describes the cathode / anode voltage

[0245] 52…Cathode / anode voltage of existing pn diodes

[0246] 53…Instruction Delay Module

[0247] 54…Circuit-breaking command triggered fixed pulse generation module

[0248] 55…Delay Module

[0249] 56…Logic Product Module

[0250] 57… Output Buffer

[0251] 58… Trigger signal generation module

[0252] 59…Conduction Level

[0253] 60… open circuit level

[0254] 62…Command signal for PWM operation of the inverter

[0255] 63… Command signal for the upper bridge arm

[0256] 64… Command signal for the lower bridge arm

[0257] 66… Gate control circuit

[0258] 67… Gate terminal of IGBT

[0259] 68…Gate terminal of a gate-controlled diode

[0260] 69…Emitter Sensing Terminal

[0261] 70…zero bias or positive bias

[0262] 71… Negative bias less than the threshold voltage

[0263] 72… Positive external power supply

[0264] 73…cavitation layer

[0265] 74…hole carriers

[0266] 75… Electron carriers

[0267] 76… electron layer

[0268] 77…P-type anode layer

[0269] 78… Ohmic contact (barrier)

[0270] 81…Gate electrode

[0271] 82… Gate insulating film (gate oxide film)

[0272] 83…Insulated Gate (Gate)

[0273] 84…P-type anode layer

[0274] 85…N-type potential well layer

[0275] 86… Anode electrode

[0276] 87…N-type cathode drift layer

[0277] 88…N+ type cathode layer

[0278] 89… Cathode electrode

[0279] 90… Neutral point

[0280] 91…IGBT

[0281] 92… Upper bridge arm

[0282] 93…Gate-controlled diode

[0283] 94…Lower bridge arm

[0284] 95…Inductive load

[0285] 96… Upper or lower bridge arm

[0286] 97… Gate control signal of the upper bridge arm IGBT

[0287] 98… Gate control signal of the upper bridge arm gate-controlled diode

[0288] 99… Cathode / anode voltage V of the gate-controlled diode on the upper bridge arm KA

[0289] 100… Cathode current I of the upper bridge arm gate-controlled diode K

[0290] 101… Gate control signal of the lower bridge arm IGBT

[0291] 102… Gate control signal of the lower bridge arm gate-controlled diode

[0292] 103… Collector / emitter voltage V of the lower arm IGBT CE

[0293] 104… Collector current I of the lower arm IGBT C

[0294] 105…Conduction period of the lower arm IGBT

[0295] 106… On-time of the upper bridge arm gate-controlled diode

[0296] The current flowing through the 107… diode

[0297] 108… Cathode / Anode Voltage

[0298] 109… The period during which the diode is in the conducting state, the conduction period

[0299] 110… The period during which the diode is in reverse recovery state, the reverse recovery period

[0300] 111…Die during reverse bias and non-conducting periods

[0301] 112… Negative bias less than the threshold voltage

[0302] 113…positive bias above threshold voltage

[0303] 115… Collector / emitter voltage V of the upper bridge arm IGBT CE

[0304] 116… Collector current I of the upper arm IGBT C

[0305] 117… Cathode / anode voltage V of the lower bridge arm gate-controlled diode KA

[0306] 118… Cathode current I of the lower bridge arm gate-controlled diode K

[0307] 119…Conduction period of the lower bridge arm gate-controlled diode

[0308] 120… On-time of the upper arm IGBT

[0309] 121… Neutral point of a three-phase AC inverter

[0310] 122… Neutral point of a three-phase AC inverter

[0311] 123… Neutral point of a three-phase AC inverter

[0312] 130… Single-phase AC inverter ( Figure 2 )

[0313] 140…A circuit for an inverter formed by connecting the gate control circuit to the bridge arm ( Figure 10 )

[0314] 150… Single-phase AC inverter ( Figure 12 )

[0315] 160…A circuit for an inverter formed by connecting the gate control circuit to the bridge arm ( Figure 15 )

[0316] 164…Control Circuit

[0317] 167…Control circuit for controlling the gate of the IGBT

[0318] 168…Inductive load

[0319] 169…DC voltage (power) source

[0320] 170…IGBT

[0321] 171…Insulating gate (terminal) of IGBT70

[0322] 172… A diode connected in reverse parallel with IGBT70

[0323] 200, 200'... Method of Example 1

[0324] 201… Method of a comparative example relative to Example 1

[0325] 203… Gate-controlled diode

[0326] 300, 300'... Method of Example 2

[0327] 400… The method of Example 3, the case where g is longer during the input conduction command period.

[0328] 401…The method of Example 3, the case where f is short during the input conduction command period.

[0329] 500… Three-phase AC inverter

[0330] 501… A variation of a three-phase AC inverter

[0331] 600… Three-phase AC inverter ( Figure 20 )

[0332] 700… Evaluation Circuit ( Figure 21)

[0333] 901…Dual-gate IGBT

[0334] 902… Gate control circuit

[0335] 950… Electric motor

[0336] 951… Command section of three-phase AC inverter

[0337] T…time

Claims

1. A semiconductor circuit control method for controlling a semiconductor circuit, wherein the semiconductor circuit is composed of a double-bridge arm formed by connecting bridge arms in series, the bridge arm being formed by connecting gate-controlled diodes to an IGBT, the semiconductor circuit control method being characterized in that: In the bridge arm, the collector and emitter of the IGBT are connected in parallel with the anode and cathode of the gate-controlled diode in opposite directions. The dual bridge arms connect the gate-controlled diode and the IGBT in series from one bridge arm to the other. The gate-controlled diode has an anode electrode, a cathode electrode, and a gate electrode disposed in an insulated manner on a semiconductor substrate. In response to the voltage applied to the gate electrode, the carrier concentration in the drift region within the semiconductor substrate is controlled. In the positive recovery state, a negative bias voltage signal is applied between the gate electrode and the anode electrode to generate a hole layer at the interface of the gate electrode. In the reverse recovery state, a voltage signal is applied between the gate electrode and the anode electrode to generate an electron layer at the interface of the gate electrode, either with zero bias or positive bias. After the positive recovery state, the voltage signal is switched from the negative bias to either the zero bias or the positive bias. The pulse width of one bridge arm is determined in a manner corresponding to the pulse width of one of the bridge arms, and the period during which the zero bias or the positive bias is applied is variably controlled according to the non-conducting period of the series-connected IGBTs. The non-conducting period of the series-connected IGBTs is defined as t. off ,and, Regarding the state of the gate-controlled diode. The period from the application of the zero bias or the positive bias between the gate electrode and the anode electrode until the reverse recovery state is reached is defined as t. d_rr , The period of the positive recovery state is defined as t. fr , With respect to the non-conducting period t off The period t during which the reverse recovery state is reached d_rr The period t of the positive recovery state fr The total period t d_rr + t fr The relation satisfies t off ≥ t d_rr + t fr According to the non-conduction period t off The length of t can be variably controlled to determine the period t during which the reverse recovery state is reached. d_rr .

2. The semiconductor circuit control method as described in claim 1, characterized in that: Let it be independent of the non-conduction period t off The fixed period is b. During the non-conducting period t off Satisfy t off > b + t fr In the case of the relationship, let t be the period t during which the recovery state is reached. d_rr For the fixed period b, According to the non-conduction period t off The period t for reaching the recovery state can be variably controlled. d_rr .

3. The semiconductor circuit control method as described in claim 2, characterized in that: The semiconductor circuit described below includes: a first IGBT disposed in one of the bridge arms; a second IGBT disposed in the other bridge arm; and a gate-controlled diode connected in series with the first IGBT. Let the terminal that can apply a voltage between the gate electrode and the emitter electrode of the first IGBT be called the first gate terminal. Let the terminal that can apply a voltage between the gate electrode and the emitter electrode of the second IGBT be the second gate terminal. For the first gate terminal and the second gate terminal, a voltage signal is input that controls the first IGBT and the second IGBT to be complementaryly turned on or off at certain intervals. This voltage signal is obtained based on a first PWM command signal and a second PWM command signal modulated with pulse widths. The voltage signal applied between the gate electrode and the anode electrode of the gate-controlled diode is generated based on the second PWM command signal.

4. The semiconductor circuit control method as described in claim 3, characterized in that: The voltage signal applied to the second gate terminal and the voltage signal applied between the gate electrode and the anode electrode of the gate-controlled diode are generated on the same gate control circuit board upon receiving the second PWM command signal.

5. The semiconductor circuit control method as described in claim 4, characterized in that: The voltage signal applied between the gate electrode and the anode electrode of the gate-controlled diode is used in the gate control circuit board to delay the second PWM command signal for a certain period of time. Furthermore, the timing for switching the voltage signal is generated by taking the logical product of a PWM trigger signal that is synchronized with the pulse width of the second PWM command signal and a fixed trigger signal that has a conduction command period longer than the fixed period b.

6. The semiconductor circuit control method as described in claim 5, characterized in that: In the pulses of the PWM trigger signal and the fixed trigger signal, the timing of the pulse fall is delayed until it passes through the reverse recovery state of the gate-controlled diode.

7. The semiconductor circuit control method as described in claim 6, characterized in that: The first gate terminal and the second gate terminal respectively receive voltage signals that are delayed by the same certain period 'a' from the first PWM command signal and the second PWM command signal. When the interval between the turn-on command signals in the first PWM command signal and the second PWM command signal is DT, Let the relationship between the fixed period b, the certain period a, and the interval period DT be b = a + DT, and, In the fixed trigger signal having a conduction command period longer than the fixed period b, the turn-on command is input at the moment when the pulse of the second PWM command signal falls.

8. A power converter that applies the semiconductor circuit control method according to any one of claims 1 to 7, characterized in that: The gate-controlled diode includes: The semiconductor substrate of the first conductivity type; A cathode region of a first conductivity type is disposed on the first surface side of the semiconductor substrate; A second conductivity type anode region is disposed on the second surface side of the semiconductor substrate, opposite to the first surface side; An anode electrode disposed on the second surface side of the anode region; and The gate electrode adjacent to the anode region, separated by a gate insulating film. In the gate electrode, the interior of the trench extending from the second surface side through the anode region to the cathode region is surrounded by the gate insulating film. The anode region and the potential well region of the first conductivity type that is in contact with the gate insulating film are in contact. The potential well region is adjacent to the drift region of the first conductivity type that is in contact with the cathode region. When the negative bias is applied to the gate electrode relative to the anode electrode, a hole layer is formed in the portion of the potential well region that contacts the gate insulating film. During the positive recovery state, holes are injected into the drift region from the hole layer formed in the potential well region.

9. The power converter as described in claim 8, characterized in that: The IGBT is a dual-gate IGBT with two gate terminals. It has a control function that transitions from a non-conducting state to a conducting state when a voltage above a threshold is applied to at least one of the two gate terminals, and transitions from a conducting state to a non-conducting state when the voltages applied to both gate terminals are below the threshold.

10. The power converter as described in claim 8 or 9, characterized in that: To convert direct current into single-phase or three-phase alternating current to supply power to a load, a circuit is constructed using a double bridge arm with a number of groups corresponding to the number of phases of the converted alternating current. One end and the other end of the two extreme points of the double bridge arm are respectively used as the input terminals of the DC power supply, which are connected to the positive and negative terminals. For each of the dual bridge arms corresponding to the number of phases, the neutral point where each bridge arm is connected to the other is respectively used as an AC terminal connected to the load.

Images