Three-dimensional integrated chip, three-dimensional integrated chip testing method and detection device

Abstract

The present application relates to the field of semiconductor technology and discloses a three-dimensional integrated chip, a testing method for the three-dimensional integrated chip, and a detection device. The three-dimensional integrated chip includes: at least one first chip; at least one second chip, the second chip being connected to the first chip via an interconnection module; wherein the first chip includes a first circuit and a first test module, the first circuit being connected to the first test module; and the second chip includes a second circuit and a second test module, the second circuit being connected to the second test module; wherein the test results obtained by connecting the first circuit to the first test module and the test results obtained by connecting the second circuit to the second test module represent the cause of a failure of the three-dimensional integrated chip. Through the above-described method, it is possible to detect faults in the three-dimensional integrated chip and locate the location of the fault.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional integrated chip, a testing method for the three-dimensional integrated chip, and a detection device. Background Art

[0002] The emergence of three-dimensional chips has brought new vitality to the semiconductor industry. This approach utilizes three-dimensional integrated chips to create a three-dimensional chip by fabricating different circuit units on multiple planar wafers and connecting them together through bonding or TSV (Through Silicon Via) technology. This new chip structure, formed by stacking and interconnecting multiple wafers vertically, boasts high integration, low power consumption, high bandwidth, compact footprint, short interconnects, and support for heterogeneous integration. Both bonding and TSV can be used to transmit signals and power between chips.

[0003] After the three-dimensional chip packaging is completed, the resulting package needs to be inspected so that unqualified packages can be identified. However, even if the faulty package can be identified during testing, it is difficult to locate the fault in the three-dimensional integrated chip, whether it is inside a chip or in the connection between chips. It is also difficult to determine whether the connection between different chips is intact and whether the signal transmission between different chips can maintain good signal integrity. Summary of the Invention

[0004] The present application provides a three-dimensional integrated chip, a testing method for the three-dimensional integrated chip, and a detection device to solve the technical problem in the prior art that it is difficult to locate the location of a fault in the three-dimensional integrated chip.

[0005] To solve the above problems, the present application provides a three-dimensional integrated chip, comprising:

[0006] at least one first chip;

[0007] at least one second chip, wherein the second chip is connected to the first chip via an interconnection module;

[0008] The first chip includes a first circuit and a first test module, and the first circuit is connected to the first test module;

[0009] The second chip includes a second circuit and a second test module, and the second circuit is connected to the second test module;

[0010] The test result obtained by connecting the first circuit with the first test module and the test result obtained by connecting the second circuit with the second test module represent the cause of the failure of the three-dimensional integrated chip.

[0011] Furthermore, the first chip includes: a first switch circuit connecting the first circuit and the interconnection module; and a second switch circuit connecting the first circuit and the first test module.

[0012] Furthermore, the second chip includes: a third switch circuit, the third switch circuit connecting the second circuit and the interconnection module; and a fourth switch circuit, the fourth switch circuit connecting the second test module and the interconnection module.

[0013] The present application also proposes a testing method for a three-dimensional integrated chip, which includes: detecting a first circuit or a second circuit or an interconnection module based on a first test module and a second test module to obtain a test result; and determining a cause of failure of the three-dimensional integrated chip based on the test result.

[0014] The present application also proposes a detection device, which is applied to the above-mentioned test method for the three-dimensional integrated chip and is used to detect the three-dimensional integrated chip.

[0015] The present application provides a three-dimensional integrated chip, a testing method for the three-dimensional integrated chip, and a detection device. The three-dimensional integrated chip includes: at least one first chip; at least one second chip, the second chip being connected to the first chip via an interconnection module; wherein the first chip includes a first circuit and a first test module, the first circuit being connected to the first test module; the second chip includes a second circuit and a second test module, the second circuit being connected to the second test module; wherein the test results obtained by connecting the first circuit to the first test module and the test results obtained by connecting the second circuit to the second test module represent the cause of the failure of the three-dimensional integrated chip. Based on the above method, by connecting and coordinating the first circuit, the first test module, the second circuit, and the second test module, the three-dimensional integrated chip is tested, thereby realizing fault detection of the second chip or the first chip in the three-dimensional integrated chip and the connection between the chips, and locating the location of the failure based on the test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a circuit diagram of the first embodiment of the three-dimensional integrated chip provided by this application;

[0017] Figure 2 A schematic flow chart of a first embodiment of a testing method for a three-dimensional integrated chip provided in this application;

[0018] Figure 3 This is a flow chart of a second embodiment of a method for testing a three-dimensional integrated chip provided by the present application;

[0019] Figure 4 This is a flow chart of a third embodiment of a method for testing a three-dimensional integrated chip provided by the present application;

[0020] Figure 5 This is a flow chart of a fourth embodiment of a method for testing a three-dimensional integrated chip provided by the present application;

[0021] Figure 6 This is a circuit diagram of the second embodiment of the three-dimensional integrated chip provided by this application;

[0022] Figure 7 This is a circuit diagram of the third embodiment of the three-dimensional integrated chip provided by this application;

[0023] Figure 8 This is a circuit diagram of a fourth embodiment of the three-dimensional integrated chip provided by the present application;

[0024] Figure 9 It is a structural schematic diagram of an embodiment of the detection device provided by this application. DETAILED DESCRIPTION

[0025] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0026] The terms "first," "second," and the like in this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0027] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] See also Figure 1 , Figure 11 is a circuit diagram of a first embodiment of a three-dimensional integrated chip 10 of the present application. The three-dimensional integrated chip 10 of this embodiment includes at least one first chip 11 and a second chip 12 connected to the first chip 11 via an interconnection module 13 .

[0029] The three-dimensional integrated chip 10 further includes a plurality of first chips 11 and a plurality of second chips 12. For example, the plurality of first chips 11 and the plurality of second chips 12 may be arranged at intervals, for example, from top to bottom, in the order of second chip 12, first chip 11, second chip 12, first chip 11, ... For another example, the plurality of first chips 11 and the plurality of second chips 12 may be arranged symmetrically, for example, from top to bottom, in the order of second chip 12, second chip 12, ..., first chip 11, first chip 11, .... The first chip 11 includes a first circuit 111 and a first test module 112, and the second chip 12 includes a second circuit 121 and a second test module 122.

[0030] Specifically, first chip 11 includes a first circuit 111 and a first test module 112. It is the lower-layer chip in 3D integrated chip 10 and is connected to upper-layer second chip 12 via interconnection module 13 for signal and power transmission. First chip 11 also includes a first switching circuit 113 for enabling interaction between first circuit 111 and second chip 12, and a second switching circuit 114 for enabling interaction between first circuit 111 and first test module 112. First switching circuit 113 connects first circuit 111 and interconnection module 13.

[0031] Second chip 12, comprising a second circuit 121 and a second test module 122, is the upper chip within 3D integrated chip 10. It is connected to first chip 11 below via interconnect module 13 for signal and power transmission. Second chip 12 also includes a third switch circuit 123 for enabling interaction between second circuit 121 and first chip 11, and a fourth switch circuit 124 for enabling interaction between second test module 122 and first chip 11. Third switch circuit 123 connects second circuit 12 and interconnect module 13, while fourth switch circuit 124 connects second test module 122 and interconnect module 13.

[0032] It should be noted that interconnect module 13 is used to connect first chip 11 and second chip 12 and can be a through-silicon via (TSV) or a bonding column. A bonding column can directly bond two clean, atomically flat semiconductor materials of the same or different nature under certain conditions, bonding the wafers together through van der Waals, molecular, or even atomic forces. TSVs use an etching process to create holes in the silicon wafer, shortening the path for signals to be transmitted from one chip to the next or from one circuit layer to the next, thereby increasing interconnect density.

[0033] Specifically, by controlling the on / off switching of the first switch circuit 113, the second switch circuit 114, the third switch circuit 123, and the fourth switch circuit 124, the first circuit 111, the interconnection module 13, and the second circuit 121 can be tested. The first switch circuit 113, the second switch circuit 114, the third switch circuit 123, and the fourth switch circuit 124 can be implemented as switches, switching circuits, or selection circuits, and their on / off switching is used to control signal transmission between the first circuit 111, the first test module 112, the second circuit 121, and the second test module 122 in the three-dimensional integrated chip 10.

[0034] It should be noted that Figure 1 The lines between the above connections and circuit modules shown do not necessarily exist, and are only used to illustrate the connection relationship between the above connections and circuit modules.

[0035] The three-dimensional integrated chip 10 of this embodiment includes: at least one first chip 11; at least one second chip 12, the second chip 12 being connected to the first chip 11 via an interconnection module 13. The first chip 11 includes a first circuit 111 and a first test module 112, the first circuit 111 being connected to the first test module 112; the second chip 12 includes a second circuit 121 and a second test module 122, the second circuit 121 being connected to the second test module 122. The test results obtained by connecting the first circuit 111 with the first test module 112 and the test results obtained by connecting the second circuit 121 with the second test module 122 represent the cause of a failure of the three-dimensional integrated chip 10. Through the above-described method, the connection and coordination of the first circuit 111, the first test module 112, the second circuit 121, and the second test module 122 can be completed, the three-dimensional integrated chip 10 can be tested, and based on the obtained test results, a fault analysis of the three-dimensional integrated chip 10 can be performed to locate the location of the fault.

[0036] See also Figure 2 , Figure 2 1 is a flow chart illustrating a first embodiment of a test method for a three-dimensional integrated chip 10 provided herein. It should be noted that the first test module 112 and the second test module 122 are pre-tested modules that test the first circuit 111 or the second circuit 121 or the interconnect module 13 of the three-dimensional integrated chip 10. The first test module 112 and the second test module 122 perform pre-tests before being connected to the circuit to ensure that the first test module 112 and the second test module 122 function properly when testing the circuit components of the three-dimensional integrated chip 10.

[0037] like Figure 2As shown, the testing method of the three-dimensional integrated chip 10 of the present application includes the following steps:

[0038] S101 : Detecting the first circuit 111 or the second circuit 121 or the interconnection module 13 based on the first test module 112 and the second test module 122 to obtain a test result.

[0039] Specifically, the first switch circuit 113, the second switch circuit 114, the third switch circuit 123 and the fourth switch circuit 124 are controlled to be turned on or off, and the first test module 112 and the second test module 122 are connected to the first circuit 111 or the second circuit 121 or the interconnection module 13, so that the first test module 112 and the second test module 122 detect the first circuit 111 or the second circuit 121 or the interconnection module 13 and obtain corresponding test results.

[0040] S102: Determine the failure cause of the three-dimensional integrated chip 10 based on the test results.

[0041] Specifically, based on the detection results of the first test module 112 or the second test module 122 detecting the first circuit 111 or the second circuit 121 or the interconnection module 13, it can be determined whether there is an error inside a chip in the three-dimensional integrated chip 10, and whether the connection between different chips is intact, thereby locating the fault position of the three-dimensional integrated chip 10.

[0042] See also Figure 3-5 , the testing process of the three-dimensional integrated chip 10 is described in detail below.

[0043] See also Figure 3 , Figure 3 It is a flow chart of the second embodiment of the testing method of the three-dimensional integrated chip 10 provided by the present application.

[0044] S201 : Control the second switch circuit 114 to be turned on, detect the first circuit 111 and the first test module 112 , and obtain a first test result.

[0045] Specifically, when the 3D integrated chip 10 enters the test mode, the second switch circuit 121 is controlled to conduct, and the first circuit 111 and the first test module 112 are tested to obtain a first test result. A determination is made as to whether the first test result is correct. If the first test result is incorrect, the process proceeds to step S202; if the first test result is correct, the process proceeds to step S203.

[0046] In a specific embodiment, when entering the test mode, it is possible to selectively access the normal working circuits in each / certain / some chips, such as the first circuit 111, to test them.

[0047] S202 : In response to the first test result being an error, the failure cause of the three-dimensional integrated chip 10 is an error in the first circuit 111 .

[0048] Specifically, a judgment is made based on a first test result obtained by testing the first circuit 111 and the first test module 112 . When it is determined that the first test result is an error, it is determined that the first circuit 111 has an error.

[0049] S203 : In response to the first test result being correct, controlling the first switch circuit 113 and the fourth switch circuit 124 to be turned on, detecting the first circuit 111 and the second test module 122 , and obtaining a second test result.

[0050] Specifically, if the first test result is correct, it indicates that the first circuit 111 is not faulty. Based on the correct first test result, the first switch circuit 113 and the fourth switch circuit 124 are controlled to conduct, and the first circuit 111 and the second test module 122 are tested to obtain a second test result. It will be appreciated that when testing the first circuit 111 and the second test module 122, the test signal will pass through the interconnect module 13, which means that the second test result can indicate whether the interconnect module 12 is intact. Specifically, the second test result is determined to be correct. If the second test result is determined to be incorrect, the process proceeds to step S204; if the second test result is determined to be correct, the process proceeds to step S205.

[0051] S204 : In response to the second test result being an error, the failure of the three-dimensional integrated chip 10 is caused by an error in the interconnection module 13 .

[0052] Specifically, based on the second test result obtained by testing the first circuit 111 and the second test module 122 , when it is determined that the second test result is erroneous, it is determined that the interconnection module 13 connecting the first circuit 111 and the second test module 122 is erroneous.

[0053] S205 : In response to the second test result being correct, controlling the first switch circuit 113 and the third switch circuit 123 to be turned on, detecting the first circuit 111 and the second circuit 121 , and obtaining a third test result.

[0054] Specifically, if the second test result is correct, it indicates that the interconnection module 13 connecting the first circuit 111 and the second test module 122 is not faulty. Based on the correct second test result, the first switch circuit 113 and the third switch circuit 123 are controlled to be conductive, and the first circuit 111 and the second circuit 121 are tested to obtain a third test result. Whether the third test result is correct is determined. If the third test result is determined to be incorrect, the process proceeds to step S206; if the third test result is determined to be correct, the process proceeds to step S207.

[0055] S206 : In response to the third test result being an error, the failure cause of the three-dimensional integrated chip 10 is an error in the second circuit 121 .

[0056] Specifically, based on the third test result obtained by testing the first circuit 111 and the second circuit 121 , when it is determined that the third test result is an error, it is determined that the second circuit 121 is faulty, and the three-dimensional integrated chip 10 is faulty.

[0057] S207 : In response to the third test result being correct, the three-dimensional integrated chip 10 has no errors.

[0058] Specifically, based on the third test result obtained by testing the first circuit 111 and the second circuit 121 , when it is determined that the third test result is correct, it is determined that the second circuit 121 is not faulty and the three-dimensional integrated chip 10 is not faulty.

[0059] This embodiment provides a flow chart for performing fault detection on a three-dimensional integrated chip 10. It should be noted that the flow chart provided in this embodiment is only one of the methods for performing fault detection on the three-dimensional integrated chip 10. The conventional working circuits and test circuits within each / certain / some chips in the three-dimensional integrated chip 10 can be combined and adjusted during the test process to achieve the same effect of fault detection on the three-dimensional integrated chip 10.

[0060] Unlike existing technologies, the present invention's testing method for a three-dimensional integrated chip 10 utilizes a first test module 112 and a second test module 122 to test the first circuit 111, the second circuit 121, or the interconnect module 13 to obtain test results. The test results are then used to determine the cause of a failure in the three-dimensional integrated chip 10. By connecting and arranging the first circuit 111, the first test module 112, the second circuit 121, and the second test module 122, the three-dimensional integrated chip 10 is tested. This method can detect internal errors in a particular chip within the three-dimensional integrated chip 10, verify the integrity of connections between different chips, and verify that signal transmission between the chips maintains good signal integrity.

[0061] See also Figure 4 , Figure 4 It is a flow chart of the third embodiment of the testing method of the three-dimensional integrated chip 10 provided in this application.

[0062] S301 : Control the fourth switch circuit 124 to be turned on, detect the first test module 112 and the second test module 122 , and obtain a first test result.

[0063] Specifically, when the three-dimensional integrated chip 10 enters test mode, the fourth switch circuit 124 is turned on, and the first test module 112 and the second test module 122 are tested to obtain a first test result. It will be appreciated that when testing the first circuit 111 and the second test module 122, the test signal will pass through the interconnect module 13, indicating that the first test result can indicate whether the interconnect module 12 is intact. Specifically, the first test result is determined to be correct. If the first test result is determined to be incorrect, the process proceeds to step S302; if the first test result is determined to be correct, the process proceeds to step S303.

[0064] S302 : In response to the first test result being an error, the failure cause of the three-dimensional integrated chip 10 is an error in the interconnection module 13 .

[0065] Specifically, based on the first test result obtained by testing the first test module 112 and the second test module 122 , when it is determined that the first test result is wrong, it is determined that the interconnection module 13 connecting the first test module 112 and the second test module 122 is wrong.

[0066] S303 : In response to the first test result being correct, controlling the second switch circuit 114 to be turned on, detecting the first circuit 111 and the first test module 112 , and obtaining a second test result.

[0067] Specifically, if the first test result is correct, it indicates that the interconnection module 13 connecting the first test module 112 and the second test module 122 is not faulty. Based on the correct first test result, the second switch circuit 114 is controlled to conduct, and the first circuit 111 and the first test module 112 are tested to obtain a second test result. Whether the second test result is correct is determined. If the second test result is determined to be incorrect, the process proceeds to step S304; if the second test result is determined to be correct, the process proceeds to step S305.

[0068] S304 : In response to the second test result being an error, the failure of the three-dimensional integrated chip is caused by an error in the first circuit 111 .

[0069] Specifically, a judgment is made based on a second test result obtained by testing the first circuit 111 and the first test module 112 . When it is determined that the second test result is an error, it is determined that the first circuit 111 has an error.

[0070] S305 : In response to the second test result being correct, controlling the first switch circuit 113 and the third switch circuit 123 to be turned on, detecting the first circuit 111 and the second circuit 121 , and obtaining a third test result.

[0071] Specifically, if the second test result is correct, it indicates that the first circuit 111 is not faulty. Based on the correct second test result, the first switch circuit 113 and the third switch circuit 123 are controlled to be conductive, and the first circuit 111 and the second circuit 121 are tested to obtain a third test result. A determination is made as to whether the third test result is correct. If the third test result is incorrect, the process proceeds to step S306; if the third test result is correct, the process proceeds to step S307.

[0072] S306 : In response to the third test result being an error, the failure cause of the three-dimensional integrated chip 10 is an error in the second circuit 121 .

[0073] Specifically, based on the third test result obtained by testing the first circuit 111 and the second circuit 121 , when it is determined that the third test result is an error, it is determined that the second circuit 121 is faulty, and the three-dimensional integrated chip 10 is faulty.

[0074] S307 : In response to the third test result being correct, the three-dimensional integrated chip 10 has no errors.

[0075] Specifically, based on the third test result obtained by testing the first circuit 111 and the second circuit 121 , when it is determined that the third test result is correct, it is determined that the second circuit 121 is not faulty and the three-dimensional integrated chip 10 is not faulty.

[0076] Different from the prior art, the present invention's testing method for a three-dimensional integrated chip 10 uses a first test module 112 and a second test module 122 to test the first circuit 111, the second circuit 121, or the interconnect module 13 to obtain test results. The cause of a failure in the three-dimensional integrated chip 10 is determined based on the test results. The present invention's method connects and coordinates the first circuit 111, the first test module 112, the second circuit 121, and the second test module 122 to test the three-dimensional integrated chip 10. This method can detect whether a chip within the three-dimensional integrated chip 10 has an internal error, and can also test whether the connections between different chips are intact and whether signal transmission between the chips maintains good signal integrity.

[0077] See also Figure 5 , Figure 5 1 is a flow chart of a fourth embodiment of a method for testing a three-dimensional integrated chip 10 provided in this application.

[0078] S401 : Control the fourth switch circuit 124 to be turned on, detect the first test module 112 and the second test module 122 , and obtain a first test result.

[0079] Specifically, when the three-dimensional integrated chip 10 enters test mode, the fourth switch circuit 124 is turned on, and the first test module 112 and the second test module 122 are tested to obtain a first test result. It will be appreciated that when testing the first circuit 111 and the second test module 122, the test signal will pass through the interconnect module 13, indicating that the first test result can indicate whether the interconnect module 12 is intact. Specifically, the first test result is determined to be correct. If the first test result is determined to be incorrect, the process proceeds to step S402; if the first test result is determined to be correct, the process proceeds to step S403.

[0080] S402 : In response to the first test result being an error, the failure cause of the three-dimensional integrated chip 10 is an error in the interconnection module 13 .

[0081] Specifically, based on the first test result obtained by testing the first test module 112 and the second test module 122 , when it is determined that the first test result is wrong, it is determined that the interconnection module 13 connecting the first test module 112 and the second test module 122 is wrong.

[0082] S403: In response to the first test result being correct, the first switch circuit 113 and the fourth switch circuit 124 are controlled to be turned on, the first circuit 111 and the second test module 122 are detected, and a second test result is obtained.

[0083] Specifically, if the first test result is correct, it indicates that the interconnection module 13 connecting the first test module 112 and the second test module 122 is not faulty. Based on the correct first test result, the first switch circuit 113 and the fourth switch circuit 124 are controlled to be conductive, and the first circuit 111 and the second test module 122 are tested to obtain a second test result. A determination is made as to whether the second test result is correct. If the second test result is determined to be incorrect, the process proceeds to step S404; if the second test result is determined to be correct, the process proceeds to step S405.

[0084] S404 : In response to the second test result being an error, the failure of the three-dimensional integrated chip is caused by an error in the first circuit 111 .

[0085] Specifically, a judgment is made based on a second test result obtained by testing the first circuit 111 and the second test module 122 . When it is determined that the second test result is an error, it is determined that the first circuit 111 is faulty.

[0086] S405 : In response to the second test result being correct, controlling the first switch circuit 113 and the third switch circuit 123 to be turned on, detecting the first circuit 111 and the second circuit 121 , and obtaining a third test result.

[0087] Specifically, if the second test result is correct, it indicates that the first circuit 111 is not faulty. Based on the fact that the second test result is correct, the first switch circuit 113 and the third switch circuit 123 are controlled to be conductive, and the first circuit 111 and the second circuit 121 are tested to obtain a third test result. A determination is made as to whether the third test result is correct. If the third test result is determined to be incorrect, the process proceeds to step S406; if the third test result is determined to be correct, the process proceeds to step S407.

[0088] S406 : In response to the third test result being an error, the failure cause of the three-dimensional integrated chip 10 is an error in the second circuit 121 .

[0089] Specifically, based on the third test result obtained by testing the first circuit 111 and the second circuit 121 , when it is determined that the third test result is an error, it is determined that the second circuit 121 is faulty, and the three-dimensional integrated chip 10 is faulty.

[0090] S407 : In response to the third test result being correct, the three-dimensional integrated chip 10 has no errors.

[0091] Specifically, based on the third test result obtained by testing the first circuit 111 and the second circuit 121 , when it is determined that the third test result is correct, it is determined that the second circuit 121 is not faulty and the three-dimensional integrated chip 10 is not faulty.

[0092] Unlike existing technologies, the present invention's testing method for a three-dimensional integrated chip 10 utilizes a first test module 112 and a second test module 122 to test the first circuit 111, the second circuit 121, or the interconnect module 13 to obtain test results. The test results are then used to determine the cause of a failure in the three-dimensional integrated chip 10. By connecting and arranging the first circuit 111, the first test module 112, the second circuit 121, and the second test module 122, the three-dimensional integrated chip 10 is tested. This method can detect internal errors in a particular chip within the three-dimensional integrated chip 10, verify the integrity of connections between different chips, and verify that signal transmission between the chips maintains good signal integrity.

[0093] See also Figure 6 , Figure 6 FIG. 1 is a circuit diagram of a second embodiment of a three-dimensional integrated chip 10 of the present application. The three-dimensional integrated chip 10 of this embodiment includes a control chip 14 and a memory chip 15 interconnected with the control chip 14 .

[0094] Specifically, the control chip 14 in the three-dimensional integrated chip 10 includes a control circuit 141 and a first test module 142, the storage chip 15 includes a storage circuit 151 and a second test module 152, and the three-dimensional integrated chip 10 also includes an interconnection module 13, a first switch circuit 143, a second switch circuit 144, a third switch circuit 153 and a fourth switch circuit 154.

[0095] By controlling the conduction or disconnection of the first switch circuit 143, the second switch circuit 144, the third switch circuit 153 and the fourth switch circuit 154, the connection and deployment of the control circuit 141, the first test module 142, the storage circuit 151 and the second test module 152 can be completed, thereby detecting the control circuit 141, the storage circuit 151 and the interconnection module 13.

[0096] The three-dimensional integrated chip 10 of this embodiment includes a control chip 14 and a memory chip 15 interconnected with the control chip 14. With the three-dimensional integrated chip 10 of this application, the control circuit 141 controls the conduction and disconnection of the first switch circuit 143, the second switch circuit 144, the third switch circuit 153, and the fourth switch circuit 154 to complete the connection and coordination of the control circuit 141, the first test module 142, the memory circuit 151, and the second test module 152, thereby testing the three-dimensional integrated chip 10. Based on the test results, fault analysis of the three-dimensional integrated chip 10 can be performed to locate the fault.

[0097] See also Figure 7-8 , Figure 7 is a circuit diagram of the third embodiment of the three-dimensional integrated chip provided by this application, Figure 8 This is a circuit diagram of the fourth embodiment of the three-dimensional integrated chip provided by this application. Figure 7 As shown, the three-dimensional integrated chip 10 of this embodiment is a three-layer chip stacked in sequence, including a chip 31 , a chip 32 and a chip 33 .

[0098] Specifically, chip 31 in the three-dimensional integrated chip 10 is connected to an adjacent chip 32 via an interconnection module 13. Chips 31 and 32 can serve as the first chip 11 and the second chip 12 of the present application. Chip 32 is connected to an adjacent chip 33 via an interconnection module 13. Chips 32 and 33 can serve as the first chip 11 and the second chip 12 of the present application. Chip 31 is connected to a non-adjacent chip 33 via an interconnection module 13. Chips 31 and 33 can serve as the first chip 11 and the second chip 12 of the present application. The three-layer stacked chips formed by chips 31, 32, and 33 in the three-dimensional integrated chip 10 can use the test method provided in the present application. The chips can be control chips, storage chips, power chips, communication chips, audio processing chips, etc.

[0099] like Figure 8 As shown, the three-dimensional integrated chip 10 of this embodiment is a five-layer chip stacked in sequence, including a chip 41 , a chip 42 , a chip 43 , a chip 44 and a chip 45 .

[0100] Specifically, the chip 41 in the three-dimensional integrated chip 10 is connected to the adjacent chip 42 through the interconnection module 13, and the chip 41 and the chip 42 can be used as the first chip 11 and the second chip 12 of the present application; the chip 41 is connected to the non-adjacent chip 43 through the interconnection module 13, and the chip 41 and the chip 43 can be used as the first chip 11 and the second chip 12 of the present application; the chip 41 is connected to the non-adjacent chip 44 through the interconnection module 13, and the chip 41 and the chip 44 can be used as the first chip 11 and the second chip 12 of the present application; the chip 41 is connected to the non-adjacent chip 45 through the interconnection module 13, and the chip 41 and the chip 45 can be used as the first chip 11 and the second chip 12 of the present application; the chip 42 is connected to the adjacent chip 43 through the interconnection module 13, and the chip 42 and the chip 43 can be used as the first chip 11 and the second chip 12 of the present application. The second chip 12; the chip 42 is connected to the non-adjacent chip 44 through the interconnection module 13, and the chip 42 and the chip 44 can be used as the first chip 11 and the second chip 12 of the present application; the chip 42 is connected to the non-adjacent chip 45 through the interconnection module 13, and the chip 42 and the chip 45 can be used as the first chip 11 and the second chip 12 of the present application; the chip 43 is connected to the adjacent chip 44 through the interconnection module 13, and the chip 43 and the chip 44 can be used as the first chip 11 and the second chip 12 of the present application; the chip 43 is connected to the non-adjacent chip 45 through the interconnection module 13, and the chip 43 and the chip 45 can be used as the first chip 11 and the second chip 12 of the present application; the chip 44 is connected to the adjacent chip 45 through the interconnection module 13, and the chip 44 and the chip 45 can be used as the first chip 11 and the second chip 12 of the present application. The five-layer chips stacked in sequence formed by chip 41, chip 42, chip 43, chip 44 and chip 45 in the above-mentioned three-dimensional integrated chip 10 can use the testing method provided in this application. At the same time, the above-mentioned chips can be control chips and storage chips, and can also be power chips, communication chips and audio processing chips, etc.

[0101] It should be noted that the number of chips in the three-dimensional integrated chip 10 of the present application is not limited to 2, 3 or 5 as described in the above embodiments, and can be n chips, where n is an integer greater than or equal to 2.

[0102] The three-dimensional integrated chip 10 of the present application includes multiple layers of chips stacked in sequence, wherein two adjacent layers of chips in the multi-layer chip and connected by an interconnection module 13 serve as the first chip 11 and the second chip 12, or two non-adjacent layers of chips in the multi-layer chip and connected by an interconnection module 13 serve as the first chip 11 and the second chip 12. The method of the present application can be used to inspect the three-dimensional integrated chip 10 of the present application, as well as the three-dimensional integrated chip 10 formed by three-dimensional stacking technology, to detect whether an internal error exists in a chip in the three-dimensional integrated chip 10, and to test whether the connections between different chips are intact and whether the signal transmission between different chips can maintain good signal integrity.

[0103] See also Figure 9 , Figure 9 Schematic diagram of the structure of an embodiment of the detection device 20 provided by this application. Figure 9 As shown, the detection device 20 is used to implement the test method of the three-dimensional integrated chip 10 mentioned above.

[0104] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A three-dimensional integrated chip, characterized in that: include: at least one first chip; at least one second chip, wherein the second chip is connected to the first chip via an interconnection module; The first chip includes a first circuit and a first test module, and the first circuit is connected to the first test module; The second chip includes a second circuit and a second test module, and the second circuit is connected to the second test module; The test result obtained by connecting the first circuit with the first test module and the test result obtained by connecting the second circuit with the second test module represent the cause of the failure of the three-dimensional integrated chip; The first chip includes: a first switch circuit connecting the first circuit and the interconnection module; a second switch circuit connecting the first circuit and the first test module; The second chip includes: a third switch circuit, the third switch circuit connecting the second circuit and the interconnection module; a fourth switch circuit, the fourth switch circuit connecting the second test module and the interconnection module; By controlling the on or off of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit, the detection of the first circuit, the interconnection module, and the second circuit is completed.

2. The three-dimensional integrated chip according to claim 1, characterized in that: The interconnect modules each include through silicon vias or bonding pillars, and the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit each include a switch, a switching circuit, or a selection circuit.

3. A method for testing a three-dimensional integrated chip, characterized in that: The three-dimensional integrated chip is the three-dimensional integrated chip according to claim 1, and the method comprises: Detecting the first circuit or the second circuit or the interconnection module based on the first test module and the second test module to obtain a test result; A failure cause of the three-dimensional integrated chip is determined based on the test result.

4. The testing method according to claim 3, wherein: The step of detecting the first circuit or the second circuit or the interconnection module based on the first test module and the second test module to obtain the test result includes: controlling the second switch circuit to be turned on, detecting the first circuit and the first test module, and obtaining a first test result; The step of determining the cause of the failure of the three-dimensional integrated chip based on the test result includes: In response to the first test result being an error, the failure cause of the three-dimensional integrated chip is an error in the first circuit.

5. The testing method according to claim 4, characterized in that: In response to the first test result being correct, controlling the first switch circuit and the fourth switch circuit to be turned on, detecting the first circuit and the second test module, and obtaining a second test result; In response to the second test result being an error, the failure cause of the three-dimensional integrated chip is an error in the interconnection module.

6. The testing method according to any one of claims 3 to 5, characterized in that: The step of detecting the first circuit or the second circuit or the interconnection module based on the first test module and the second test module to obtain the test result further includes: controlling the fourth switch circuit to be turned on, detecting the first test module and the second test module, and obtaining the first test result; The step of determining the cause of the failure of the three-dimensional integrated chip based on the test result further includes: In response to the first test result being an error, the cause of the failure of the three-dimensional integrated chip is an error in the interconnection module; In response to the first test result being correct, controlling the second switch circuit to be turned on, detecting the first circuit and the first test module, and obtaining the second test result; In response to the second test result being an error, the failure cause of the three-dimensional integrated chip is an error in the first circuit.

7. The testing method according to any one of claims 3 to 5, characterized in that: The step of detecting the first circuit or the second circuit or the interconnection module based on the first test module and the second test module to obtain the test result further includes: controlling the fourth switch circuit to be turned on, detecting the first test module and the second test module, and obtaining the first test result; The step of determining the cause of the failure of the three-dimensional integrated chip based on the test result further includes: In response to the first test result being an error, the cause of the failure of the three-dimensional integrated chip is an error in the interconnection module; In response to the first test result being correct, controlling the first switch circuit and the fourth switch circuit to be turned on, detecting the first circuit and the second test module, and obtaining the second test result; In response to the second test result being an error, the failure cause of the three-dimensional integrated chip is an error in the first circuit.

8. The testing method according to claim 5, wherein: The method further comprises: In response to the second test result being correct, controlling the first switch circuit and the third switch circuit to be turned on, detecting the first circuit and the second circuit, and obtaining a third test result; In response to the third test result being an error, the failure cause of the three-dimensional integrated chip is an error in the second circuit; In response to the third test result being correct, the three-dimensional integrated chip has no errors.

9. A detection device, characterized in that: The detection device is applied to the test method of the three-dimensional integrated chip according to any one of claims 3 to 8, and is used to detect the three-dimensional integrated chip.

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