Output data delay control circuit and display device

Abstract

The output data delay control circuit and display device provided by the embodiment of the present application include a first output module, a phase detection module, a delay control module and a second output module. The delay control module can delay the raising of the control signal of the second output module, and the second control signal will start to be raised only when the first clock signal is at a low level. Therefore, the high level of the control signal of the second output module will not overlap with the high level phase of the first clock signal, so that the working timing of the output of the output data delay control circuit is restored to normal, and the display screen of the display panel will not show abnormal display.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an output data delay control circuit and a display device. Background Art

[0002] At present, for display panels with larger sizes or high refresh rates, the charging time of the display panel will be shortened. In addition, due to the influence of the wiring impedance of the fanout area at the far end of the source driver circuit, the far end of the source driver circuit will be insufficiently charged (the charging time at the far end is shorter than that at the near end), resulting in uneven display brightness. However, by using the output data delay control (ODDC) circuit, the far end can output first and the near end later, so that the charging of the far and near ends is consistent, thereby achieving consistency in the picture display.

[0003] However, the clock signal received by the output data delay control circuit may be attenuated and distorted due to factors such as parasitic parameters or circuit coupling in the circuit. During the following process, the output data delay control circuit may output an erroneous control clock signal due to signal sampling errors or the output data delay control circuit may output an erroneous control clock signal, thereby causing abnormal display images.

[0004] Therefore, how to avoid factors such as parasitic parameters or circuit coupling in the circuit causing the output data delay control circuit to output an erroneous control clock signal is a difficult problem that existing panel manufacturers need to work hard to overcome. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide an output data delay control circuit and a display device, which can solve the technical problem that the existing output data delay control circuit is easily affected by factors such as parasitic parameters or circuit coupling in the circuit and outputs an erroneous control clock signal.

[0006] The embodiment of the present application provides an output data delay control circuit, a first output module, a phase detection module, a delay control module and a second output module; wherein,

[0007] The first output module is electrically connected to the phase detection module, the delay control module and the second output module, and the first output module is used to output the first clock signal to the phase detection module, the delay control module and the second output module;

[0008] The phase detection module is electrically connected to the delay control module, and is used to detect the first clock signal, and output a first control signal to the delay control module when waveform attenuation of the first clock signal is detected;

[0009] The delay control module is electrically connected to the second output module, and the second output module is used to output a second control signal to the second output module under the control of the first clock signal; wherein, the second control signal is the delayed output of the first control signal, and when the second control signal is in a period of being pulled from a low level to a high level, the first clock signal is at a low level.

[0010] The output module is used to output a second clock signal under the control of the second control signal, and the second clock signal is a delayed output of the first clock signal.

[0011] In the output data delay control circuit described in the present application, the delay control module includes a waveform flipping unit and a delay control unit; wherein the waveform flipping unit is used to flip the first clock signal to generate a third clock signal, and output the third clock signal to the delay control unit, and the delay control unit is used to output the second control signal to the second output module under the control of the third clock signal.

[0012] In the output data delay control circuit described in the present application, the waveform flipping unit is a NOT gate, and the delay control unit is a D flip-flop.

[0013] In the output data delay control circuit described in the present application, the D trigger includes a CP input terminal, a D input terminal and a Q output terminal; wherein the CP input terminal is electrically connected to the waveform flip unit, and the CP input terminal is used to input the third clock signal, the D input terminal is electrically connected to the phase detection module, the D input terminal is used to input the first control signal, the Q output terminal is electrically connected to the second output module, and the Q output terminal is used to output the second control signal to the second output module.

[0014] In the output data delay control circuit described in the present application, the delay control module also includes a delay output unit, which is electrically connected to the waveform flipping unit and electrically connected to the delay control unit. The delay output unit is used to delay the third clock signal to generate a fourth clock signal, and output the fourth clock signal to the delay control unit.

[0015] In the output data delay control circuit described in the present application, when the third clock signal is at a high level, the delay output unit follows the third clock signal, and when the third clock signal is at a low level, the delay output unit delays the third clock signal.

[0016] In the output data delay control circuit described in the present application, within one cycle, the sum of the delay duration of the fourth clock signal and the duration of the second control signal being pulled from a low level to a high level is less than or equal to half the duration of the cycle.

[0017] In the output data delay control circuit described in the present application, the delay output unit is a monostable trigger.

[0018] In the output data delay control circuit described in the present application, the second output module includes a first input terminal, a second input terminal and an output terminal, the first input terminal is electrically connected to the first output module, the first input terminal is used to input the first clock signal, the second input terminal is electrically connected to the delay control module, the second input terminal is used to input the second control signal, and the output terminal is used to output the second clock signal.

[0019] An embodiment of the present application further provides a display device, comprising a display panel and the output data delay control circuit as described above, wherein the display panel is electrically connected to the output data delay control circuit.

[0020] In the output data delay control circuit and display device provided in the embodiment of the present application, a first output module, a phase detection module, a delay control module and a second output module are included. By setting the delay control module, the control signal of the second output module can be delayed and raised, and the second control signal will only start to be raised when the first clock signal is at a low level. Therefore, the high level of the control signal of the second output module will not overlap with the high level phase of the first clock signal, so that the working timing of the output of the output data delay control circuit is restored to normal, and then the display screen of the display panel will not show abnormal display phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 The figure is a circuit diagram of an output data delay control circuit in the prior art.

[0023] Figure 2 It is a timing diagram of the output data delay control circuit in the prior art when it is not disturbed.

[0024] Figure 3 This is a timing diagram of the output data delay control circuit in the prior art when it is disturbed.

[0025] Figure 4 A schematic structural diagram of a first implementation of an output data delay control circuit provided in an embodiment of the present application.

[0026] Figure 5 A schematic structural diagram of a second implementation of the output data delay control circuit provided in an embodiment of the present application.

[0027] Figure 6 A circuit diagram of a second implementation of the output data delay control circuit provided in an embodiment of the present application.

[0028] Figure 7 This is a timing diagram of a second implementation of the output data delay control circuit provided in an embodiment of the present application.

[0029] Figure 8 A schematic structural diagram of a third implementation manner of the output data delay control circuit provided in an embodiment of the present application.

[0030] Fig. 9 A circuit diagram of a third implementation of the output data delay control circuit provided in an embodiment of the present application.

[0031] Fig.10 This is a timing diagram of the third implementation of the output data delay control circuit provided in an embodiment of the present application.

[0032] Fig.11 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0034] See also Figure 1 , Figure 2 as well as Figure 3 , Figure 1 is a circuit diagram of an output data delay control circuit in the prior art, Figure 2 is a timing diagram of the output data delay control circuit of the prior art when it is not disturbed, Figure 3 FIG. 1 is a timing diagram of the output data delay control circuit of the prior art when it is disturbed. Figure 1 , Figure 2 as well as Figure 3As shown, the output data delay control circuit provided by the prior art includes a CDR module, a Lock Detect module and an ODDC CLK GEN module. Among them, the CDR module is used to output a CDR Clock signal to the Lock Detect module and the ODDC CLK GEN module. The Lock Detect module is used to output a P_Lock signal to the ODDC CLK GEN module. The ODDC CLK GEN module is used to output an ODDC Clock signal.

[0035] Specifically, Figure 2 As shown, when the output data delay control circuit of the prior art is not disturbed. The output data delay control circuit starts to work, and when the Lock Detect module detects the first falling edge of the CDR Clock signal, the P_Lock signal starts to rise until the P_Lock signal rises to a high potential, and the ODDC CLK GEN module outputs the ODDC Clock signal. Since the stage of the P_Lock signal rising is at the low level stage of the CDR Clock signal. Therefore, when the output data delay control circuit of the prior art is not disturbed, the output data delay control circuit can work normally.

[0036] Specifically, Figure 3 As shown, when the output data delay control circuit of the prior art is disturbed, the output data delay control circuit starts to work. Due to the influence of factors such as circuit parasitic parameters, the CDR Clock signal will appear as shown in FIG. Figure 3 The waveform shown is attenuated, and the level is high at this time, but the attenuation is large. At this time, although the CDR Clock signal has not reached its first falling edge, and the CDR Clock signal is still at a high potential, the Lock Detect module detects that the CDR Clock signal has been pulled down to a large extent, and will mistakenly believe that the CDR Clock signal has reached its first falling edge, and the P_Lock signal begins to rise until the P_Lock signal is pulled up to a high potential, and the ODDC CLK GEN module outputs the ODDC Clock signal. Therefore, when the output data delay control circuit of the prior art is disturbed, the P_Lock signal and the CDR Clock signal will overlap at a high level, thereby causing the ODDC Clock signal to be output in advance, that is, the output data delay control circuit works abnormally, which will cause the display screen of the display panel to be abnormal.

[0037] See also Figure 4 , Figure 4 This is a schematic diagram of the structure of the first implementation of the output data delay control circuit provided in the embodiment of the present application. Figure 1As shown, the output data delay control circuit 10 provided in the embodiment of the present application includes a first output module 101 , a phase detection module 102 , a delay control module 103 and a second output module 104 .

[0038] The first output module 101 is electrically connected to the phase detection module 102 , the delay control module 103 and the second output module 104 . The first output module 101 is used to output the first clock signal CDR Clock to the phase detection module 102 , the delay control module 103 and the second output module 104 .

[0039] The phase detection module 102 is electrically connected to the delay control module 103. The phase detection module 102 is used to detect the first clock signal CDR Clock, and output the first control signal P_Lock_M to the delay control module 103 when the waveform attenuation of the first clock signal CDR Clock is detected.

[0040] The delay control module 103 is electrically connected to the second output module 104. The delay control module 103 is used to output the second control signal P_Lock to the second output module 104 under the control of the first clock signal CDR Clock.

[0041] The output module 104 is used for outputting the second clock signal ODDCClock under the control of the second control signal P_Lock.

[0042] The second control signal P_Lock is the delayed output first control signal P_Lock_M, when the second control signal P_Lock is in the period from low level to high level, the first clock signal CDR Clock is low level. The second clock signal ODDC Clock is the delayed output first clock signal CDR Clock.

[0043] It should be noted that the output data delay control circuit 10 provided in the embodiment of the present application adds a delay control module 103, and the delay control module 103 is located between the phase detection module 102 and the second output module 104. The delay control module 103 is used to generate a second control signal P_Lock based on the first control signal P_Lock_M to control the output of the second output module 104. When the first clock signal CDR Clock has waveform attenuation due to factors such as circuit parasitic parameters: First, although the phase detection module 102 will pull up the first control signal P_Lock_M, the first control signal P_Lock_M and the first clock signal CDR Clock will overlap at a high level. However, the first control signal P_Lock_M is not a control signal directly used to control the second output module 104 to output the clock signal, and will not cause the second output module 104 to erroneously output an abnormal control signal, and will not affect the display effect of the display screen of the display panel; second, the second control signal P_Lock is the first control signal P_Lock_M output with a delay. The delay control module 103 can detect or flip the first clock signal CDR Clock, so that only when the first clock signal CDR Clock is at a low level, the second control signal P_Lock is pulled from a low level to a high level. The second control signal P_Lock is a control signal directly used to control the second output module 104 to output a clock signal, and there is no high-level overlap between the second control signal P_Lock and the first clock signal CDR Clock. Therefore, the second output module 104 will not erroneously output an abnormal control signal, and will not affect the display effect of the display screen of the display panel.

[0044] Please visit Figure 5 , Figure 5 A schematic diagram of the structure of a second implementation of the output data delay control circuit provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the delay control module 103 includes a waveform flipping unit 1031 and a delay control unit 1032 .

[0045] The waveform flipping unit 1031 is used for flipping the first clock signal CDR Clock to generate a third clock signal CDR Clock A, and outputting the third clock signal CDR Clock A to the delay control unit 1032 .

[0046] The delay control unit 1032 is used for outputting the second control signal P_Lock to the second output module 104 under the control of the third clock signal CDR Clock A.

[0047] It should be noted that the first clock signal CDR Clock is flipped by the waveform flip unit 1031 to generate the third clock signal CDR Clock A. The potential of the third clock signal CDR Clock A is kept in opposite phase to that of the first clock signal CDR Clock. Therefore, even if the first clock signal CDR Clock has a waveform attenuation phenomenon, the first clock signal CDR Clock is at a high level potential, and the third clock signal CDR Clock A is still at a low level potential, so that the delay control unit 1032 will not output the second control signal P_Lock to the second output module 104 at this time. Only when the first clock signal CDR Clock is at a low level potential and the third clock signal CDR Clock A is at a high level potential, the delay control unit 1032 will output the second control signal P_Lock to the second output module 104. Therefore, the second control signal P_Lock of the embodiment of the present application does not overlap with the first clock signal CDR Clock at a high level, so the second output module 104 will not erroneously output an abnormal control signal, and will not affect the display effect of the display screen of the display panel.

[0048] Please visit Figure 6 as well as Figure 7 , Figure 6 A circuit diagram of a second implementation of the output data delay control circuit provided in an embodiment of the present application, Figure 7 This is a timing diagram of a second implementation of the output data delay control circuit provided in an embodiment of the present application. Figure 6 as well as Figure 7 As shown, the waveform flip unit 1031 is a NOT gate, and the delay control unit 1032 is a D flip-flop.

[0049] The D flip-flop includes a CP input terminal 1032a, a D input terminal 1032b and a Q output terminal 1032c; wherein the CP input terminal 1032a is electrically connected to the waveform flip unit 1031, and the CP input terminal 1032a is used to input the third clock signal CDRClock A, the D input terminal 1032b is electrically connected to the phase detection module 102, the D input terminal 1032b is used to input the first control signal P_Lock_M, the Q output terminal 1032c is electrically connected to the second output module 104, and the Q output terminal 1032c is used to output the second control signal P_Lock to the second output module 104.

[0050] The second output module 104 includes a first input terminal 104a, a second input terminal 104b and an output terminal 104c. The first input terminal 104a is electrically connected to the first output module 101, and is used to input the first clock signal CDRClock. The second input terminal 104b is electrically connected to the delay control module 103, and is used to input the second control signal P_Lock. The output terminal 104c is used to output the second clock signal ODDC Clock.

[0051] Please visit Figure 8 , Figure 8 This is a structural diagram of a third implementation of the output data delay control circuit provided in an embodiment of the present application, such as Figure 8 As shown, the delay control module 103 also includes a delay output unit 1033, which is electrically connected to the waveform flip unit 1031 and electrically connected to the delay control unit 1032. The delay output unit 1033 is used to delay the third clock signal CDR Clock A to generate a fourth clock signal CDR Clock B, and output the fourth clock signal CDR Clock B to the delay control unit 1032.

[0052] When the third clock signal CDR Clock A is at a high level, the delay output unit 1033 performs a follow process on the third clock signal; when the third clock signal CDR Clock A is at a low level, the delay output unit 1033 performs a delay process on the third clock signal CDR Clock A.

[0053] It should be noted that, by setting the delay output unit 1033, the delay control unit 1032 can delay receiving the signal of the third clock signal CDR Clock A at a low level, thereby delaying the second control signal P_Lock from a low level to a high level.

[0054] Since the time for the second control signal P_Lock to rise from a low level to a high level in one cycle is much shorter than the time for the first clock signal CDR Clock to be at a low level, firstly, the delay control unit 1032 delaying the raising of the potential of the second control signal P_Lock will not affect the normal output of the second clock signal ODDC Clock by the second output module 104; secondly, it can avoid the delay control unit 1032 raising the potential of the second control signal P_Lock in advance when the third clock signal CDR Clock A alternates from a high level to a low level, resulting in the phenomenon that the second control signal P_Lock and the first clock signal CDR Clock overlap at a high level; by setting the delay output unit 1033, it can ensure that the second control signal P_Lock and the first clock signal CDR Clock do not overlap at a high level, so that the second output module 104 will not erroneously output an abnormal control signal, and will not affect the display effect of the display screen of the display panel.

[0055] In one cycle, the sum of the delay time of the fourth clock signal CDR Clock B and the time during which the second control signal P_Lock is pulled from a low level to a high level is less than or equal to half the time of the cycle.

[0056] It should be noted that, since the second output module 104 needs to output the second clock signal ODDC Clock before the first clock signal CDR Clock changes to a high level again at the latest, within one cycle, the sum of the delay of the fourth clock signal CDRClock B and the duration of the second control signal P_Lock being pulled from a low level to a high level is at most the duration of the first clock signal CDR Clock being at a low level, that is, the duration of half a cycle.

[0057] Please visit Fig. 9 as well as Fig. 9 , Fig. 9 A circuit diagram of a third implementation of the output data delay control circuit provided in an embodiment of the present application, Fig.10 This is a timing diagram of the third implementation of the output data delay control circuit provided in the embodiment of the present application. Fig. 9 as well as Fig.10 As shown, the delay output unit 1033 is a monostable trigger.

[0058] It should be noted that the delay output unit 1033 may also be other structures, as long as it satisfies the following conditions when the third clock signal CDR Clock A is at a high level, and the delay output unit 1033 performs delay processing on the third clock signal CDR Clock A when the third clock signal CDR Clock A is at a low level.

[0059] In the output data delay control circuit provided in the embodiment of the present application, a first output module, a phase detection module, a delay control module and a second output module are included. By setting the delay control module, the control signal of the second output module can be delayed and raised, and the second control signal will only start to be raised when the first clock signal is at a low level. Therefore, the high level of the control signal of the second output module will not overlap with the high level phase of the first clock signal, so that the working timing of the output of the output data delay control circuit is restored to normal, and then the display screen of the display panel will not show abnormal display.

[0060] Fig.11 The present invention also provides a display device 100, including a display panel 20 and the output data delay control circuit 10 as described above, wherein the display panel 20 is electrically connected to the output data delay control circuit 10. The output data delay control circuit 10 provided in the present invention can be specifically described in the above description of the output data delay control circuit 10, which will not be described in detail here.

[0061] In the display device provided in the embodiment of the present application, a first output module, a phase detection module, a delay control module and a second output module are included. By setting the delay control module, the control signal of the second output module can be delayed to be pulled up, and the second control signal will be pulled up only when the first clock signal is at a low level. Therefore, the high level of the control signal of the second output module will not overlap with the high level phase of the first clock signal, so that the working timing of the output of the output data delay control circuit is restored to normal, and then the display screen of the display panel will not show abnormal display.

[0062] The above is a detailed introduction to an output data delay control circuit and a display device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An output data delay control circuit, characterized in that: It includes a first output module, a phase detection module, a delay control module and a second output module; wherein, The first output module is electrically connected to the phase detection module, the delay control module and the second output module, and the first output module is used to output the first clock signal to the phase detection module, the delay control module and the second output module; The phase detection module is electrically connected to the delay control module, and is used to detect the first clock signal, and output a first control signal to the delay control module when waveform attenuation of the first clock signal is detected; The delay control module is electrically connected to the second output module, and is used to output a second control signal to the second output module under the control of the first clock signal; wherein the second control signal is the first control signal output with delay, and when the second control signal is in the stage of being pulled from a low level to a high level, the first clock signal is at a low level; The second output module is used to output a second clock signal under the control of the second control signal, and the second clock signal is a delayed output of the first clock signal.

2. The output data delay control circuit according to claim 1, characterized in that: The delay control module includes a waveform flipping unit and a delay control unit; wherein the waveform flipping unit is used to flip the first clock signal to generate a third clock signal, and output the third clock signal to the delay control unit, and the delay control unit is used to output the second control signal to the second output module under the control of the third clock signal.

3. The output data delay control circuit according to claim 2, characterized in that: The waveform flip unit is a NOT gate, and the delay control unit is a D flip-flop.

4. The output data delay control circuit according to claim 3, characterized in that: The D flip-flop includes a CP input terminal, a D input terminal and a Q output terminal; wherein the CP input terminal is electrically connected to the waveform flip unit, and the CP input terminal is used to input the third clock signal, the D input terminal is electrically connected to the phase detection module, the D input terminal is used to input the first control signal, the Q output terminal is electrically connected to the second output module, and the Q output terminal is used to output the second control signal to the second output module.

5. The output data delay control circuit according to claim 2, characterized in that: The delay control module also includes a delay output unit, which is electrically connected to the waveform flip unit and to the delay control unit. The delay output unit is used to delay the third clock signal to generate a fourth clock signal and output the fourth clock signal to the delay control unit.

6. The output data delay control circuit according to claim 5, characterized in that: When the third clock signal is at a high level, the delay output unit performs a follow process on the third clock signal, and when the third clock signal is at a low level, the delay output unit performs a delay process on the third clock signal.

7. The output data delay control circuit according to claim 6, characterized in that: In one cycle, the sum of the delay duration of the fourth clock signal and the duration of the second control signal rising from a low level to a high level is less than or equal to half the duration of the cycle.

8. The output data delay control circuit according to claim 5, characterized in that: The delay output unit is a monostable trigger.

9. The output data delay control circuit according to claim 1, characterized in that: The second output module includes a first input end, a second input end and an output end, the first input end is electrically connected to the first output module, the first input end is used to input the first clock signal, the second input end is electrically connected to the delay control module, the second input end is used to input the second control signal, and the output end is used to output the second clock signal.

10. A display device, characterized in that: The display device comprises a display panel and the output data delay control circuit according to any one of claims 1 to 9, and the display panel is electrically connected to the output data delay control circuit.

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