Sub word line driver

Abstract

The present application relates to sub-wordline drivers. A memory array may include multiple sub-arrays arranged with gaps between the multiple sub-arrays. A wordline may be arranged across the multiple sub-arrays and drive access transistors for selectively accessing rows (e.g., rows of memory cells) within the sub-arrays. In some examples, signals applied to a selection device driving the wordline may be overdriven for a duration at or near a desired transition of the wordline, and some signals may be driven to a relatively high level for a duration around high and low transitions of a global row line. Whether a signal is overdriven or driven to a relatively high level may depend on the type of transistors used in each wordline driver.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 170,743, filed by Kim et al. on February 8, 2021, entitled “SUB WORD LINE DRIVER,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to sub-word line drivers. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to different states. For example, a binary memory cell can be programmed to one of two supported states, usually indicated by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state in the memory device.

[0005] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), optional memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Non-volatile memory such as FeRAM can maintain its stored logic state for a long time even in the absence of external power. Volatile memory devices such as DRAM may lose their stored state when disconnected from the external power supply. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a memory cell array arranged in a plurality of sub-arrays each including a plurality of memory cells; a first selection device of a first type located on a first side of a first sub-array of the plurality of sub-arrays, wherein the first selection device is configured to couple the first access line with a second access line based at least in part on a third access line, the second access line accessing a subset of the memory cell array for an access operation after transitioning from a first level to a second level higher than the first level; a second selection device of a second type located on a second side of the first sub-array of the plurality of sub-arrays, wherein the second selection device is configured to couple the first access line with a second access line based at least in part on a third access line, the second access line accessing a subset of the memory cell array for an access operation after transitioning from a first level to a second level higher than the first level; a fourth access line and coupling the first access line with the second access line; and a controller coupled to the first selection device and the second selection device, the controller being configured to: drive the third access line to the first level and the fourth access line to a third level at a first time, wherein the third level is higher than the second level; drive the first access line to the second level at a second time; drive the fourth access line to the second level at a third time; and drive the fourth access line to the third level at a fourth time, the fourth time occurring after the third time and when the first access line is at the second level.

[0007] An apparatus is described. The apparatus may include: a memory cell array arranged in a plurality of sub-arrays each including a plurality of memory cells; a first selection device of a first type located on a first side of a first sub-array of the plurality of sub-arrays, wherein the first selection device is configured to couple the first access line with a second access line based at least in part on a third access line, the second access line accessing a subset of the memory cell array for an access operation after transitioning from a first level to a second level higher than the first level; a second selection device of the first type located on a second side of the first sub-array of the plurality of sub-arrays, wherein the second selection device is configured to couple the first access line with the second access line based at least in part on the third access line; and a controller coupled to the first selection device and the second selection device, the controller being configured to: drive the third access line to a third level at a first time, wherein the third level is lower than the first level and the second level; and drive the first access line to the second level at a second time after the first time.

[0008] A method is described. The method may include: driving a third access line and a fourth access line to complementary levels at a first time and while the first access line is at a first level, wherein at least one of the complementary levels is different from the first level and a second level associated with a second access line, the second access line providing access to a subset of an array of memory cells, and wherein the first access line is coupled to the second access line via a first selection device of a first type and a second selection device of a second type based at least in part on driving at least one of the third access line and the fourth access line to the complementary level; driving the first access line to the second level at a second time; driving the third access line to the second level and the fourth access line to the first level at a third time based at least in part on driving the first access line to the second level; and driving the third access line and the fourth access line to the complementary levels at a fourth time and while the first access line is at the second level. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting a sub-wordline driver according to examples as disclosed herein is described.

[0010] Figure 2 An example of a memory die supporting sub-word line drivers according to examples as disclosed herein is illustrated.

[0011] Figure 3A and 3B Examples of circuit diagrams and corresponding timing diagrams supporting sub-wordline drivers according to examples as disclosed herein are illustrated.

[0012] Figure 4A and 4B Examples of circuit diagrams and corresponding timing diagrams supporting sub-wordline drivers according to examples as disclosed herein are illustrated.

[0013] Figure 5A and 5B Examples of circuit diagrams and corresponding timing diagrams supporting sub-wordline drivers according to examples as disclosed herein are illustrated.

[0014] Fig. 6A and 6B Examples of circuit diagrams and corresponding timing diagrams supporting sub-wordline drivers according to examples as disclosed herein are illustrated.

[0015] Figure 7 A block diagram of a memory device supporting sub-word line drivers according to examples as disclosed herein is shown.

[0016] Figure 8A flow chart illustrating one or more methods of supporting a sub-wordline driver according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0017] A memory array may be arranged in subarrays, with word lines passing through multiple subarrays, and additional row line drivers (e.g., word line select devices) may be fabricated within the spacing (e.g., gaps) between subarrays to provide additional drive to the word lines. A typical driver may have multiple transistors of different types in the gaps, and reducing the size of the spacing between subarrays may be beneficial. To access the memory cells of a subarray, a two-step decoding may be used to decode the memory address into a word line. A global row line common to a group of word lines may be decoded, while a phase signal may be used to activate individual word lines within the group with the activated global row line. The phase signal may be asserted before activating the global row line, thus coupling the global row line to one of the local row lines. When the global row line is asserted, it will drive the selected row line. Conventional drive mechanisms for select transistors to couple global word lines to local word lines may not drive the select transistor to a level that provides a sufficiently strong drive for the desired slew rate of the word line, or may overdrive the select transistor and cause possible transistor breakdown. Therefore, a solution is needed to provide sufficient drive to the select transistor while preventing transistor breakdown.

[0018] A memory architecture is described herein that provides adequate drive for select transistors while preventing transistor breakdown. Specifically, a single transistor driver may be fabricated in the gaps between memory subarrays. Certain signals (e.g., phase signals) may be overdriven for a duration at or near a desired transition of a word line (e.g., transition from a high voltage to a low voltage or from a low voltage to a high voltage). In some cases, n-channel (e.g., NMOS) transistors may be used in the gaps, and the phase signal may be driven to a higher level (e.g., a higher threshold voltage or greater than a higher threshold voltage) for a duration around the high and low transitions of a global row line. In other cases, p-channel (e.g., PMOS) transistors may be used in the gaps so that the inverted (PHF) signal drops below ground for a duration around the high and low transitions of a global row line. A hybrid driver may use both n-channel and p-channel transistors in the same or alternating gaps, and one or both types of select transistors may be overdriven for a duration around the high and low transitions of a global row line. In either of the configurations, the driver can drive the select transistors in each gap to a level that provides sufficiently strong drive for the desired slew rate of the corresponding word line, while preventing overdrive that might otherwise cause the select transistors to break down over time.

[0019] First, in the reference Figure 1 and 2 Features of the present disclosure are described in the context of the described systems and dies. Figures 3A to 6B The features of the present disclosure are described in the context of the discussed circuit diagrams and corresponding timing diagrams. These and other features of the present disclosure are further illustrated by reference to Figure 7 and 8 The described sub-word line driver is illustrated and described with reference to the device diagram and flow chart.

[0020] Figure 1 An example of a system 100 supporting a sub-word line driver according to examples as disclosed herein is illustrated. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0021] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a notebook computer, a tablet computer, a smart phone, a cellular phone, a wearable device, a networked device, a vehicle controller, etc. Memory device 110 may be a component of the system that may be used to store data for one or more other components of system 100.

[0022] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes within, for example, a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a notebook computer, a tablet computer, a smart phone, a cellular phone, a wearable device, a networked device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0023] Memory device 110 may be a separate device or component that may be used to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: a modulation scheme used to modulate a signal, various pin configurations used to communicate a signal, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0024] Memory device 110 may be used to store data for components of host device 105. In some examples, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0025] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of host device 105 may be coupled to each other using a bus 135.

[0026] Processor 125 may be used to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 may be implemented by or be part of processor 125.

[0027] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of a read-only memory (ROM), flash memory, or other non-volatile memory.

[0028] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more sectors), where each memory cell can be used to store at least one bit of data. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0029] The memory die 160 may be an example of a two-dimensional (2D) memory cell array, or may be an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may include a single memory array 170. A 3D memory die 160 may include two or more memory arrays 170, which may be stacked on top of each other or positioned proximate to each other (e.g., relative to a substrate). In some examples, the memory arrays 170 in a 3D memory die 160 may be referred to as stacks, tiers, layers, or dies. The 3D memory die 160 may include any number of stacked memory arrays 170 (e.g., two high stacked memory arrays, three high stacked memory arrays, four high stacked memory arrays, five high stacked memory arrays, six high stacked memory arrays, seven high stacked memory arrays, eight high stacked memory arrays). In some 3D memory dies 160, different stacks may share at least one common access line, such that some stacks may share one or more of a word line, a digit line, or a plate line.

[0030] The device memory controller 155 may include circuitry, logic, or components that may be used to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0031] A local memory controller 165 (e.g., local to the memory die 160) may include circuitry, logic, or components that may be used to control the operation of the memory die 160. In some examples, the local memory controller 165 may be used to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands or both). In some examples, the memory device 110 may not include a device memory controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers that may be used to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0032] The external memory controller 120 may be used to enable one or more of communicating information, data, or commands between a component of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between a component of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or its functions described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or its functions described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0033] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium that carries information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path that may be used to carry a signal. For example, channel 115 may include a first terminal that includes one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be used to serve as part of a channel.

[0034] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling may be conveyed via channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both a rising and falling edge of a clock signal).

[0035] In some examples, memory device 110 may receive a command (e.g., an access command) from host device 105. The address of the command may be decoded as described herein. For example, device memory controller 155 or local memory controller 165 may decode the address associated with the command and may activate one or more drivers and / or apply one or more signals to corresponding signal lines associated with memory array 170.

[0036] For example, the memory array 170-a may include multiple sub-arrays, and may include various word line drivers to drive selected word lines. Each sub-array may be associated with a set of word lines that extend across the entire memory array 170, as well as global row lines. In addition, the memory array 170 may include one or more phase lines (e.g., and inverting or phase reversal lines). The device memory controller 155 or the local memory controller 165-a may apply various signals to the global row lines, phase lines, and phase reversal lines, as described herein, to facilitate access operations. The driver associated with each sub-array may drive the select transistors in each gap (e.g., each gap between each sub-array) to a level that provides sufficiently strong drive for the desired slew rate of the selected word line, while preventing overdrive that might otherwise cause the select transistors to break down over time.

[0037] Figure 2 An example of a memory die 200 supporting a sub-word line driver according to an example as disclosed herein is illustrated. The memory die 200 may be a reference Figure 1 An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmable to store a different logical state (e.g., programmed to one of a set of two or more possible states). For example, the memory cell 205 may be used to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell) may be used to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). In some examples, the memory cells 205 may be arranged in an array, as described with reference to FIG. Figure 1 Memory array 170 is depicted.

[0038] Memory cell 205 may store a charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor that includes a dielectric material to store a charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be used. Memory cell 205 may include a logic storage component, such as capacitor 230 and a switch component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. The node of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage, such as Vpl, or may be grounded, such as Vss.

[0039] Memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digit lines 215) arranged in a pattern such as a grid-like pattern. Access lines may be conductive lines coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some examples, word lines 210 may be referred to as row lines. In some examples, digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, etc. may be interchanged without affecting understanding or operation. Memory cells 205 may be positioned at the intersection of word lines 210 and digit lines 215.

[0040] Operations such as reading and writing can be performed on the memory cell 205 by activating or selecting an access line, such as one or more of the word line 210 or the digit line 215. By biasing the word line 210 and the digit line 215 (e.g., applying a voltage to the word line 210 or the digit line 215), a single memory cell 205 can be accessed at its intersection. The intersection of the word line 210 and the digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of the memory cell 205.

[0041] Access to the memory cells 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word lines 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and may activate the digit lines 215 based on the received column address. In some examples, the row decoder 220 and / or the column decoder 225 may decode an access command, which may cause various signals to be applied to access lines (e.g., to a global row line, a phase line, a phase reversal line, etc.) to facilitate the access operation.

[0042] Selecting or deselecting the memory cell 205 may be achieved by activating or deactivating the switch component 235 using the word line 210. The capacitor 230 may be coupled to the digit line 215 using the switch component 235. For example, when the switch component 235 is deactivated, the capacitor 230 may be isolated from the digit line 215, and when the switch component 235 is activated, the capacitor 230 may be coupled to the digit line 215.

[0043] The sensing component 245 may be used to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. The sensing component 245 may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell 205. The sensing component 245 may compare the signal detected from the memory cell 205 to a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sensing component 245 (e.g., to an input / output 255), and the detected logic state may be indicated to another component of the memory device including the memory die 200.

[0044] The local memory controller 260 may control access to the memory cell 205 through various components (eg, the row decoder 220, the column decoder 225, the sensing component 245). The local memory controller 260 may be a reference Figure 1 1. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 245 can be collocated with the local memory controller 260. The local memory controller 260 can be used to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the command or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate the target word line 210 and the target digital line 215. The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein may vary and may be different for the various operations discussed in operating the memory die 200 .

[0045] The local memory controller 260 may be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 may be used to perform other access operations not listed here or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0046] In some examples, local memory controller 260 may receive data from a host device (eg, as described in reference Figure 1 The host device 105 described receives a command (e.g., an access command). The address of the command can be decoded by the column decoder 225 and the row decoder 220. The address associated with the command is decoded and may cause one or more drivers to be activated and / or one or more signals to be applied to corresponding signal lines associated with the memory array die 200.

[0047] For example, the memory array die 200 may be an instance of one of a plurality of sub-arrays of a memory array, and may include various word line drivers to drive a selected word line. The sub-array may be associated with a set of word lines 210 extending across the entire memory array, as well as global row lines (not shown). In addition, the memory array may include one or more phase lines and phase reversal lines (not shown). The local memory controller 260 may apply various signals to the global row lines, phase lines, and phase reversal lines, as described herein, to facilitate access operations. The driver associated with each sub-array may drive the select transistors in each gap (e.g., each gap between each sub-array) to a level that provides a sufficiently strong drive for the desired slew rate of the selected word line, while preventing overdrive that might otherwise cause the select transistors to break down over time.

[0048] Figure 3A An example of a circuit diagram 300-a supporting a sub-wordline driver according to an example as disclosed herein is illustrated. The circuit diagram 300-a may illustrate an example of one or more drivers (or one or more aspects of one or more drivers) that may be used to drive a particular wordline (e.g., wordline 330-a or wordline 330-b). The circuit diagram 300-a may illustrate an array of memory cells arranged in a plurality of sub-arrays 305. One or more wordlines 330 may pass through the sub-arrays, and additional drivers may be located in the gap between each sub-array 305. For example, a main gap 350 (e.g., a main sub-wordline driver (SWD) gap) may include a first driver for driving wordline 330-a using a global wordline (GR) 325, a phase line (PH) 340-a, and a phase reversal line (PHF) 335-a. In some examples, the main gap 350 may also include additional wordline drivers for driving other wordlines. Additionally or alternatively, the gaps following the main gap (e.g., each SWD gap) may include a single transistor driver, which may reduce the spacing between each subarray 305, or may reduce the spacing between different types of transistors, since no additional transistor wells are required. Furthermore, the driver may drive the select transistors in each gap to a level that provides sufficiently strong drive for the desired slew rate of the corresponding word line, while preventing overdrive that might otherwise cause the select transistors to break down over time.

[0049] As described in this article, Figure 3A , may be located on a first side of the first sub-array 305. The main SWD gap 350 may include a first selection device 310-a of a first type (e.g., a first transistor). In some examples, the first selection device 310-a may be a p-type (e.g., PMOS) transistor. A source of the first selection device 310-a may be coupled to a first access line 325, and a drain of the first selection device 310-a may be coupled to a second access line 330-a. The first access line 325 may be a global row line, and the second access line 330-a may be a word line. In some examples, the first selection device 310-a may couple the global row line 325 with the word line 330-a based on a third access line 335-a. For example, the third access line 335-a may be a phase reversal line 335-a coupled to a gate of the first selection device 310-a. Thus, the first selection device 310-a can couple the global row line 325 with the word line 330-a based on a low (relatively low or negative) voltage (e.g., VNWL) applied to the phase reversal line 335-a. For example, the voltage (e.g., VNWL) can be the N-well voltage of the memory array, and can be ground or can be a voltage other than ground (e.g., a negative voltage).

[0050] In some examples, the main SWD gap 350 may include an additional selection device 315-a of the second type. In some examples, the selection device 315-a may be an n-type (e.g., NMOS) transistor. The source of the selection device 315-a may be coupled to a voltage source (e.g., VNWL), and the drain of the selection device 315-a may be coupled to the word line 330-a. In some examples, the selection device 315-a may couple the word line 330-a to the voltage source (e.g., VNWL) based on a relatively high (e.g., high relative to VNWL) voltage applied to the phase reversal line 335-a.

[0051] Additionally or alternatively, main SWD gap 350 may include one or more select devices associated with additional word lines 330. In some examples, a first select device 310-b (e.g., similar to select device 310-a but with a drain coupled to word line 330-b) may be configured to couple global row line 325 with word line 330-b based on a signal applied to an additional phase inversion line. The word line drivers in main SWD gap 350 (which includes select device 310-a and select device 315-a) may be repeated for word line 330-b and for each additional word line extending across the memory array. For example, SWD gap 355 may include select device 320-b configured to couple global row line 325 with word line 330-b, and SWD gap 360 may include select device 320-d to couple global row line 325 with word line 330-b.

[0052] The additional word line drivers may be driven by the additional phase reversal line 340-b. In some examples, the SWD gap may include additional select devices configured to couple additional word lines with the global row line 325 and may be driven by the additional phase lines. For example, the additional word line drivers may be driven by additional phase lines such as PH0, PH1 and additional phase reversal lines such as PHF0, PHF1. Furthermore, a second select device (e.g., similar to select device 315-a but with a drain coupled to word line 330-b) may be coupled to a voltage source (e.g., VNWL) and may be configured to couple word line 330-b to the voltage source based on a high (e.g., high relative to VNWL) voltage applied to the additional phase reversal line.

[0053] The circuit diagram 300-a may illustrate additional gaps (e.g., SWD gaps) located between each of the sub-arrays 305. For example, the first SWD gap 355 may be located on the second side of the first sub-array 305 (and on the first side of the second sub-array 305-a). Because each word line 330 extending through the memory array may have a significant capacitance and resistance, a local word line driver may be fabricated in each SWD gap (e.g., each SWD gap such as the first SWD gap 355, the second SWD gap 360, etc.). In some examples, the local word line drivers in each gap may be configured to drive a subset of the total number of word lines 330. For example, in some SWD gaps (e.g., the "even" SWD gaps), the local drivers may be configured to drive the even word lines 330 (e.g., the second word line 330, the fourth word line 330, etc.). In other examples, in some SWD gaps (e.g., “odd” SWD gaps), the local drivers may be configured to drive odd word lines 330 (e.g., first word line 330, third word line 330, etc.). In this configuration, the main SWD gap may be configured to drive even word lines 330, and the circuit diagram 300-a may include a second main SWD gap 365 located at an opposite end of the array, the second main SWD gap including a select device 310-b and a select device 315-b coupled to a phase reversal line 335-b and configured to drive odd word lines 330, such as word lines 330-b.

[0054] like Figure 3A, the local word line driver located in the first SWD gap 355 can include a second selection device 320-a of a second type (e.g., a second transistor). As described herein, the second selection device of the second type can be an NMOS transistor. The local word line driver including the second selection device can receive substantially the same signal used to control the driver in the main SWD gap 350. However, the presence of the driver in the first SWD gap 355 (and subsequent SWD gaps) can provide a sufficiently strong drive for the desired slew rate of the corresponding word line while preventing overdrive that might otherwise cause the select transistor to break down over time.

[0055] In some examples, the second selection device 320-a may be an n-type (e.g., NMOS) transistor. The source of the second selection device 320-a may be coupled to the word line 330-a, and the drain of the second selection device 320-a may be coupled to the global row line 325. In some examples, the second selection device 320-a may couple the global row line 325 to the word line 330-a based on the fourth access line 340-a. For example, the fourth access line 340-a may be a phase line 340-a coupled to the gate of the second selection device 320-a. Therefore, the second selection device 320-a may couple the global row line 325 to the word line 330-a based on a high (e.g., high relative to VNWL) voltage applied to the phase line 340-a. In some examples, phase line 340-a and phase line 340-b (and any additional phase lines not shown in FIG. 3 ) may extend vertically through the SWD gap in the memory array, and may therefore not extend across the array (e.g., in the direction of the word lines). By extending the phase lines vertically through the SWD gap, the area available for word lines and global row lines may be increased.

[0056] The first SWD gap 355 may include a plurality of additional transistors configured to couple a respective local word line to the global row line 325. The select device 320-b may be configured to couple the word line 330-b to the global row line 325 based on a relatively high (e.g., high relative to VNWL) voltage applied to the second phase line 340-b. Thus, each SWD gap may include a plurality of transistors each associated with a respective word line and configured to couple the respective word line with the global row line 325. For example, each gap may include N transistors coupled to N phase lines and each associated with a respective word line. In this example, N may be a positive integer corresponding to the number of word lines corresponding to a single global row line (e.g., global row line 325) extending through the memory array. Alternatively, as discussed above, each gap may include N / K transistors coupled with N / K of the N phase lines, where K is an integer less than N (e.g., even gaps may have transistors for even word lines and odd gaps may have transistors for odd word lines).

[0057] In some examples, the global row line 325 may be common to a set of word lines including the word line 330-a and the word line 330-b. As described herein, a two-step decoding may be used to decode a memory address into a word line, and the global word line may be associated with the timing of an access operation. For example, a signal may be asserted to the phase line 340-a (e.g., asserted to the gate of the select device 320-a) to couple the global row line 325 to the word line 330-a before driving the global row line 325 (e.g., to VCCP). Thus, when the global row line 325 is driven to VCCP, the selected word line 330-a is also driven to the same voltage (e.g., to VCCP). In some examples, the VCCP, which may be referred to herein as the second level, may correspond to a desired voltage for the word line 330-a to drive the select transistor of the memory cell to access the memory cell (e.g., to read or write the memory cell from a bit line).

[0058] The circuit diagram 300-a may illustrate an additional SWD gap located between each of the sub-arrays 305. For example, the circuit diagram 300-a may illustrate a second SWD gap 360 including a select device 320-c and a select device 320-d. Each SWD gap may include an additional transistor coupled with a respective word line and a phase line. For example, each SWD gap may include one transistor to drive each word line from a global row line 325, and the gate of each additional transistor may be coupled with a respective phase line of a set of phase lines (e.g., PH0, PH1, PH2, etc.). Each select device may couple the global row line 325 with a respective word line based on the respective phase line being driven to a relatively high voltage (e.g., VCCP or VCCP2). As discussed herein, the presence of a driver in each SWD gap may provide sufficiently strong drive for the desired slew rate of the corresponding word line while preventing overdrive that might otherwise cause the select transistor to break down over time. The size of SWD gaps 355 and 360 may be determined by the area of ​​select device 320, and therefore, reducing the size or number of devices within the gaps may reduce the size of the gaps and ultimately the size of the memory devices.

[0059] Figure 3B An example of a timing diagram 300-b for supporting a sub-word line driver according to an example as disclosed herein is illustrated. The timing diagram 300-b may be similar to the timing diagram 300-b of FIG. Figure 3A The timing diagram 300-b may be used to describe the operation of the circuit diagram 300-a. Figure 3AThe timing of the signals of the global row line 325, the phase reversal line 335-a, the phase line 340-a, and the word line 330-a are described. For example, the signal 326 may be applied to the global row line 325, the signal 336 may be applied to the phase reversal line 335-a, the signal 341 may be applied to the phase line 340-a, and the signal 331 may be applied to the word line 330-a. The signals applied to each of the lines may activate or deactivate a particular select transistor to a level that provides a sufficiently strong drive for the desired slew rate of the word line 330-a, while preventing overdrive that might otherwise cause the select transistor to break down over time.

[0060] At t0, the first access line 325 (e.g., global row line 325), the second access line 330-a (e.g., word line 330-a), and the fourth access line 340-a (e.g., phase line 340-a) can each be maintained at a first level (e.g., VNWL). In some examples, VNWL can be a relatively low (ground or negative) voltage level. At t0, the third access line 335-a (e.g., phase reversal line 335-a) can be maintained at a second level (e.g., VCCP). In some examples, the third access line 335-a can be driven (e.g., actively driven) to a second level, and the second level can be a level higher than the first level (e.g., VCCP can be higher than VNWL). When the phase reversal line 335-a is maintained at the second level (or driven to the second level), the selection device 315-a can be activated, thereby coupling the word line 330-a with the source (e.g., VNWL) of the selection device 315-a. Additionally or alternatively, when the phase reversal line 335-a is maintained at the second level (or driven to the second level) and the phase line 340-a is maintained at the first level, the selection device 310-a and the selection device 320-a can each be deactivated. Therefore, at t0, the global row line 325 may not be coupled to the word line 330-a.

[0061] At t1, the phase reversal line 335-a may transition to a first level (e.g., to VNWL). In some instances, the phase reversal line 335-a may be driven (e.g., actively driven) to VNWL. Additionally or alternatively, the phase line 340-a may transition to a third level (e.g., VCCP2), which may be higher than the second level (e.g., VCCP2 may be higher than VCCP). In some instances, the phase line 340-a may be driven (e.g., actively driven) to VCCP2. At t1, the global row line 325 may be maintained at a first level (e.g., at VNWL). As described herein, the global row line 325 may be driven (e.g., actively driven) to a first level. At t1, the word line 330-a may remain at a first level (e.g., at VNWL). When the phase inversion line 335-a is driven to the first level, the selection device 315-a may be deactivated and the selection device 310-a may be activated, thereby coupling the global row line 325 with the word line 330-a. In addition, when the phase line 340-a is driven to the third level, the selection devices 320-a, 320-c, and 320-d may be activated, thereby coupling the global row line 325 with the word line 330-a.

[0062] At t2, the global row line 325 may be driven to a second level (e.g., to VCCP), and the phase reversal line 335-a and the phase line 340-a may be maintained at the same level. Because the global row line 325 may be coupled to the word line 330-a (e.g., based on the signaling at t1), the word line 330-a may begin to transition to the second level (e.g., to VCCP). Therefore, the word line 330-a may reach VCCP for a duration after t2 (and before t3).

[0063] At t3, the phase line 340-a may be driven to a second level (e.g., to VCCP), and the global row line 325, the word line 330-a, and the phase reversal line 335-a may be maintained at the same level. The second level (e.g., VCCP) may be a threshold voltage of the selection device 320-a, which is lower than the third level (e.g., VCCP2). Therefore, driving the phase line 340-a to the second level may not deactivate the selection devices 320-a, 320-c, and 320-d. Alternatively, the selection devices may remain activated and the word line 330-a may be maintained at the second level (e.g., at VCCP). For example, driving the gates of the selection devices 320-a, 320-c, and 320-d to VCCP2 may ensure that the entire transition of the word line 330-a occurs without the selection devices being at a cutoff value or subthreshold, and thus may be actively driven using the selection devices 320-a, 320-c, and 320-d. If VCCP is used for the gates of select devices 320-a, 320-c, and 320-d during the transition of word line 330-a, then select devices 320-a, 320-c, and 320-d can provide good drive strength for word line 330-a until word line 330-a reaches a threshold below VCCP. At this point (e.g., when word line 330-a reaches a threshold below VCCP), select devices 320-a, 320-c, and 320-d can begin to operate in a subthreshold or cutoff value region, where the strength of the select devices is much lower. Therefore, word line 330-a will be effectively driven to VCCP by select device 310-a from a threshold below VCCP. Once word line 330-a reaches VCCP, reducing the gate voltage on select device 320-a can also effectively put the select device at a subthreshold or cutoff value. However, because word line 330-a is already driven (e.g., to VCCP), less drive is required to maintain word line 330-a at VCCP, thereby mitigating any effects of word line 330-a being driven only by select device 310-a. Driving phase line 340-a to VCCP during times when the global row line is asserted rather than transitioning prevents overdrive on select devices 320-a, 320-c, and 320-d that would otherwise cause select devices 320-a, 320-c, and 320-d to break down over time.

[0064] At t4, the phase line 340-a may be driven to a third level (e.g., to VCCP2), and the global row line 325, the word line 330-a, and the phase reversal line 335-a may be maintained at the same level. Driving the phase line 340-a to VCCP 2 may provide additional drive when the global row line 325 transitions from VCCP to a threshold below VCCP. In some examples, the phase line 340-a may not be driven to the third level within the second time, but may be driven to the second level (e.g., VCCP) for an extended duration (e.g., until t6).

[0065] At t5, the global row line 325 may be driven to the first level (e.g., to VNWL), and the phase reversal line 335-a and the phase line 340-a may be maintained at the same level. Because the global row line 325 may be coupled to the word line 330-a (e.g., based on the signaling at t1), the word line 330-a may begin to transition downward to the first level (e.g., to VNWL). Therefore, for a duration after t5 (and before t6), the word line 330-a may reach VNWL.

[0066] At t6, the phase reversal line 335-a may transition to a second level (e.g., to VCCP). In some instances, the phase reversal line 335-a may be driven (e.g., actively driven) to VCCP. Additionally or alternatively, the phase line 340-a may transition to a first level (e.g., VNWL). In some instances, the phase line 340-a may be driven (e.g., actively driven) to VNWL. At t6, the global row line 325 and the word line 330-a may each be maintained at a first level (e.g., at VNWL). When the phase reversal line 335-a is driven to the second level, the selection device 315-a may be activated and the selection device 310-a may be deactivated, thereby coupling the word line 330-a to the source of the selection device 315-a. Furthermore, when the phase line 340-a is driven to the first level, the selection device 320-a may be deactivated, thereby decoupling the global row line 325 from the word line 330-a. Thus, with reference to Figure 3B The described timing scheme may provide sufficiently strong drive for the desired slew rate of word line 330-a while preventing overdrive that might otherwise cause select devices 320-a, 320-c, and 320-d to break down over time.

[0067] Figure 4AAn example of a circuit diagram 400-a supporting a sub-wordline driver according to an example as disclosed herein is illustrated. The circuit diagram 400-a may illustrate an example of one or more drivers (or one or more aspects of one or more drivers) that may be used to drive a particular wordline (e.g., wordline 430). The circuit diagram 400-a may illustrate an array of memory cells arranged in a plurality of subarrays 405. One or more wordlines 430 may pass through the subarrays, and additional drivers may be located in the gap between each subarray 405. For example, a main SWD gap 450 may include a driver for driving the wordline 430-a from a global row line (GR) 425, a phase line 440-a, and a phase reversal line 435-a. In some examples, the SWD gaps following the main SWD gap 450 (e.g., each SWD gap) may include a single transistor driver, which may reduce the spacing between each subarray 405. Furthermore, the driver can drive the select transistors in each gap to a level that provides sufficiently strong drive for the desired slew rate of the corresponding word line, while preventing overdrive that might otherwise cause the select transistors to break down over time.

[0068] As described in this article, Figure 4A 4. The main SWD gap 450 illustrated in FIG. 4 may be located on a first side of the first sub-array 405. The main SWD gap 450 may include a first selection device 410-a of a first type (e.g., a first transistor). In some examples, the first selection device 410-a may be a p-type (e.g., PMOS) transistor. A source of the first selection device 410-a may be coupled to a first access line 425, and a drain of the first selection device 410-a may be coupled to a second access line 430-a. The first access line 425 may be a global row line, and the second access line 430-a may be a word line. In some examples, the first selection device 410-a may couple the global row line 425 with the word line 430-a based on a third access line 435-a. For example, the third access line 435-a may be a phase reversal line 435 coupled to the gate of the first selection device 410-a. Thus, the first selection device 410-a can couple the global row line 425 with the word line 430-a based on a relatively low (or negative) voltage (e.g., VNWL) applied to the phase reversal line 435-a. For example, the voltage (e.g., VNWL) can be the N-well voltage of the memory array, and can be ground or can be a voltage other than ground (e.g., a negative voltage).

[0069] In some examples, the main SWD gap 450 may include a third selection device 417-a of the second type. In some examples, the third selection device 417-a may be an n-type (e.g., NMOS) transistor. The source of the third selection device 417-a may be coupled to the global row line 425, and the drain of the third selection device 417-a may be coupled to the word line 430-a. The gate of the third selection device 417-a may be coupled to the fourth access line 440-a, which may be the phase line 440-a. In some examples, the third selection device 417-a may couple the word line 430-a to the global row line 425 based on a relatively high voltage (e.g., VCCP) applied to the phase line 440-a. In some examples, the presence of the third selection device 417-a may increase the rate at which the word line 430-a is driven to a voltage (e.g., VCCP). For example, the third selection device 417-a can be an n-type (e.g., NMOS) transistor, and thus can have a relatively high carrier mobility. Additionally, when the signal of the phase reversal line 440-a goes low and the global row line 425 is less than a threshold above VNWL, the first selection device 410-a can be subthreshold and can turn on poorly. Thus, the third selection device 417-a can help drive the word line 430-a during this duration (e.g., during the early portion of the transition of the global row line 425 from VNWL to VCCP).

[0070] In some examples, the main SWD gap 450 may include an additional select device 415-a of the second type. In some examples, the select device 415-a may be an n-type (e.g., NMOS) transistor. The source of the select device 415-a may be coupled to a voltage source (e.g., VNWL), and the drain of the select device 415-a may be coupled to the word line 430-a. In some examples, the select device 415-a may couple the word line 430-a to the voltage source (e.g., VNWL) based on a relatively high voltage (e.g., VCCP) applied to the phase reversal line 435-a. Additionally or alternatively, the main SWD gap 450 may include one or more select devices associated with the additional word line 430.

[0071] The word line drivers in the main SWD gap 450 (which includes select devices 410-a, select devices 415-a, and select devices 417-a) may be repeated for additional word lines in a set of word lines associated with the global row lines. In some cases, the memory device may include main SWD gaps 450 and 465 on opposite sides of the subarray 405. In this configuration, the main SWD gap 450 may be configured to drive the even word lines 430, and the circuit diagram 400-a may include a second main SWD gap 465 at the opposite end of the array, the second main SWD gap including select devices 417-b configured to couple the global row line 425 with the word line 430-b based on the phase line 440-b, and select devices 410-b and 415-b that may couple the word line 430-b with the global row line 425 or a voltage source based on the phase reversal line 435-b.

[0072] The circuit diagram 400-a may illustrate additional gaps (e.g., SWD gaps) located between each of the sub-arrays 405. For example, a first SWD gap 455 may be located on the second side of the first sub-array 405 (and on the first side of the second sub-array 405-a). Because each word line 430 extending through the memory array may have a significant capacitance and resistance, a local word line driver may be fabricated in each SWD gap. In some examples, the local word line driver may be configured to drive a subset of the total number of word lines 430. For example, in some SWD gaps (e.g., “even” SWD gaps), the local driver may be configured to drive even word lines 430 (e.g., second word line 430, fourth word line 430, etc.). In other examples, in some SWD gaps (e.g., “odd” SWD gaps), the local driver may be configured to drive odd word lines 430 (e.g., first word line 430, third word line 430, etc.).

[0073] like Figure 4A , the local word line driver located in the first SWD gap 455 may include a second select device 420-a of the first type (e.g., a second transistor). The local word line driver including the second select device may receive substantially the same signal used to control the driver in the main SWD gap 450. However, the presence of the driver in the first SWD gap 450 (and subsequent SWD gaps) may provide sufficiently strong drive for the desired slew rate of the corresponding word line while preventing overdrive that might otherwise cause the select transistor to break down over time.

[0074] In some examples, the second selection device 420-a may be a p-type (e.g., PMOS) transistor. The source of the second selection device 420-a may be coupled to the global row line 425, and the drain of the second selection device 420-a may be coupled to the word line 430-a. In some examples, the second selection device 420-a may couple the global row line 425 with the word line 430-a based on a signal applied to the phase reversal line 435-a. For example, the second selection device 420-a may couple the global row line 425 with the word line 430-a based on a relatively low voltage (e.g., VNWL or VNWL_DEEP) applied to the phase reversal line 435-a. As described herein, in some examples, the phase reversal line 435-a may be driven to VNWL_DEEP for a certain duration in order to more strongly activate the selection device 410-a and the selection device 420-a. In some examples, VNWL_DEEP can be a voltage lower than VNWL (eg, lower than a threshold voltage of VNWL).

[0075] The first SWD gap 455 may include a plurality of additional transistors configured to couple the respective word lines to the global row line 425. For example, as shown in FIG. Figure 3A As described, each word line in a set of word lines may be coupled to a global row line 425 via a respective select device located in each SWD gap. Thus, each SWD gap may include a plurality of transistors each associated with a respective word line (in a set of word lines) and configured to couple the respective word line to the global row line 425 (or another global row line associated with the memory array). Additional word line drivers may be driven by additional phase reversal lines such as PHF0, PHF1, etc. For example, SWD gap 455 may include a select device 420-b configured to couple the global row line 425 to the word line 430-b, and SWD gap 460 may include a select device 420-d to couple the global row line 425 to the word line 430-b.

[0076] In some examples, global row line 425 may be common to a set of word lines including word line 430-a and word line 430-b (and other word lines not shown). As described herein, a two-step decode may be used to decode a memory address to a word line, and global row line 425 may be associated with the timing of an access operation. For example, a signal may be asserted to phase inversion line 435-a (e.g., asserted to the gate of select device 420-a) to couple global row line 425 to word line 430-a before driving global row line 425 (e.g., to VCCP). Thus, when global row line 425 is driven to a relatively high voltage, selected word line 430-a is also driven to the same voltage (e.g., to VCCP).

[0077] Circuit diagram 400-a may illustrate additional SWD gaps located between each of the sub-arrays 405. For example, circuit diagram 400-a may illustrate a second SWD gap 460 including select device 420-c and select device 420-d. Each SWD gap may include an additional transistor coupled to a respective word line and a phase reversal line. Each select device may couple a global row line 425 with a respective word line 430 based on the respective phase reversal line being driven to a relatively low voltage (e.g., VNWL or VNWL_DEEP). As discussed herein, the presence of a driver in each SWD gap may provide sufficiently strong drive for the desired slew rate of the corresponding word line while preventing overdrive that might otherwise cause the select transistors to break down over time. The size of SWD gaps 455 and 460 may be determined by the area of ​​select device 420, and therefore, reducing the size or number of devices within the gaps may reduce the size of the gaps and ultimately the size of the memory device.

[0078] Figure 4B An example of a timing diagram 400-b for supporting a sub-word line driver according to an example as disclosed herein is illustrated. The timing diagram 400-b may be similar to the timing diagram 400-b of FIG. Figure 4A The timing diagram 400-b may be used to describe the operation of the circuit diagram 400-a. Figure 4A The timing of the signals of global row line 425, phase reversal line 435-a, phase line 440-a, and word line 430-a are described. For example, signal 426 may be applied to global row line 425, signal 436 may be applied to phase reversal line 435-a, signal 441 may be applied to phase line 440-a, and signal 431 may be applied to word line 430-a. The signals applied to each of the lines may activate or deactivate a particular select transistor to a level that provides a sufficiently strong drive for the desired slew rate of word line 430-a, while preventing overdrive that might otherwise cause the select transistor to break down over time.

[0079] At t0, the first access line 425 (e.g., global row line 425) and the fourth access line 440-a (e.g., phase line 440-a) may each be maintained at a first level (e.g., VNWL). In some instances, VNWL may be a relatively low (or negative) voltage level. At t0, the third access line 435-a (e.g., phase reversal line 435-a) may be maintained at a second level (e.g., VCCP). In some instances, the third access line 435-a may be driven (e.g., actively driven) to a second level, and the second level may be a level higher than the first level (e.g., VCCP may be higher than VNWL). When the phase reversal line 435-a is maintained at the second level (or driven to the second level), the selection device 415-a may be activated, thereby coupling the word line 430-a to the voltage source (e.g., VNWL). Additionally or alternatively, when the phase inversion line 435-a is maintained at the second level (or driven to the second level) and the phase line 440-a is maintained at the first level, the selection device 410-a, the selection device 417-a, and the selection device 420-a may each be deactivated. Thus, at t0, the global row line 425 may not be coupled to the word line 430-a.

[0080] At t1, the phase reversal line 435-a may be driven to a fourth level (e.g., to VNWL_DEEP). In some examples, the phase reversal line 435-a may be driven (e.g., actively driven) to VNWL_DEEP. Driving the phase reversal line 435-a to VNWL_DEEP may ensure activation of the select device 410-a and the select device 420-a. As discussed herein, VNWL_DEEP may be a relatively low voltage that activates the select device 410-a and the select device 420-a more strongly than, for example, applying VNWL. By applying VNWL_DEEP and more strongly activating the select device 410-a and the select device 420-a, the voltage of the word line 430-a may increase from VNWL to VCCP more quickly.

[0081] Additionally or alternatively, the phase line 440-a may transition to a second level (e.g., VCCP). In some instances, the phase line 440-a may be driven (e.g., actively driven) to VCCP. At t1, the global row line 425 and the word line 430-a may each be maintained at the first level (e.g., at VNWL). When the phase reversal line 435-a is driven to the fourth level, the select device 415-a and the select device 420-a may be deactivated and the select device 410-a may be activated, thereby coupling the global row line 425 with the word line 430-a. Furthermore, when the phase line 440-a is driven to the second level, the select device 417-a may be activated, thereby coupling the global row line 425 with the word line 430-a.

[0082] At t2, the global row line 425 may be driven to a second level (e.g., to VCCP), and the phase reversal line 435-a and the phase line 440-a may be maintained at the same level. Because the global row line 425 may be coupled to the word line 430-a (e.g., based on the signaling at t1), the word line 430-a may begin to transition to the second level (e.g., to VCCP). Specifically, since a relatively low voltage (e.g., VNWL_DEEP) is applied to the phase reversal line 435-a, the rate at which the word line 430-a transitions to VCCP may be increased. Therefore, by applying VNWL_DEEP, the selection device 410-a and the selection device 420 may be activated more strongly than when VNWL is applied. That is, applying VNWL_DEEP to the phase reversal line 430-a may activate the selection device 410-a and the selection device 420 more strongly than when VNWL is applied, which may allow the word line 430-a to reach VCCP more quickly. Therefore, a duration after t2 (and before t3), word line 430-a may reach VCCP.

[0083] At t3, the phase reversal line 435-a may be driven to a first level (e.g., VNWL), and the global row line 425, the word line 430-a, and the phase line 440-a may be maintained at the same level. For example, after the word line 430-a reaches VCCP, the phase reversal line 435-a may be driven to VNWL. Driving the phase reversal line 435-a to the first level may not deactivate the selection device 410-a or the selection device 420. Alternatively, the selection device 410-a and the selection device 420 may remain activated, and the word line 430-a may be maintained at a second level (e.g., at VCCP). By driving the phase reversal line 435-a to VNWL (e.g., after driving the bit reversal line 435-a to VNWL_DEEP for a period of time), less stress may be applied to the selection device 410-a and the selection device 420. Thus, driving the phase reversal line 435 - a to VNWL after driving it to VNWL_DEEP may provide a sufficiently strong drive for the desired slew rate of the word line 430 - a .

[0084] At t4, the phase reversal line 435-a may be driven to a fourth level (e.g., to VNWL_DEEP), and the global row line 425, the word line 430-a, and the phase line 440-a may be maintained at the same level. In some examples, the phase reversal line 435-a may not be driven to the fourth level within the second time, but may be driven to the first level (e.g., VNWL) for an extended duration (e.g., until t6).

[0085] At t5, the global row line 425 may be driven to a first level (e.g., to VNWL), and the phase reversal line 435-a and the phase line 440-a may be maintained at the same level. Because the global row line 425 may be coupled to the word line 430-a (e.g., based on the selection device 410-a and the selection device 420), the word line 430-a may begin to transition downward to the first level (e.g., to VNWL). Therefore, for a duration after t5 (and before t6), the word line 430-a may reach VNWL.

[0086] At t6, the phase reversal line 435-a may transition to a second level (e.g., to VCCP). In some instances, the phase reversal line 435-a may be driven (e.g., actively driven) to VCCP. Additionally or alternatively, the phase line 440-a may transition to a first level (e.g., VNWL). In some instances, the phase line 440-a may be driven (e.g., actively driven) to VNWL. At t6, the global row line 425 and the word line 430-a may each be maintained at the first level (e.g., at VNWL). When the phase reversal line 435-a is driven to the second level, the selection device 415-a may be activated and the selection device 410-a and the selection device 420-a may be deactivated, thereby coupling the word line 430-a to the source of the selection device 415-a. Furthermore, when the phase line 440-a is driven to the first level, the selection device 417-a may be deactivated, thereby decoupling the global row line 425 from the word line 430-a. Figure 4B The described timing scheme may provide sufficiently strong drive for the desired slew rate of word line 430-a while preventing overdrive that might otherwise cause select device 420 to break down over time.

[0087] Figure 5A An example of a circuit diagram 500-a supporting a sub-wordline driver according to an example as disclosed herein is illustrated. The circuit diagram 500-a may illustrate an example of one or more drivers (or one or more aspects of one or more drivers) that may be used to drive a particular wordline (e.g., wordline 530). The circuit diagram 500-a may illustrate an array of memory cells arranged in a plurality of subarrays 505. One or more wordlines 530 may pass through the subarrays, and additional drivers may be located in the gap between each subarray 505. For example, a main SWD gap 550 may include a driver for driving the wordline 530 using a phase line (PH) 525, a global row reversal line (GRF) 535, and a phase reversal line 540. The phase line 525 may extend horizontally across the memory array, while the global row reversal line 535 and / or the phase reversal line 540-a may extend horizontally across the array or vertically in each SWD gap.

[0088] In some examples, the main gap and subsequent SWD gaps may include additional word line drivers for driving each word line. Additionally or alternatively, the gaps following the main gap (e.g., each SWD gap) may include a single transistor driver, which may reduce the spacing between each sub-array 505. Furthermore, the driver may drive the select transistors in each gap to a level that provides sufficiently strong drive for the desired slew rate of the corresponding word line while preventing overdrive that might otherwise cause the select transistors to break down over time.

[0089] As described in this article, Figure 5A , may be located on a first side of the first sub-array 505. The main SWD gap 550 may include a first selection device 510-a of a first type (e.g., a first transistor). In some examples, the first selection device 510-a may be a p-type (e.g., PMOS) transistor. A source of the first selection device 510-a may be coupled to a fourth access line 525-a, and a drain of the first selection device 510-a may be coupled to a second access line 530-a. The fourth access line 525-a may be a phase line, and the second access line 530-a may be a word line. In some examples, the first selection device 510-a may couple the phase line 525-a with the word line 530-a based on a fifth access line 535. For example, the fifth access line 535 may be a global row inversion line 535 coupled to a gate of the first selection device 510-a. Thus, the first selection device 510-a can couple the phase line 525-a with the word line 530-a based on a relatively low (or negative) voltage (e.g., VNWL) applied to the global row inversion line 535. For example, the voltage (e.g., VNWL) can be the N-well voltage of the memory array, and can be ground or can be a voltage other than ground (e.g., a negative voltage).

[0090] In some examples, the main SWD gap 550 may include a second selection device 515-a of a second type. In some examples, the second selection device 515-a may be an n-type (e.g., NMOS) transistor. The source of the second selection device 515-a may be coupled to a voltage source (e.g., VNWL), and the drain of the second selection device 515-a may be coupled to the word line 530-a. In some examples, the second selection device 515-a may couple the word line 530-a to the voltage source (e.g., VNWL) based on a relatively high voltage (e.g., VCCP) applied to the global row inversion line 535. Additionally or alternatively, the main SWD gap 550 may include one or more additional second selection devices associated with additional word lines 330 (e.g., having respective source terminals coupled to VNWL, respective gates coupled to the global row inversion line 535, and respective drains coupled to respective word lines 330).

[0091] In some examples, the main SWD gap 550 may include a third selection device 517-a of the second type. In some examples, the third selection device 517-a may be an n-type (e.g., NMOS) transistor. In a first configuration of the third selection device 517-a, the drain of the third selection device 517-a may be coupled to the word line 530-a, and the source 542-a of the third selection device 517-a may be coupled to a voltage source. The gate of the third selection device 517-a may be coupled to the phase reversal line 540-a. In some examples, the third selection device 517-a may couple the word line 530-a to the voltage source (e.g., VNWL) based on a relatively high voltage (e.g., VCCP) applied to the phase reversal line 540-a. In a second configuration of the third selection device 517-a, its drain may be coupled to the word line 530-a, its source 542-a may be coupled to a different word line 530 (e.g., word line 530-b), and its gate may be coupled to a global row inversion line (e.g., global row inversion line 535) so that when the global row inversion line is high, the third selection device 517-a may act as a separate path or alternative path or pull-down device for the word line 530-a. In yet another third alternative configuration for the third selection device 517-a (not shown), its drain may be coupled to the word line 530-a, its source 542-a may be coupled to the phase line 525-a, and its gate may be coupled to the global row line. For example, the third selection device 517-a may be an n-type (e.g., NMOS) transistor, and thus may have a relatively high carrier mobility. Additionally, when the signal of the global row inversion line 535 goes low and the phase line 525 is less than a threshold above VNWL, the first selection device 510-a may be sub-threshold and may not turn on properly. Thus, the third selection device 517-a may help drive the word line 530-a during this duration (e.g., during the early portion of the transition of the phase line 525 from VNWL to VCCP). In some cases, multiple of these configurations for the third selection device 517-a may be used together (e.g., using additional selection devices).

[0092] The word line drivers in main SWD gap 550 (which includes select device 510-a, select device 515-a, and select device 517-a) may be repeated for additional word lines in a set of word lines associated with global row lines and global row inversion lines.

[0093] The circuit diagram 500-a may illustrate additional gaps (e.g., SWD gaps) located between each of the sub-arrays 505. For example, a first SWD gap 555 may be located on the second side of the first sub-array 505 (and on the first side of the second sub-array 505-a). Because each word line 530 extending through the memory array may have a significant capacitance and resistance, additional word line drivers may be fabricated in each SWD gap. In some examples, the additional word line drivers may be configured to drive a subset of the total number of word lines 530. For example, in some SWD gaps (e.g., “even” SWD gaps), the local drivers may be configured to drive even word lines 530 (e.g., the second word line 530, the fourth word line 530, etc.). In other examples, in some SWD gaps (e.g., “odd” SWD gaps), the local drivers may be configured to drive odd word lines 530 (e.g., the first word line 530, the third word line 530, etc.). In this configuration, the main SWD gap can be configured to drive the even word line 530, and the circuit diagram 500-a can include a second main SWD gap 565 located at the opposite end of the array, the second main SWD gap including a selection device 517-b configured to couple the word line 530-b to a voltage source based on a phase inversion line 540-b, and selection devices 510-b and 515-b that can couple the word line 530-b to a phase line 525-b or a voltage source based on a global row inversion line 535.

[0094] like Figure 5A , a word line driver located in the first SWD gap 555 may include a second select device 520-a of the first type (e.g., a second transistor). The word line driver including the second select device may receive substantially the same signal used to control the driver in the main SWD gap 550. However, the presence of the driver in the first SWD gap 555 (and subsequent SWD gaps) may provide sufficiently strong drive for the desired slew rate of the corresponding word line while preventing overdrive that might otherwise cause the select transistor to break down over time. For example, the SWD gap 555 may include a select device 520-b configured to couple the phase line 525-b with the word line 530-b, and the SWD gap 560 may include a select device 520-d to couple the phase line 525-b with the word line 530-b. Additional word line drivers may be driven by additional global row inversion lines such as GRF0, GRF1, and additional phase lines such as PH0, PH1.

[0095] In some examples, the second selection device 520-a may be a p-type (e.g., PMOS) transistor. The source of the second selection device 520-a may be coupled to the phase line 525-a, and the drain of the second selection device 520-a may be coupled to the word line 530-a. In some examples, the second selection device 520-a may couple the phase line 525-a with the word line 530-a based on a signal applied to the global row inversion line 535. For example, the second selection device 520-a may couple the phase line 525 with the word line 530-a based on a relatively low voltage (e.g., VNWL or VNWL_DEEP) applied to the global row inversion line 535. As described herein, in some examples, the global row inversion line 535 may be driven to VNWL_DEEP for a certain duration in order to more strongly activate the selection device 510-a and the selection device 520-a. In some examples, VNWL_DEEP can be a voltage lower than VNWL.

[0096] The first SWD gap 555 may include a plurality of additional transistors configured to couple the respective local word lines to the respective phase lines 525. For example, as shown in FIG. Figure 3A As described, each word line in a set of word lines can be coupled to a respective phase line 525 via a respective selection device located in one or more SWD gaps. Thus, each SWD gap can include a plurality of transistors each associated with a respective word line and configured to couple the respective word line to the respective phase line 525.

[0097] In some examples, global row inversion line 535 may be common to a set of word lines including word line 530-a and word line 530-b (as well as other word lines not shown). As described herein, a memory address may be decoded to a word line using two-step decoding, and thus, phase line 525 may be associated with the timing of an access operation. For example, a signal may be asserted to global row inversion line 535 (e.g., asserted to the gate of select device 520) to couple phase line 525-a to word line 530-a prior to activating phase line 525-a (e.g., to VCCP). Thus, when phase line 525-a is driven to a relatively high voltage, selected word line 530-a is also driven to the same voltage (e.g., to VCCP).

[0098] Circuit diagram 500-a may illustrate additional SWD gaps located between each of the sub-arrays 505. For example, circuit diagram 500-a may illustrate a second SWD gap 560 including select device 520-c and select device 520-d. Each SWD gap may include additional transistors coupled with a respective word line and phase line. Each select device may couple a respective phase line 525 with a respective word line 530 based on the global row inversion line 535 being driven to a relatively low voltage (e.g., VNWL or VNWL_DEEP). As discussed herein, the presence of a driver in each SWD gap may provide sufficiently strong drive for the desired slew rate of the corresponding word line while preventing overdrive that might otherwise cause the select transistors to break down over time.

[0099] Figure 5B An example of a timing diagram 500-b for supporting a sub-word line driver according to an example as disclosed herein is illustrated. The timing diagram 500-b may be similar to the timing diagram 500-b of FIG. Figure 5A The timing diagram 500-b may be used to describe the operation of the circuit diagram 500-a. Figure 5A The timing of the signals of the phase line 525-a, the phase inversion line 540-a, and the global row inversion line 535 are described. For example, signal 526 may be applied to the phase line 525-a, signal 536 may be applied to the global row inversion line 535, signal 541 may be applied to the phase inversion line 540-a, and signal 531 may illustrate the corresponding signal on the word line 530-a. The signals applied to each of the lines may activate or deactivate a particular select transistor to a level that provides a sufficiently strong drive for the desired slew rate of the word line 530-a, while preventing overdrive that might otherwise cause the select transistor to break down over time.

[0100] At t0, the phase line 525-a may be maintained at a first level (e.g., VNWL). In some instances, VNWL may be a relatively low (or negative) voltage level. At t0, the phase reversal line 540-a and the global row reversal line 535 may be maintained at a second level (e.g., VCCP). In some instances, the phase reversal line 540-a and the global row reversal line 535 may be driven (e.g., actively driven) to a second level, and the second level may be a level higher than the first level (e.g., VCCP may be higher than VNWL). When the global row reversal line 535 is maintained at the second level (or driven to the second level), the selection device 515-a may be activated, thereby coupling the word line 530-a to the voltage source (VNWL) via the selection device 515-a. Additionally or alternatively, when the global row inversion line 535 is maintained at the second level (or driven to the second level), the selection device 510-a and the selection device 520 may be deactivated respectively, while the selection device 515-a is activated. Therefore, at t0, the phase line 525-a may not be coupled to the word line 530-a.

[0101] At t1, the global row inversion line 535 may be driven to a fourth level (e.g., to VNWL_DEEP). In some examples, the global row inversion line 535 may be driven (e.g., actively driven) to VNWL_DEEP. Driving the global row inversion line 535 to VNWL_DEEP may ensure activation of the selection device 510-a and the selection device 520-a. As discussed herein, VNWL_DEEP may be a relatively low voltage that more strongly activates the selection device 510-a and the selection devices 520-a and 520-c than, for example, if VNWL is applied. By applying VNWL_DEEP and more strongly activating the selection device 510-a and the selection devices 520-a and 520-c, the voltage of the word line 530-a may increase from VNWL to VCCP more quickly.

[0102] Additionally or alternatively, the phase reversal line 540-a may transition to a first level (e.g., VNWL). In some examples, the phase reversal line 540-a may be driven (e.g., actively driven) to VNWL. At t1, the phase line 525-a may be maintained at the first level (e.g., at VNWL). When the global row reversal line 535 is driven to a fourth level, the selection device 510-a and the selection device 520 may be activated and the selection device 515-a may be deactivated, thereby coupling the phase line 525-a with the word line 530-a. Furthermore, when the phase reversal line 540-a is driven to the first level, the selection device 517-a may be deactivated. Alternatively, if the source of the selection device is coupled to the phase line 525-a, its drain is coupled to the word line 530-a and its gate is coupled to the global row line, then the selection device may also be activated at t1 when the global row inversion line 535 is driven to the fourth level and the global row line is driven to the second level or a third level higher than the second level (for example, VCCP2).

[0103] At t2, the phase line 525-a may be driven to a second level (e.g., to VCCP), and the global row inversion line 535 and the phase inversion line 540-a may be maintained at the same level. Because the phase line 525-a may be coupled to the word line 530-a (e.g., based on the signaling at t1), the word line 530-a may begin to transition to the second level (e.g., to VCCP). Specifically, since a relatively low voltage (e.g., VNWL_DEEP) is applied to the global row inversion line 535, the rate at which the word line 530-a transitions to VCCP may be increased. Therefore, by applying VNWL_DEEP, the selection device 510-a and the selection device 520 may be activated more strongly than when VNWL is applied. That is, applying VNWL_DEEP to the global row inversion line 535 may activate the selection device 510-a and the selection device 520 more strongly than when VNWL is applied, which may allow the word line 530-a to reach VCCP more quickly. Therefore, a duration after t2 (and before t3), word line 530-a may reach VCCP.

[0104] At t3, the global row inversion line 535 may be driven to a first level (e.g., VNWL), and the phase line 525-a, the word line 530-a, and the phase inversion line 540-a may be maintained at the same level. For example, after the word line 530-a reaches VCCP, the global row inversion line 535 may be driven to VNWL. Driving the global row inversion line 535 to the first level may not deactivate the selection device 510-a or the selection device 520. Alternatively, the selection device 510-a and the selection device 520 may remain activated, and the word line 530-a may be maintained at a second level (e.g., at VCCP). By driving the global row inversion line 535 to VNWL (e.g., after driving the global row inversion line 535 to VNWL_DEEP for a period of time), less stress may be applied to the selection device 510-a and the selection device 520. Thus, driving the global row inversion line 535 to VNWL after driving it to VNWL_DEEP may provide a strong enough drive for the desired slew rate of the word line 530-a without overstressing the select devices.

[0105] At t4, the global row inversion line 535 may be driven to a fourth level (e.g., to VNWL_DEEP), and the phase line 525-a and the phase inversion line 540-a may be maintained at the same level. In some examples, the global row inversion line 535 may not be driven to the fourth level within the second time, but may be driven to the first level (e.g., to VNWL) for an extended duration (e.g., until t6).

[0106] At t5, the phase line 525-a may be driven to a first level (e.g., to VNWL), and the global row inversion line 535 and the phase inversion line 540-a may be maintained at the same level. Because the phase line 525-a may be coupled to the word line 530-a (e.g., based on the selection device 510-a and the selection device 520), the word line 530-a may begin to transition downward to the first level (e.g., to VNWL). Therefore, for a duration after t5 (and before t6), the word line 530-a may reach VNWL.

[0107] At t6, the global row inversion line 535 may transition to a second level (e.g., to VCCP). In some instances, the global row inversion line 535 may be driven (e.g., actively driven) to VCCP. Additionally or alternatively, the phase inversion line 540-a may transition to a first level (e.g., VNWL). In some instances, the phase inversion line 540-a may be driven (e.g., actively driven) to VNWL. At t6, the phase line 525-a may be maintained at the first level (e.g., at VNWL). When the global row inversion line 535 is driven to the second level, the selection device 515-a may be activated and the selection device 510-a and the selection device 520-a may be deactivated, thereby coupling the word line 530-a with the source of the selection device 515-a (e.g., VNWL). In addition, when the phase inversion line 540-a is driven to the first level, the selection device 517-a may be activated. Alternatively, if the drain of the selection device 517-a is coupled to the word line 530-a, its source 542-a is coupled to a different word line 530 (e.g., word line 530-b) and its gate is coupled to the global row inversion line (e.g., the second configuration), then when the global row inversion line is asserted (e.g., driven to the second level), the selection device can provide an additional path to VNWL through other word lines. Alternatively, if the source of the selection device 517-a is coupled to the phase line 525, its drain is coupled to the word line 530-a and its gate is coupled to the global row line (e.g., the third configuration), then the selection device can also be deactivated at t6 when the global row line is driven to the first level (e.g., VNWL). Therefore, with reference to Figure 5B The described timing scheme can provide a sufficiently strong drive for the desired slew rate of word line 530-a while preventing overdrive that might otherwise cause select devices 510-a and 520 to break down over time.

[0108] Fig. 6AAn example of a circuit diagram 600-a supporting sub-wordline drivers according to examples as disclosed herein is illustrated. The circuit diagram 600-a may illustrate an example of one or more drivers (or one or more aspects of one or more drivers) that may be used to drive a particular wordline (e.g., wordline 330-a or wordline 330-b). The circuit diagram 600-a may illustrate an array of memory cells arranged in a plurality of subarrays 605. One or more wordlines 630 may pass through the subarrays, and additional drivers may be located in the gap between each subarray 605. For example, a main gap (e.g., main SWD gap 650) may include a driver for driving wordline 630 using a global wordline (GR) 625, a phase line (PH) 640, and a phase reversal line (PHF) 635. In some examples, the main gap may also include additional wordline drivers for driving additional wordlines. Additionally or alternatively, a gap following the main gap (e.g., each SWD gap) may include a single transistor driver that may reduce the spacing between each subarray 605. Furthermore, the driver can drive the select transistors in each gap to a level that provides sufficiently strong drive for the desired slew rate of the corresponding word line, while preventing overdrive that might otherwise cause the select transistors to break down over time.

[0109] As described in this article, Fig. 6A 605. The main SWD gap 650 illustrated in FIG. 605 may be located on a first side of the first sub-array 605. The main SWD gap 650 may include a first selection device 610-a of a first type (e.g., a first transistor). In some examples, the first selection device 610-a may be a p-type (e.g., PMOS) transistor. A source of the first selection device 610-a may be coupled to a first access line 625, and a drain of the first selection device 610-a may be coupled to a second access line 630-a. The first access line 625 may be a global row line, and the second access line 630-a may be a word line. In some examples, the first selection device 610-a may couple the global row line 625 to the word line 630-a based on a third access line 635-a. For example, the third access line 635-a may be a phase reversal line 635-a coupled to a gate of the first selection device 610-a. Thus, the first selection device 610-a can couple the global row line 625 with the word line 630-a based on a relatively low (or negative) voltage (e.g., VNWL) applied to the phase reversal line 635-a. For example, the voltage (e.g., VNWL) can be the N-well voltage of the memory array, and can be ground or can be a voltage other than ground (e.g., a negative voltage).

[0110] In some examples, the main SWD gap 650 may include an additional selection device 615-a of the second type. In some examples, the selection device 615-a may be an n-type (e.g., NMOS) transistor. The source of the selection device 615-a may be coupled to a voltage source (e.g., VNWL), and the drain of the selection device 615-a may be coupled to the word line 630-a. In some examples, the selection device 615-a may couple the word line 630-a to the voltage source (e.g., VNWL) based on a relatively high voltage (e.g., VCCP) applied to the phase reversal line 635-a. Additionally or alternatively, the main SWD gap 650 may include one or more selection devices associated with additional word lines. For example, the word line drivers in the main SWD gap 650 (which includes the selection device 610-a and the selection device 615-a) may be repeated for additional word lines extending across the memory array. The additional word line drivers may be driven by the global row line and the additional phase reversal line. For example, additional word line drivers may be driven by additional global row lines GR and additional phase inversion lines such as PHF0, PHF1.

[0111] The circuit diagram 600-a may be Figure 3A 6. That is, the SWD gaps following the main SWD gap 650 (e.g., the first SWD gap 655, the second SWD gap 660, the third SWD gap, the fourth SWD gap, etc.) may have different (e.g., alternating each gap or alternating more than one gap) transistor types. For example, the first SWD gap 655 may be located on the second side of the first sub-array 605 (and on the first side of the second sub-array 605-a). The word line driver located in the first SWD gap 655 may include a second selection device 620-a of a second type (e.g., a second transistor). In some examples, the second selection device 620-a may be an n-type (e.g., NMOS) transistor. The source of the second selection device 620-a may be coupled to the word line 630-a, and the drain of the second selection device 620-a may be coupled to the global row line 625.

[0112] In some examples, the second selection device 620-a may couple the global row line 625 with the word line 630-a based on the fourth access line 640-a. For example, the fourth access line 640-a may be a phase line 640-a coupled to the gate of the second selection device 620-a. Thus, the second selection device 620-a may couple the global row line 625 with the word line 630-a based on a relatively high voltage (e.g., VCCP or VCCP2) applied to the phase line 640-a. In some examples, the phase line 640-a may extend vertically through a subset of the SWD gaps in the memory array and may therefore not extend across the array. By extending the phase line vertically through the SWD gaps, the area available for the word lines may be increased. In addition, the SWD gap 655 may include a selection device for each additional word line 630-a. For example, the selection device 620-b may couple the global row line 625 with the word line 630-b based on the phase line 640-b.

[0113] Additionally or alternatively, the word line driver located in the second SWD gap 660 may include a fourth selection device 620-c of the first type (e.g., a fourth transistor). In some examples, the fourth selection device 620-c may be a p-type (e.g., PMOS) transistor. The drain of the fourth selection device 620-c may be coupled to the word line 630-a, and the source of the fourth selection device 620-c may be coupled to the global row line 625. In some examples, the fourth selection device 620-c may couple the global row line 625 with the word line 630-a based on the third access line 635-a. For example, the third access line 635-a may be a phase reversal line 635-a coupled to the gate of the fourth selection device 620-b. Therefore, the fourth selection device 620-b may couple the global row line 625 with the word line 630-a based on the relatively low voltage (e.g., VNWL) applied to the phase line 640-a.

[0114] In addition, SWD gap 660 may include a selection device for each additional word line 630. For example, selection device 620-d may couple global row line 625 with word line 630-b based on phase reversal line 635-b. In some examples, phase line 640 and phase reversal line 635 may extend vertically through a subset of SWD gaps in the memory array, and may therefore not extend across the array. By extending the phase lines and phase reversal lines vertically through the SWD gaps, the area available for word lines on the memory array may be increased.

[0115] As described herein, subsequent SWD gaps may include (e.g., alternating) patterns of transistor types such that each subset of transistors is configured to be activated (or deactivated) based on either the phase reversal line 635 or the phase line 640. Each SWD gap may include a plurality of transistors (of the same type as other transistors in the same gap) that each correspond to a word line in a group of word lines. Each group of word lines may correspond to a global row line 625. In such a configuration, a main SWD gap may be configured to drive even word lines 630, and the circuit diagram 600-a may include a second main SWD gap 665 at an opposite end of the array, the second main SWD gap including a select device 610-b and a select device 615-b coupled to the phase reversal line 635-b and configured to drive odd word lines 630, such as word lines 630-b.

[0116] Although illustrated as alternating transistor types for each SWD gap, other patterns may be used, including a pattern having one or more SWD gaps having transistors of a first type followed by one or more SWD gaps having transistors of a second type, wherein the pattern is repeated. Alternatively, the pattern may not repeat, and may have a first number of SWD gaps having transistors of the first type and a second number of SWD gaps having transistors of the second type. The presence of a driver in each SWD gap may provide sufficiently strong drive for the desired slew rate of the corresponding word line while preventing overdrive that might otherwise cause the select transistor to break down over time.

[0117] Figure 6B An example of a timing diagram 600-b for supporting a sub-wordline driver according to an example as disclosed herein is illustrated. The timing diagram 600-b may be similar to the timing diagram 600-b of FIG. Fig. 6A The timing diagram 600-a may be associated with the operational aspects of the circuit diagram 600-a. For example, the timing diagram 600-b may be illustrated as applied to the circuit diagram 600-a. Fig. 6A The timing of the signals of the global row line 625, the phase reversal line 635-a, the phase line 640-a, and the word line 630-a are described. For example, the signal 626 may be applied to the global row line 625, the signal 636 may be applied to the phase reversal line 635-a, the signal 641 may be applied to the phase line 640-a, and the signal 631 may be applied to the word line 630-a. The signals applied to each of the lines may activate or deactivate a particular select transistor to a level that provides a sufficiently strong drive for the desired slew rate of the word line 630-a, while preventing overdrive that might otherwise cause the select transistor to break down over time.

[0118] At t0, the first access line 625 (e.g., global row line 625) and the fourth access line 640-a (e.g., phase line 640-a) may each be maintained at a first level (e.g., VNWL). In some instances, VNWL may be a relatively low (or negative) voltage level. At t0, the third access line 635-a (e.g., phase reversal line 635-a) may be maintained at a second level (e.g., VCCP). In some instances, the third access line 635-a may be driven (e.g., actively driven) to a second level, and the second level may be a level higher than the first level (e.g., VCCP may be higher than VNWL). When the phase reversal line 635-a is maintained at the second level (or driven to the second level), the selection device 615-a may be activated, thereby coupling the word line 630-a to the voltage source (e.g., VNWL). Additionally or alternatively, when the phase reversal line 635-a is maintained at the second level (or driven to the second level) and the phase line 640-a is maintained at the first level, the select device 610-a (and any select devices located in the SWD gap) may be deactivated. Thus, at t0, the global row line 625 may not be coupled to the word line 630-a.

[0119] At t1, the phase reversal line 635-a may transition to a first level (e.g., to VNWL). In some instances, the phase reversal line 635-a may be driven (e.g., actively driven) to VNWL. Additionally or alternatively, the phase line 640-a may transition to a third level (e.g., VCCP2), which may be higher than the second level (e.g., VCCP2 may be higher than VCCP). In some instances, the phase line 640-a may be driven (e.g., actively driven) to VCCP2. At t1, the global row line 625 may be maintained at a first level (e.g., at VNWL). As described herein, the global row line 625 may be driven (e.g., actively driven) to a first level. Thus, at t1, the word line 630-a may remain at the first level (e.g., at VNWL).

[0120] In some examples (not shown), the phase reversal line 635-a may be driven to a fourth level (eg, to VNWL_DEEP), as shown in FIG. Figure 4AAs described. For example, the phase reversal line 635-a can be driven (e.g., actively driven) to VNWL_DEEP. Driving the phase reversal line 635-a to VNWL_DEEP can ensure that the selection device 610-a and the selection devices 620-c and 620-d are activated with sufficient drive strength. As discussed herein, VNWL_DEEP can be a relatively low voltage that activates the selection devices 610-a and 620-c more strongly than, for example, applying VNWL. By applying VNWL_DEEP and more strongly activating the selection devices 610-a and 620-c, the voltage of the word line 630-a can increase from VNWL to VCCP more quickly.

[0121] When the phase inversion line 635-a is driven to the first level or the fourth level, the selection device 615-a can be deactivated and the selection devices 610-a, 620-c (and any other PMOS selection devices 620 located in the SWD gap) can be activated, thereby coupling the global row line 625 with the word line 630-a. In addition, when the phase line 340 is driven to the third level, the selection device 620-a (and any other NMOS selection devices located in the SWD gap) can be activated, thereby coupling the global row line 625 with the word line 630-a.

[0122] At t2, the global row line 625 may be driven to a second level (e.g., to VCCP), and the phase reversal line 635-a and the phase line 640-a may be maintained at the same level. Because the global row line 625 may be coupled to the word line 630-a (e.g., based on the signaling at t1), the word line 630-a may begin to transition to the second level (e.g., to VCCP). Therefore, the word line 630-a may reach VCCP for a duration after t2 (and before t3).

[0123] At t3, the phase line 640-a may be driven to the second level (e.g., to VCCP) and the global row line 625 may be maintained at the same level. If the phase reversal line 635-a was driven to the fourth level at t1, it may be driven to the first level at t3. If the phase reversal line 635-a was driven to the first level at t1, it may be maintained at the first level at t3. The second level (e.g., VCCP) may be a threshold voltage of the selection device 620-a that is lower than the third level (e.g., VCCP2). Therefore, driving the phase line 640-a to the second level may not deactivate the selection device 620-a (or any other NMOS selection device located in the SWD gap). Alternatively, the selection device 620-a may remain activated and the word line 630-a may be maintained at the second level (e.g., at VCCP). For example, driving the gate of select device 620-a to VCCP2 can ensure that the entire transition of word line 630-a occurs without select device 620-a being at cutoff or subthreshold, and can therefore be actively driven using select device 620-a. If VCCP is used on the gate of select device 620-a during the transition of word line 630-a, select device 620-a can provide good drive strength for word line 630-a until word line 630-a reaches a threshold below VCCP. At this point (e.g., when word line 630-a reaches a threshold below VCCP), select device 620-a can begin to operate in the subthreshold or cutoff region, where the strength of the select device is much lower. Therefore, word line 630-a will be effectively driven to VCCP by PMOS select devices 610-a and 620-c. Additionally, once word line 630-a reaches VCCP, reducing the gate voltage on select device 620-a may also effectively place the select device at a subthreshold or cutoff value. However, because word line 630-a is already driven (e.g., to VCCP), less drive is required to maintain word line 630-a at VCCP, thereby mitigating any effects of word line 630-a being driven only by PMOS select devices 610-a and 620-c. Thus, driving phase line 640-a to VCCP may prevent overdrive on select device 620-a that would otherwise cause select device 620-a to break down over time.

[0124] At t4, the phase line 640-a may be driven to a third level (e.g., to VCCP2), and the global row line 625 may be maintained at the same level. In some examples, the phase line 640-a may not be driven to the third level within the second time, but may be driven to the second level (e.g., VCCP) for an extended duration (e.g., until t6). In some examples, the phase reversal line 635-a may be driven to a fourth level (not shown) at t4. Alternatively, the phase reversal line 635-a may be maintained at the first level at t4.

[0125] At t5, the global row line 625 may be driven to a first level (e.g., to VNWL), and the phase reversal line 635-a and the phase line 640-a may be maintained at the same level. Because the global row line 625 may be coupled to the word line 630-a (e.g., based on the levels of the phase line 640-a and the phase reversal line 635-a), the word line 630-a may begin to transition downward to the first level (e.g., to VNWL). Therefore, for a duration after t5 (and before t6), the word line 630-a may reach VNWL.

[0126] At t6, the phase reversal line 635-a may transition to the second level (e.g., to VCCP). In some examples, the phase reversal line 635-a may be driven (e.g., actively driven) to VCCP. At t6, the phase line 640-a may transition to the first level (e.g., VNWL). In some examples, the phase line 640-a may be driven (e.g., actively driven) to VNWL. At t6, the global row line 625 may be maintained at the first level (e.g., at VNWL).

[0127] When the phase inversion line 635-a is driven to the second level, the selection device 615-a may be activated and the selection device 610-a (and any other PMOS selection devices located in the SWD gap) may be deactivated, thereby coupling the word line 630-a to the voltage source (e.g., to VNWL). In addition, when the phase line 640-a is driven to the first level, the selection device 620-a may be deactivated, thereby decoupling the global row line 625 from the word line 630-a. Thus, referring to Figure 6B The described timing scheme can provide sufficiently strong drive for the desired slew rate of word line 630-a while preventing overdrive that might otherwise cause select device 620 to break down over time.

[0128] Figure 7 A block diagram 700 is shown of a memory device 720 supporting a sub-word line driver according to an example as disclosed herein. The memory device 720 may be a memory device as described in reference to Figure 16. The memory device 720 or its various components may be examples of devices for performing various aspects of the sub-word line driver as described herein. For example, the memory device 720 may include a third access line driver 725, a first access line driver 730, a fourth access line driver 735, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0129] The third access line driver 725 may be configured as or otherwise support means for driving the third access line and the fourth access line to complementary levels at a first time and when the first access line is at a first level, wherein at least one of the complementary levels is different from the first level and a second level associated with a second access line, the second access line providing access to a subset of the memory cell array, and wherein the first access line is coupled to the second access line via a first selection device of a first type and a second selection device of a second type based at least in part on driving at least one of the third access line and the fourth access line to the complementary levels.

[0130] In some examples, the third access line driver 725 may be configured as or otherwise support means for driving the third access line and the fourth access line to complementary levels at a fourth time and when the first access line is at the second level. In some examples, the third access line driver 725 may be configured as or otherwise support means for driving the third access line to a third level at a first time based at least in part on driving the fourth access line to the first level, wherein the third level is lower than the first level and the second level.

[0131] In some examples, the third access line driver 725 may be configured as or otherwise support means for performing the following operations: after driving the third access line to the third level, at a fifth time, driving the third access line to a first level, wherein the first level is greater than the third level and less than at least the second level. In some examples, the second selection means is configured to couple the first access line with the second access line based at least in part on the third access line.

[0132] The first access line driver 730 may be configured as or otherwise support means for driving the first access line to a second level at a second time.

[0133] The fourth access line driver 735 may be configured as or otherwise support means for driving the third access line to the second level and the fourth access line to the first level at a third time based at least in part on driving the first access line to the second level.

[0134] Figure 8A flow chart illustrating a method 800 for supporting a sub-word line driver according to an example as disclosed herein is shown. The operations of the method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 800 may be implemented by a memory device or components thereof as described herein. Figures 1 to 7 The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform various aspects of the described functions.

[0135] At 805, the method may include driving a third access line and a fourth access line to complementary levels at a first time and when the first access line is at a first level, wherein at least one of the complementary levels is different from the first level and a second level associated with a second access line that provides access to a subset of the array of memory cells, and wherein the first access line is coupled to the second access line via a first selection device of a first type and a second selection device of a second type based at least in part on driving at least one of the third access line and the fourth access line to the complementary levels. The operations of 805 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 805 may be performed as described with reference to Figure 7 The third access line driver 725 described above is implemented.

[0136] At 810, the method may include driving the first access line to a second level at a second time. The operations of 810 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 810 may be performed as described in reference to Figure 7 The first access line driver 730 described above is implemented.

[0137] At 815, the method may include driving the third access line to the second level and the fourth access line to the first level at a third time based at least in part on driving the first access line to the second level. The operations of 815 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 815 may be implemented as described in reference to Figure 7 The fourth access line driver 735 described above is performed.

[0138] At 820, the method may include driving the third access line and the fourth access line to complementary levels at a fourth time and when the first access line is at the second level. The operations of 820 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 820 may be implemented as described in reference to Figure 7 The third access line driver 725 described above is implemented.

[0139] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: driving a third access line and a fourth access line to complementary levels at a first time and when the first access line is at a first level, wherein at least one of the complementary levels is different from the first level and a second level associated with a second access line, the second access line providing access to a subset of an array of memory cells, and wherein the first access line is coupled to the second access line via a first selection device of a first type and a second selection device of a second type based at least in part on driving at least one of the third access line and the fourth access line to the complementary levels; driving the first access line to the second level at a second time; driving the third access line to the second level and the fourth access line to the first level at a third time based at least in part on driving the first access line to the second level; and driving the third access line and the fourth access line to the complementary levels at a fourth time and when the first access line is at the second level.

[0140] In some examples of methods 800 and apparatus described herein, the third access line is driven to a third level at a first time based at least in part on driving the fourth access line to the first level, where the third level may be lower than the first level and the second level.

[0141] In some examples of methods 800 and apparatus described herein, the third access line is driven to a first level at a fifth time after the third access line is driven to a third level, where the first level may be greater than the third level and less than at least the second level.

[0142] In some examples of the method 800 and apparatus described herein, the second selection device may be configured to couple the first access line with the second access line based at least in part on the third access line.

[0143] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0144] An apparatus is described. The apparatus may include: a memory cell array arranged in a plurality of sub-arrays each including a plurality of memory cells; a first selection device of a first type located on a first side of a first sub-array of the plurality of sub-arrays, wherein the first selection device is configured to couple the first access line with a second access line based at least in part on a third access line, the second access line accessing a subset of the memory cell array for an access operation after transitioning from a first level to a second level higher than the first level; a second selection device of a second type located on a second side of the first sub-array of the plurality of sub-arrays, wherein the second selection device is configured to couple the first access line with a second access line based at least in part on a third access line, the second access line accessing a subset of the memory cell array for an access operation after transitioning from a first level to a second level higher than the first level; a fourth access line and coupling the first access line with the second access line; and a controller coupled to the first selection device and the second selection device, the controller being configured to: drive the third access line to the first level and the fourth access line to a third level at a first time, wherein the third level is higher than the second level; drive the first access line to the second level at a second time; drive the fourth access line to the second level at a third time; and drive the fourth access line to the third level at a fourth time, the fourth time occurring after the third time and when the first access line is at the second level.

[0145] In some examples, the apparatus may include driving the first access line to the first level at a fifth time occurring after the fourth time.

[0146] In some examples, the apparatus may include a third selection device of the first type located on the second side of a second subarray of the plurality of subarrays, wherein the third selection device may be configured to couple the first access line with the second access line based at least in part on the third access line.

[0147] In some examples, the apparatus may include driving the third access line to a fourth level at the first time.

[0148] In some examples of the apparatus, the first access line may be associated with a timing of the access operation.

[0149] In some examples, the apparatus may include a plurality of second selection devices of the second type located on the second side of each subarray of at least a subset of the plurality of subarrays.

[0150] In some examples of the apparatus, the second level may be a threshold voltage of the second selection device that is lower than the third level.

[0151] In some examples of the apparatus, the first selection means includes a p-channel transistor and the second selection means includes an n-channel transistor.

[0152] Another apparatus is described. The apparatus may include: a memory cell array arranged in a plurality of sub-arrays each including a plurality of memory cells; a first selection device of a first type located on a first side of a first sub-array of the plurality of sub-arrays, wherein the first selection device is configured to couple the first access line with a second access line based at least in part on a third access line, the second access line accessing a subset of the memory cell array for an access operation after transitioning from a first level to a second level higher than the first level; a second selection device of the first type located on a second side of the first sub-array of the plurality of sub-arrays, wherein the second selection device is configured to couple the first access line with the second access line based at least in part on the third access line; a controller coupled to the first selection device and the second selection device, the controller being configured to: drive the third access line to a third level at a first time, wherein the third level is lower than the first level and the second level; and drive the first access line to the second level at a second time after the first time.

[0153] In some examples, the apparatus may include driving the third access line to the first level at a third time, wherein the third time occurs after the second time and when the first access line may be driven to the second level.

[0154] In some examples, the apparatus may include driving the third access line to the third level at a fourth time, the fourth time occurring after the third time and when the first access line may be driven to the second level.

[0155] In some examples, the apparatus may include driving the first access line to the first level at a fifth time after the fourth time and driving the third access line to the second level at a sixth time, the sixth time occurring after the fifth time and when the first access line can be driven to the first level.

[0156] In some examples, the apparatus may include a third selection device of a second type located on the first side of the first subarray of the plurality of subarrays, wherein the third selection device may be configured to pull down the second access line based at least in part on a fourth access line, wherein the controller may be configured to drive the fourth access line to the first level at the first time, wherein at least a portion of the third access line may be inverted relative to the fourth access line.

[0157] In some examples of the apparatus, the first access line and the third access line are each decodable from separate bits of an address.

[0158] In some examples of the apparatus, the third access line may be associated with selecting a plurality of word lines of the first subarray, and the first access line may be associated with selecting a single word line of the plurality of word lines based at least in part on the first access line being driven to the second level.

[0159] In some examples of the apparatus, the first selection means and the second selection means each include a p-channel transistor.

[0160] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0161] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between the components that are electronically connected with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0162] The term "coupled" refers to a condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between the components via a conductive path, to a closed circuit relationship between the components, in which signals are able to communicate between the components via the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0163] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between the components, the components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, the controller implements a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0164] The devices including memory arrays discussed herein may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0165] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may make the channel conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0166] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to other examples." The detailed description includes specific details that provide an understanding of the described technology. However, embodiments may be implemented without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0167] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0168] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0169] For example, the various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0170] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be understood to refer to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on".

[0171] Computer-readable media include both non-transitory computer storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the desired program code device in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor. And, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, the coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0172] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a memory cell array arranged in a plurality of sub-arrays each comprising a plurality of memory cells; a first selection device of a first type located on a first side of a first subarray of the plurality of subarrays, wherein the first selection device is configured to couple the first access line with a second access line based at least in part on a third access line, the second access line accessing a subset of the memory cell array for an access operation after transitioning from a first level to a second level higher than the first level; a second selection device of a second type located on a second side of the first of the plurality of subarrays, wherein the second selection device is configured to couple the first access line with the second access line based at least in part on a fourth access line; as well as a controller coupled to the first selection device and the second selection device, the controller being configured to: driving the third access line to the first level and the fourth access line to a third level at a first time, wherein the third level is higher than the second level; driving the first access line to the second level at a second time; driving the fourth access line to the second level at a third time; and The fourth access line is driven to the third level at a fourth time that occurs after the third time and when the first access line is at the second level.

2. The apparatus of claim 1, wherein the controller is configured to: The first access line is driven to the first level at a fifth time occurring after the fourth time.

3. The apparatus according to claim 1, further comprising: A third selection device of the first type is located on the second side of a second subarray of the plurality of subarrays, wherein the third selection device is configured to couple the first access line with the second access line based at least in part on the third access line.

4. The apparatus of claim 3, wherein the controller is configured to: The third access line is driven to a fourth level at the first time.

5. The apparatus of claim 1, wherein the first access line is associated with a timing of the access operation.

6. The apparatus of claim 1, further comprising: A plurality of second selection devices of the second type are located on the second side of each sub-array of at least a subset of the plurality of sub-arrays.

7. The apparatus of claim 1, wherein the second level is a threshold voltage of the second selection device that is lower than the third level.

8. The apparatus of claim 1, wherein the first selection means comprises a p-channel transistor and the second selection means comprises an n-channel transistor.

9. A device comprising: a memory cell array arranged in a plurality of sub-arrays each comprising a plurality of memory cells; a first selection device of a first type located on a first side of a first subarray of the plurality of subarrays, wherein the first selection device is configured to couple the first access line with a second access line based at least in part on a third access line, the second access line accessing a subset of the memory cell array for an access operation after transitioning from a first level to a second level higher than the first level; a second selection device of the first type located on a second side of the first of the plurality of subarrays, wherein the second selection device is configured to couple the first access line with the second access line based at least in part on the third access line; as well as a controller coupled to the first selection device and the second selection device, the controller being configured to: driving the third access line to a third level at a first time, wherein the third level is lower than the first level and the second level; and The first access line is driven to the second level at a second time after the first time.

10. The apparatus of claim 9, wherein the controller is configured to: The third access line is driven to the first level at a third time, wherein the third time occurs after the second time and when the first access line is driven to the second level.

11. The apparatus of claim 10, wherein the controller is configured to: The third access line is driven to the third level at a fourth time that occurs after the third time and when the first access line is driven to the second level.

12. The apparatus of claim 11, wherein the controller is configured to: driving the first access line to the first level at a fifth time after the fourth time; and The third access line is driven to the second level at a sixth time that occurs after the fifth time and when the first access line is driven to the first level.

13. The apparatus of claim 9, further comprising: a third selection device of a second type located on the first side of the first of the plurality of subarrays, wherein the third selection device is configured to pull down the second access line based at least in part on a fourth access line, wherein the controller is configured to: The fourth access line is driven to the first level at the first time, wherein at least a portion of the third access line is inverted relative to the fourth access line.

14. The apparatus of claim 9, wherein the first access line and the third access line are each decoded from a separate bit of an address.

15. The apparatus according to claim 9, wherein The third access line is associated with a plurality of word lines that select the first sub-array, and The first access line is associated with selecting a single word line of the plurality of word lines based at least in part on the first access line being driven to the second level.

16. The apparatus of claim 9, wherein the first selection means and the second selection means each comprise a p-channel transistor.

17. A method comprising: driving a third access line and a fourth access line to complementary levels at a first time and while the first access line is at a first level, wherein at least one of the complementary levels is different from the first level and a second level associated with a second access line, the second access line providing access to a subset of an array of memory cells, and wherein the first access line is coupled to the second access line via a first selection device of a first type and a second selection device of a second type based at least in part on driving at least one of the third access line and the fourth access line to the complementary levels; driving the first access line to the second level at a second time; driving the third access line to the second level and the fourth access line to the first level at a third time based at least in part on driving the first access line to the second level; as well as The third access line and the fourth access line are driven to the complementary level at a fourth time and while the first access line is at the second level.

18. The method according to claim 17, further comprising: The third access line is driven to a third level at the first time based at least in part on driving the fourth access line to the first level, wherein the third level is lower than the first level and the second level.

19. The method according to claim 18, further comprising: After the third access line is driven to the third level, the third access line is driven to the first level at a fifth time, wherein the first level is greater than the third level and less than at least the second level.

20. The method of claim 17, wherein the second selection means is configured to couple the first access line with the second access line based at least in part on the third access line.

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