NAND error handling method, device, computer equipment and storage medium with static ECC error correction

Abstract

The present invention relates to a NAND error handling method, device, computer equipment, and storage medium for static ECC error correction. The method comprises: if an ECC error occurs when reading page data, entering a normal flash memory reread state; determining whether an ECC error occurs when entering the normal flash memory reread state; if an ECC error occurs, determining whether all levels of flash memory reread have been completed; if so, performing static ECC error correction; determining whether an ECC error occurs when performing static ECC error correction; if an ECC error occurs, obtaining a PE value and right-shifting the PE value by 10 bits to obtain an L value; determining whether the number of static ECC error correction cycles is equal to the L value; if equal to the L value, performing Riad decoding. The present invention gradually enhances the error correction capability under static ECC and improves the static ECC error correction process, thereby achieving efficient static ECC error correction NAND error process protection.

Description

Technical Field

[0001] The present invention relates to the technical field of static ECC error correction, and in particular to a NAND error processing method, device, computer equipment and storage medium for static ECC error correction. Background Art

[0002] Currently, most SSDs use static ECC error correction. The size of the ECC correction unit (user data) and ECC calibration data remains fixed throughout the SSD's lifecycle, meaning the error correction capability remains constant. While the probability of bit flips in flash memory is low during initial use, the probability of errors increases with use.

[0003] The current traditional NAND error process is that after Read page (reading page data), once ECC fail occurs, it will enter Read Retry (flash memory rereading). If ECC fail still occurs, it will enter static ECC error correction. If ECC fail still occurs, it will enter Raid. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a NAND error handling method, apparatus, computer equipment and storage medium with static ECC error correction.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] In a first aspect, this embodiment provides a NAND error handling method with static ECC error correction, comprising the following steps:

[0007] If an ECC error occurs when reading page data, the normal flash memory reread state is entered;

[0008] Determine whether an ECC error occurs when entering the normal flash memory reread state;

[0009] If an ECC error occurs when entering the normal flash memory reread state, it is determined whether the flash memory reread has completed all levels;

[0010] If the flash memory has completed all levels of rereading, static ECC error correction is performed;

[0011] Determine whether an ECC error occurs when performing static ECC error correction;

[0012] If an ECC error occurs when performing static ECC error correction, the PE value is obtained and the PE value is right-shifted by 10 bits to obtain the L value;

[0013] Determine whether the number of static ECC error correction cycles is equal to the L value;

[0014] If the number of static ECC error correction cycles is equal to the L value, Riad decoding is performed.

[0015] Its further technical solution is: if an ECC error occurs when entering the normal flash memory reread state, it is determined whether the flash memory reread has completed all level steps. If the flash memory reread has not completed all levels, the number of levels required to execute the flash memory reread is increased, and the process returns to execution. If an ECC error occurs when reading page data, the process enters the normal flash memory reread state.

[0016] A further technical solution is: if the flash memory has completed rereading all levels, static ECC error correction is performed in the step of performing static ECC error correction by using a low-density parity check code.

[0017] Its further technical solution is: after the step of determining whether the number of static ECC error correction cycles is equal to the L value, it also includes: if the number of static ECC error correction cycles is not equal to the L value, recording the number of static ECC error correction cycles, and returning to execute the static ECC error correction if the flash memory reread has completed all levels.

[0018] In a second aspect, this embodiment provides a NAND error handling device with static ECC error correction, comprising: an entry unit, a first judgment unit, a second judgment unit, a first execution unit, a third judgment unit, an acquisition unit, a fourth judgment unit, and a second execution unit;

[0019] The occurrence entry unit is used to enter a normal flash memory reread state if an ECC error occurs in reading page data;

[0020] The first judging unit is used to judge whether an ECC error occurs when entering a normal flash memory reread state;

[0021] The second judgment unit is used to judge whether the flash memory reread has completed all levels if an ECC error occurs when the flash memory enters a normal reread state;

[0022] The first execution unit is configured to perform static ECC error correction if the flash memory has completed rereading all levels;

[0023] The third judgment unit is used to judge whether an ECC error occurs during the static ECC error correction;

[0024] The obtaining unit is configured to obtain a PE value if an ECC error occurs when performing static ECC error correction, and right-shift the PE value by 10 bits to obtain an L value;

[0025] The fourth judgment unit is used to judge whether the number of static ECC error correction cycles is equal to the L value;

[0026] The second execution unit is configured to perform Riad decoding if the number of cycles of static ECC error correction is equal to the L value.

[0027] Its further technical solution is: it also includes: adding a return unit, which is used to increase the number of levels required to reread the flash memory if the flash memory reread has not completed all levels, and return to execute the said if an ECC error occurs in reading page data, then enter the normal flash memory reread state.

[0028] A further technical solution is: in the first execution unit, static ECC error correction is performed through low-density parity check code.

[0029] Its further technical solution is: it also includes: an error correction return unit, which is used to record the number of static ECC error correction cycles if the number of static ECC error correction cycles is not equal to the L value, and return to execute the static ECC error correction if the flash memory reread has completed all levels.

[0030] In a third aspect, this embodiment provides a computer device, comprising a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the NAND error handling method with static ECC error correction as described above is implemented.

[0031] In a fourth aspect, this embodiment provides a storage medium storing a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the NAND error handling method with static ECC error correction as described above can be implemented.

[0032] The beneficial effects of the present invention compared with the prior art are: with the use of solid-state hard drives, the error correction capability under static ECC is gradually enhanced, the static ECC error correction process is improved, and thus efficient static ECC error correction NAND error process protection is achieved.

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1A flowchart of a NAND error handling method using static ECC error correction provided by an embodiment of the present invention;

[0036] Figure 2 A schematic block diagram of a NAND error handling device with static ECC error correction provided by an embodiment of the present invention;

[0037] Figure 3 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0039] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0040] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0041] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0042] The present invention relates to the following English words, and the corresponding translations are as follows:

[0043] ECC is the abbreviation of "Error Correcting Code". ECC is a technology that can achieve "error checking and correction";

[0044] NAND, particles, flash memory;

[0045] PE, which means P / E with a slash in the middle, stands for P / ECycle (P / E for short), and is used to indicate the number of times the Flash memory can be erased and written. Each time the entire SSD is programmed (written) or erased once, one P / E count is counted.

[0046] Read page, read page data;

[0047] Raid is the abbreviation of "Redundant Array of Independent Disk", which means independent redundant disk array in Chinese;

[0048] Read Retry, flash memory reread;

[0049] ECC fail, Error Correcting Code error;

[0050] Retry Table Read Retry, normal read retry (flash reread) process;

[0051] Level, different gears of flash memory reread;

[0052] LDPC, encoding and decoding technology, the abbreviation of Low Density Parity Check Code, means low-density parity check code;

[0053] TLC PE, TLC among flash memory SLC, MLC, and TLC, triple level cell (TLC for short);

[0054] RAID Decode, RAID decoding.

[0055] See also Figure 1 In the specific embodiment shown, the present invention discloses a NAND error handling method with static ECC error correction, comprising the following steps:

[0056] S1: If an ECC error occurs when reading page data, the normal flash memory reread state is entered;

[0057] Specifically, the data that the user needs to transmit is encoded through LDPC, CRC and other codecs to form ECC check bits. When receiving data, the data and ECC check bits will be decoded through LDPC, CRC, etc. If the decoding is correct, it means the data is correct (ECC pass); if the decoding fails, it means the data is wrong (ECC fail); Among them, there is an ECC error correction module on the solid-state drive controller, and some flash memories also integrate an ECC error correction module. Commonly used flash memory ECC error correction algorithms include BCH and LDPC.

[0058] S2, determining whether an ECC error occurs when the flash memory enters a normal reread state; if no ECC error occurs when the flash memory enters a normal reread state, then the operation ends;

[0059] The ECC error in step S2 is similar to the ECC error in step S1.

[0060] S3, if an ECC error occurs when the flash memory enters a normal reread state, it is determined whether the flash memory reread has completed all levels; if the flash memory reread has not completed all levels, the process jumps to step S9;

[0061] S4, if the flash memory has completed all levels of rereading, static ECC error correction is performed;

[0062] Specifically, in step S4, static ECC error correction is performed using a low-density parity-check code.

[0063] Specifically, LDPC is a commonly used codec, so simply stating that it's used is sufficient. Simply put, it provides a computationally moderate array, known as a parity-check code, which is encoded with the data. This code is then used for cyclic decoding, similar to the parity-check code used for decoding. This is a commonly used codec, and the relevant knowledge is universal.

[0064] S5, determining whether an ECC error occurs when performing static ECC error correction; if no ECC error occurs when performing static ECC error correction, then ending the operation;

[0065] The ECC error in step S5 is similar to the ECC error in step S1 described above. Specifically, static ECC refers to a fixed parity bit length for encoding and decoding (hence the word "static"). Dynamic ECC refers to a variable parity bit length. To further explain the difference between static and dynamic ECC, most SSDs currently use static ECC error correction schemes. The size of the ECC error correction unit (user data) and ECC calibration data remains fixed throughout the SSD's lifecycle, meaning the error correction capability remains constant. Since the probability of bit flips in flash memory is low during initial use, the probability of errors increases with use. Therefore, some SSDs have begun using dynamic ECC error correction schemes: initially, fewer error correction codes are used to store more user data in the flash memory pages. As the SSD uses itself, error correction capability needs to be enhanced. The smaller the proportion of user data in the flash memory pages, the larger the proportion of error correction codes. Dynamic ECC error correction schemes dynamically adjust the SSD's ECC error correction capability as it is used.

[0066] S6, if an ECC error occurs when performing static ECC error correction, obtain the PE value and right-shift the PE value by 10 bits to obtain the L value;

[0067] Specifically, the PE value is obtained and right-shifted by 10 bits, which has the effect of dividing PE by 1024 and rounding it up. For example, when TLCPE is less than 1024, L=0; if it is greater than 1024 and less than 2048, L=1.

[0068] Specifically, obtaining the PE value means that the firmware will count a table. Once it finds that the flash memory is completely erased once, it will be recorded as 1 P / E and saved in a specific space in the flash memory.

[0069] S7, determining whether the number of static ECC error correction cycles is equal to the L value; if the number of static ECC error correction cycles is not equal to the L value, jumping to step S10;

[0070] The firmware sets a maximum number of times, L, which means that the ECC error correction can be performed for a maximum of L times. The value of L is 0, 1, or other values.

[0071] S8, if the number of static ECC error correction cycles is equal to the L value, then perform Riad decoding;

[0072] Specifically, when Riad decoding is executed, the result is that the erroneous data is corrected, that is, an ECC error indicates that an error has occurred in the data, and the erroneous data is then corrected through Raid.

[0073] S9, increasing the number of levels required to reread the flash memory, and returning to the execution state of entering the normal flash memory reread state if an ECC error occurs in reading the page data;

[0074] Specifically, this is the flash memory reread function, which provides a way to adjust the reference voltage to reread data. Generally speaking, different flash memory manufacturers provide 36 levels of voltage adjustment. The Level here refers to these 36 levels of reference voltage adjustment, which gives the opportunity to read the correct data by adjusting the reference voltage.

[0075] S10, recording the number of cycles of static ECC error correction, and returning to execute the static ECC error correction if the flash memory has completed rereading all levels.

[0076] Specifically, static ECC error correction will perform a cycle and record the number of cycles.

[0077] The present invention dynamically adjusts the static ECC error correction process according to the PE usage status, so that different static ECC error correction capabilities are used in different PEs. The static ECC error correction scheme can also gradually enhance its error correction capability as the solid-state drive is used, thereby improving the static ECC error correction process and realizing efficient static ECC error correction NAND error process protection.

[0078] See also Figure 2As shown, the present invention also discloses a NAND error handling device with static ECC error correction, comprising: an entry unit 10, a first judgment unit 20, a second judgment unit 30, a first execution unit 40, a third judgment unit 50, an acquisition unit 60, a fourth judgment unit 70 and a second execution unit 80;

[0079] The occurrence entry unit 10 is used to enter the normal flash memory reread state if an ECC error occurs in reading page data;

[0080] The first determination unit 20 is used to determine whether an ECC error occurs when the flash memory enters a normal reread state;

[0081] The second judgment unit 30 is used to judge whether the flash memory reread has completed all levels if an ECC error occurs when the flash memory enters a normal reread state;

[0082] The first execution unit 40 is configured to perform static ECC error correction if the flash memory has completed rereading all levels;

[0083] The third judgment unit 50 is used to judge whether an ECC error occurs during the static ECC error correction;

[0084] The obtaining unit 60 is configured to obtain a PE value if an ECC error occurs during static ECC error correction, and right-shift the PE value by 10 bits to obtain an L value;

[0085] The fourth judgment unit 70 is used to judge whether the number of static ECC error correction cycles is equal to the L value;

[0086] The second execution unit 80 is configured to execute Riad decoding if the number of static ECC error correction cycles is equal to the L value.

[0087] The device further includes: an increasing return unit 90 for increasing the number of levels required for flash memory rereading if all levels are not completed, and returning to execute the above-mentioned step of entering a normal flash memory rereading state if an ECC error occurs in reading page data.

[0088] Wherein, in the first execution unit 40, static ECC error correction is performed by low-density parity-check code.

[0089] The device further includes an error correction return unit 100 for recording the number of static ECC error correction cycles if the number of static ECC error correction cycles is not equal to the L value, and returning to execute the static ECC error correction if the flash memory has completed all levels of rereading.

[0090] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the NAND error handling device and each unit of the above-mentioned static ECC error correction can refer to the corresponding description in the aforementioned method embodiment. For the convenience and brevity of the description, it will not be repeated here.

[0091] The NAND error handling device with static ECC correction can be implemented as a computer program. Figure 3 Runs on the computer equipment shown.

[0092] See also Figure 3 , Figure 3 This is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 500 can be a terminal or a server. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, personal digital assistant, wearable device, or other electronic device with communication capabilities. The server can be a standalone server or a server cluster consisting of multiple servers.

[0093] See Figure 3 The computer device 500 includes a processor 502 , a memory, and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .

[0094] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions, which, when executed, can cause the processor 502 to execute a NAND error handling method using static ECC error correction.

[0095] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500.

[0096] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a NAND error handling method with static ECC error correction.

[0097] The network interface 505 is used to communicate with other devices through the network. Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 500 to which the solution of the present application is applied. The specific computer device 500 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0098] The processor 502 is configured to execute a computer program 5032 stored in the memory to implement the following steps:

[0099] Step S1: If an ECC error occurs when reading page data, the normal flash memory reread state is entered;

[0100] Step S2, determining whether an ECC error occurs when entering a normal flash memory reread state;

[0101] Step S3: If an ECC error occurs when the flash memory enters a normal reread state, it is determined whether the flash memory reread has completed all levels;

[0102] Step S4: If the flash memory has completed all levels of rereading, static ECC error correction is performed;

[0103] Step S5, determining whether an ECC error occurs when performing static ECC error correction;

[0104] Step S6: If an ECC error occurs when performing static ECC error correction, obtain the PE value and right-shift the PE value by 10 bits to obtain the L value;

[0105] Step S7, determining whether the number of static ECC error correction cycles is equal to the L value;

[0106] Step S8: If the number of static ECC error correction cycles is equal to the L value, Riad decoding is performed.

[0107] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0108] Those skilled in the art will appreciate that all or part of the steps in the method of the above-described embodiment can be implemented by instructing the relevant hardware through a computer program. The computer program includes program instructions, which can be stored in a storage medium that is computer-readable. The program instructions are executed by at least one processor in the computer system to implement the steps in the method of the above-described embodiment.

[0109] Therefore, the present invention also provides a storage medium. The storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the NAND error handling method with static ECC error correction can be implemented. The storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the NAND error handling method with static ECC error correction can be implemented. The program instructions include the following steps:

[0110] Step S1: If an ECC error occurs when reading page data, the normal flash memory reread state is entered;

[0111] Step S2, determining whether an ECC error occurs when entering a normal flash memory reread state;

[0112] Step S3: If an ECC error occurs when the flash memory enters a normal reread state, it is determined whether the flash memory reread has completed all levels;

[0113] Step S4: If the flash memory has completed all levels of rereading, static ECC error correction is performed;

[0114] Step S5, determining whether an ECC error occurs when performing static ECC error correction;

[0115] Step S6: If an ECC error occurs when performing static ECC error correction, obtain the PE value and right-shift the PE value by 10 bits to obtain the L value;

[0116] Step S7, determining whether the number of static ECC error correction cycles is equal to the L value;

[0117] Step S8: If the number of static ECC error correction cycles is equal to the L value, Riad decoding is performed.

[0118] The storage medium may be any computer-readable storage medium that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.

[0119] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0120] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the various units is merely a logical functional division, and actual implementation may employ other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0121] The steps in the methods of the embodiments of the present invention may be adjusted in order, combined, or deleted as needed. The units in the devices of the embodiments of the present invention may be combined, divided, or deleted as needed. Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0122] If this integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the existing technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, terminal, or network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present invention.

[0123] The above embodiments are preferred implementation schemes of the present invention. In addition, the present invention can also be implemented in other ways. Any obvious replacement without departing from the concept of the present technical solution is within the scope of protection of the present invention.

Claims

1. A NAND error handling method with static ECC error correction, characterized in that: The following steps are involved: If an ECC error occurs when reading page data, the normal flash memory reread state is entered; Determine whether an ECC error occurs when entering the normal flash memory reread state; If an ECC error occurs when entering the normal flash memory reread state, it is determined whether the flash memory reread has completed all levels; If the flash memory has completed all levels of rereading, static ECC error correction is performed; Determine whether an ECC error occurs when performing static ECC error correction; If an ECC error occurs when performing static ECC error correction, the PE value is obtained and the PE value is right-shifted by 10 bits to obtain the L value; Determine whether the number of static ECC error correction cycles is equal to the L value; If the number of static ECC error correction cycles is equal to the L value, Riad decoding is performed; Among them, obtaining the PE value means that the firmware counts a table. Once it is found that the flash memory is completely erased once, it will be recorded as 1 P / E and saved in a specific space of the flash memory; executing Riad decoding, the result is to correct the erroneous data, that is, the ECC error indicates that the data is erroneous, and the erroneous data is then corrected through Raid.

2. The NAND error handling method with static ECC correction according to claim 1, characterized in that: If an ECC error occurs when entering the normal flash memory reread state, it is determined whether the flash memory reread has completed all level steps. If the flash memory reread has not completed all levels, the number of levels required to execute the flash memory reread is increased, and the process returns to execution. If an ECC error occurs when reading page data, the normal flash memory reread state is entered.

3. The NAND error handling method with static ECC error correction according to claim 1, wherein: If the flash memory has completed rereading all levels, the static ECC error correction step is performed using a low-density parity check code.

4. The NAND error handling method with static ECC error correction according to claim 1, wherein: After the step of determining whether the number of static ECC error correction cycles is equal to the L value, the method further includes: if the number of static ECC error correction cycles is not equal to the L value, recording the number of static ECC error correction cycles, and returning to execute the step of performing static ECC error correction if the flash memory reread has completed all levels.

5. A NAND error handling device with static ECC error correction, characterized in that: include: An entry unit occurs, a first judgment unit, a second judgment unit, a first execution unit, a third judgment unit, an acquisition unit, a fourth judgment unit, and a second execution unit; The occurrence entry unit is used to enter a normal flash memory reread state if an ECC error occurs in reading page data; The first judging unit is used to judge whether an ECC error occurs when entering a normal flash memory reread state; The second judgment unit is used to judge whether the flash memory reread has completed all levels if an ECC error occurs when the flash memory enters a normal reread state; The first execution unit is configured to perform static ECC error correction if the flash memory has completed rereading all levels; The third judgment unit is used to judge whether an ECC error occurs during the static ECC error correction; The obtaining unit is configured to obtain a PE value if an ECC error occurs when performing static ECC error correction, and right-shift the PE value by 10 bits to obtain an L value; The fourth judgment unit is used to judge whether the number of static ECC error correction cycles is equal to the L value; The second execution unit is configured to perform Riad decoding if the number of static ECC error correction cycles is equal to the L value; Among them, obtaining the PE value means that the firmware counts a table. Once it is found that the flash memory is completely erased once, it will be recorded as 1 P / E and saved in a specific space of the flash memory; executing Riad decoding, the result is to correct the erroneous data, that is, the ECC error indicates that the data is erroneous, and the erroneous data is then corrected through Raid.

6. The NAND error handling device with static ECC correction according to claim 5, characterized in that: Also includes: A return unit is added for increasing the number of levels required for flash memory rereading if all levels are not completed, and returning to execute the above-mentioned step of entering a normal flash memory rereading state if an ECC error occurs in reading page data.

7. The NAND error handling device with static ECC correction according to claim 5, characterized in that: In the first execution unit, static ECC error correction is performed using low-density parity-check codes.

8. The NAND error handling device with static ECC error correction according to claim 5, characterized in that: Also includes: The error correction return unit is used to record the number of static ECC error correction cycles if the number of static ECC error correction cycles is not equal to the L value, and return to execute the static ECC error correction if the flash memory reread has completed all levels.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the NAND error handling method with static ECC error correction according to any one of claims 1 to 4 when executing the computer program.

10. A storage medium, characterized in that: The storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor, the NAND error handling method with static ECC error correction according to any one of claims 1 to 4 can be implemented.

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