Testing Method and System for DRAM Circuit

Abstract

The present application discloses a DRAM circuit test method and system. The test method is used in a DRAM circuit test system, and the DRAM circuit test system includes a register circuit and a DRAM circuit; the test method includes generating a first enable signal based on a read instruction, and sending the first enable signal to the register circuit; the register circuit obtains expected data via a data line based on the first enable signal; after obtaining the expected data, a delay signal is generated based on the read instruction, and the delay signal is sent to the DRAM circuit, the DRAM circuit reads the stored data in the DRAM based on the delay signal, and outputs the DRAM circuit test results obtained based on the expected data and the stored data via the data line. The DRAM circuit test method and system of the present application can shorten the test time of the DRAM circuit and improve the production and test efficiency of the DRAM circuit.

Description

Technical Field

[0001] This application relates to the technical field of memory testing, and in particular, to a testing method and system for a DRAM circuit. Background Art

[0002] During the production test of a dynamic random access memory (DRAM) circuit, the expected value of the test data is written into a register and then the test data is read from the DRAM, and it is compared whether the read value of the test data is consistent with the expected value. Before reading the test data, a dummy write operation needs to be performed first, that is, the expected value of the test data artificially set in the register is written into the register for comparison with the read value of the test data.

[0003] Since the data path formed by sharing the data line (which can also be called the input / output line IO line) for reading the test data and writing the expected value, it is necessary to complete the writing of the expected value through a special write command before the read command for reading the test data. In the prior art solutions, since the read command and the special write command need to occupy multiple clock cycles, the test time of the DRAM circuit is relatively long and the test efficiency is relatively low in the low-frequency environment of the test. Summary of the Invention

[0004] The main technical problem to be solved by this application is to provide a testing method and system for a DRAM circuit, which can shorten the test time of the DRAM circuit and improve the production test efficiency of the DRAM circuit.

[0005] To solve the above technical problem, a technical solution adopted by this application is to provide a testing method for a DRAM circuit. The testing method is used for a testing system of the DRAM circuit. The testing system of the DRAM circuit includes a register circuit and a DRAM circuit. The testing method includes generating a first enable signal based on a read command and sending the first enable signal to the register circuit; the register circuit obtains expected data via a data line based on the first enable signal; after obtaining the expected data, generating a delay signal based on the read command and sending the delay signal to the DRAM circuit. The DRAM circuit reads the stored data in the DRAM based on the delay signal and outputs the test result of the DRAM circuit obtained based on the expected data and the stored data via the data line.

[0006] To solve the above technical problems, another technical solution adopted by this application is to provide a test system for a DRAM circuit. The test system for the DRAM circuit includes a control circuit, a register circuit, and a DRAM circuit. The control circuit is configured to receive a read instruction and generate a first enable signal based on the read instruction. The register circuit is connected to the control circuit and is configured to obtain expected data via a data line based on the first enable signal. The DRAM circuit is connected to the control circuit and is configured to read stored data in the DRAM based on a delay signal and output a test result of the DRAM circuit obtained based on the expected data and the stored data via the data line. Among them, the control circuit further generates a delay signal after the register circuit obtains the expected data based on the read instruction.

[0007] Beneficial technical effects: In the DRAM circuit test method provided by this application, a first enable signal is generated based on a read instruction received by the control circuit. After the register circuit obtains the expected data (i.e., the expected value of the test data) under the control of the first enable signal, a delay signal is generated. The DRAM circuit reads the stored data in the DRAM (i.e., the read value of the test data) under the control of the delay signal. Therefore, this application can generate a first enable signal for completing the expected data writing operation and a delay signal for the stored data reading operation in the DRAM through one read instruction, which can shorten the instruction cycle of the control circuit, thereby shortening the test time of the DRAM circuit and improving the efficiency of the entire DRAM circuit test. Since the operation of obtaining the expected data (which can also be called the writing operation) needs to occupy the data line, and the operation of reading the stored data in the DRAM also needs to occupy the data line, this application uses the delay between the first enable signal and the delay signal to avoid the conflict of occupying the data line during the execution of the two operations, and can ensure the test effect. Further, the operation of outputting the test result also needs to occupy the data line, and this application further avoids the conflict of occupying the data line by these three operations. Description of the Drawings

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. Among them:

[0009] Figure 1 It is a schematic flowchart of an embodiment of the test method for the DRAM circuit of this application;

[0010] Figure 2 It is a schematic timing diagram of an embodiment in which the control circuit generates a first enable signal and a delay signal;

[0011] Figure 3It is a schematic flowchart of an embodiment of step S131;

[0012] Figure 4 It is a schematic structural diagram of an embodiment of a test system for a DRAM circuit of the present application;

[0013] Figure 5 It is a schematic timing diagram of an embodiment in which a control circuit of the present application generates a first enable signal, a precharge signal, and a second enable signal;

[0014] Figure 6 It is a schematic circuit diagram of an embodiment of a precharge circuit of the present application;

[0015] Figure 7 It is a schematic circuit diagram of another embodiment of a test system for a DRAM circuit of the present application;

[0016] Figure 8 It is a schematic circuit diagram of yet another embodiment of a test system for a DRAM circuit of the present application. Detailed implementation manners

[0017] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. According to the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0018] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly defined and limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific situations.

[0019] In the embodiments of the present application, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0020] The present application proposes a method for testing a DRAM circuit. Refer to Figure 1 ,Figure 1 This is a schematic flowchart of an embodiment of the test method for the DRAM circuit of the present application. The test method for the DRAM circuit of the present application is used for the test system of the DRAM circuit. The test system of the DRAM circuit includes a register circuit (not labeled in the figure) and the DRAM circuit 22 (refer to Figure 6 ). As Figure 1 shown, the test method for the DRAM circuit of the present application is executed by the control circuit 23. The test method for the DRAM circuit includes the following steps:

[0021] Step S110: Generate a first enable signal based on the read instruction and send the first enable signal to the register circuit.

[0022] The control circuit 23 receives a read instruction for testing the DRAM circuit 22 from the outside. After receiving the read instruction, the control circuit 23 generates a first enable signal and a delay signal successively. Among them, the first enable signal is sent to the register circuit. That is, when the control circuit 23 obtains a read instruction from the outside, it first generates a first enable signal.

[0023] Step S120: The register circuit obtains the expected data via the data line based on the first enable signal.

[0024] The register circuit receives the first enable signal of the control circuit 23 and, under the drive of the first enable signal, obtains the expected data via the data line.

[0025] Optionally, the register circuit (refer to Figure 5 ) includes a buffer register 211 and a local register 212 of the DRAM. The expected data can be pre-written into the buffer register 211. The register circuit writes the expected data pre-stored in the buffer register 211 into the local register 212 via the data line based on the first enable signal, so that the subsequent DRAM circuit 22 can obtain the expected data from the local register 212. It should be noted that, in one embodiment, the buffer register 211 is a global register of the entire DRAM device, and the local register 212 is a local register 212 possessed by each DRAM cell (such as each bank).

[0026] Step S130: After obtaining the expected data, generate a delay signal based on the read instruction and send the delay signal to the DRAM circuit. The DRAM circuit reads the stored data in the DRAM based on the delay signal and outputs the test result of the DRAM circuit obtained based on the expected data and the stored data via the data line.

[0027] After the register circuit obtains the expected data, the control circuit 23 generates a delay signal based on the read instruction and sends the delay signal to the DRAM circuit 22.

[0028] How to ensure that the control circuit 23 generates the delay signal for the DRAM circuit 22 after the register circuit obtains the expected data, so as to avoid the conflict of data line occupation between the register circuit and the DRAM circuit 22, will be described in detail later.

[0029] The DRAM circuit 22 reads the stored data in the DRAM based on the delay signal, and outputs the test result of the DRAM circuit 22 obtained based on the expected data and the stored data via the data line.

[0030] Based on the delay signal, after obtaining the expected data, the DRAM circuit 22 performs the operation of reading the stored data in the DRAM, completing the operation of the external read instruction.

[0031] In one embodiment, the DRAM circuit 22 includes a precharge circuit (not labeled in the figure). The operation of reading the stored data in the DRAM is the precharge-evaluate logic, that is, first use the precharge circuit to charge the data line to "1", and then discharge or hold the data line according to whether the read data is "0" or "1".

[0032] Specifically, the DRAM circuit 22 precharges the data line based on the delay signal after the register circuit obtains the expected data, so as to avoid the conflict of data line occupation between obtaining the expected data and precharging the data line.

[0033] The control circuit 23 generates a delay signal to the DRAM circuit 22 after generating the first enable signal based on the read instruction (in one embodiment, after the register circuit obtains the expected data). The DRAM circuit 22 precharges the data line based on the delay signal after the register circuit obtains the expected data (specific details can be referred to later).

[0034] After or at the same time as or before the DRAM circuit 22 precharges the data line, the stored data read from the DRAM cell (such as a bank) can be amplified and output. In one embodiment, the operation of amplifying and outputting the read stored data can also be controlled based on the delay signal or a third enable signal (not labeled in the figure) based on the delay signal. Since this operation itself does not occupy the data line, it will not be described in detail here.

[0035] In one embodiment of the control circuit 23, the DRAM circuit 22 further includes a comparison circuit 221, which obtains the expected data from the local register 212, and outputs the test result obtained by comparing the obtained expected data with the read stored data to the control circuit 23 via the data line based on the delay signal. In this embodiment, after the expected data uses up the data line, the test result is output via the data line to further avoid the conflict of data line occupation between obtaining the expected data and outputting the test result.

[0036] The control circuit 23 can be a Global controller (GC); the control circuit 23 generates a first enable signal and a delay signal successively based on the read instruction, and controls the desired data in the buffer register 211 to be written into the local register 212 near the second sensor amplifier (SSA) through the data line by the first enable signal; controls the DRAM circuit 22 to read the stored data in the DRAM through the data line based on the delay signal. The acquisition operation (which can also be called the write operation) of the desired data and the read operation of the stored data in the DRAM both occupy the data line. In this application, by generating a first enable signal and a delay signal having a delay relative to the first enable signal successively after receiving the read instruction, the conflict in occupying the data line during the execution of the two operations can be avoided, and the test effect can be ensured. Further, the operation of outputting the test result also needs to occupy the data line, and this application further avoids the conflict in occupying the data line by these three operations. In addition, generating the first enable signal and the delay signal based on the same read instruction can shorten the instruction cycle of the control circuit 23, thereby shortening the test time of the DRAM circuit 22 and improving the efficiency of the entire DRAM circuit 22 test.

[0037] Optionally, in step S110, the control circuit 23 generating the first enable signal based on the read instruction may further include the following steps:

[0038] Step S111: Receive the read instruction, and assert the first enable signal within the clock cycle of the read instruction.

[0039] Reference Figure 2 , after the control circuit 23 receives the read instruction, it "asserts" the first enable signal at time t0 within the clock cycle of the read instruction. Among them, "assert" means giving a signal an effective level, and this level can be a high level or a low level. "Asserting" the first enable signal can be understood as: the effective signal of the first enable signal can be a high level or a low level.

[0040] In step S130, the control circuit 23 generating the delay signal based on the read instruction may further include the following steps:

[0041] Step S131: Assert the delay signal within the clock cycle and after the effective pulse width of the first enable signal.

[0042] The control circuit 23 "asserts" the delay signal within the clock cycle and after the effective pulse width of the first enable signal.

[0043] Reference Figure 2, after the control circuit 23 receives a read instruction, it "asserts" a delay signal at time t1 within the clock cycle of the read instruction. Here, time t1 and time t0 can be within the same clock cycle of the read instruction, and it can be controlled that time t1 is after the effective pulse width p0 of the first enable signal, so that the operation of the DRAM circuit 22 to read stored data is after the operation of the register circuit to obtain the desired data, ensuring that the occupation of the data line during their respective executions does not conflict.

[0044] See Figure 2 , Figure 2 is a timing schematic diagram of an embodiment in which the control circuit of the present application generates a first enable signal and a delay signal. As Figure 2 shown, during the period when the control circuit 23 receives an external read instruction, at time t0 within the clock cycle during the instruction period, it "asserts" a first enable signal, and the register circuit obtains the desired data based on this first enable signal; the control circuit 23 "asserts" a delay signal at time t1 within this clock cycle and after the effective pulse width p0 of the first enable signal, and the DRAM circuit 22 reads the data stored in the DRAM based on the delay signal, and outputs the test result of the DRAM circuit obtained based on the desired data and the stored data via the data line. Among them, in order to ensure that the operation of the DRAM circuit 22 to read stored data is after the operation of the register circuit to obtain the desired data, assuming that the time difference between the rising edge of the clock cycle and the time when the first enable signal is "asserted" is t0, and the effective pulse width of the first enable signal is p0, and assuming that the time difference between the rising edge of the clock cycle and the time when the delay signal is "asserted" is t1, when the condition t1 > t0 + p0 is satisfied, the operation of reading stored data and the operation of obtaining desired data do not interfere with each other.

[0045] Optionally, the effective pulse width p0 of the first enable signal is set to a fixed pulse width, and the time t1 when the control circuit 23 "asserts" the delay signal is set to the time t0 when the first enable signal is "asserted" plus this fixed pulse width p0 to meet the condition of t1 > t0 + p0. By setting the first enable signal as a signal with a fixed pulse width, during the DRAM circuit test, the test time is further shortened and the test efficiency is improved.

[0046] See Figure 3 , Figure 3 is a flow schematic diagram of an embodiment of step S131. As Figure 3 shown, to further improve the control circuit 23 to "assert" the delay signal within the clock cycle and after the effective pulse width p0 of the first enable signal, the following steps are included:

[0047] Step S1311: Receive the feedback signal of the first enable signal.

[0048] The control circuit 23 receives a read command and issues a first enable signal. After the first enable signal triggers the register circuit to obtain the desired data, the first enable signal returns to the control circuit 23, that is, the control circuit 23 receives the feedback signal of the first enable signal. After the control circuit 23 receives the feedback signal of the first enable signal, it is considered that the register circuit has obtained the desired data. In an embodiment, the register circuit includes a buffer register 211 and a local register 212. The buffer register 211 is a global register of the entire DRAM device, and the local register 212 is a local register 212 possessed by each DRAM cell (for example, each bank). In this embodiment, the enable terminals of multiple local registers 212 can be connected in series, and the signal on the enable terminal of the last local register 212 in the series connection can be used as the aforementioned feedback signal, indicating that the last local register 212 is also enabled. Therefore, all local registers 212 have obtained the desired data.

[0049] Step S1312: Based on the feedback signal, "de-assert" the first enable signal and "assert" the delay signal.

[0050] The control circuit 23 "de-asserts" the first enable signal based on the feedback signal and "asserts" the delay signal to satisfy the condition of t1 > t0 + p0, where the time interval between the time t0 when the first enable signal is "asserted" and the time when the first enable signal is "de-asserted" is p0, and the time when the delay signal is "asserted" is t1. Among them, "de-assert" means giving a signal an invalid level, and this level can be a high level or a low level. "De-asserting" the first enable signal can be understood as: the invalid signal of the first enable signal can be a high-level signal or a low-level signal.

[0051] In this embodiment, within the clock cycle when the control circuit 23 issues the first enable signal and the delay signal, after receiving the feedback signal of the first enable signal, it is considered that the register circuit has obtained the desired data. Then the control circuit 23 "de-asserts" the first enable signal after the feedback signal and "asserts" the delay signal. The DRAM circuit 22 starts to execute the step of reading the stored data based on the delay signal.

[0052] After the delay signal is obtained by the DRAM circuit 22, the step of reading the stored data is executed, ensuring that the register circuit completes the step of obtaining the desired data, and then making the data line in an idle state, which can be occupied when the DRAM circuit 22 executes the step of reading the stored data, to ensure the validity of the stored data and the desired data.

[0053] This application also proposes a test system for a DRAM circuit. Refer to Figure 4 , Figure 4 which is a schematic structural diagram of an embodiment of the test system for the DRAM circuit of this application. As Figure 4 shown, the test system includes a control circuit 23, a register circuit (including the buffer register 211 and the local register 212 in Figure 4 ) and a DRAM circuit 22; the control circuit 23 is used to receive a read instruction and generate a first enable signal based on the read instruction; the register circuit is connected to the control circuit 23 and is used to obtain desired data via a data line based on the first enable signal; the DRAM circuit 22 is connected to the control circuit 23 and is used to read the stored data in the DRAM based on a delay signal and output the test result of the DRAM circuit 22 obtained based on the desired data and the stored data via the data line; wherein, the control circuit 23 further generates the delay signal after the register circuit obtains the desired data based on the read instruction.

[0054] The control circuit 23 is respectively connected to the register circuit and the DRAM circuit 22. When it receives an external read instruction, the control circuit 23 first generates a first enable signal and then generates a delay signal after the first enable signal. Among them, the first enable signal is sent to the register circuit, and the register circuit obtains desired data based on the first enable signal; the delay signal is sent to the DRAM circuit 22, and the DRAM circuit 22 starts to read the stored data in the DRAM only after the register circuit obtains the desired data based on the delay signal, and outputs the test result of the DRAM circuit obtained based on the desired data and the stored data via the data line.

[0055] The test system for the DRAM circuit provided by this application generates a first enable signal based on a read instruction received by the control circuit 23. The register circuit generates a delay signal after obtaining the expected data (i.e., the expected value of the test data) under the control of the first enable signal. The DRAM circuit 22 reads the data stored in the DRAM (i.e., obtains the read value of the test data) under the control of the delay signal. Therefore, this application can generate a first enable signal for completing the write operation of the expected data and a delay signal for reading the stored data in the DRAM through one read instruction, which can shorten the instruction cycle of the control circuit 23, thereby shortening the test time of the DRAM circuit 22 and improving the test efficiency of the entire DRAM circuit 22. Since the operation of obtaining the expected data (which can also be called the write operation) needs to occupy the data line, and the operation of reading the stored data in the DRAM also needs to occupy the data line, this application uses the delay between the first enable signal and the delay signal to avoid the conflict of occupying the data line during the execution of the two operations, and can ensure the test effect. Further, the operation of outputting the test result also needs to occupy the data line, and this application further avoids the conflict of occupying the data line by these three operations.

[0056] Optionally, the control circuit 23 generates a first enable signal within the clock cycle of the read instruction, and within the clock cycle, and "asserts" the delay signal after the pulse width of the first enable signal.

[0057] Refer to Figure 2 , the control circuit 23 "asserts" the delay signal at time t1 within the clock cycle of the read instruction, where time t1 and time t0 can be within the same clock cycle of the read instruction, and it can be controlled that time t1 is after the effective pulse width p0 of the first enable signal, so that the operation of the DRAM circuit 22 reading the stored data is after the operation of the register circuit obtaining the expected data, ensuring that the occupation of the data line during their respective executions does not conflict.

[0058] Further, the pulse width of the first enable signal is a fixed pulse width. The control circuit 23 sets the time of "asserting" the delay signal to be the time of "asserting" the first enable signal plus the fixed pulse width; or the control circuit 23 receives the feedback signal of the first enable signal, and "de-asserts" the first enable signal based on the feedback signal, and asserts the delay signal.

[0059] The pulse width of the first enable signal can be a fixed pulse width. For example, its pulse width can be less than half a cycle. Then, the first enable signal with a pulse width less than half a cycle will shorten the time for the register circuit to obtain the expected data, thereby improving the test efficiency of the DRAM circuit 22. It can be referred to Figure 2, the moment t1 when the control circuit 23 "asserts" the delay signal is set to the moment t0 when the first enable signal is "asserted" plus the fixed pulse width p0 to meet the condition of t1 > t0 + p0.

[0060] Alternatively, the control circuit 23 issues the first enable signal based on the read instruction, and after receiving the feedback signal of the first enable signal, "de-asserts" the first enable signal based on the feedback signal and "asserts" the delay signal. That is, after ensuring that the register circuit obtains the expected data from the data line, the control circuit 23 generates a delay pulse signal to make the DRAM circuit 22 read the stored data from the data line, so as to prevent conflicts on the data line during the above two processes and ensure the validity of the expected data of the register circuit and the stored data read by the DRAM circuit 22.

[0061] Optionally, the register circuit includes a buffer register 211 and a local register 212 of the DRAM. The buffer register 211 is used to pre-store the expected data; the local register 212 is connected to the buffer register 211 and the control circuit 23, and the register circuit writes the expected data in the buffer register 211 to the local register 212 via the data line based on the first enable signal.

[0062] The register circuit includes a buffer register 211 and a local register 212 of the DRAM. Among them, the buffer register 211 can be used to pre-store the expected data, that is, the expected data can be pre-written into the buffer register 211 in advance, thereby reducing the time for writing data through external instructions. The local register 212 is connected to the buffer register 211 and the control circuit 23, and the register circuit writes the expected data pre-stored in the buffer register 211 to the local register 212 via the data line so that the subsequent DRAM circuit 22 can obtain the expected data from the local register 212.

[0063] Optionally, the delay signal includes a precharge signal and a second enable signal. The DRAM circuit 22 further includes a comparison circuit 221, an amplification circuit (not labeled in the figure), and a precharge circuit (not labeled in the figure). Among them, the amplification circuit is connected to the DRAM and is used to amplify the stored data read from the DRAM; the control circuit 23 is connected to the comparison circuit 221, the precharge circuit, and the buffer register 211, and is used to generate the first enable signal, the precharge signal, and the second enable signal based on the read instruction; the precharge circuit is used to precharge the data line after obtaining the expected data based on the precharge signal; the comparison circuit 221 is further connected to the local register 212 and the amplification circuit, and is used to output the test result of the DRAM circuit 22 obtained by comparing the expected data and the amplified stored data via the data line based on the second enable signal.

[0064] Refer toFigure 5 , Figure 5 is a timing schematic diagram of an embodiment in which the control circuit of the present application generates a first enable signal, a precharge signal, and a second enable signal. As Figure 5 shown, the control circuit 23 generates a first enable signal, a precharge signal, and a second enable signal based on a read instruction. Refer to Figure 4 , the DRAM circuit 22 further includes a comparison circuit 221, an amplification circuit, and a precharge circuit. Among them, the amplification circuit is connected to the DRAM and is used to amplify the stored data read from the DRAM. The control circuit 23 is connected to the comparison circuit 221, the precharge circuit, and the buffer register 211. The control circuit 23 generates a first enable signal, a precharge signal, and a second enable signal based on a read instruction. The precharge circuit is used to precharge the data line after obtaining the desired data based on the precharge signal; the comparison circuit 221 is also connected to the local register 212 and the amplification circuit, and is used to output the test result of the DRAM circuit 22 obtained by comparing the desired data and the amplified stored data via the data line based on the second enable signal.

[0065] Refer to Figure 6 , Figure 6 is a circuit schematic diagram of an embodiment of the precharge circuit of the present application. As Figure 6 shown, before the data to be read is valid, a precharge operation needs to be performed first: pull down the PRCH potential and precharge point A to Vprch. When the data to be read is valid, PRCH is pulled high, and the data line (data line or I / O line) changes according to whether the data to be read is "0" or "1": if it is "0", the NMOS is turned on to pull the I / O line to the ground (discharge) to output data 0, and if it is "1", the I / O line is held to output data 1.

[0066] Refer to Figure 7 , Figure 7 is a circuit schematic diagram of an embodiment of the test system of the DRAM circuit of the present application. As Figure 7 shown, the control circuit 23 receives an external read instruction and generates a first enable signal; the buffer register 211 writes the pre-stored desired data into the local register 212 through the data line based on the first enable signal; the control circuit 23 generates a precharge signal and a second enable signal after a preset delay. The precharge signal is used to precharge the precharge circuit, and the second enable signal is used for the comparison circuit 221 to compare the desired data and the stored data, and the comparison result is used as the test result of the DRAM circuit 22.

[0067] Refer to Figure 8 , Figure 8 is a circuit schematic diagram of another embodiment of the test system of the DRAM circuit of the present application. As Figure 8As shown, the control circuit 23 receives an external read instruction and generates a first enable signal; based on the first enable signal, the buffer register 211 writes the pre-stored expected data into the local register 212 through the data line; after the control circuit 23 receives the feedback signal of the first enable signal and after the falling edge of the first enable signal, it generates a pre-charge signal and a second enable signal. The pre-charge signal is used to pre-charge the pre-charge circuit, and the second enable signal is used for the comparison circuit 221 to compare the expected data and the stored data, and the comparison result is used as the test result of the DRAM circuit 22.

[0068] The above are only the embodiments of the present application, and do not limit the patent scope of the present application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A test method for a DRAM circuit, characterized in that, a test system for a DRAM circuit, the test system for the DRAM circuit includes a register circuit and a DRAM circuit, and the test method includes: generating a first enable signal based on a read instruction and sending the first enable signal to the register circuit; the register circuit obtaining expected data via a data line based on the first enable signal; after obtaining the expected data, generating a delay signal based on the read instruction and sending the delay signal to the DRAM circuit, the DRAM circuit reading stored data in the DRAM based on the delay signal and outputting a test result of the DRAM circuit obtained based on the expected data and the stored data via the data line.

2. The test method according to claim 1, characterized in that, generating the first enable signal based on the read instruction further includes: receiving the read instruction and asserting the first enable signal within a clock cycle of the read instruction; generating the delay signal based on the read instruction further includes: asserting the delay signal within the clock cycle and after an active pulse width of the first enable signal.

3. The test method according to claim 2, characterized in that, the active pulse width of the first enable signal is a fixed pulse width, and a time for asserting the delay signal is set to be after a time for asserting the first enable signal plus the fixed pulse width.

4. The test method according to claim 2, characterized in that, further includes: receiving a feedback signal of the first enable signal; de-asserting the first enable signal based on the feedback signal and asserting the delay signal.

5. The test method according to claim 1, characterized in that, the register circuit includes a buffer register and a local register of the DRAM, the register circuit obtaining expected data via the data line based on the first enable signal includes: writing the expected data pre-stored in the buffer register to the local register via the data line based on the first enable signal; the DRAM circuit outputting a test result of the DRAM circuit obtained based on the expected data and the stored data via the data line includes: obtaining the expected data from the local register; outputting a test result of the DRAM circuit obtained by comparing the expected data with the stored data via the data line based on a second enable signal in the delay signal.

6. The test method according to claim 1, characterized in that, the DRAM circuit reading stored data in the DRAM based on the delay signal includes: pre-charging the data line based on a pre-charge signal in the delay signal after the register circuit obtains the expected data; and amplifying and outputting the stored data read from the DRAM.

7. A test system for a DRAM circuit, characterized in that, includes: a control circuit for receiving a read instruction and generating a first enable signal based on the read instruction; A register circuit, connected to the control circuit, for obtaining desired data via a data line based on the first enable signal; A DRAM circuit, connected to the control circuit, for reading stored data in the DRAM based on a delay signal and outputting a test result of the DRAM circuit obtained based on the desired data and the stored data via the data line; Wherein, the control circuit further generates the delay signal after the register circuit obtains the desired data based on the read instruction.

8. The test system according to claim 7, wherein, The control circuit generates the first enable signal within the clock cycle of the read instruction, and within the clock cycle, and after the pulse width of the first enable signal, asserts the delay signal.

9. The test system according to claim 8, wherein, The pulse width of the first enable signal is a fixed pulse width, and the control circuit sets the time to assert the delay signal to be after the time to assert the enable signal plus the fixed pulse width; or The control circuit receives a feedback signal of the first enable signal, and based on the feedback signal, asserts the first enable signal and asserts the delay signal.

10. The test system according to claim 7, wherein, The register circuit includes: A buffer register for pre-storing the desired data; A local register of the DRAM, connected to the buffer register and the control circuit, and the register circuit writes the desired data in the buffer register into the local register via the data line based on the first enable signal.

11. The test system according to claim 10, wherein, The delay signal includes a precharge signal and a second enable signal, and the DRAM circuit further includes a comparison circuit, an amplification circuit and a precharge circuit. Among them, the amplification circuit is connected to the DRAM and is used for amplifying the stored data read from the DRAM; The control circuit is connected to the comparison circuit, the precharge circuit and the buffer register, and is used for generating the first enable signal, the precharge signal and the second enable signal based on the read instruction; The precharge circuit is used for precharging the data line after obtaining the desired data based on the precharge signal; The comparison circuit is further connected to the local register and the amplification circuit, and is used for outputting the test result of the DRAM circuit obtained by comparing the desired data and the amplified stored data via the data line based on the second enable signal.

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