Method of forming a semiconductor device

Abstract

The application discloses a semiconductor device forming method, which comprises the following steps: providing a substrate; forming a multilayer structure on the surface of the substrate, wherein the multilayer structure comprises an opening; forming a first amorphous silicon layer on the surface of the opening, wherein the first amorphous silicon layer conformally covers the opening; forming a stress layer on the surface of the first amorphous silicon layer; performing an annealing process on the stress layer and the first amorphous silicon layer, converting the first amorphous silicon layer into a polycrystalline silicon layer, and the stress layer applies stress to the first amorphous silicon layer during the annealing process; and removing the stress layer after the annealing process. The application can improve the crystal conversion rate of the amorphous silicon layer and improve the conductive performance of the obtained polycrystalline silicon layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for forming a semiconductor device. Background Technology

[0002] Polycrystalline silicon (Poly-Si) layers are widely used in semiconductor structures due to their advantages such as high mobility and low resistance caused by strong electric field effects. In the formation of most semiconductor structures, amorphous silicon (A-Si) can be converted into polycrystalline silicon to form the corresponding polycrystalline silicon layer. However, the inventors, while researching polycrystalline silicon conversion schemes, discovered that traditional conversion methods suffer from low conversion rates. Summary of the Invention

[0003] In view of this, this application provides a method for forming a semiconductor device to solve the problem of low crystal conversion rate in traditional conversion schemes.

[0004] This application provides a method for forming a semiconductor device, comprising:

[0005] Provide substrate;

[0006] A multilayer structure is formed on the surface of the substrate, the multilayer structure including openings;

[0007] A first amorphous silicon layer is formed on the surface of the opening, and the first amorphous silicon layer conformally covers the opening;

[0008] A stress layer is formed on the surface of the first amorphous silicon layer;

[0009] The stress layer and the first amorphous silicon layer are subjected to an annealing process to convert the first amorphous silicon layer into a polycrystalline silicon layer, and the stress layer applies stress to the first amorphous silicon layer during the annealing process.

[0010] Remove the stress layer after the annealing process.

[0011] Optionally, the stress layer is annealed to form a polycrystalline layer; the lattice constant of the polycrystalline layer is greater than the lattice constant of the polycrystalline silicon layer, so that the stress layer applies compressive stress to the first amorphous silicon layer during the annealing process.

[0012] Optionally, the material of the stress layer includes at least one of germanium silicon, silicon nitride, and silicon carbide.

[0013] Optionally, the annealing process is operated at a temperature between 550°C and 1000°C, and the annealing time is between 10 seconds and 1 hour.

[0014] Optionally, the method of forming a first amorphous silicon layer on the surface of the opening further includes: growing the first amorphous silicon layer on the substrate surface using a furnace tube growth process.

[0015] Optionally, the growth temperature of the furnace tube growth process is between 300°C and 600°C.

[0016] Optionally, the thickness of the first amorphous silicon layer is less than the thickness of the stress layer.

[0017] Optionally, the multilayer structure comprises, from bottom to top, a first conductor layer, a second amorphous silicon layer, a first dielectric layer, a second conductor layer, a third conductor layer, and a second dielectric layer.

[0018] Optionally, after the annealing process, the second amorphous silicon layer is partially converted into polycrystalline silicon, and the first amorphous silicon layer is completely converted into a polycrystalline silicon layer.

[0019] Optionally, a portion of the second amorphous silicon layer is exposed at the bottom of the opening.

[0020] Optionally, the forming method further includes: forming a gate structure on the surface of the polysilicon layer that fills the opening.

[0021] This application also provides a semiconductor device, including:

[0022] Substrate, the substrate including an opening;

[0023] A polycrystalline silicon layer located on the surface of the substrate and conformally covering the opening, the polycrystalline silicon layer being formed by annealing an amorphous silicon layer and stress applied to the surface structure during annealing.

[0024] The above-mentioned method for forming a semiconductor device involves forming a first amorphous silicon layer on the opening surface, forming a stress layer on the surface of the first amorphous silicon layer, and performing an annealing process on the stress layer and the first amorphous silicon layer. During the annealing process, the stress layer applies stress to the first amorphous silicon layer. Under the action of annealing and the stress applied by the stress layer during annealing, the first amorphous silicon layer can be more fully transformed into a polycrystalline silicon layer. The crystal conversion rate of the first amorphous silicon layer, especially the crystal conversion rate of the sidewall portion, is effectively improved, resulting in higher electron mobility and better conductivity of the polycrystalline silicon layer.

[0025] The lattice constant of the polycrystalline layer corresponding to the stress layer is greater than that of the polycrystalline silicon layer, so that the stress layer can apply compressive stress to the first amorphous silicon layer during the annealing process to ensure the stress effect; the thickness of the first amorphous silicon layer is less than that of the stress layer, so that the stress applied by the stress layer to the first amorphous silicon layer during the annealing process is as large as possible.

[0026] It is evident that this application can improve the crystal conversion efficiency of the first amorphous silicon layer and enhance the conductivity of the resulting polycrystalline silicon layer from multiple aspects, thereby improving the performance of the corresponding semiconductor structure. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1a and Figure 1b This is a schematic diagram of the traditional polycrystalline silicon layer formation process;

[0029] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of this application;

[0030] Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 3e and Figure 3f This is a schematic diagram of the structure obtained in each step of an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of a multi-layer structure in one embodiment of this application;

[0032] Figure 5 This is a schematic diagram of a semiconductor device structure in one embodiment of this application. Detailed Implementation

[0033] During their research, the inventors discovered that when forming a polycrystalline silicon layer on a channeled semiconductor structure, traditional methods often result in... Figure 1a As shown, an amorphous silicon (A-Si) layer is deposited on the bottom, sidewalls, and semiconductor surface of the channel, and then the amorphous silicon layer is annealed. Figure 1b As shown, the amorphous silicon layer is converted into a polycrystalline silicon layer after annealing. Although this method yields a conformally conformally covering polycrystalline silicon layer over the channel, the conversion rate of polycrystalline silicon is limited, especially at the channel sidewalls where the conversion rate is low, resulting in poor conductivity.

[0034] To address the aforementioned issues, the semiconductor device and its formation method provided in this application form a stress layer on the surface of a first amorphous silicon layer and then perform an annealing process on the stress layer and the first amorphous silicon layer. During the annealing process, the stress layer applies stress to the first amorphous silicon layer. As a result, under the combined effects of annealing and the stress applied by the stress layer during annealing, the first amorphous silicon layer can be more fully transformed into a polycrystalline silicon layer, and the crystal conversion rate of the first amorphous silicon layer, especially the crystal conversion rate of the sidewall portion, is effectively improved.

[0035] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0036] This application provides a method for forming a semiconductor device in its first aspect, with reference to... Figure 2 As shown, the forming method includes steps S110 to S160.

[0037] S110, Reference Figure 3a As shown, a substrate 210 is provided; the substrate 210 includes a silicon substrate, a silicon-containing substrate and / or an epitaxial silicon substrate, etc.

[0038] S120, Reference Figure 3b As shown, a multilayer structure 220 is formed on the surface of the substrate 210, and the multilayer structure 220 includes an opening 221. The specific structure of the multilayer structure 220 is determined according to the function of the semiconductor device, and typically includes structures such as conductor layers, semiconductor layers, and / or dielectric layers to respond to the corresponding function of the semiconductor device. The opening 221 can penetrate at least one layer above the multilayer structure 220, the sidewalls of the opening 221 can expose each penetrating layer, and the bottom exposes a portion of the surface of the layer located below the opening 221.

[0039] S130, Reference Figure 3c As shown, a first amorphous silicon layer 231 is formed on the surface of the opening 221, and the first amorphous silicon layer 231 conformally covers the opening 221. Figure 3c As shown, the first amorphous silicon layer 231 has the same thickness at all locations, covering the bottom, sidewalls and surface of the multilayer structure 220 on both sides of the opening 221 respectively; after the first amorphous silicon layer 231 is formed, a new opening is formed above the opening 221.

[0040] S140, Reference Figure 3d As shown, a stress layer 241 is formed on the surface of the first amorphous silicon layer 231. The stress layer 241 is used to apply stress to the first amorphous silicon layer 231 during the annealing process.

[0041] S150, the stress layer 241 and the first amorphous silicon layer 231 are subjected to an annealing process to transform the first amorphous silicon layer 231 into a polycrystalline silicon layer 232. During the annealing process, the stress layer 241 applies stress to the first amorphous silicon layer 231 to ensure a more complete transformation of the first amorphous silicon layer 231, particularly its sidewall portions. (Reference) Figure 3eAs shown, after annealing, the first amorphous silicon layer 231 can be transformed into a polycrystalline silicon layer 232, and the stress layer 241 can be transformed into the corresponding polycrystalline layer 242.

[0042] S160, Reference Figure 3f As shown, after removing the stress layer 241 after the annealing process, a corresponding semiconductor device is obtained. In this semiconductor device, the electron mobility of the polysilicon layer 232 is higher, and the conductivity is further optimized.

[0043] The above-mentioned semiconductor device formation method involves forming a first amorphous silicon layer 231 on the surface of the opening 221, forming a stress layer 241 on the surface of the first amorphous silicon layer 231, and performing an annealing process on the stress layer 241 and the first amorphous silicon layer 231. During the annealing process, the stress layer 241 applies stress to the first amorphous silicon layer 231. Under the action of annealing and the stress applied by the stress layer 241 during annealing, the first amorphous silicon layer 231 can be more fully transformed into a polycrystalline silicon layer 232. The crystal conversion rate of the first amorphous silicon layer 231, especially the crystal conversion rate of the sidewall portion, is effectively improved, resulting in higher electron mobility and better conductivity of the polycrystalline silicon layer 232, thereby improving the conductivity of the corresponding semiconductor structure.

[0044] In one embodiment, the stress layer 241 is annealed to form a polycrystalline layer 242; the lattice constant of the polycrystalline layer 242 is greater than that of the polycrystalline silicon layer 232, so that the stress layer 241 applies compressive stress to the first amorphous silicon layer 231 during the annealing process to ensure the stress effect and further improve the crystal conversion efficiency of the first amorphous silicon layer 231.

[0045] Optionally, the stress layer 241 may be made of at least one of silicon germanium (SiGe), silicon nitride (Si3N4), and silicon carbide (SiC) to stably apply stress to the first amorphous silicon layer 231 during the annealing process.

[0046] In one embodiment, the various process parameters of the annealing process can be set based on factors such as the crystallization characteristics of the first amorphous silicon layer 231 and the stress layer 241. Optionally, the operating temperature of the annealing process is between 550°C and 1000°C, such as 550°C, 700°C, 800°C, or 1000°C, to ensure the stability of the annealing process. Optionally, the annealing time is between 10 seconds and 1 hour, such as 10 seconds, 60 seconds, 0.2 hours, 0.5 hours, or 1 hour, to improve the corresponding conversion efficiency while ensuring that the first amorphous silicon layer 231 is fully converted into the polycrystalline silicon layer 232.

[0047] In one embodiment, the method for forming a first amorphous silicon layer 231 on the surface of the opening 221 further includes: growing the first amorphous silicon layer 231 on the surface of the opening 221 using a furnace tube growth process. Optionally, the growth temperature of the furnace tube growth process is between 300°C and 600°C, such as 300°C, 410°C, 500°C, or 600°C, etc. This growth temperature is lower than the crystallization temperature corresponding to amorphous silicon, which enables the stable formation of the first amorphous silicon layer 231.

[0048] In one embodiment, the thickness of the first amorphous silicon layer 231 is less than the thickness of the stress layer 241, so that during the annealing process, the stress applied by the stress layer 241 to the first amorphous silicon layer 231 is as large as possible, further improving the crystal conversion efficiency of the first amorphous silicon layer 231. Specifically, the thickness of the first amorphous silicon layer 231 or the polycrystalline silicon layer 232 can be set according to the size of the corresponding semiconductor device and / or the function of the polycrystalline silicon layer 232 in the semiconductor device. The thickness of the stress layer 241 can be set according to the thickness of the first amorphous silicon layer 231 and / or the stress requirements of the first amorphous silicon layer 231 during crystallization.

[0049] Optionally, the thickness of the first amorphous silicon layer 231 is between 40 angstroms and 80 angstroms, for example, it can be 40 angstroms, 60 angstroms or 80 angstroms, so that the obtained polycrystalline silicon layer 232 can achieve the conductive function without increasing the size of the semiconductor device.

[0050] Optionally, the thickness of the stress layer 241 is between 80 angstroms and 200 angstroms, for example, it can be 80 angstroms, 100 angstroms, 150 angstroms or 200 angstroms, so that during the annealing process, the stress layer 241 can apply a sufficiently large stress to the first amorphous silicon layer 231.

[0051] In one embodiment, the multilayer structure comprises, from bottom to top, a first conductor layer 222, a second amorphous silicon layer 223, a first dielectric layer 224, a second conductor layer 225, a third conductor layer 226, and a second dielectric layer 227.

[0052] The materials and thicknesses of the first conductor layer 222, the second conductor layer 225, and the third conductor layer 226 can be set according to their functions in the corresponding semiconductor devices and / or the dimensions of the semiconductor devices. Optionally, the material of the first conductor layer 222 may include titanium nitride (TiN), and the thickness may be between 8 nm (nanometers) and 12 nm, such as 8 nm, 10 nm, or 12 nm. Optionally, the material of the second conductor layer 225 may include titanium nitride, and the thickness may be between 4 nm and 6 nm, such as 4 nm, 5 nm, or 6 nm. Optionally, the material of the third conductor layer 226 may include tungsten (W), and the thickness may be between 50 nm and 60 nm, such as 50 nm, 55 nm, or 60 nm.

[0053] The thickness of the second amorphous silicon layer 223 can be set according to factors such as the size of the semiconductor device. Optionally, the thickness of the second amorphous silicon layer 223 can be between 18nm and 22nm, such as 18nm, 20nm, or 22nm, etc.

[0054] The material and thickness of the first dielectric layer 224 and the second dielectric layer 227 can be set according to their function in the corresponding semiconductor device and / or the size of the semiconductor device. For example, the first dielectric layer 224 and the second dielectric layer 227 can be made of materials such as TEOS (electronic grade tetraethyl orthosilicate). Optionally, the thickness of the first dielectric layer 224 can be between 8 nm and 12 nm, such as 8 nm, 10 nm, or 12 nm. The thickness of the second dielectric layer 227 can be between 32 nm and 38 nm, such as 32 nm, 35 nm, or 38 nm.

[0055] Optionally, such as Figure 4 As shown, the bottom of the opening 221 exposes a portion of the second amorphous silicon layer 223; the opening 221 penetrates the second dielectric layer 227, the third conductor layer 226, the second conductor layer 225, and the first dielectric layer 224; thus, the subsequently formed polycrystalline silicon layer 232 can cover the portion of the second amorphous silicon layer 223 exposed by the opening 221.

[0056] Optionally, after the annealing process, the second amorphous silicon layer 223 is partially converted into polycrystalline silicon. For example, the portion covered by the first amorphous silicon layer 231 is converted into the corresponding polycrystalline silicon layer, or most of the upper half of the second amorphous silicon layer 223 is converted into the corresponding polycrystalline silicon layer, and a small portion of the lower half is converted into the corresponding polycrystalline silicon layer, etc. Optionally, after the annealing process, the first amorphous silicon layer 231 is completely converted into the polycrystalline silicon layer 232, and the corresponding crystal conversion rate is effectively improved.

[0057] In one embodiment, reference Figure 5As shown, the forming method further includes: forming a gate structure 250 filled in the opening 221 on the surface of the polycrystalline silicon layer 232, so that the semiconductor device forms a transistor. In the transistor, the crystal conversion efficiency of the first amorphous silicon layer 231 is effectively improved, the corresponding resistivity is reduced, and the conductivity is optimized, thereby reducing the heat loss and power consumption of the obtained transistor and improving the response speed and stability of the transistor.

[0058] Specifically, such as Figure 5 As shown, the gate structure 250 may include a gate dielectric layer 251 and a gate 252. Optionally, an insulating layer (not shown) may be disposed between the gate dielectric layer 251 and the polysilicon layer 232 to isolate the gate dielectric layer 251 and the polysilicon layer 232. Optionally, Figure 5 In the transistor shown, the first conductor layer 222 can lead out the source of the transistor, and the second conductor layer 225 and / or the third conductor layer 226 can lead out the drain of the transistor.

[0059] In the above method for forming semiconductor devices, the first amorphous silicon layer 231, under the action of annealing and the stress applied during annealing of the stress layer 241, can be more fully transformed into a polycrystalline silicon layer 232. The crystal conversion rate of the first amorphous silicon layer 231, especially the crystal conversion rate of the sidewall portion, is effectively improved, resulting in higher electron mobility and better conductivity of the polycrystalline silicon layer 232. Furthermore, the lattice constant of the polycrystalline layer 242 corresponding to the stress layer 241 is greater than that of the polycrystalline silicon layer 232, which enhances the performance of the stress layer 241 during annealing. During the processing, compressive stress can be applied to the first amorphous silicon layer 231 to ensure the stress effect. The thickness of the first amorphous silicon layer 231 is less than the thickness of the stress layer 241 so that the stress applied by the stress layer 241 to the first amorphous silicon layer 231 is as large as possible during the annealing process. It can be seen that the above-mentioned semiconductor device formation method can improve the crystal conversion efficiency of the first amorphous silicon layer 231 and improve the conductivity of the resulting polycrystalline silicon layer 232 in many ways, thereby improving the power consumption, response speed and stability of the corresponding semiconductor structure.

[0060] A second aspect of this application provides a semiconductor device, with reference to... Figure 3f As shown, the semiconductor device includes:

[0061] Substrate 210;

[0062] A multilayer structure 220 located on the surface of the substrate 210, the multilayer structure 220 including an opening 221;

[0063] A polycrystalline silicon layer 232 is located on the surface of the opening 221 and conformally covers the opening 221. The polycrystalline silicon layer 232 is formed by the annealing of the amorphous silicon layer and the stress applied by the surface structure (such as the stress layer 241) during annealing.

[0064] The semiconductor device described above can be formed using the semiconductor device formation method described in any of the above embodiments, and has all the beneficial effects of the semiconductor device formation method described in any of the above embodiments, which will not be repeated here.

[0065] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if it is not necessarily structurally equivalent to the disclosed structure that performs the functions in the exemplary implementations of this specification shown herein.

[0066] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0067] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0068] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A method for forming a semiconductor device, characterized in that, The forming method includes: Provide substrate; A multilayer structure is formed on the surface of the substrate, the multilayer structure comprising, from bottom to top: a first conductor layer, a second amorphous silicon layer, a first dielectric layer and a second conductor layer, the multilayer structure including an opening, the bottom of the opening exposing a portion of the second amorphous silicon layer; A first amorphous silicon layer is formed on the surface of the opening, and the first amorphous silicon layer conformally covers the opening; A stress layer is formed on the surface of the first amorphous silicon layer; The stress layer and the first amorphous silicon layer are subjected to an annealing process, during which the stress layer applies stress to the first amorphous silicon layer; after the annealing process, the first amorphous silicon layer is converted into a polycrystalline silicon layer, and the second amorphous silicon layer is partially converted into polycrystalline silicon. Remove the stress layer after the annealing process; A gate structure is formed on the surface of the polysilicon layer to fill the opening, the gate structure including a gate dielectric layer and a gate.

2. The method for forming a semiconductor device according to claim 1, characterized in that, The stress layer is annealed to form a polycrystalline layer; the lattice constant of the polycrystalline layer is greater than that of the polycrystalline silicon layer, so that the stress layer applies compressive stress to the first amorphous silicon layer during the annealing process.

3. The method for forming a semiconductor device according to claim 2, characterized in that, The material of the stress layer includes at least one of germanium silicon, silicon nitride, and silicon carbide.

4. The method for forming a semiconductor device according to claim 1, characterized in that, The annealing process operates at a temperature between 550°C and 1000°C, and the annealing time is between 10 seconds and 1 hour.

5. The method for forming a semiconductor device according to claim 1, characterized in that, The method for forming a first amorphous silicon layer on the surface of the opening further includes: The first amorphous silicon layer is grown on the surface of the substrate using a furnace tube growth process.

6. The method for forming a semiconductor device according to claim 5, characterized in that, The growth temperature of the furnace tube growth process is between 300℃ and 600℃.

7. The method for forming a semiconductor device according to claim 1, characterized in that, The thickness of the first amorphous silicon layer is less than the thickness of the stress layer.

8. The method for forming a semiconductor device according to claim 1, characterized in that, The multilayer structure further includes: a third conductor layer and a second dielectric layer, wherein the third conductor layer is located on the second conductor layer and the second dielectric layer is located on the third conductor layer.

9. A semiconductor device, characterized in that, The semiconductor device is formed using the forming method according to any one of claims 1 to 8, comprising: Substrate, the substrate including an opening; A polycrystalline silicon layer located on the surface of the substrate and conformally covering the opening, the polycrystalline silicon layer being formed by annealing an amorphous silicon layer and stress applied to the surface structure during annealing.

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