Memory

Abstract

The present invention provides a memory, wherein a substrate comprises a plurality of active areas extending along a first predetermined direction; the substrate is formed with a plurality of bit line structures extending along a second predetermined direction and passing through corresponding active areas, the portion of the bit line structure located on the substrate constitutes a first bit line structure, and the portion of the bit line structure extending from the substrate to the active area constitutes a second bit line structure; a metal silicide layer is formed between the second bit line structure and the active area, the active area and the second bit line structure are electrically connected via the metal silicide layer, and since the metal silicide layer has a relatively low resistivity, the contact resistance between the active area and the second bit line structure can be reduced, thereby improving the performance of the memory.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a memory. Background Art

[0002] A memory, such as a dynamic random access memory (DRAM), generally has a memory cell array, wherein the memory cell array includes a plurality of memory cells arranged in an array. The memory also has a plurality of bit line structures, each of which is electrically connected to a corresponding memory cell. At present, the excessive contact resistance between the bit line structure and the corresponding memory cell is one of the reasons that limit the performance of the memory. How to reduce the contact resistance between the bit line structure and the corresponding memory cell is a technical problem that needs to be solved urgently. Summary of the invention

[0003] An object of the present invention is to provide a memory device to reduce the contact resistance between a bit line structure and a corresponding memory cell.

[0004] In order to achieve the above object, the present invention provides a memory, characterized in that it includes:

[0005] A substrate including a plurality of active regions extending along a first predetermined direction;

[0006] a plurality of bit line structures, located on the substrate and extending along a second predetermined direction to pass through corresponding active regions, wherein portions of the bit line structures located on the substrate constitute first bit line structures, and portions of the bit line structures extending from the substrate to the active regions constitute second bit line structures; and,

[0007] The metal silicide layer is located between the second bit line structure and the active area, and is used to electrically connect the active area and the second bit line structure.

[0008] Optionally, the bit line structure includes a bit line conductive layer, a bit line shielding layer and an isolation sidewall, the bit line shielding layer covers a top wall of the bit line conductive layer, and the isolation sidewall covers the bit line conductive layer and side walls of the bit line shielding layer.

[0009] Optionally, the isolation sidewall also covers the sidewall of the metal silicide layer.

[0010] Optionally, in a direction perpendicular to the height, a width dimension of the metal silicide layer is greater than or equal to a width dimension of the bit line conductive layer.

[0011] Optionally, the bottom of the isolation sidewall is located at a first depth position in the substrate, and the bottom of the metal silicide layer is located at a second depth position in the substrate, and the first depth position is lower than the second depth position.

[0012] Optionally, the material of the metal silicide layer includes one or more of cobalt silicide, titanium silicide, tungsten silicide, molybdenum silicide, tantalum silicide or platinum silicide.

[0013] The present invention provides a method for forming a memory, comprising:

[0014] Providing a substrate including a plurality of active regions extending along a first predetermined direction;

[0015] forming a plurality of bit line structures on the substrate, wherein the bit line structures extend along a second predetermined direction to pass through corresponding active regions, wherein portions of the bit line structures located on the substrate constitute first bit line structures, and portions of the bit line structures extending from the substrate to the active regions constitute second bit line structures; and,

[0016] A metal silicide layer is formed between the second bit line structure and the active region to electrically connect the active region and the second bit line structure.

[0017] Optionally, the metal silicide layer is formed before forming the plurality of bit line structures, and the step of forming the metal silicide layer includes:

[0018] forming a mask layer on the substrate;

[0019] forming a plurality of bit line trenches in the mask layer, wherein the bit line trenches extend along a second predetermined direction, and portions of the bit line trenches located on the substrate constitute first bit line trenches, and portions of the bit line structures extending from the substrate to the active region constitute second bit line trenches; and

[0020] The metal silicide layer is formed at the bottom of the second bit line trench.

[0021] Optionally, the metal silicide layer is formed at the bottom of the second bit line trench by using a self-aligned silicide process.

[0022] Optionally, the step of forming a plurality of bit line structures on the substrate includes:

[0023] sequentially forming a bit line conductive layer and a bit line shielding layer in the bit line trench; and,

[0024] An isolation sidewall is formed in the bit line trench, and the isolation sidewall covers the sidewalls of the bit line conductive layer and the bit line shielding layer.

[0025] In the memory provided by the present invention, the substrate includes a plurality of active areas extending along a first predetermined direction; the substrate is formed with a plurality of bit line structures extending along a second predetermined direction and passing through the corresponding active areas, the portion of the bit line structure located on the substrate constitutes a first bit line structure, and the portion of the bit line structure extending from the substrate to the active area constitutes a second bit line structure; a metal silicide layer is formed between the second bit line structure and the active area, and the active area and the second bit line structure are electrically connected through the metal silicide layer. Since the metal silicide layer has a lower resistivity, the contact resistance between the active area and the second bit line structure can be reduced, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A flowchart of a method for forming a memory provided in Embodiment 1 of the present invention;

[0027] Figure 2a to Figure 2d A schematic diagram of a structure formed by the method for forming a memory provided by the first embodiment of the present invention;

[0028] Figure 2e A simplified diagram of a memory provided in Embodiment 1 of the present invention, wherein: Figure 2a to Figure 2d yes Figure 2e Schematic cross-sectional view of the structure along the a-a' and b-b' directions;

[0029] Figure 3 A schematic diagram of the structure of a memory provided in Embodiment 2 of the present invention;

[0030] Figure 4 A schematic diagram of the structure of a memory provided in Embodiment 3 of the present invention;

[0031] Figure 5 A schematic diagram of the structure of a memory provided in Embodiment 4 of the present invention;

[0032] Wherein, the accompanying drawings are marked as follows:

[0033] 100-substrate; AA-active area; SIT-trench isolation structure; 300a-first barrier layer; 300b-second barrier layer; 310-mask layer; 500-metal silicide layer;

[0034] WL-word line structure; 200a-gate oxide layer; 200b-gate conductive layer; 200c-gate insulating layer;

[0035] BL-bit line structure; 400a-first bit line conductive layer; 400b-second bit line conductive layer; 400c-third bit line conductive layer; 400d-bit line shielding layer; 400e-isolation sidewall; 400f-bit line conductive layer;

[0036] BL1-first bit line structure; BL1-second bit line structure; Tr-bit line trench; Tr1-first bit line trench; Tr2-second bit line trench;

[0037] X1-width dimension of the metal silicide layer;

[0038] X2-width dimension of the bit line conductive layer;

[0039] H1 - first depth position;

[0040] H2 - Second depth position. DETAILED DESCRIPTION

[0041] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] Embodiment 1

[0043] Figure 2d is a partial structural diagram of the memory in this embodiment, Figure 2e for Figure 2d A simplified diagram of the memory in Figure 2d for Figure 2e Schematic diagram of the cross-section of the memory in the a-a' and bb' directions.

[0044] like Figure 2d and Figure 2e As shown, the memory includes: a substrate 100 and a word line structure WL formed in the substrate 100. A plurality of active areas AA extending along a first predetermined direction (Z direction) and a trench isolation structure STI are formed in the substrate 100, and the trench isolation structure STI separates adjacent active areas AA. The plurality of active areas AA are arranged in an array, and the trench isolation structure STI is used to make each active area AA independent of each other, so as to avoid mutual interference between the active areas AA.

[0045] Furthermore, a word line trench is formed in the substrate 100, and the word line trench is used to accommodate the word line structure WL. Specifically, the word line trench extends along a third predetermined direction (X direction) to pass through the corresponding active area AA and the trench isolation structure STI, and the word line trench has a portion located in the trench isolation structure STI and a portion located in the active area AA.

[0046] In this embodiment, the opening size of the word line trench in the trench isolation structure STI is larger than the opening size of the word line trench in the active area AA. Furthermore, the bottom position of the word line trench in the trench isolation structure STI is also lower than the bottom position of the word line trench in the active area AA.

[0047] As described above, the word line trench passes through the corresponding active area AA and the trench isolation structure STI, so the word line structure WL also passes through the active area AA and the trench isolation structure STI accordingly. In this embodiment, the bottom position of the word line structure WL in the trench isolation structure STI is lower than the bottom position of the word line structure WL in the active area AA, and the top position of the word line structure WL is at the same height position. The word line structure WL is formed in the word line trench, so a channel region buried in the active area AA with a curved structure can be formed. Therefore, compared with a linear channel region, the curved channel region can have a relatively large length, which can improve the short channel effect of the transistor.

[0048] Continue to refer Figure 2d and Figure 2e As shown, the word line structure WL includes a gate dielectric layer 200a, a gate conductive layer 200b and a gate insulating layer 200c, wherein the gate dielectric layer 200a covers the inner wall of the word line groove, the gate conductive layer 200b is located on the gate dielectric layer 200a and fills a partial depth of the word line groove, and the gate insulating layer 200c is located on the gate conductive layer 200b and fills the remaining depth of the word line groove.

[0049] Further, the active area AA is used to form a storage transistor, for example, and a source / drain region may be formed in the active area AA, the source / drain region including a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region are respectively located on both sides of the word line structure WL to form the storage transistor together. It can be understood that the bottoms of the first source / drain region and the second source / drain region are lower than the top of the gate conductive layer 200b, so that there is an overlapping area between the first source / drain region and the second source / drain region and the gate conductive layer 200b.

[0050] Continue to refer Figure 2d and Figure 2e As shown, in this embodiment, a barrier layer is further formed on the substrate 100, and the barrier layer includes a first barrier layer 300a and a second barrier layer 300b from bottom to top. The material of the first barrier layer 300a may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and a combination thereof. The material of the second barrier layer 300b may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and a combination thereof.

[0051] Continue to refer Figure 2d and Figure 2e As shown, a plurality of bit line structures BL are formed on the substrate 100 and extend along a second predetermined direction (Y direction) to pass through corresponding active areas AA. Figure 2d As shown, the bit line structure BL includes a bit line conductive layer, and the bit line conductive layer includes a first bit line conductive layer 400a, a second bit line conductive layer 400b, and a third bit line conductive layer 400c stacked in sequence from bottom to top. The material of the first bit line conductive layer 400a includes, for example, doped polysilicon, the material of the second bit line conductive layer 400b includes, for example, titanium nitride, and the material of the third bit line conductive layer 200c includes, for example, tungsten.

[0052] Furthermore, the bit line structure BL may further include a bit line shielding layer 400d and an isolation spacer 400e, wherein the bit line shielding layer 400d is formed above the sequentially stacked bit line conductive layers, and the isolation spacer 400e at least covers the sidewalls of the sequentially stacked bit line conductive layers and the sidewalls of the bit line shielding layer 400d.

[0053] In this embodiment, in the vertical height direction, the first bit line conductive layer 400a, the second bit line conductive layer 400b, the third bit line conductive layer 400c and the bit line shielding layer 400d have the same width, and the isolation spacer 400e covers the sidewalls of the bit line conductive layer and the bit line shielding layer 400d. Figure 2d As shown, in the vertical height direction, the width dimensions of the bit line conductive layer and the bit line shielding layer 400d are both X2.

[0054] Continue to refer Figure 2d and Figure 2e As shown, each of the bit line structures BL has a portion located on the substrate 100 and a portion extending from the substrate 100 to the active area AA. For ease of description, the portion of the bit line structure BL located on the substrate 100 is referred to as the first bit line structure BL1, and the portion of the bit line structure BL extending from the substrate 100 to the active area AA is referred to as the second bit line structure BL2. The first bit line structure BL1 is located on the substrate 100 and is located directly above the trench isolation structure STI; the second bit line structure BL2 passes through the first barrier layer 300a and the second barrier layer 300b from the substrate 100 and extends to the active area AA. Alternatively, it can also be understood that the first bit line structure BL1 and the second bit line structure BL2 are two parts of a bit line structure BL.

[0055] Continue to refer Figure 2dAs shown, a metal silicide layer 500 is formed between the second bit line structure BL2 and the active area AA, and the upper and lower surfaces of the metal silicide layer 500 are respectively electrically connected to the first bit line conductive layer 400a in the second bit line structure BL2 and the active area AA, thereby electrically connecting the bit line structure BL to the active area AA. It can be understood that the metal silicide layer 500 enables the bit line structure BL to form an ohmic contact with the active area AA, thereby reducing the contact resistance between the bit line structure BL and the active area AA, and improving the performance of the memory.

[0056] Optionally, the material of the metal silicide layer 500 may be one or more of cobalt silicide, titanium silicide, polysilicide, tungsten silicide, molybdenum silicide, tantalum silicide or platinum silicide, which is not limited in the present invention.

[0057] Furthermore, in this embodiment, in the direction perpendicular to the height, the width dimension X1 of the metal silicide layer 500 is greater than the width dimension X2 of the bit line conductive layer. That is to say, the bit line conductive layer and the bit line shielding layer 400d are both formed above the metal silicide layer 500, and the metal silicide layer 500 has a large width, which can ensure that the bottom of the bit line conductive layer is completely in contact with the active area AA through the metal silicide layer 500, thereby further reducing the contact resistance between the bit line structure BL and the active area AA.

[0058] The following is combined with Figure 1 and Figure 2a to Figure 2e The method for forming the memory as described above in this embodiment is described in detail. Figure 1 is a flow chart of a method for forming a memory in an embodiment of the present invention, Figure 2a to Figure 2e It is a schematic diagram of the structure formed during the preparation process of the memory in the embodiment of the present invention.

[0059] like Figure 1 As shown, the method for forming the memory includes:

[0060] Step S100: providing a substrate, wherein the substrate comprises a plurality of active regions extending along a first predetermined direction;

[0061] Step S200: forming a plurality of bit line structures on the substrate, wherein the bit line structures extend along a second predetermined direction to pass through corresponding active regions, wherein portions of the bit line structures located on the substrate constitute first bit line structures, and portions of the bit line structures extending from the substrate to the active regions constitute second bit line structures; and,

[0062] Step S300: forming a metal silicide layer between the second bit line structure and the active region to electrically connect the active region and the second bit line structure.

[0063] Specifically, first refer to Figure 2a As shown, step S100 is performed to provide a substrate 100 , in which a trench isolation structure STI is formed, and a plurality of active areas AA extending along a first predetermined direction are defined by the trench isolation structure SIT.

[0064] Then continue to refer to Figure 2a As shown, a word line structure WL is formed in the substrate 100, and the word line structure WL extends along a third predetermined direction and passes through the corresponding active area AA and the trench isolation structure STI. Further, the lateral width (width dimension in a direction perpendicular to the height) of the word line structure WL in the active area AA is smaller than the lateral width of the word line structure WL in the trench isolation structure STI; the bottom of the word line structure WL in the active area AA is lower than the bottom of the word line structure WL in the trench isolation structure STI.

[0065] The steps of forming the word line structure WL may be as follows:

[0066] forming a word line trench (not shown) in the substrate 100 and extending along a third predetermined direction;

[0067] Forming a gate dielectric layer 200a on the substrate 100, wherein the gate dielectric layer 200a covers the inner wall of the word line trench, and the gate dielectric layer 200a can be used as an insulating layer for isolating the word line and the active area AA;

[0068] Then, a gate conductive layer 200b is formed in the word line groove. The gate conductive layer 200b is a conductive film layer, such as polysilicon or tungsten. The gate conductive layer 200b fills a part of the depth of the word line groove. Specifically, for example, the height of the gate conductive layer 200b in the word line groove can be reduced by an etch-back process, so that the top surface of the gate conductive layer 200b is lower than the upper surface of the substrate 100. In this way, the lower part of the word line groove is filled with the gate conductive layer 200b, and the upper part of the word line groove is still in an empty state.

[0069] A gate insulating layer 200c is formed on the gate conductive layer 200b. The gate insulating layer 200c covers the gate conductive layer 200b and completely fills the word line trench. The gate dielectric layer 200a, the gate conductive layer 200b and the gate insulating layer 200c together constitute the word line structure WL.

[0070] It should be noted that although the mask layer on the surface of the substrate 100 is not shown in the drawings of this embodiment, it should be recognized that in the process of etching the substrate 100 to form the word line groove, a mask layer is usually formed on the surface of the substrate 100 to prevent areas in the substrate 100 that do not correspond to the groove from being etched.

[0071] Continue to refer Figure 2a As shown, the method for forming the memory also includes: forming a source / drain region in the substrate 100, the side edge boundary of the source / drain region extends to the side wall of the word line groove close to the top opening, and the bottom boundary of the source / drain region is lower than the top position of the gate conductive layer 200b, so that there is an overlapping area facing each other between the source / drain region and the gate conductive layer 200b, and in the overlapping area, the gate conductive layer 200b and the source / drain region are separated from each other by the gate dielectric layer 200a.

[0072] Specifically, the source / drain region includes a first source / drain region and a second source / drain region, and the first source / drain region and the second source / drain region are respectively located on both sides of the word line structure WL. In this embodiment, the side edge boundary of the first source / drain region also extends to the sidewall of the trench isolation structure STI.

[0073] It should be noted that in this embodiment, the source and drain regions are prepared after the word line grooves and word line structures WL are formed. However, in other embodiments, the source and drain regions may be formed first, and then the word line grooves and word line structures WL are prepared in sequence, which is not limited here.

[0074] Continue to refer Figure 2a As shown, the substrate 100 is sequentially formed with a first barrier layer 300a and a second barrier layer 300b from bottom to top, and the first barrier layer 300a and the second barrier layer 300b together constitute a barrier layer. The barrier layer can protect the substrate 100 in a subsequent etching process.

[0075] refer to Figure 2b As shown, step S200 and step S300 are performed to form a bit line structure on the substrate 100. When forming the bit line structure, a bit line trench Tr needs to be formed first. Specifically, a mask layer 310 is formed on the barrier layer, and then the mask layer 310 is patterned to form the bit line trench Tr. Since the bit line trench Tr forms a bit line structure in a subsequent step, the bit line trench Tr needs to extend along the second predetermined direction.

[0076] like Figure 2bAs described, a portion of the bit line trench Tr is located in the mask layer 310, and another portion of the bit line trench Tr passes through the barrier layer from the mask layer 310 and extends downward to the active area AA of the substrate 100. For the convenience of description, the portion of the bit line trench Tr located in the mask layer 310 is referred to as a first bit line trench Tr1, and the portion of the bit line trench Tr extending from the mask layer 310 to the active area AA of the substrate 100 is referred to as a second bit line trench Tr2.

[0077] It can be understood that the first bit line trench Tr1 can be formed by etching the mask layer 310; and the second bit line trench Tr2 needs to be formed by etching the mask layer 310, the barrier layer and a portion of the active area AA of the substrate 100 in sequence from top to bottom. Due to the miniaturization of device size, the lateral dimensions between adjacent word line structures WL are further shortened. In order to increase the bit line structure, the second bit line trench Tr2 is usually extended laterally to above the gate conductive layer 200b of the word line structure WL. That is, when forming the second bit line trench Tr2, a portion of the height of the side wall of the gate insulating layer 200c of the word line structure WL is also etched away, so that the second bit line trench Tr2 is laterally widened.

[0078] Furthermore, the bottom of the second bit line trench Tr2 needs to be higher than the top of the gate conductive layer 200 b in the word line structure WL, so as to prevent the gate conductive layer 200 b in the word line structure WL2 from being damaged.

[0079] refer to Figure 2c As shown, a metal silicide layer 500 is formed in the second bit line trench Tr2 , and the metal silicide layer 500 covers the bottom of the second bit line trench Tr2 .

[0080] In this embodiment, the metal silicide layer 500 is formed by a self-aligned silicide process. Specifically, taking the material of the metal silicide layer 500 as titanium silicide as an example, the steps of forming the metal silicide layer 500 include:

[0081] First, a titanium metal layer is formed on the entire surface of the substrate 100, and the titanium metal layer covers the surface of the barrier layer, the surface of the mask layer 310, and the inner walls of the first bit line trench Tr1 and the second bit line trench Tr2;

[0082] Then, a first rapid annealing process is performed, so that the portion of the titanium metal layer in contact with the active area AA (the titanium metal layer at the bottom of the second bit line trench Tr2) reacts with silicon in the substrate 100 to generate titanium silicide;

[0083] Next, all the unreacted titanium metal layer is removed by a wet etching process such as ammonium hydroxide and hydrogen peroxide, leaving titanium silicide at the bottom of the second bit line trench Tr2;

[0084] Finally, a second rapid annealing process is performed to produce a metal silicide phase with low resistivity.

[0085] In this embodiment, the metal silicide layer 500 is formed by a self-aligned silicide process, so that alignment errors can be avoided. However, it should be understood that the metal silicide layer 500 can also be formed by other processes, and the present invention is not limited thereto.

[0086] See also Figure 2d As shown, a bit line structure BL is formed in the bit line trench Tr and the mask layer is removed. The bit line structure BL includes a bit line conductive layer, and the bit line conductive layer includes three conductive material layers of different materials stacked in sequence. Based on this, the formed bit line structure BL can include a first bit line conductive layer 400a, a second bit line conductive layer 400b and a third bit line conductive layer 400c. Further, the bit line structure BL also includes a bit line shielding layer 400d, and the bit line shielding layer 400d can be a patterned film layer and formed above the bit line conductive layer. In an optional scheme, for example, the patterned bit line shielding layer 400d is used to sequentially perform a patterning process on the conductive material layer below it. In this embodiment, the method for forming the bit line structure BL also includes: forming an isolation sidewall 400e on the sidewalls of the first bit line conductive layer 400a, the second bit line conductive layer 400b, the third bit line conductive layer 400c and the bit line shielding layer 400d.

[0087] See also Figure 2d As shown, the bit line structure BL includes a first bit line structure BL1 and a second bit line structure BL2, the first bit line structure BL1 is located on the substrate 100, and the second bit line structure BL2 extends from the substrate 100 to the active area, and the second bit line structure BL2 is formed on the metal silicide layer 500 and is electrically connected to the active area AA through the metal silicide layer 500.

[0088] Embodiment 2

[0089] Figure 3 FIG. 1 is a schematic diagram of a partial structure of the memory in this embodiment. Figure 3 As shown, the difference from the first embodiment is that in this embodiment, the bit line conductive layer 400f in the bit line structure BL is a single film layer, and the material of the bit line conductive layer 400f is the same as that of the gate conductive layer 200b.

[0090] Specifically, the bit line structure BL includes a single-layer bit line conductive layer 400f, a bit line shielding layer 400d and an isolation sidewall 400e, wherein the bit line shielding layer 400d covers the bit line conductive layer 400f, and the isolation sidewall 400e covers the sidewalls of the bit line conductive layer 400f and the bit line shielding layer 400d. In this embodiment, the gate conductive layer 200b is made of doped polysilicon, and the bit line conductive layer 400f is also made of doped polysilicon, but this should not be limited thereto.

[0091] Please continue reading Figure 3 Furthermore, the method for forming the memory in this embodiment can be the same as the method for forming the memory in the first embodiment. The only difference is that when forming the bit line conductive layer of the bit line structure BL, only a film layer of the same material as the gate conductive layer 200b is formed, and then the bit line conductive layer 400f is formed by etching. Compared with the first embodiment, the structure of the bit line structure BL is simplified in this embodiment, and the process of forming the bit line structure BL can be simpler.

[0092] Embodiment 3

[0093] Figure 4 FIG. 1 is a schematic diagram of a partial structure of the memory in this embodiment. Figure 4 As shown, the difference from the first embodiment is that in this embodiment, the isolation sidewall 400e also covers the sidewall of the metal silicide layer 500.

[0094] Specifically, there is a gap between the metal silicide layer 500 and the sidewall of the bit line conductive layer and the second bit line trench, and the isolation spacer 400e is filled in the gap to simultaneously cover the sidewalls of the metal silicide layer 500 and the bit line conductive layer. At this time, in the direction perpendicular to the height, the width dimension X1 of the metal silicide layer 500 is equal to the width dimension X2 of the bit line conductive layer.

[0095] In this embodiment, the metal silicide layer 500 and the isolation spacer 400 e are both formed in the bit line trench, and the bottom of the metal silicide layer 500 and the isolation spacer 400 e are located at the same depth position of the substrate 100 .

[0096] Please continue reading Figure 4, further, the method for forming the memory in this embodiment can be the same as the method for forming the memory in the first embodiment. The only difference is that in the process of forming the bit line conductive layer, the sidewall of the metal silicide layer 500 can also be partially etched so that the width of the metal silicide layer 500 is equal to that of the formed bit line conductive layer. Compared with the first embodiment, the isolation sidewall 400e in this embodiment can protect the metal silicide layer 500 and the bit line conductive layer at the same time, and can prevent the metal silicide layer 500 from interfering with the word line structure WL.

[0097] Embodiment 4

[0098] Figure 5 FIG. 1 is a schematic diagram of a partial structure of the memory in this embodiment. Figure 5 As shown, the difference from the third embodiment is that in this embodiment, the depth position of the bottom of the isolation sidewall 400e in the substrate 100 is lower than the depth position of the bottom of the metal silicide layer 500 in the substrate 100.

[0099] For more details, please refer to Figure 5 , the bottom of the isolation sidewall 400e is located at a first depth position H1 of the substrate 100, and the bottom of the metal silicide layer 500 is located at a second depth position H2 in the substrate 100, and the first depth position H1 is lower than the second depth position H2. Alternatively, it can be understood that the metal silicide layer 500 is located in the bit line trench, and the isolation sidewall 400e is located in the bit line trench and extends downward from the bottom of the bit line trench to a certain depth.

[0100] It should be understood that in this embodiment, in a direction perpendicular to the height, the width dimension X1 of the metal silicide layer 500 is equal to the width dimension X2 of the bit line conductive layer.

[0101] Please continue reading Figure 5 , further, the method for forming the memory in this embodiment can be the same as the method for forming the memory in the third embodiment. The only difference is that, in the process of forming the bit line conductive layer, the side wall of the metal silicide layer 500 can also be partially etched, so that the width of the metal silicide layer 500 is equal to that of the formed bit line conductive layer, and the substrate 100 at the bottom of the bit line trench is also etched to a certain depth, so that the parts of the bit line trench located at both ends of the metal silicide layer 500 extend into the substrate 100 to the first depth position H1. Then, the isolation sidewall 400e is formed in the bit line trench, and the isolation sidewall 400e extends upward from the first depth position H1 and covers the metal silicide layer 500 and the sidewall of the bit line conductive layer.

[0102] Compared with the third embodiment, the isolation spacer 400e in this embodiment can better protect the metal silicide layer 500 and the bit line conductive layer, thereby improving the effect of preventing the metal silicide layer 500 from interfering with the word line structure WL.

[0103] In summary, in the memory provided by the embodiment of the present invention, the substrate includes a plurality of active areas extending along a first predetermined direction; the substrate is formed with a plurality of bit line structures extending along a second predetermined direction and passing through the corresponding active areas, the portion of the bit line structure located on the substrate constitutes a first bit line structure, and the portion of the bit line structure extending from the substrate to the active area constitutes a second bit line structure; a metal silicide layer is formed between the second bit line structure and the active area, and the active area and the second bit line structure are electrically connected through the metal silicide layer. Since the metal silicide layer has a lower resistivity, the contact resistance between the active area and the second bit line structure can be reduced, thereby improving the performance of the memory.

[0104] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0105] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0106] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0107] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

[0108] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A memory, characterized in that: include: A substrate, comprising a plurality of active regions extending along a first predetermined direction and a trench isolation structure for separating adjacent active regions; A plurality of bit line structures, located on the substrate and extending along a second predetermined direction to pass through corresponding active regions, wherein portions of the bit line structures located on the substrate constitute first bit line structures, and portions of the bit line structures extending from the substrate to the active regions constitute second bit line structures; as well as, a metal silicide layer, located between the second bit line structure and the active area, and used to electrically connect the active area and the second bit line structure; The bit line structure includes a bit line conductive layer, a bit line shielding layer and an isolation side wall, wherein the bit line shielding layer covers the top wall of the bit line conductive layer, the isolation side wall at least covers the bit line conductive layer and the bit line shielding layer, and the isolation side wall is in direct contact with both the metal silicide layer and the trench isolation structure.

2. The memory according to claim 1, wherein: The bottom of the isolation spacer is located at a first depth position in the substrate, and the bottom of the metal silicide layer is located at a second depth position in the substrate. The first depth position is lower than the second depth position.

3. The memory according to claim 1, wherein: In a direction perpendicular to the height, the width of the metal silicide layer is greater than or equal to the width of the bit line conductive layer.

4. The memory according to claim 1, wherein: The material of the metal silicide layer includes one or more of cobalt silicide, titanium silicide, tungsten silicide, molybdenum silicide, tantalum silicide or platinum silicide.

5. The memory according to claim 1, wherein: The bottom surface of the metal silicide layer is lower than the bottom surface of the isolation sidewall.

6. The memory according to claim 1, wherein: A top surface of the metal silicide layer is lower than a top surface of the substrate.

7. The memory according to claim 1, wherein: Also included is a circuit located in the word line trench of the substrate: A word line structure comprises a gate dielectric layer, a gate conductive layer and a gate insulating layer, wherein the gate dielectric layer covers the inner wall of the word line groove, the gate conductive layer is located on the gate dielectric layer and fills a partial depth of the word line groove, the gate insulating layer is located on the gate conductive layer and fills the remaining depth of the word line groove, and the metal silicide layer contacts the gate insulating layer.

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