Charge pump circuit and control method

Abstract

The application discloses a charge pump circuit and a control method. The circuit comprises a plurality of charge-discharge circuits and a filter circuit. The charge-discharge circuit comprises a first switch unit, a charge-discharge unit and a second switch unit connected in sequence. The opening and closing of the first switch unit and the second switch unit realizes the charge-discharge of the charge-discharge unit. The charge-discharge circuit outputs corresponding output signals in different time periods. The superposition of the output signals reduces the amplitude of the ripple on the total output signal and increases the frequency of the ripple on the total output signal. The filter circuit is used for filtering the ripple on the total output signal. According to the charge pump circuit, the number of the charge-discharge circuits is selected, the number of the output signals output by the charge-discharge circuit in different time periods is increased, the superposition of the output signals reduces the amplitude of the ripple on the total output signal and increases the frequency of the ripple, the same filter circuit produces a better filtering effect, and the area and power consumption of the circuit are not significantly increased.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a charge pump circuit and control method. Background Technology

[0002] When traditional charge pump structures are used as internal power sources for chips, they introduce internal ripple, which is ultimately reflected at the output, affecting the stability of the chip's output waveform. Figure 1 The diagram shows a common charge pump structure, consisting of a MOSFET M1, a capacitor C, and a MOSFET M2. MOSFET M1, capacitor C, and MOSFET M2 are all controlled by the input waveform of the control circuit. The ripple frequency is also generally the frequency of the input waveform of the control circuit. The ripple generated by this structure is generally large.

[0003] Ripple is generally considered in terms of both amplitude and frequency. The smaller the amplitude, the better, and the higher the frequency, the better. A simple traditional solution is to increase the frequency of the clock signal generation circuit to push it to a higher frequency, but this increases the cost of the increased current. Some existing ripple suppression structures are quite complex, and the additional structure can significantly increase the instantaneous power consumption or area of ​​the circuit.

[0004] Additionally, we typically connect a load capacitor to the output of the charge pump, and if we add a resistor in series, this forms a low-pass filter to optimize ripple. However, if the charge pump's current load is too large, we cannot use a large resistor (the voltage drop would be too great), and the low-pass filter's effectiveness will deteriorate. If the ripple is pushed to higher frequencies, we only need a small resistor to achieve a good filtering effect.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a charge pump circuit and control method that can reduce the amplitude of ripple and increase the frequency of ripple under similar area power consumption.

[0007] To achieve the above objectives, embodiments of the present invention provide a charge pump circuit, including: multiple parallel charging and discharging circuits and a filter circuit.

[0008] The charging and discharging circuit includes a first switching unit, a charging and discharging unit, and a second switching unit connected in series. All three units are controlled by a control signal. Closing the first switching unit and opening the corresponding second switching unit controls the corresponding charging and discharging unit to charge. Closing the second switching unit and opening the corresponding first switching unit controls the corresponding charging and discharging unit to discharge. The second switching unit of each charging and discharging circuit is closed at different time points within a control cycle, so that each charging and discharging circuit outputs an output signal based on the discharge of the charging and discharging unit at different time points. By superimposing the output signals of multiple parallel charging and discharging circuits, the amplitude of the ripple on the total output signal is reduced, and the frequency of the ripple on the total output signal is increased.

[0009] The filter circuit is connected to the charging and discharging circuit and is used to filter out the ripple on the total output signal.

[0010] In one or more embodiments of the present invention, the amplitude of the ripple on the total output signal is 1 / n times the amplitude of the ripple on the output signal, and the frequency of the ripple on the total output signal is n times the frequency of the output signal, where n is the number of charging and discharging circuits.

[0011] In one or more embodiments of the present invention, the first switching unit includes a first MOSFET, a first diode, and a first capacitor. The source of the first MOSFET is connected to a power supply voltage. The gate of the first MOSFET is connected to the cathode of the first diode and the first terminal of the first capacitor. The anode of the first diode is connected to a power supply voltage. The drain of the first MOSFET is connected to the first terminal of a charging / discharging unit and a second switching unit. The second terminal of the first capacitor is used to receive a corresponding control signal.

[0012] In one or more embodiments of the present invention, the second switching unit includes a second MOS transistor, a second diode, and a second capacitor. The drain of the second MOS transistor is connected to the first terminal of the charging and discharging unit. The gate of the second MOS transistor is connected to the cathode of the second diode and the first terminal of the second capacitor. The anode of the second diode is connected to the power supply voltage. The second terminal of the second capacitor is used to receive a corresponding control signal. The source of the second MOS transistor is used to output an output signal.

[0013] In one or more embodiments of the present invention, the filter circuit includes a resistor and a third capacitor. The first end of the resistor is connected to the charging and discharging circuit, the second end of the resistor is connected to the first end of the third capacitor and is used to output the total output signal, and the second end of the third capacitor is grounded.

[0014] In one or more embodiments of the present invention, the charge pump circuit further includes a control signal generation circuit connected to the charging and discharging circuit. The control signal generation circuit includes a signal generator, a signal processing and distribution unit, and a signal shaping and driving unit. The signal processing and distribution unit is connected to the signal generator and is used to output multiple driving signals. The signal shaping and driving unit is connected to the signal processing and distribution unit. Multiple signal shaping and driving units are provided and correspond to the charging and discharging circuit. Each signal shaping and driving unit generates a control signal according to the driving signal to control the first switching unit, the charging and discharging unit, and the second switching unit of the charging and discharging circuit respectively.

[0015] In one or more embodiments of the present invention, the signal processing allocation unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, and a thirteenth inverter;

[0016] The CK terminal of the first D flip-flop is connected to the signal generator, the D input terminal of the first D flip-flop is connected to the QN output terminal and the input terminal of the second inverter, and the Q output terminal of the first D flip-flop is connected to the input terminal of the third inverter.

[0017] The input terminal of the first inverter is connected to the signal generator, the CK input terminal of the second D flip-flop is connected to the output terminal of the first inverter, the D input terminal of the second D flip-flop is connected to the output terminal of the second inverter, the QN output terminal of the second D flip-flop is connected to the input terminal of the fourth inverter, and the Q output terminal of the second D flip-flop is connected to the input terminal of the fifth inverter.

[0018] The CK input of the third D flip-flop is connected to the output of the second inverter. The D input of the first slave D flip-flop is connected to the QN input and the input of the sixth inverter. The output of the sixth inverter is used to output the first drive signal. The Q output of the third D flip-flop is connected to the input of the seventh inverter. The output of the seventh inverter is used to output the second drive signal.

[0019] The CK input of the fourth D flip-flop is connected to the output of the fourth inverter, the D input of the fourth D flip-flop is connected to the output of the sixth inverter, the QN output of the fourth flip-flop is connected to the input of the eighth inverter, the output of the eighth inverter is used to output the third drive signal, and the Q output of the fourth flip-flop is connected to the input of the ninth inverter, the output of the ninth inverter is used to output the fourth drive signal.

[0020] The CK input of the fifth D flip-flop is connected to the output of the third inverter, the D input of the fifth D flip-flop is connected to the output of the eighth inverter, the QN output of the fifth D flip-flop is connected to the input of the tenth inverter, the output of the tenth inverter is used to output the fifth drive signal, and the Q output of the fifth D flip-flop is connected to the input of the eleventh inverter, the output of the eleventh inverter is used to output the sixth drive signal.

[0021] The CK input of the sixth D flip-flop is connected to the output of the fifth inverter, the D input of the sixth D flip-flop is connected to the output of the tenth inverter, the QN output of the sixth D flip-flop is connected to the input of the twelfth inverter, the output of the twelfth inverter is used to output the seventh drive signal, and the Q output of the sixth D flip-flop is connected to the input of the thirteenth inverter, the output of the thirteenth inverter is used to output the eighth drive signal.

[0022] In one or more embodiments of the present invention, the signal shaping driving unit includes a NOR gate, a fourteenth inverter, a fifteenth inverter, a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a NAND gate, a twentieth inverter, and a twenty-first inverter;

[0023] The first and second input terminals of the NOR gate are respectively used to receive corresponding drive signals. The output terminal of the NOR gate is connected to the input terminal of the fourteenth inverter. The output terminal of the fourteenth inverter is connected to the input terminal of the fifteenth inverter. The output terminal of the fifteenth inverter is used to output a first control signal to control the first switching unit.

[0024] The sixteenth, seventeenth, and eighteenth inverters are connected in series. The input terminal of the sixteenth inverter is used to receive the corresponding drive signal, and the output terminal of the eighteenth inverter is used to output the second control signal for controlling the charging and discharging unit.

[0025] The first and second input terminals of the NAND gate are respectively used to receive corresponding drive signals. The output terminal of the NAND gate is connected to the input terminal of the twentieth inverter. The output terminal of the twentieth inverter is connected to the input terminal of the twentieth inverter. The output terminal of the twentieth inverter is used to output a third control signal to control the second switching unit.

[0026] This invention also discloses a charge pump circuit control method, comprising:

[0027] Within a certain time period of a control cycle, the first switching unit of several charging and discharging circuits is closed and the corresponding second switching unit is opened, thereby controlling the corresponding charging and discharging unit to charge.

[0028] During a certain time period of the control cycle, the second switching unit of one of the charging and discharging circuits is closed and the corresponding first switching unit is opened, thereby controlling the corresponding charging and discharging unit to discharge.

[0029] During the control cycle, the output signals generated by the discharge of each charging and discharging unit of the charging and discharging circuit are superimposed to reduce the amplitude of the ripple on the total output signal and increase the frequency of the ripple on the total output signal.

[0030] The total output signal is filtered to remove ripples.

[0031] In one or more embodiments of the present invention, the control method includes:

[0032] During the control cycle from T0 to T1, the first and second switching units of the first charging and discharging circuit are disconnected; the first switching unit of the second charging and discharging circuit is disconnected and the second switching unit is closed, controlling the charging and discharging unit to discharge; the first and second switching units of the third charging and discharging circuit are disconnected; the second switching unit of the fourth charging and discharging circuit is disconnected and the first switching unit is controlled to go from closed to open, controlling the charging and discharging unit to charge.

[0033] During the control period T1 to T2, the second switch unit of the first charging and discharging circuit is disconnected and the first switch unit is controlled to close, and the charging and discharging unit is controlled to charge; the first switch unit and the second switch unit of the second charging and discharging circuit are disconnected; the first switch unit of the third charging and discharging circuit is disconnected and the second switch unit is closed, and the charging and discharging unit is controlled to discharge; the first switch unit and the second switch unit of the fourth charging and discharging circuit are disconnected.

[0034] During the control cycle from T2 to T3, the second switch unit of the first charging and discharging circuit is disconnected and the first switch unit is closed, controlling the charging and discharging unit to charge; the second switch unit of the second charging and discharging circuit is disconnected and the first switch unit is controlled to go from open to closed, controlling the charging and discharging unit to charge; the first switch unit and the second switch unit of the third charging and discharging circuit are disconnected; the first switch unit of the fourth charging and discharging circuit is disconnected and the second switch unit is closed, controlling the charging and discharging unit to discharge.

[0035] During the control cycle from T3 to T4, the first switch unit of the first charging and discharging circuit is disconnected and the second switch unit is closed, controlling the charging and discharging unit to discharge; the first switch unit of the second charging and discharging circuit is closed and the second switch unit is disconnected, controlling the charging and discharging unit to charge; the second switch unit of the third charging and discharging circuit is disconnected and the first switch unit is controlled to go from open to closed, controlling the charging and discharging unit to charge; the first switch unit and the second switch unit of the fourth charging and discharging circuit are disconnected.

[0036] Compared with the prior art, the charge pump circuit and control method according to the embodiments of the present invention, by selecting the number of charging and discharging circuits, increases the number of output signals output by the charging and discharging circuits at different time periods. By superimposing multiple output signals, the amplitude of the ripple on the total output signal is reduced and the frequency of the ripple is increased, so that the same filtering circuit produces a better filtering effect, and the circuit area and power consumption are not significantly increased. Attached Figure Description

[0037] Figure 1 This is a circuit diagram of a charge pump circuit in the prior art.

[0038] Figure 2 This is a circuit diagram of a charge pump circuit according to Embodiment 1 of the present invention.

[0039] Figure 3 This is a circuit diagram of the signal generator and signal processing and distribution unit of the control signal generation circuit according to Embodiment 1 of the present invention.

[0040] Figure 4 This is a circuit diagram of the signal shaping and driving unit of the control signal generation circuit according to Embodiment 1 of the present invention.

[0041] Figure 5 This is a waveform diagram of the control signal output by the control signal generation circuit according to Embodiment 1 of the present invention.

[0042] Figure 6 This is a flowchart of a charge pump circuit control method according to Embodiment 1 of the present invention. Detailed Implementation

[0043] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0044] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0045] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0046] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0047] like Figure 2 As shown, a charge pump circuit includes: multiple parallel charging and discharging circuits and a filter circuit. The charging and discharging circuits are connected to a power supply voltage AVDD and the filter circuit. Preferably, there are two or four charging and discharging circuits. In other embodiments, the number of charging and discharging circuits can be other numbers, such as three or more.

[0048] Each charging and discharging circuit outputs its corresponding output signal, which is generally a voltage signal. The total output signal is formed by superimposing multiple output signals. By superimposing the output signals of multiple parallel charging and discharging circuits, the amplitude of the ripple on the total output signal is reduced and the frequency of the ripple on the total output signal is increased. Finally, the ripple on the total output signal is filtered out by a filter circuit.

[0049] Each charging / discharging circuit includes a first switching unit, a charging / discharging unit, and a second switching unit connected together. Both the first and second switching units are connected to the first terminal of the charging / discharging unit, and all three are controlled by a control signal.

[0050] The first switching unit of the charging / discharging circuit is closed while the corresponding second switching unit is open, controlling the corresponding charging / discharging unit to charge. Conversely, the second switching unit of the charging / discharging circuit is closed while the corresponding first switching unit is open, controlling the corresponding charging / discharging unit to discharge. By controlling the second switching unit of each charging / discharging circuit to close at different time periods within a control cycle, each charging / discharging circuit outputs an output signal based on the discharge generated by the charging / discharging unit at different time periods.

[0051] like Figure 3 and Figure 4 As shown, the charge pump circuit also includes a control signal generation circuit connected to the charge / discharge circuit. The control signal generation circuit is used to generate control signals to control the first switching unit, the charge / discharge unit, and the second switching unit of the charge / discharge circuit, respectively.

[0052] In this embodiment, the amplitude of the ripple on the total output signal formed by the superposition of multiple output signals is 1 / n times the amplitude of the ripple on a single output signal, and the frequency of the ripple on the total output signal is n times the frequency of a single output signal, where n is the number of charging and discharging circuits. Therefore, the more charging and discharging circuits there are, the smaller the amplitude and the higher the frequency of the ripple on the total output signal, thus greatly reducing the impact of ripple on the stability of the output waveform. Furthermore, it also improves the filtering effect of the filtering circuit on ripple.

[0053] For example, the original ripple amplitude was 100mV, and the main frequency was 10MHz. By using a four-charge-discharge circuit structure, the amplitude was reduced to 25mV, the main frequency became 40MHz, and the area and power consumption did not increase significantly. In addition, the filtering circuit with the same capability also had a better filtering effect at 40MHz.

[0054] The invention will now be described using an example of four charging and discharging circuits.

[0055] like Figure 2 As shown, the four charging and discharging circuits are the first charging and discharging circuit 10, the second charging and discharging circuit 20, the third charging and discharging circuit 30, and the fourth charging and discharging circuit 40.

[0056] The first charging and discharging circuit 10 includes a first switching unit 11, a charging and discharging unit, and a second switching unit 12 connected together.

[0057] The charging and discharging unit includes a capacitor C10. The first end of the capacitor C10 is connected to the first switching unit 11 and the second switching unit 12, and the second segment of the capacitor C10 is used to receive the corresponding control signal.

[0058] The first switching unit 11 includes a first MOSFET NM11, a first diode D11, and a first capacitor C11. The source of the first MOSFET NM11 is connected to the power supply voltage AVDD. The gate of the first MOSFET NM11 is connected to the cathode of the first diode D11 and the first terminal of the first capacitor C11. The drain of the first MOSFET NM11 is connected to the first terminal of the capacitor C10 and the second switching unit 12. The anode of the first diode D11 is connected to the power supply voltage AVDD. The second terminal of the first capacitor C11 is used to receive the corresponding control signal. The first diode D11 and the first capacitor C11 are used to improve the switching capability of the first MOSFET NM11.

[0059] The second switching unit 12 includes a second MOSFET PM11, a second diode D12, and a second capacitor C12.

[0060] The drain of the second MOSFET PM11 is connected to the first terminal of capacitor C10. The gate of the second MOSFET PM11 is connected to the cathode of the second diode D12 and the first terminal of the second capacitor C12. The anode of the second diode D12 is connected to the power supply voltage AVDD. The second terminal of the second capacitor C12 is used to receive the corresponding control signal, and the source of the second MOSFET PM11 is used to output the output signal. The second diode D12 and the second capacitor C12 are used to improve the switching capability of the second MOSFET PM11.

[0061] like Figure 2 As shown, the second charging and discharging circuit 20 includes a first switching unit 21, a charging and discharging unit, and a second switching unit 22 connected together.

[0062] The charging and discharging unit includes a capacitor C20. The first end of the capacitor C20 is connected to the first switching unit 21 and the second switching unit 22, and the second segment of the capacitor C20 is used to receive the corresponding control signal.

[0063] The first switching unit 21 includes a first MOSFET NM21, a first diode D21, and a first capacitor C21. The source of the first MOSFET NM21 is connected to the power supply voltage AVDD. The gate of the first MOSFET NM21 is connected to the cathode of the first diode D21 and the first terminal of the first capacitor C21. The drain of the first MOSFET NM21 is connected to the first terminal of the capacitor C21 and the second switching unit 22. The anode of the first diode D21 is connected to the power supply voltage AVDD. The second terminal of the first capacitor C21 is used to receive the corresponding control signal. The first diode D21 and the first capacitor C21 are used to improve the switching capability of the first MOSFET NM21.

[0064] The second switching unit 22 includes a second MOSFET PM21, a second diode D22, and a second capacitor C22.

[0065] The drain of the second MOSFET PM21 is connected to the first terminal of capacitor C20. The gate of the second MOSFET PM21 is connected to the cathode of the second diode D22 and the first terminal of the second capacitor C22. The anode of the second diode D22 is connected to the power supply voltage AVDD. The second terminal of the second capacitor C22 is used to receive the corresponding control signal, and the source of the second MOSFET PM21 is used to output the output signal. The second diode D22 and the second capacitor C22 are used to improve the switching capability of the second MOSFET PM21.

[0066] like Figure 2 As shown, the third charging and discharging circuit 30 includes a first switching unit 31, a charging and discharging unit, and a second switching unit 32 connected together.

[0067] The charging and discharging unit includes a capacitor C30. The first end of the capacitor C30 is connected to the first switching unit 31 and the second switching unit 32, and the second end of the capacitor C30 is used to receive the corresponding control signal.

[0068] The first switching unit 31 includes a first MOSFET NM31, a first diode D31, and a first capacitor C31. The source of the first MOSFET NM31 is connected to the power supply voltage AVDD. The gate of the first MOSFET NM31 is connected to the cathode of the first diode D31 and the first terminal of the first capacitor C31. The drain of the first MOSFET NM31 is connected to the first terminal of the capacitor C31 and the second switching unit 32. The anode of the first diode D31 is connected to the power supply voltage AVDD. The second terminal of the first capacitor C31 is used to receive the corresponding control signal. The first diode D31 and the first capacitor C31 are used to improve the switching capability of the first MOSFET NM31.

[0069] The second switching unit 32 includes a second MOSFET PM31, a second diode D32, and a second capacitor C32.

[0070] The drain of the second MOSFET PM31 is connected to the first terminal of capacitor C30. The gate of the second MOSFET PM31 is connected to the cathode of the second diode D32 and the first terminal of the second capacitor C32. The anode of the second diode D32 is connected to the power supply voltage AVDD. The second terminal of the second capacitor C32 is used to receive the corresponding control signal, and the source of the second MOSFET PM31 is used to output the output signal. The second diode D32 and the second capacitor C32 are used to improve the switching capability of the second MOSFET PM31.

[0071] like Figure 2 As shown, the fourth charging and discharging circuit 40 includes a first switching unit 41, a charging and discharging unit, and a second switching unit 42 connected together.

[0072] The charging and discharging unit includes a capacitor C40. The first end of the capacitor C40 is connected to the first switching unit 41 and the second switching unit 42, and the second end of the capacitor C40 is used to receive the corresponding control signal.

[0073] The first switching unit 41 includes a first MOSFET NM41, a first diode D41, and a first capacitor C41. The source of the first MOSFET NM41 is connected to the power supply voltage AVDD. The gate of the first MOSFET NM41 is connected to the cathode of the first diode D41 and the first terminal of the first capacitor C41. The drain of the first MOSFET NM41 is connected to the first terminal of the capacitor C41 and the second switching unit 42. The anode of the first diode D41 is connected to the power supply voltage AVDD. The second terminal of the first capacitor C41 is used to receive corresponding control signals. The first diode D41 and the first capacitor C41 are used to improve the switching capability of the first MOSFET NM41.

[0074] The second switching unit 42 includes a second MOSFET PM41, a second diode D42, and a second capacitor C42.

[0075] The drain of the second MOSFET PM41 is connected to the first terminal of capacitor C40. The gate of the second MOSFET PM41 is connected to the cathode of the second diode D42 and the first terminal of the second capacitor C42. The anode of the second diode D42 is connected to the power supply voltage AVDD. The second terminal of the second capacitor C42 is used to receive the corresponding control signal, and the source of the second MOSFET PM41 is used to output the output signal. The second diode D42 and the second capacitor C42 are used to improve the switching capability of the second MOSFET PM41.

[0076] like Figure 2 As shown, the filter circuit 50 includes a resistor R and a third capacitor C50. The first end of the resistor R is connected to the source of the second MOSFET PM11, the source of the second MOSFET PM21, the source of the second MOSFET PM31, and the source of the second MOSFET PM41. The second end of the resistor R is connected to the first end of the third capacitor C50 and is used to output the total output signal AVDD_CP. The second end of the third capacitor C50 is grounded.

[0077] In this embodiment, the filter circuit 50, composed of a resistor R with a fixed resistance value and a third capacitor C50 with a fixed capacitance value, has the characteristic that the higher the frequency of the signal, the better the filtering effect. Therefore, by using four charging and discharging circuits, the amplitude of the superimposed ripple is reduced to one-quarter of the original value, and the frequency is increased to four times the original value. Thus, only a small resistor R is needed to improve the filtering effect of the filter circuit 50, making the total output signal more stable.

[0078] Furthermore, the main area of ​​the charge pump circuit depends on the areas of capacitors C10, C20, C30, and C40. The areas of capacitors C10, C20, C30, and C40 are all equal, and the sum of their areas equals... Figure 1 In the prior art, the area of ​​capacitor C1, i.e. the capacitance values ​​of capacitors C10, C20, C30 and C40 are all 1 / 4*C1, so the only increase in area is due to the additional switching transistors.

[0079] Meanwhile, the power consumption of the charge pump circuit depends on the instantaneous current during charging and discharging. The current changes from charging one capacitor C1 to charging four capacitors C10, C20, C30 and C40. Accordingly, the size of the MOSFET is reduced, so the instantaneous current increase is only in the current of some small-sized devices.

[0080] like Figure 3 , Figure 4 and Figure 2As shown, the control signal generation circuit 60 includes a signal generator CLK, a signal processing and distribution unit 61, and a signal shaping and driving unit. The signal processing and distribution unit 61 is connected to the signal generator CLK and is used to output multiple drive signals. Multiple signal shaping and driving units are connected to the signal processing and distribution unit 61 and correspond to the charging and discharging circuits. Each signal shaping and driving unit generates a control signal based on the drive signal to control the first switching unit, the charging and discharging unit, and the second switching unit of the charging and discharging circuit, respectively.

[0081] In this embodiment, four signal shaping and driving units are provided: a first signal shaping and driving unit 621, a second signal shaping and driving unit 622, a third signal shaping and driving unit 623, and a fourth signal shaping and driving unit 624, which correspond to the first charging and discharging circuit 10, the second charging and discharging circuit 20, the third charging and discharging circuit 30, and the fourth charging and discharging circuit 40, respectively. In other embodiments, the number of signal shaping and driving units 62 can be adjusted accordingly depending on the number of charging and discharging circuits, and the structure of the signal processing and distribution unit 61 can also be adjusted accordingly.

[0082] Specifically, such as Figure 3 As shown, the signal processing and distribution unit 61 includes a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, a first inverter U1, a second inverter U2, a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a seventh inverter U7, an eighth inverter U8, a ninth inverter U9, a tenth inverter U10, an eleventh inverter U11, a twelfth inverter U12, and a thirteenth inverter U13.

[0083] The CK terminal of the first D flip-flop D1 is connected to the signal generator CLK. The D input terminal of the first D flip-flop D1 is connected to the QN output terminal and the input terminal of the second inverter U2. The Q output terminal of the first D flip-flop D1 is connected to the input terminal of the third inverter U3.

[0084] The input of the first inverter U1 is connected to the signal generator CLK. The CK input of the second D flip-flop D2 is connected to the output of the first inverter U1. The D input of the second D flip-flop D2 is connected to the output of the second inverter U2. The QN output of the second D flip-flop D2 is connected to the input of the fourth inverter U4. The Q output of the second D flip-flop D2 is connected to the input of the fifth inverter U5.

[0085] The CK input of the third D flip-flop D3 is connected to the output of the second inverter U2. The D input of the first D flip-flop is connected to the QN terminal and the input of the sixth inverter U6. The output of the sixth inverter U6 is used to output the first drive signal PH1. The Q output of the third D flip-flop D3 is connected to the input of the seventh inverter U7. The output of the seventh inverter U7 is used to output the second drive signal PH2.

[0086] The CK input of the fourth D flip-flop D4 is connected to the output of the fourth inverter U4. The D input of the fourth D flip-flop D4 is connected to the output of the sixth inverter U6. The QN output of the fourth flip-flop is connected to the input of the eighth inverter U8. The output of the eighth inverter U8 is used to output the third drive signal PH3. The Q output of the fourth flip-flop is connected to the input of the ninth inverter U9. The output of the ninth inverter U9 is used to output the fourth drive signal PH4.

[0087] The CK input of the fifth D flip-flop D5 is connected to the output of the third inverter U3. The D input of the fifth D flip-flop D5 is connected to the output of the eighth inverter U8. The QN output of the fifth D flip-flop D5 is connected to the input of the tenth inverter U10. The output of the tenth inverter U10 is used to output the fifth drive signal PH5. The Q output of the fifth D flip-flop D5 is connected to the input of the eleventh inverter U11. The output of the eleventh inverter U11 is used to output the sixth drive signal PH6.

[0088] The CK input of the sixth D flip-flop D6 is connected to the output of the fifth inverter U5. The D input of the sixth D flip-flop D6 is connected to the output of the tenth inverter U10. The QN output of the sixth D flip-flop D6 is connected to the input of the twelfth inverter U12. The output of the twelfth inverter U12 is used to output the seventh drive signal PH7. The Q output of the sixth D flip-flop D6 is connected to the input of the thirteenth inverter U13. The output of the thirteenth inverter U13 is used to output the eighth drive signal PH8.

[0089] like Figure 4 As shown, the first signal shaping and driving unit 621 includes a NOR gate, a fourteenth inverter U14, a fifteenth inverter U15, a sixteenth inverter U16, a seventeenth inverter U17, an eighteenth inverter U18, a nineteenth inverter U19, a NAND gate, a twentieth inverter U20, and a twenty-first inverter U21.

[0090] The first and second inputs of the NOR gate are used to receive the first driving signal PH1 and the second driving signal PH3, respectively. The output of the NOR gate is connected to the input of the fourteenth inverter U14, the output of the fourteenth inverter U14 is connected to the input of the fifteenth inverter U15, and the output of the fifteenth inverter U15 is connected to the second terminal of the first capacitor C11. The output of the fifteenth inverter U15 outputs a first control signal A1 to the second terminal of the first capacitor C11 to control the opening and closing of the first MOSFET NM11.

[0091] The sixteenth inverter U16, the seventeenth inverter U17, and the eighteenth inverter U18 are connected in series. The input terminal of the sixteenth inverter U16 is used to receive the second drive signal PH2. The output terminal of the eighteenth inverter U18 is connected to the second terminal of the capacitor C10. The output terminal of the eighteenth inverter U18 outputs the second control signal B1 to the second terminal of the control capacitor C10 to control the charging and discharging of the capacitor C10.

[0092] The first and second input terminals of the NAND gate are used to receive the first driving signal PH1 and the third driving signal PH3, respectively. The output terminal of the NAND gate is connected to the input terminal of the twentieth inverter U20. The output terminal of the twentieth inverter U20 is connected to the input terminal of the twentieth inverter U21. The output terminal of the twentieth inverter U21 is connected to the second terminal of the second capacitor C12. The output terminal of the twentieth inverter U21 outputs the third control signal C1 to the second terminal of the second capacitor C12 to control the opening and closing of the second MOS transistor PM11.

[0093] like Figure 4 As shown, the circuit structures of the second signal shaping and driving unit 622, the third signal shaping and driving unit 623, and the fourth signal shaping and driving unit 624 are the same as those of the first signal shaping and driving unit 621, and will not be described again here.

[0094] The second signal shaping and driving unit 622 receives the third driving signal PH3 and the fifth driving signal PH5 to output a first control signal A2 to control the opening and closing of the first MOSFET NM21. The second signal shaping and driving unit 622 receives the fourth driving signal PH4 to output a second control signal B2 to control the charging and discharging of capacitor C20. The second signal shaping and driving unit 622 receives the third driving signal PH3 and the fifth driving signal PH5 to output a third control signal C2 to control the opening and closing of the second MOSFET PM21.

[0095] The third signal shaping and driving unit 623 receives the fifth driving signal PH5 and the seventh driving signal PH7 to output a first control signal A3 to control the opening and closing of the first MOSFET NM31. The third signal shaping and driving unit 623 receives the sixth driving signal PH6 to output a second control signal B3 to control the charging and discharging of capacitor C30. The third signal shaping and driving unit 623 receives the fifth driving signal PH5 and the seventh driving signal PH7 to output a third control signal C3 to control the opening and closing of the second MOSFET PM31.

[0096] The fourth signal shaping and driving unit 624 receives the seventh driving signal PH7 and the first driving signal PH1 to output a first control signal A4 to control the opening and closing of the first MOSFET NM41. The fourth signal shaping and driving unit 624 receives the eighth driving signal PH8 to output a second control signal B4 to control the charging and discharging of capacitor C40. The fourth signal shaping and driving unit 624 receives the seventh driving signal PH7 and the first driving signal PH1 to output a fourth control signal C4 to control the opening and closing of the second MOSFET PM41.

[0097] In one embodiment, control signals A1, B1, and C1 are a set of non-overlapping control signals, control signals A2, B2, and C2 are a set of non-overlapping control signals, control signals A3, B3, and C3 are a set of non-overlapping control signals, and control signals A4, B4, and C4 are a set of non-overlapping control signals.

[0098] In another embodiment, the switching transistors controlled by control signals C1, C2, C3, and C4 are not turned on simultaneously.

[0099] In this embodiment, the first MOSFETs NM11, NM21, NM31, and NM41 are N-channel MOSFETs, and the second MOSFETs PM11, PM21, PM31, and PM41 are P-channel MOSFETs. When the first control signals A1, A2, A3, and A4 are high, the first MOSFETs NM11, NM21, NM31, and NM41 are closed. Simultaneously, if the second control signals B1, B2, B3, and B4 are low, capacitors C10, C20, C30, and C40 are charged. When the third control signals C1, C2, C3, and C4 are low, the second MOSFETs PM11, PM21, PM31, and PM41 are closed. If the second control signals B1, B2, B3, and B4 are high, capacitors C10, C20, C30, and C40 are discharged. The charging and discharging of capacitors C10, C20, C30 and C40 do not occur simultaneously.

[0100] In other embodiments, by changing the high and low levels of the control signal and the circuit connection method, the first MOSFETs NM11, NM21, NM31 and NM41 can be P-channel MOSFETs, and the second MOSFETs PM11, PM21, PM31 and PM41 can be N-channel MOSFETs; or the first MOSFETs NM11, NM21, NM31 and NM41 and the second MOSFETs PM11, PM21, PM31 and PM41 are all N-channel MOSFETs or all P-channel MOSFETs.

[0101] like Figure 6 Combination Figure 2 As shown, based on the above-described charge pump circuit, the present invention also discloses a charge pump circuit control method, comprising:

[0102] S1. During a certain time period of a control cycle, the first switching unit of a certain charging and discharging circuit is closed and the corresponding second switching unit is opened, thereby controlling the corresponding charging and discharging unit to charge.

[0103] S2. During a certain period of the control cycle, close the second switch unit of one of the charging and discharging circuits and open the corresponding first switch unit to control the corresponding charging and discharging unit to discharge.

[0104] S3. During the control cycle, the output signals generated by the discharge of each charging and discharging unit of the charging and discharging circuit are superimposed to reduce the amplitude of the ripple on the total output signal and increase the frequency of the ripple on the total output signal.

[0105] S4. Filter the total output signal to remove ripples from the total output signal.

[0106] like Figure 5 Combination Figure 2 As shown, taking four charging and discharging circuits as an example, the charge pump circuit control method specifically includes:

[0107] The control period is divided into the time periods T0 to T1, T1 to T2, T2 to T3, and T3 to T4.

[0108] During the control cycle from T0 to T1, the first switch unit 11 and the second switch unit 12 of the first charging and discharging circuit 10 are disconnected; the first switch unit 21 of the second charging and discharging circuit 20 is disconnected and the second switch unit 22 is closed, controlling the charging and discharging unit to discharge; the first switch unit 31 and the second switch unit 32 of the third charging and discharging circuit 30 are disconnected; the second switch unit 42 of the fourth charging and discharging circuit 40 is disconnected and the first switch unit 41 is controlled to go from closed to open, controlling the charging and discharging unit to charge.

[0109] During the control period T1 to T2, the second switch unit 12 of the first charging and discharging circuit 10 is disconnected and the first switch unit 11 is controlled to close, thereby controlling the charging and discharging unit to charge; the first switch unit 21 and the second switch unit 22 of the second charging and discharging circuit 20 are disconnected; the first switch unit 31 of the third charging and discharging circuit 30 is disconnected and the second switch unit 32 is closed, thereby controlling the charging and discharging unit to discharge; the first switch unit 41 and the second switch unit 42 of the fourth charging and discharging circuit 40 are disconnected.

[0110] During the control cycle from T2 to T3, the second switch unit 12 of the first charging / discharging circuit 10 is disconnected and the first switch unit 11 is closed, controlling the charging / discharging unit to charge; the second switch unit 22 of the second charging / discharging circuit 20 is disconnected and the first switch unit 21 is controlled to go from open to closed, controlling the charging / discharging unit to charge; the first switch unit 31 and the second switch unit 32 of the third charging / discharging circuit 30 are disconnected; the first switch unit 41 of the fourth charging / discharging circuit 40 is disconnected and the second switch unit 42 is closed, controlling the charging / discharging unit to discharge.

[0111] During the control cycle from T3 to T4, the first switch unit 11 of the first charging / discharging circuit 10 is disconnected and the second switch unit 12 is closed, controlling the charging / discharging unit to discharge; the first switch unit 21 of the second charging / discharging circuit 20 is closed and the second switch unit 22 is disconnected, controlling the charging / discharging unit to charge; the second switch unit 32 of the third charging / discharging circuit 30 is disconnected and the first switch unit 31 is controlled to go from open to closed, controlling the charging / discharging unit to charge; the first switch unit 41 and the second switch unit 42 of the fourth charging / discharging circuit 40 are disconnected.

[0112] In summary, during a certain period of the control cycle, one or more of the first MOSFETs NM11, NM21, NM31, and NM41 can be closed, and one or more of the corresponding capacitors C10, C20, C30, and C40 can be charged. However, during a certain period of the control cycle, only one of the second MOSFETs PM11, PM21, PM31, and PM41 can be closed, and only one of the corresponding capacitors C10, C20, C30, and C40 can be discharged, thereby preventing the circuit from generating series current.

[0113] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A charge pump circuit, characterized in that, include: At least four parallel charging and discharging circuits are provided. Each charging and discharging circuit includes a first switching unit, a charging and discharging unit, and a second switching unit connected to each other. The first switching unit, the charging and discharging unit, and the second switching unit are all controlled by a control signal. Closing the first switching unit of the charging and discharging circuit and opening the corresponding second switching unit controls the corresponding charging and discharging unit to charge. Closing the second switching unit of the charging and discharging circuit and opening the corresponding first switching unit controls the corresponding charging and discharging unit to discharge. Specifically, the second switching unit controlling each charging and discharging circuit closes at different time periods within a control cycle, so that each charging and discharging circuit outputs an output signal based on the discharge generated by the charging and discharging unit at different time periods. By superimposing the output signals of multiple parallel charging and discharging circuits, the amplitude of the ripple on the total output signal is reduced, and the frequency of the ripple on the total output signal is increased. A filter circuit, connected to the second switching unit of all the charging and discharging circuits, is used to filter out the ripple on the total output signal. The amplitude of the ripple on the total output signal is 1 / n times the amplitude of the ripple on the output signal, and the frequency of the ripple on the total output signal is n times the frequency of the output signal, where n is the number of charging and discharging circuits, and n≥4. The charge pump circuit further includes a control signal generation circuit connected to the charging and discharging circuit. The control signal generation circuit includes a signal generator, a signal processing and distribution unit, and a signal shaping and driving unit. The signal processing and distribution unit is connected to the signal generator and is used to output multiple driving signals. The signal shaping and driving unit is connected to the signal processing and distribution unit. Multiple signal shaping and driving units are provided and correspond to the charging and discharging circuit. Each signal shaping and driving unit generates a control signal according to the driving signal to control the first switching unit, the charging and discharging unit, and the second switching unit of the charging and discharging circuit respectively. The signal processing and distribution unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, and a thirteenth inverter; The CK terminal of the first D flip-flop is connected to the signal generator, the D input terminal of the first D flip-flop is connected to the QN output terminal and the input terminal of the second inverter, and the Q output terminal of the first D flip-flop is connected to the input terminal of the third inverter. The input terminal of the first inverter is connected to the signal generator, the CK input terminal of the second D flip-flop is connected to the output terminal of the first inverter, the D input terminal of the second D flip-flop is connected to the output terminal of the second inverter, the QN output terminal of the second D flip-flop is connected to the input terminal of the fourth inverter, and the Q output terminal of the second D flip-flop is connected to the input terminal of the fifth inverter. The CK input of the third D flip-flop is connected to the output of the second inverter. The D input of the third D flip-flop is connected to the QN input and the input of the sixth inverter. The output of the sixth inverter is used to output the first drive signal. The Q output of the third D flip-flop is connected to the input of the seventh inverter. The output of the seventh inverter is used to output the second drive signal. The CK input of the fourth D flip-flop is connected to the output of the fourth inverter, the D input of the fourth D flip-flop is connected to the output of the sixth inverter, the QN output of the fourth D flip-flop is connected to the input of the eighth inverter, the output of the eighth inverter is used to output the third drive signal, and the Q output of the fourth D flip-flop is connected to the input of the ninth inverter, the output of the ninth inverter is used to output the fourth drive signal. The CK input of the fifth D flip-flop is connected to the output of the third inverter, the D input of the fifth D flip-flop is connected to the output of the eighth inverter, the QN output of the fifth D flip-flop is connected to the input of the tenth inverter, the output of the tenth inverter is used to output the fifth drive signal, and the Q output of the fifth D flip-flop is connected to the input of the eleventh inverter, the output of the eleventh inverter is used to output the sixth drive signal. The CK input of the sixth D flip-flop is connected to the output of the fifth inverter, the D input of the sixth D flip-flop is connected to the output of the tenth inverter, the QN output of the sixth D flip-flop is connected to the input of the twelfth inverter, the output of the twelfth inverter is used to output the seventh drive signal, and the Q output of the sixth D flip-flop is connected to the input of the thirteenth inverter, the output of the thirteenth inverter is used to output the eighth drive signal. During the control cycle from T0 to T1, the first and second switching units of the first charging and discharging circuit are disconnected; the first switching unit of the second charging and discharging circuit is disconnected and the second switching unit is closed, controlling the charging and discharging unit to discharge; the first and second switching units of the third charging and discharging circuit are disconnected; the second switching unit of the fourth charging and discharging circuit is disconnected and the first switching unit is controlled to go from closed to open, controlling the charging and discharging unit to charge. During the control period T1~T2, the second switch unit of the first charging and discharging circuit is disconnected and the first switch unit is controlled to close, and the charging and discharging unit is controlled to charge; the first switch unit and the second switch unit of the second charging and discharging circuit are disconnected; the first switch unit of the third charging and discharging circuit is disconnected and the second switch unit is closed, and the charging and discharging unit is controlled to discharge; the first switch unit and the second switch unit of the fourth charging and discharging circuit are disconnected. During the control cycle from T2 to T3, the second switch unit of the first charging and discharging circuit is disconnected and the first switch unit is closed, controlling the charging and discharging unit to charge; the second switch unit of the second charging and discharging circuit is disconnected and the first switch unit is controlled to go from open to closed, controlling the charging and discharging unit to charge; the first switch unit and the second switch unit of the third charging and discharging circuit are disconnected; the first switch unit of the fourth charging and discharging circuit is disconnected and the second switch unit is closed, controlling the charging and discharging unit to discharge. During the control cycle from T3 to T4, the first switch unit of the first charging and discharging circuit is disconnected and the second switch unit is closed, controlling the charging and discharging unit to discharge; the first switch unit of the second charging and discharging circuit is closed and the second switch unit is disconnected, controlling the charging and discharging unit to charge; the second switch unit of the third charging and discharging circuit is disconnected and the first switch unit is controlled to go from open to closed, controlling the charging and discharging unit to charge; the first switch unit and the second switch unit of the fourth charging and discharging circuit are disconnected.

2. The charge pump circuit as described in claim 1, characterized in that, The first switching unit includes a first MOSFET, a first diode, and a first capacitor. The source of the first MOSFET is connected to the power supply voltage. The gate of the first MOSFET is connected to the cathode of the first diode and the first terminal of the first capacitor. The anode of the first diode is connected to the power supply voltage. The drain of the first MOSFET is connected to the first terminal of the charging / discharging unit and the second switching unit. The second terminal of the first capacitor is used to receive the corresponding control signal.

3. The charge pump circuit as described in claim 1, characterized in that, The second switching unit includes a second MOSFET, a second diode, and a second capacitor. The drain of the second MOSFET is connected to the first terminal of the charging / discharging unit. The gate of the second MOSFET is connected to the cathode of the second diode and the first terminal of the second capacitor. The anode of the second diode is connected to the power supply voltage. The second terminal of the second capacitor is used to receive the corresponding control signal. The source of the second MOSFET is used to output the output signal.

4. The charge pump circuit as described in claim 1, characterized in that, The filter circuit includes a resistor and a third capacitor. The first end of the resistor is connected to the charging and discharging circuit, the second end of the resistor is connected to the first end of the third capacitor and is used to output the total output signal, and the second end of the third capacitor is grounded.

5. The charge pump circuit as described in claim 1, characterized in that, The signal shaping and driving unit includes a NOR gate, a fourteenth inverter, a fifteenth inverter, a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a NAND gate, a twentieth inverter, and a twenty-first inverter; The first and second input terminals of the NOR gate are respectively used to receive corresponding drive signals. The output terminal of the NOR gate is connected to the input terminal of the fourteenth inverter. The output terminal of the fourteenth inverter is connected to the input terminal of the fifteenth inverter. The output terminal of the fifteenth inverter is used to output a first control signal to control the first switching unit. The sixteenth, seventeenth, and eighteenth inverters are connected in series. The input terminal of the sixteenth inverter is used to receive the corresponding drive signal, and the output terminal of the eighteenth inverter is used to output the second control signal for controlling the charging and discharging unit. The first and second input terminals of the NAND gate are respectively used to receive corresponding drive signals. The output terminal of the NAND gate is connected to the input terminal of the twentieth inverter. The output terminal of the twentieth inverter is connected to the input terminal of the twentieth inverter. The output terminal of the twentieth inverter is used to output a third control signal to control the second switching unit.

6. A charge pump circuit control method, characterized in that, The charge pump circuit according to any one of claims 1 to 5 includes: Multiple drive signals are output through a signal processing and distribution unit connected to a signal generator; Multiple signal shaping and driving units corresponding to the charging and discharging circuit generate control signals according to the driving signals to control the first switching unit, the charging and discharging unit and the second switching unit of the charging and discharging circuit respectively. Within a certain time period of a control cycle, the first switching unit of several charging and discharging circuits is closed and the corresponding second switching unit is opened by the corresponding control signal, thereby controlling the corresponding charging and discharging unit to charge. During a certain period of the control cycle, the second switching unit of one of the charging and discharging circuits is closed and the corresponding first switching unit is opened by a corresponding control signal, thereby controlling the corresponding charging and discharging unit to discharge. During the control cycle, the output signals generated by the discharge of each charging and discharging unit of the charging and discharging circuit are superimposed to reduce the amplitude of the ripple on the total output signal and increase the frequency of the ripple on the total output signal. The total output signal is filtered by a filtering circuit to remove ripples from the total output signal. The control method shown includes: during the T0~T1 time period of the control cycle, disconnecting the first and second switching units of the first charging and discharging circuit; disconnecting the first switching unit of the second charging and discharging circuit and closing the second switching unit to control the charging and discharging unit to discharge; disconnecting the first and second switching units of the third charging and discharging circuit; disconnecting the second switching unit of the fourth charging and discharging circuit and controlling the first switching unit to go from closed to open to control the charging and discharging unit to charge. During the control period T1~T2, the second switch unit of the first charging and discharging circuit is disconnected and the first switch unit is controlled to close, and the charging and discharging unit is controlled to charge; the first switch unit and the second switch unit of the second charging and discharging circuit are disconnected; the first switch unit of the third charging and discharging circuit is disconnected and the second switch unit is closed, and the charging and discharging unit is controlled to discharge; the first switch unit and the second switch unit of the fourth charging and discharging circuit are disconnected. During the control cycle from T2 to T3, the second switch unit of the first charging and discharging circuit is disconnected and the first switch unit is closed, controlling the charging and discharging unit to charge; the second switch unit of the second charging and discharging circuit is disconnected and the first switch unit is controlled to go from open to closed, controlling the charging and discharging unit to charge; the first switch unit and the second switch unit of the third charging and discharging circuit are disconnected; the first switch unit of the fourth charging and discharging circuit is disconnected and the second switch unit is closed, controlling the charging and discharging unit to discharge. During the control cycle from T3 to T4, the first switch unit of the first charging and discharging circuit is disconnected and the second switch unit is closed, controlling the charging and discharging unit to discharge; the first switch unit of the second charging and discharging circuit is closed and the second switch unit is disconnected, controlling the charging and discharging unit to charge; the second switch unit of the third charging and discharging circuit is disconnected and the first switch unit is controlled to go from open to closed, controlling the charging and discharging unit to charge; the first switch unit and the second switch unit of the fourth charging and discharging circuit are disconnected.

Images