Readout circuit, processor, error processing method and device

Abstract

The present application relates to a readout circuit, processor, error processing method, and device. The readout circuit includes: a randomization circuit, a signal processing circuit, and an analog-to-digital converter, wherein the signal processing circuit includes multiple sampling capacitors and a signal processor, at least one of the multiple sampling capacitors corresponding to sampling a target charge signal of at least one channel; the randomization circuit randomizes the order in which each sampling capacitor is flipped to the signal processing circuit; the signal processor sequentially holds the target charge signals sampled by each sampling capacitor according to the randomized order, and transmits the held target charge signals to the analog-to-digital converter to obtain a quantized result of the target charge signal. The readout circuit can effectively reduce the errors between channels in the readout circuit, thereby improving image quality.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a readout circuit, a processor, an error processing method and a device. Background Art

[0002] The readout circuit can perform pre-processing and signal conversion on the analog signal collected by the signal collector to generate a current signal. It is the signal transmission channel from the analog signal collected by the signal collector to the subsequent system application. Its performance directly affects the performance indicators of the signal collector.

[0003] Typically, the signal collector is multi-channel, and the analog signals collected by it also correspond to multi-channel analog signals. Therefore, when the readout circuit processes the analog signals of these channels, it processes the signals of each channel separately.

[0004] However, in some cases, when a readout circuit processes a multi-channel analog signal, a fixed-trend error may exist between the multiple channels. This error may result in poor quality of an image generated based on the readout analog signal. Summary of the Invention

[0005] The embodiments of the present application provide a readout circuit, a processor, an error processing method and an apparatus, which can effectively reduce the errors between channels in the readout circuit, thereby improving image quality.

[0006] In a first aspect, an embodiment of the present application provides a readout circuit, the readout circuit comprising: a randomization circuit, a signal processing circuit, and an analog-to-digital converter; the signal processing circuit comprising a plurality of sampling capacitors and a signal processor;

[0007] At least one of the plurality of sampling capacitors corresponds to sampling a target charge signal of at least one channel;

[0008] A randomization circuit, used for randomizing the order in which the sampling capacitors are flipped to the signal processing circuit;

[0009] The signal processor is used to hold the target charge signal sampled by each sampling capacitor in sequence according to the order after randomization, and transmit the held target charge signal to the analog-to-digital converter to obtain a quantized result of the target charge signal.

[0010] In one embodiment, each sampling capacitor samples a target charge signal of one channel.

[0011] In one embodiment, the target charge signal is obtained based on an analog signal.

[0012] In one embodiment, the readout circuit further includes an analog front-end circuit;

[0013] The analog front-end circuit is used to collect the analog signal of the target device and convert the analog signal into a target charge signal.

[0014] In one embodiment, the analog front-end circuit includes a signal collector and an integrator; the signal collector includes at least one channel, and each channel of the signal collector is connected to at least one integrator;

[0015] The signal collector is used to collect the analog signal of the target device, transmit the analog signal to the integrator corresponding to each channel, and obtain the target charge signal output by each integrator.

[0016] In one embodiment, the signal processing circuit further includes a sampling switch;

[0017] A sampling switch is connected to each end of at least one sampling capacitor; the sampling switch is closed when the corresponding sampling capacitor is charged or discharged.

[0018] In one embodiment, a sampling switch is connected across each sampling capacitor.

[0019] In one embodiment, each sampling capacitor is bottom plate sampling.

[0020] In one embodiment, the signal processing circuit further includes a reset capacitor;

[0021] A first end of the reset capacitor is connected to a sampling input end of the signal processor, and a second end of the reset capacitor is connected to an output end of the signal processor;

[0022] The reset capacitor is used to reset the voltage of the sampling input terminal of the signal processor to the input initial voltage and reset the voltage of the output terminal of the signal processor to the output initial voltage after each processing of the target charge signal.

[0023] In one embodiment, the signal processing circuit further includes a reset switch;

[0024] A reset switch is connected to each end of the reset capacitor; the reset switch is closed when the reset capacitor is reset.

[0025] In one embodiment, the signal processing circuit further includes a hold switch;

[0026] A holding switch is connected between the first end of the reset capacitor and the common mode voltage input end, and between the second end of the reset capacitor and the common mode voltage output end; the holding switch is closed during the period when the second signal processor performs holding processing.

[0027] In one embodiment, the signal processor is a capacitive flip-type signal processor.

[0028] In one embodiment, the signal processor adopts a gain-enhanced folded cascode structure.

[0029] In a second aspect, an embodiment of the present application provides a processor, which includes the readout circuit provided by any embodiment of the first aspect above.

[0030] In a third aspect, an embodiment of the present application provides an error processing method applied to a readout circuit, the method comprising:

[0031] Sampling target charge signals of multiple channels;

[0032] randomizing the order in which the target charge signals are held;

[0033] The target charge signals are sequentially held according to the order after randomization.

[0034] In a fourth aspect, an embodiment of the present application provides an error processing device, comprising:

[0035] A sampling module, used for sampling target charge signals of multiple channels;

[0036] A sequence processing module, configured to randomize the order in which target charge signals are maintained;

[0037] The holding processing module is used to sequentially perform holding processing on each target charge signal according to the order after randomization processing.

[0038] In a fifth aspect, an embodiment of the present application provides a computer device, comprising a memory and a processor, wherein a computer program is stored in the memory. When the computer program is executed by the processor, the processor executes the method steps provided in the third aspect above.

[0039] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the method steps provided in the third aspect when the computer program is executed by a processor.

[0040] The present application provides a readout circuit, processor, error processing method, and apparatus, the readout circuit comprising: a randomization circuit, a signal processing circuit, and an analog-to-digital converter, wherein the signal processing circuit comprises a plurality of sampling capacitors and a signal processor, at least one of the plurality of sampling capacitors corresponding to a target charge signal of at least one channel; the randomization circuit randomizes the order in which each sampling capacitor is flipped to the signal processing circuit; the signal processor sequentially holds the target charge signals sampled by each sampling capacitor according to the randomized order, and transmits the held target charge signals to the analog-to-digital converter to obtain a quantization result of the target charge signal. Since the randomization circuit randomizes the order in which each sampling capacitor is flipped to the signal processor when determining the quantization result of the target charge signal, the sampling capacitors are no longer flipped to the signal processor for sampling and holding in a fixed order. In this way, the waiting time of the sampling capacitors corresponding to all channels is random, which is equivalent to converting the fixed pattern noise in the image generated according to the readout analog signal into white noise. In this way, the noise in the image cannot be recognized by the human eye, thereby improving the quality of the final generated image. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of the readout circuit structure in one embodiment of the present application;

[0042] Figure 2 Schematic diagram of the readout circuit structure in another embodiment of the present application;

[0043] Figure 3 Schematic diagram of the readout circuit structure in another embodiment of the present application;

[0044] Figure 4 Schematic diagram of the readout circuit structure in another embodiment of the present application;

[0045] Figure 5 Schematic diagram of the readout circuit structure in another embodiment of the present application;

[0046] Figure 6 Schematic diagram of the readout circuit structure in another embodiment of the present application;

[0047] Figure 7 Schematic diagram of the readout circuit structure in another embodiment of the present application;

[0048] Figure 8 Schematic diagram of the readout circuit structure in another embodiment of the present application;

[0049] Figure 9 FIG. 1 is a flow chart of a noise suppression method in an embodiment of the present application.

[0050] Description of reference numerals:

[0051] 10: readout circuit; 101: randomization circuit;

[0052] 102: signal processing circuit; 1021: sampling capacitor;

[0053] 1022: signal processor; 1023: reset capacitor;

[0054] 103: Analog-to-digital converter; 104: Analog front-end circuit;

[0055] 1041: signal collector; 1042: integrator;

[0056] 10411-1041n: Channel 1-Channel n; 10421-1042n; Integrator 1-Integrator n. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0058] It should be understood that the terms "first," "second," and the like in the claims, specification, and drawings of this application are used to distinguish between different objects, rather than to describe a specific order. The term "comprising" as used in the specification and claims of this application indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0059] It should also be understood that the terms used in this specification are merely for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this specification and claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms. It should also be further understood that the terms "and / or" used in this specification and claims refer to any combination and all possible combinations of one or more of the associated listed items, and include these combinations. As used in this specification and claims, the term "if" can be interpreted as "when..." or "once" or "in response to determining" or "in response to detecting" based on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "once it is determined" or "in response to determining" or "once [described condition or event] is detected" or "in response to detecting [described condition or event]" based on the context.

[0060] Typically, analog signals collected by a signal acquisition device are read out using a readout circuit. Signal acquisition devices are typically multi-channel, for example, each channel is a pixel channel. Analysis has shown that if each pixel (pixel channel) is quantized using a dedicated analog-to-digital converter (ADC), all pixels can be sampled, processed, and read out simultaneously, improving the efficiency of analog signal sampling, processing, and quantization. However, this design approach requires dedicated ADCs for each channel. During product implementation, each pixel requires analog power ground, a precise reference voltage source, and digital signals within the top-level bus. This makes it difficult to separate sensitive analog and digital signals, which can lead to interference from digital signals. Furthermore, due to deep nanometer processing, the power consumption of digital signals decreases with increasing frequency, resulting in a high-speed ADC's power consumption not increasing proportionally with the sampling frequency compared to a low-speed ADC. Therefore, using a dedicated ADC for each pixel increases chip area, costs, and power consumption when implementing the readout circuit.

[0061] Based on this, analysis suggests that the analog-to-digital converters and sample-and-hold amplifiers can be reused to maximize power efficiency and reduce costs. However, when using this approach in the readout circuit, it was discovered that while the charge signals of each channel are sampled at the same time in the readout circuit, the time they are quantized in the back-end analog-to-digital converter after sampling is different. As a result, the time the charge sampled by each capacitor waits for quantization varies. This difference in waiting time causes charge leakage on the sampling capacitors when the signal is large, resulting in a fixed error across multiple channels. This error can affect the quality of the image generated by the analog signal ultimately read out.

[0062] Therefore, to address the technical drawback that errors between multiple channels in a readout circuit lead to poor quality in the final image generation, the present application provides a readout circuit, processor, error processing method, and device that can effectively reduce errors between channels in the readout circuit, improve analog signal readout accuracy, and thus enhance image quality. Furthermore, it should be noted that the applicant has expended considerable creative effort in determining the implementation structure of the readout circuit, analyzing the aforementioned drawbacks, and developing the technical solutions described in the following embodiments.

[0063] Next, the readout circuit provided in the present application and the implementation process of reducing the error between channels of the readout circuit will be described in detail with reference to the accompanying drawings.

[0064] In one embodiment, Figure 1 As shown, an embodiment of the present application provides a readout circuit 10, which includes: a randomization circuit 101, a signal processing circuit 102 and an analog-to-digital converter 103; the signal processing circuit 102 includes multiple sampling capacitors 1021 and a signal processor 1022; at least one of the multiple sampling capacitors 1021 corresponds to sampling a target charge signal of at least one channel; the randomization circuit 101 is used to randomize the order in which each sampling capacitor 1021 is flipped to the signal processor 1022; the signal processor 1022 is used to hold the target charge signal sampled by each sampling capacitor 1021 in sequence according to the randomized order, and transmit the held target charge signal to the analog-to-digital converter 103 to obtain a quantization result of the target charge signal.

[0065] See Figure 1As shown, the signal processing circuit 102 includes multiple sampling capacitors 1021 and a signal processor 1022, wherein n in the multiple sampling capacitors (10211-1021n) can be 10, that is, the readout circuit has 10 channels, then there are 10 corresponding sampling capacitors. The multiple sampling capacitors are all connected to the input end of a signal processor 1022, and the output end of the signal processor 1022 is connected to the input end of the analog-to-digital converter 103. Such a connection method realizes multi-channel multiplexing of the signal processor and the analog-to-digital converter in the readout circuit, thereby reducing the power consumption and cost of the readout circuit. Among them, the signal processors in the embodiments of the present application are all sample-and-hold amplifiers. Naturally, the signal processing circuits are all sample-and-hold amplifier circuits, which will not be described in detail later.

[0066] Generally, the function of a sample-and-hold circuit is to accurately sample an analog signal during the sampling phase and to hold the sampled result for a certain period of time during the holding phase for quantization processing by the analog-to-digital converter 103, thereby improving the analog-to-digital converter's ability to process higher-frequency input signals. Specifically, the sample-and-hold circuit is the front-end circuit in the analog-to-digital converter, primarily responsible for sampling the input analog quantity and isolating the circuit, providing relatively lossless noise protection for the analog-to-digital converter. In conjunction with the embodiments of the present application, the target charge signal is held by a sample-and-hold amplifier to ensure that the correct quantization result of the analog signal is obtained after passing through the back-end analog-to-digital converter.

[0067] At least one of the plurality of sampling capacitors 1021 corresponds to sampling a target charge signal of at least one channel, where the target charge signal is obtained based on an analog signal.

[0068] Specifically, in practical applications, the readout circuit 10 may be configured such that at least one of the plurality of sampling capacitors 1021 samples a target charge signal of at least one channel, or each sampling capacitor 1021 samples a target charge signal of one channel. The target charge signal is a signal obtained after conversion and processing based on an analog signal. For example, an analog signal from a medical device may be collected by a signal collector, and the charge signal obtained after the analog signal is converted through integration or other conversion is the target charge signal.

[0069] In one embodiment, the circuit for converting the analog signal into the target charge signal is called an analog front-end circuit. Figure 2 As shown, in this embodiment, the readout circuit 10 further includes an analog front-end circuit 104 , which is used to collect analog signals from a target device and convert the analog signals into target charge signals.

[0070] The target device generally refers to any device in any field. For example, in the medical industry, the target device refers to various medical devices, including but not limited to magnetic resonance imaging (MRI) equipment, computed tomography (CT) equipment, X-ray machines, and ultrasound imaging equipment. The present embodiment does not limit the type and specific function of the target device. The analog signal collected from the target device can be an optical signal, a photoelectric signal, a voice signal, a temperature signal, and the like.

[0071] The analog front-end circuit converts the analog signal to obtain the target charge signal. The specific implementation structure of the analog front-end circuit is not limited in the present embodiment, and can be implemented using a chip with a pre-stored control program or a combination of an integrator and a signal collector.

[0072] After obtaining the target charge signal for each channel, the target charge signal needs to be sampled and held in the signal processing circuit. The signal processor 1022 in the signal processing circuit 102 is connected to the sampling capacitor 1021 to jointly implement the sample-and-hold function. The signal processing circuit 102 operates in two modes: "sample" or "hold" under the control of the input logic level. In the "sample" state, the circuit's output tracks the input analog signal. In the "hold" state, the circuit's output maintains the instantaneous input analog signal at the end of the previous sampling cycle until the next sampling cycle begins.

[0073] See Figure 3 As shown, Figure 3 The connection between the capacitor element and the signal processor element is shown in detail, and for the sake of clarity, Figure 3 Only one sampling capacitor is shown as an example. It should be understood that the connection method of other sampling capacitors is the same as that in this schematic diagram.

[0074] That is Figure 3 In the example, the first terminal of the sampling capacitor 1021 is connected to the sampling input terminal V of the signal processor 1022. IN The second end of the sampling capacitor 1021 is connected to the output end V of the signal processor 1022 OUT .

[0075] Based on this connection mode, the sampling capacitor 1021 can be charged according to the target charge signal, and the output terminal V OUT The sampled target charge signal is transmitted to the analog-to-digital converter 103 .

[0076] Specifically, during operation, the signal processor 1022 and the sampling capacitor 1021 cooperate to be in the "sampling" or "holding" working state. In the "sampling" state, the target charge signal passes through the sampling input terminal V IN In the sampling capacitor 1021 connected to the input signal processor 1022, it should be understood that the target charge signal of each channel charges the corresponding sampling capacitor. This charging process can be understood as the process of the sampling capacitor sampling the target charge signal of the corresponding channel. At this time, the output terminal V OUT The output voltage Vo can vary with the input V IN The input signal Vi changes, the voltage on the sampling capacitor 1021 is proportional to the input terminal V IN The input voltage is the same.

[0077] In the "hold" state, the sampling capacitor 1021 is no longer charged or discharged, and the moment it switches from the "sampling" state to the "hold" state indicates that the analog-to-digital converter 103 is currently performing signal conversion. During this conversion period, the sampling capacitor 1021 is no longer charged or discharged, and the target charge signal is held in the sampling capacitor 1021. At this time, the sampling input terminal V IN The value of the input signal Vi remains unchanged, and the output terminal V OUT The output voltage Vo can therefore maintain a constant output value for a considerable period of time until the signal processor 1022 switches from the "hold" state to the "sampling" state.

[0078] In this way, when switching from the "sampling" state to the "holding" state, that is, during the period when the analog-to-digital converter 103 converts the signal, the input signal is kept unchanged by the sampling capacitor 1021, so that the analog-to-digital converter 103 can correctly perform signal conversion, thereby greatly improving the signal processing accuracy.

[0079] In addition, from Figure 3 As can be seen, the signal processor 1022 also has a common mode voltage input terminal V CM，IN The common-mode voltage of its input can be regarded as a reference voltage, and its specific value can be customized according to actual conditions. Figure 3 Then Vo=V IN -V CM，IN .

[0080] Optionally, the signal processor 1022 in the embodiment of the present application is a capacitor flip signal processor. The capacitor flip type is a fully differential structure, which can well eliminate DC bias and even harmonic distortion, and suppress common mode noise from the substrate. And the feedback coefficient of the capacitor flip type structure is 1, so that at the same closed-loop bandwidth, the operational amplifier unit gain bandwidth (GBW) required by the capacitor flip type structure is small, so the embodiment of the present application adopts a capacitor flip type structure to further reduce the power consumption of the final readout circuit.

[0081] Based on this, when the signal processing circuit implements "sampling" and "holding", the sampling capacitors 1021 corresponding to each channel will be flipped to the signal processor 1022. However, if the order in which the sampling capacitors 1021 corresponding to each channel are flipped to the signal processor 1022 is designed to be fixed, it will cause the target charge signals sampled by each sampling capacitor to have different waiting times for quantization by the back-end analog-to-digital converter, which will cause a fixed error between the quantization values ​​of the analog signals read out from each channel, that is, there will be a fixed pattern of errors in the image finally generated based on the read analog signals, resulting in poor final image quality.

[0082] In the embodiment of the present application, a randomization circuit 101 is used to randomize the order in which the sampling capacitors 1021 corresponding to each channel are flipped to the capacitor flipping signal processor, so that the sampling capacitors are not sampled and held in the same fixed order. In this way, the waiting time of the sampling capacitors on all channels is random, which is equivalent to converting the fixed pattern noise in the final generated image into white noise, making it difficult for the human eye to recognize, thereby improving image quality.

[0083] For details, please see Figure 1 The randomization circuit 101 is a circuit for generating a random signal, which is connected between the sampling capacitor 1021 and the signal processor 1022 to realize randomization of the order in which the sampling capacitors 1021 corresponding to each channel are flipped to the capacitor flipping signal processor 1022 .

[0084] In one embodiment, the randomization circuit can be implemented as a chip with a pre-written control program, that is, a preset randomization algorithm is written into the chip as a randomization circuit, and the randomization circuit acts on each sampling capacitor to randomize the order in which each sampling capacitor is flipped to the signal processor.

[0085] In another embodiment, the randomization circuit may be implemented as a sampling bufferfly circuit, so that the randomization circuit acts on each sampling capacitor to randomize the order in which each sampling capacitor is flipped to the signal processor.

[0086] After randomizing the order in which the sampling capacitors are flipped to the signal processor based on the randomization circuit, the signal processor sequentially performs a hold process on the target charge signals sampled by the sampling capacitors according to the randomized order.

[0087] The signal output from the output terminal of the signal processor is the signal after the signal processor holds the target charge signal sampled on the sampling capacitor, and enters the analog-to-digital converter 103. The analog-to-digital converter 103 is an electronic component that converts analog signals into digital signals. That is, after the charge signal enters the analog-to-digital converter 103, the analog-to-digital converter 103 converts the charge signal into an output digital signal. This output digital signal is the quantization result of the analog signal of the target device collected by the signal collector. This quantization value is the value of the analog signal read out by the readout circuit.

[0088] The readout circuit provided in an embodiment of the present application includes: a randomization circuit, a signal processing circuit, and an analog-to-digital converter, wherein the signal processing circuit includes multiple sampling capacitors and a signal processor, at least one of the multiple sampling capacitors corresponding to sampling a target charge signal of at least one channel; the randomization circuit randomizes the order in which each sampling capacitor is flipped to the signal processing circuit; the signal processor holds the target charge signals sampled by each sampling capacitor in sequence according to the randomized order, and transmits the held target charge signals to the analog-to-digital converter to obtain a quantization result of the target charge signal. Since the randomization circuit randomizes the order in which each sampling capacitor is flipped to the signal processor when determining the quantization result of the target charge signal, the sampling capacitors are no longer flipped to the signal processor for sampling and holding in a fixed order. In this way, the waiting time of the sampling capacitors corresponding to all channels is random, which is equivalent to converting the fixed pattern noise in the image generated according to the readout analog signal into white noise. In this way, the noise in the image cannot be recognized by the human eye, thereby improving the quality of the final generated image.

[0089] Based on the above embodiment, an internal implementation structure of the analog front-end circuit 104 is provided, such as Figure 4 As shown, the analog front-end circuit 104 includes a signal collector 1041 and an integrator 1042; the signal collector 1041 includes at least one channel, and each channel of the signal collector 1041 is connected to at least one integrator 1042; the signal collector 1041 is used to collect the analog signal of the target device, transmit the analog signal to the integrator 1042 corresponding to each channel, and obtain the target charge signal output by each integrator 1042.

[0090] The signal collector 1041 is used to collect analog signals. For example, if the analog signal is an optical signal, a photoelectric signal, a voice signal, a temperature signal, etc., the signal collector 1041 is correspondingly various types of sensors, such as a photoelectric sensor, a voice sensor, a temperature sensor, etc.

[0091] Taking a photoelectric sensor as an example, the signal collector 1041 includes multiple channels (10411-1041n), which means that the photoelectric sensor includes multiple channels. Generally, for sensors, multi-channel is relative to single-channel. For example, the difference between multi-channel and single-channel lies in the number of measurement data. A single channel can generally only measure one data point, while a multi-channel can measure multiple data points. The specific number of channels in the multi-channel embodiment is not limited in this application embodiment. For example, 128 channels, that is, n = 128; or 10 channels, that is, n = 10.

[0092] The signal collector 1041 collects analog signals from the target device and transmits the analog signals to the integrators 1042 corresponding to each channel to obtain target charge signals output by each integrator 1042 .

[0093] Integrator 1042 is a component whose output signal is the integral of the input signal over time. An integrator can be considered a continuous version of a counter, accumulating inputs before outputting them. In this embodiment of the present application, each channel (10411-1041n) of each signal collector 1041 is connected to an integrator 1042 (including 10421-1042n). Thus, the signal collected by signal collector 1041 is converted into a target charge signal by integrator 1042. For example, the photoelectric signal collected by a photoelectric sensor is converted into a charge signal after passing through the integrator.

[0094] Please continue to see Figure 4 Assuming n = 10, there will be 10 target charge signals, all of which will enter the main signal path 101. Simultaneously, the interference noise generated in these 10 channels will also enter the main signal path 101 and the dummy signal path 102. This means that even though there are n signal collectors 1041 and corresponding n integrators 1042, the main signal path 101, the dummy signal path 102, and the back-end analog-to-digital converter 103 are all shared, with only one.

[0095] In this embodiment, the analog front-end circuit is composed of a signal collector and an integrator, and the signal collector and the integrator are a multi-channel one-to-one corresponding structure. In this way, for the analog signal of the target device collected by any signal collector, its corresponding integrator can convert it into a corresponding charge signal, so that the target charge signal obtained based on the analog signal is more accurate.

[0096] Next, some embodiments are used to illustrate one implementation structure of the signal processing circuit 102. It should be understood that the implementation structure shown in these embodiments is only an example and is not intended to be limiting.

[0097] like Figure 5 As shown, in one embodiment, for clarity of illustration, the signal processing circuit 102 is separated and illustrated separately, that is, Figure 5 Based on the above embodiment, the signal processing circuit 102 further includes a sampling switch Ss. A sampling switch Ss is connected to each end of at least one sampling capacitor 1021. The sampling switch Ss is closed when the corresponding sampling capacitor 1021 is charged or discharged.

[0098] When switching from the "sampling" state to the "holding" state, a sampling switch can be set to ensure that the sampling capacitor no longer charges or discharges. In this example, a sampling switch Ss can be connected to both ends of at least one sampling capacitor 1021, or a sampling switch can be connected to both ends of each sampling capacitor.

[0099] During operation, in the "sampling" state, when the logic control signal closes the sampling switch Ss, the sampling capacitor 1021 is charged and discharged, that is, the input signal passes through the sampling input terminal V IN The sampling capacitor 1021 connected to the input signal processor 1022 is inputted. At this time, the output terminal V OUT The output voltage Vo can vary with the input V IN The input signal changes, the voltage on the sampling capacitor 1021 and the input terminal V IN The input voltage is the same.

[0100] In the "hold" state, when the logic control signal disconnects the sampling capacitor 1021, the sampling capacitor 1021 is equivalent to being connected only to the high-impedance input terminal of the signal processor 1022. The sampling capacitor 1021 no longer charges or discharges, and the charged charge is retained in the sampling capacitor 1021. At this time, the sampling input terminal V IN The value of the input signal remains unchanged, and the output terminal V of the signal processor 1022 OUT The output voltage Vo can therefore maintain a constant output value for a considerable period of time until the control signal closes the sampling switch Ss and switches from the "hold" state to the "sampling" state.

[0101] In this embodiment, when switching from the "sampling" state to the "holding" state, the sampling switch is used to switch between charging and discharging of the sampling capacitor and no longer charging and discharging. This allows the sampling capacitor to keep the input signal unchanged during the analog-to-digital converter converting the signal, ensuring that the analog-to-digital converter correctly performs signal conversion, thereby greatly improving signal processing accuracy.

[0102] In addition, in one embodiment of the present application, the sampling capacitor 1021 samples the target charge signal of the corresponding channel using a bottom plate sampling method.

[0103] By sampling the bottom plate, the respective signals can be processed in the charge domain. Combined with the fact that the signal processor 1022 adopts a capacitor flipping signal processor, under such a structure, the feedback coefficient of the signal processor 1022 can be reduced. In this way, when the actual product is realized, the total parasitic capacitance (Cpar) caused by the layout routing of the multi-channel multiplexed signal processor 1022 will not cause the signal-to-noise ratio of the signal path to be attenuated due to the principle of charge conservation. As long as the signal of the signal processor 1022 is fully established, the point potential of their respective sampling input terminals will be equal to their respective common-mode voltage terminals, and the charge signal will be completely stored on their respective sampling capacitors, thereby ensuring the signal integrity and sampling accuracy to the greatest extent.

[0104] When the readout circuit of the above structure is implemented in a product, the parasitic capacitance caused by the reuse of the layout wiring can be minimized by properly distributing the layout wiring. The specific proper distribution of the layout wiring is not limited in the present embodiment and can be arranged according to the needs of the actual product implementation.

[0105] Multi-channel multiplexing is a process in which a common signal processor continuously processes the signal charges of multiple channels. In this way, the memory effect of the signal processor may cause crosstalk between the multiple channels, affecting the accuracy of signal processing.

[0106] Based on this, in order to reduce the crosstalk between multiple channels caused by the memory effect of the signal processor, the embodiment of the present application also provides a readout circuit, such as Figure 6 As shown, the signal processing circuit 102 also includes a reset capacitor 1023; the first end of the reset capacitor 1023 is connected to the sampling input end of the signal processor 1022, and the second end of the reset capacitor 1023 is connected to the output end of the signal processor 1022; the reset capacitor 1023 is used to reset the voltage of the sampling input end of the signal processor 1022 to the input initial voltage and reset the voltage of the output end of the signal processor 1022 to the output initial voltage after each processing of the target charge signal.

[0107] This embodiment eliminates the memory effect of the signal processor by connecting a reset capacitor.

[0108] For example, please see Figure 6 The first end of the reset capacitor 1023 is connected to the sampling input terminal V of the signal processor 1022. IN The second end of the reset capacitor 1023 is connected to the output terminal V of the signal processor 1022. OUTBased on this connection mode, the reset capacitor 1023 resets the sampling input terminal V of the signal processor 1022 after each target charge signal is processed by the signal processing circuit 102. IN The voltage of the signal processor 1022 is reset to the input initial voltage, and the output terminal V OUT The voltage is reset to the output initial voltage.

[0109] Thus, after each target charge signal is processed in sample-hold circuit 102, reset capacitor 1023 resets the input and output of signal processor 1022 to their initial values, thereby preventing crosstalk between multiple channels caused by the memory effect of the signal processor. It will be appreciated that the initial value here refers to the voltage value of the signal processor in its initial state, which can be known in advance.

[0110] Alternatively, as Figure 7 As shown, the signal processing circuit 102 further includes a reset switch Sr, and a reset switch Sr is connected to each end of the reset capacitor 1023; the reset switch Sr is closed when the reset capacitor 1023 is reset, wherein, Figure 7 The figure shows the reset switch is on.

[0111] As mentioned above, reset capacitor 1023 performs a reset function after signal processing circuit 102 completes each target charge signal processing. This reset function eliminates any remaining memory of the previous charge signal processing by signal processor 1022 within signal processing circuit 102, which could affect signal processing accuracy. It should be understood that reset capacitor 1023 does not need to perform a reset function while the same charge signal is being processed.

[0112] In this embodiment, the reset capacitor 1023 can be reset by providing a reset switch. Specifically, the reset switch Sr controls the reset capacitor 1023 to reset. The reset switch Sr can be controlled to close and open by a logic control signal. Specifically, the reset switch Sr is closed when the reset capacitor 1023 is reset and is opened when the reset capacitor 1023 does not need to reset.

[0113] It is understood that, taking the sampling capacitor 1021 as an example, after processing a charge signal in a "sampling" state, the reset capacitor 1023 performs its reset function when the sampling capacitor 1021 switches from the "sampling" state to the "holding" state. In other words, the reset switch Sr of the reset capacitor 1023 and the sampling switch Ss of the sampling capacitor 1021 cannot be closed or opened at the same time. Specifically, when the reset switch Sr is open, the sampling switch Ss is closed, and when the reset switch Sr is closed, the sampling switch Ss is open.

[0114] like Figure 8As shown, in another embodiment, the signal processing circuit 102 further includes a holding switch Sk, and a holding switch Sk is connected between the first end of the reset capacitor 1023 and the common-mode voltage input end, and between the second end of the reset capacitor 1023 and the common-mode voltage output end; the holding switch Sk is closed during the period when the signal processor 1022 performs holding processing.

[0115] When the sampling capacitor 1021 is sampling, the switch Sk is controlled to be closed by the logic control signal, so that the voltage across the reset capacitor Cr (such as Figure 8 Points A and B in the circuit are reset to the input and output common mode voltages of the signal processor 1022, that is, point A is reset to the common mode voltage input terminal V CM,IN The same input common mode voltage resets point B to the common mode voltage output terminal V CM,OUT Same output common-mode voltage.

[0116] In this way, it can be ensured that the DC operating point of the signal processor 1022 (capacitor flip type) is the same before and after the capacitor flip, thereby preventing the signal processor 1022 from deviating from the normal working state and affecting the establishment of the output signal.

[0117] Additionally, in one embodiment, the signal processor 1022 may be implemented using a gain-enhanced folded cascode structure.

[0118] The most important module in a signal processor is the operational amplifier, whose gain and bandwidth directly determine the accuracy and speed of the signal processor. High gain requires the use of multi-stage amplifiers, small bias currents, and long-channel devices; while large bandwidth requires the use of single-stage amplifiers, large bias currents, and short-channel devices. Based on this requirement, the operational amplifier of the signal processor in the embodiment of the present application adopts a gain-enhanced folded cascode structure, which can improve the gain of the amplifier and meet the requirements of high gain and large bandwidth. Therefore, because the signal processor in the embodiment of the present application adopts a gain-enhanced folded cascode structure, it can achieve the low-frequency gain and bandwidth of the signal processor to be large enough, thereby meeting the establishment accuracy and speed requirements of the load analog-to-digital converter.

[0119] It should be noted that in the circuit architecture shown in the above example, the number of channels of the readout circuit, the readout accuracy and speed, the structure, gain and bandwidth of the amplifier, etc. can all be adjusted according to actual applications, and the embodiments of the present application do not limit this.

[0120] In addition, an embodiment of the present application further provides a processor, which includes any of the readout circuits provided in the previous embodiments. In one embodiment, a computer device is further provided, which includes a processor implemented by any of the readout circuits.

[0121] A processor can be considered as a very large-scale integrated circuit, which includes an arithmetic unit, a controller, registers, a memory, and a readout circuit, etc. Processors include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), digital signal processing (DSPs), and application-specific integrated circuits (ASICs), etc., and are not limited to these in the embodiments of the present application.

[0122] The computer device refers to any terminal or electronic device that requires an external power supply or a built-in power supply, such as various personal computers, laptops, mobile phones (smart mobile terminals), tablet computers, and portable wearable devices, etc., which are not limited in this embodiment. If it is an external power supply, the power supply can be a power adapter, a mobile power supply (power bank, travel charger), etc., which is not limited in this embodiment. The computer device can include a processor implemented by any readout circuit.

[0123] In addition, the present invention also provides an error processing method. Figure 9 As shown, the error processing method can be applied to the readout circuit provided by any of the above embodiments, and the embodiment includes:

[0124] S101, sampling target charge signals of multiple channels.

[0125] S102 , randomizing the order of holding the target charge signals.

[0126] S103 , performing a holding process on each of the target charge signals in sequence according to the order after the randomization process.

[0127] A program instruction for instructing error processing can be pre-set. After the computer device receives a trigger from the program instruction, it executes a corresponding operation, namely, starting to sample target charge signals from multiple channels according to a preset configuration, and randomizing the order in which the target charge signals are retained. The computer device can then continue to execute the preset program instruction, sequentially retaining each target charge signal according to the randomized order. Afterwards, the computer device can continue to convert the retained target charge signal according to the preset program instruction, thereby obtaining a quantization result corresponding to the target charge signal, that is, a quantization result corresponding to the analog signal. For example, the conversion process can be to convert the analog signal into a digital signal.

[0128] It is understood that the above process is implemented by computer program instructions, which are provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device, so that the instructions executed by the processor of the computer or other programmable data processing device can realize the noise suppression of this embodiment. Of course, these computer program instructions can also be stored in a computer-readable memory that can guide the computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device. Alternatively, these computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are performed on the computer or other programmable device to produce a computer-implemented process, so that the computer program instructions are executed on the computer or other programmable device to realize the above-mentioned functions.

[0129] The principles and logic for implementing each step according to program instructions in this embodiment can be the same as those in the above-mentioned embodiments of the readout circuit, and will not be further described in detail in this embodiment. Of course, when implementing noise suppression in conjunction with program instructions, the implementation method can be adapted to the process, and this embodiment is not limited to this.

[0130] Based on the above noise suppression method, an embodiment of the present application further provides an error processing device, which includes: a sampling module, a sequence processing module and a holding processing module, wherein:

[0131] A sampling module, used for sampling target charge signals of multiple channels;

[0132] A sequence processing module, configured to randomize the order in which target charge signals are maintained;

[0133] The holding processing module is used to sequentially perform holding processing on each target charge signal according to the order after randomization processing.

[0134] The implementation principles of each step in the above-mentioned error processing device are the same as the principles and logic of each embodiment of the error processing method and the readout circuit. Please refer to the above description and will not be repeated here.

[0135] In addition, an embodiment of the present application further provides a computer device, including a memory and a processor, wherein a computer program is stored in the memory. When the computer program is executed by the processor, the processor executes any one of the error handling method steps provided in the above embodiments.

[0136] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, any one of the error handling method steps provided in the above embodiments is implemented.

[0137] In some embodiments, the present application further provides a chip, which includes the readout circuit provided in any of the above embodiments. In one implementation, the chip is a system-on-chip (SoC) and integrates multiple functional devices. The chip can be connected to other related components through an external interface device. The related components may be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as video codecs) and / or interface modules (such as DRAM interfaces) may be integrated on the chip. In some embodiments, the present application further provides a chip packaging structure, which includes the above chip. In some embodiments, the present application further provides a board card, which includes the above chip packaging structure.

[0138] Based on the above description, those skilled in the art can understand that the present application also provides an electronic device or apparatus, which may include one or more of the above-mentioned boards.

[0139] According to different application scenarios, the electronic equipment or device of the present application may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, Internet of Things terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, vehicles, household appliances, and / or medical equipment. The vehicles include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, range hoods; the medical equipment includes magnetic resonance imaging (MRI), ultrasound machines and / or electrocardiographs. The electronic equipment or device of the present application may also be applied to the Internet, Internet of Things, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, medical care and other fields. Furthermore, the electronic equipment or device of the present application may also be used in cloud, edge, terminal and other application scenarios related to artificial intelligence, big data and / or cloud computing. In one or more embodiments, electronic devices or apparatuses with high computing power according to the solution of the present application can be applied to cloud devices (such as cloud servers), while electronic devices or apparatuses with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0140] In this application, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solution described in the embodiments of this application. In addition, in some scenarios, multiple units in the embodiments of this application may be integrated into one unit or each unit may exist physically separately.

[0141] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the solution of the present application is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present application. The aforementioned memory may include, but is not limited to, various media that can store program code, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0142] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0143] Although multiple embodiments of the present application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art can conceive of many changes, modifications, and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The accompanying claims are intended to define the scope of protection of the present application and therefore cover equivalents or alternatives within the scope of these claims.

[0144] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. At the same time, changes or modifications made by those skilled in the art based on the ideas of the present application, the specific implementation methods, and the scope of application of the present application, all fall within the scope of protection of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

Claims

1. A readout circuit, characterized in that: The readout circuit includes: a randomization circuit, a signal processing circuit, an analog-to-digital converter, and a reset capacitor; the signal processing circuit includes multiple sampling capacitors and a signal processor; the signal processor is a capacitor flipping structure; the first end of the reset capacitor is connected to the sampling input end of the signal processor, and the second end of the reset capacitor is connected to the output end of the signal processor; At least one of the plurality of sampling capacitors adopts a bottom plate sampling method to correspondingly sample a target charge signal of at least one channel; The randomization circuit is used to randomize the order in which the sampling capacitors are flipped to the signal processing circuit; The signal processor is configured to sequentially hold the target charge signals sampled by the sampling capacitors according to the order after randomization, and transmit the held target charge signals to the analog-to-digital converter to obtain quantization results of the target charge signals; The reset capacitor is used to reset the voltage of the sampling input terminal of the signal processor to the input initial voltage and reset the voltage of the output terminal of the signal processor to the output initial voltage after each processing of the target charge signal.

2. The readout circuit according to claim 1, wherein: The readout circuit also includes an analog front-end circuit; The analog front-end circuit is used to collect analog signals from a target device and convert the analog signals into the target charge signals.

3. The readout circuit according to claim 2, wherein: The analog front-end circuit includes a signal collector and an integrator; the signal collector includes at least one channel, and each channel of the signal collector is connected to at least one integrator; The signal collector is used to collect the analog signal of the target device, transmit the analog signal to the integrator corresponding to each channel, and obtain the target charge signal output by each integrator.

4. The readout circuit according to any one of claims 1 to 3, wherein: The signal processing circuit further includes a sampling switch; Two ends of at least one of the sampling capacitors are each connected to a sampling switch; the sampling switch is closed when the corresponding sampling capacitor is charged or discharged.

5. The readout circuit according to any one of claims 1 to 3, characterized in that: The signal processing circuit further includes a reset switch; Two ends of the reset capacitor are each connected to a reset switch; the reset switch is closed when the reset capacitor is reset.

6. The readout circuit according to claim 5, wherein: The signal processing circuit further includes a holding switch; A holding switch is connected between the first end of the reset capacitor and the common mode voltage input end, and between the second end of the reset capacitor and the common mode voltage output end; the holding switch is closed during the holding process of the signal processor.

7. The readout circuit according to any one of claims 1 to 3, characterized in that: The signal processor is a sample-and-hold amplifier, and the signal processing circuit is a sample-and-hold amplifier circuit.

8. A processor, characterized in that: The processor comprises the readout circuit according to any one of claims 1 to 7.

9. An error processing method, characterized in that: Applied to the readout circuit according to any one of claims 1 to 7, the method comprising: Sampling target charge signals of multiple channels; randomizing the order in which the target charge signals are held; The target charge signals are sequentially maintained according to the order after randomization.

10. An error processing device, characterized in that: The readout circuit according to any one of claims 1 to 7, wherein the device comprises: A sampling module, used for sampling target charge signals of multiple channels; A sequence processing module, configured to randomize the order in which target charge signals are maintained; The holding processing module is used to sequentially perform holding processing on each of the target charge signals according to the order after randomization processing.

Images