A control method of a UWB baseband chip, a UWB master control chip and a storage medium

Abstract

The embodiment of the application discloses a control method of a UWB baseband chip, a UWB master control chip and a storage medium, and is used in the field of wireless communication technology. The method of the embodiment of the application comprises the following steps: establishing a data communication channel with the UWB baseband chip based on an SPI interface; acquiring a first command frame used for transmitting a command to the UWB baseband chip, wherein the first command frame comprises configurable identification bits and data bytes; configuring the identification bits of the first command frame to obtain a second command frame; and sending the second command frame to the UWB baseband chip through the data communication channel, so as to control the UWB baseband chip to perform data interaction based on the identification bits and the data bytes in the second command frame. In the embodiment of the application, the identification bits of the first command frame are configured to obtain the second command frame, and the second command frame is sent to the UWB baseband chip, so that the control of the UWB baseband chip can be efficiently and flexibly realized.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of wireless communication, and in particular to a control method of a UWB baseband chip, a UWB master control chip and a storage medium. BACKGROUND

[0002] In modern communication, Ultra Wideband (UWB) technology is a new communication technology, which is based on low-energy radio signals and can realize short-distance high-speed data transmission. UWB technology has the characteristics of high transmission rate, anti-multipath interference and simple structure, and is widely used in precise positioning, radar and wireless communication, etc. and is a hot technology in the current short-distance communication field.

[0003] The existing control process of the UWB baseband chip is generally that the UWB master control chip sends a control command to the UWB baseband chip, and the UWB baseband chip responds to the control command and performs corresponding data interaction with the UWB master control chip. However, considering the cost and power consumption, the interface connection between the UWB baseband chip and the UWB master control chip needs to be reduced as much as possible.

[0004] The existing UWB baseband chip generally uses a SPI (Serial Peripheral Interface) interface, and defines a specific SPI data frame to receive the control command from the UWB master control chip. However, the frame structure of the specific SPI data frame is generally fixed, which is difficult to provide an extensible address space and requires a large number of clock numbers to access any address space, resulting in that the control of the UWB master control chip to the UWB baseband chip becomes complex, and the transmission efficiency between the UWB master control chip and the UWB baseband chip is reduced. SUMMARY

[0005] Embodiments of the present application provide a control method of a UWB baseband chip, a UWB master control chip and a storage medium, which can efficiently and flexibly realize the control of the UWB baseband chip.

[0006] Embodiments of the present application provide a control method of a UWB baseband chip, comprising:

[0007] establishing a data communication channel with the UWB baseband chip based on a SPI interface;

[0008] obtaining a first command frame used for transmitting a command to the UWB baseband chip, the first command frame comprising a configurable identification bit and a data byte;

[0009] configuring the identification bit of the first command frame to obtain a second command frame;

[0010] sending the second command frame to the UWB baseband chip through the data communication channel to control the UWB baseband chip to interact with data based on the identification bit and the data byte in the second command frame.

[0011] Further, the identification bit of the first command frame includes a byte flag bit, a read-write flag bit, and a write mode bit.

[0012] The configuration of the identification bit of the first command frame obtains a second command frame, including:

[0013] The byte flag bit, the read-write flag bit, and the write mode bit in the first command frame are configured respectively to obtain the second command frame.

[0014] Further, the configuration of the byte flag bit, the read-write flag bit, and the write mode bit in the first command frame respectively includes:

[0015] The byte flag bit in the first command frame is configured as a double-byte;

[0016] A double-byte register read-write command is formed based on the double-byte flag bit and the register address of the identification bit;

[0017] The read-write flag bit in the first command frame is configured as a read operation; or, the read-write flag bit in the first command frame is configured as a write operation, and the write mode bit is configured as one of normal write, AND operation, OR operation, and XOR operation.

[0018] Further, the configuration of the byte flag bit, the read-write flag bit, and the write mode bit in the first command frame respectively to obtain the second command frame includes:

[0019] The byte flag bit in the first command frame is configured as a single byte to form a single-byte command;

[0020] When the single-byte command forms a single-byte register read-write command based on the register address offset of the identification bit, the read-write flag bit and the write mode bit are configured as a read operation; or, when the single-byte command is a single-byte register read-write command, the read-write flag bit is configured as a write operation, and the write mode bit is configured as one of normal write, AND operation, OR operation, and XOR operation;

[0021] When the single-byte command forms a single-byte system command based on the pre-configured system control command in the identification bit, the read-write flag bit and the write mode bit are configured as a control operation.

[0022] Further, the method further includes:

[0023] when the single-byte command is a single-byte system command and the single-byte command is greater than a preset number, expanding a data byte in the first command frame into a corresponding system command bit.

[0024] Further, the data communication channel is established between the SPI interface and the UWB baseband chip.

[0025] The SPI interface establishes data input channel, data output channel, clock signal channel and chip selection signal channel with the UWB baseband chip respectively.

[0026] Further, the second command frame is sent to the UWB baseband chip through the data communication channel.

[0027] The chip selection signal in the chip selection signal channel is used to determine a target UWB baseband chip from a plurality of UWB baseband chips.

[0028] The second command frame is sent to the target UWB baseband chip through the data input channel.

[0029] The embodiment of the application further provides a UWB master chip, which comprises:

[0030] The establishment unit is configured to establish a data communication channel between the SPI interface and the UWB baseband chip.

[0031] The acquisition unit is configured to acquire a first command frame used for transmitting a command to the UWB baseband chip, wherein the first command frame comprises a configurable identification bit and a data byte.

[0032] The configuration unit is configured to configure the identification bit of the first command frame to obtain a second command frame.

[0033] The control unit is configured to send the second command frame to the UWB baseband chip through the data communication channel, so that the UWB baseband chip performs data interaction based on the identification bit and the data byte in the second command frame.

[0034] The embodiment of the application further provides a UWB master chip, which comprises:

[0035] The central processor, the memory, the input and output interface, the wired or wireless network interface and the power supply.

[0036] The memory is a transient storage memory or a persistent storage memory.

[0037] The central processor is configured to communicate with the memory, execute the instruction operation in the memory on the control plane function entity to perform the above-mentioned control method.

[0038] The embodiment of the present application further provides a computer readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the control method.

[0039] From the above technical solutions, the embodiment of the present application has the following advantages:

[0040] In the embodiment of the present application, the first command frame for transmitting a command to the UWB baseband chip is acquired, the identification bit of the first command frame is configured to obtain the second command frame, and the second command frame is sent to the UWB baseband chip to control the UWB baseband chip to perform data interaction based on the identification bit and the data byte in the second command frame, so that the control of the UWB baseband chip can be efficiently and flexibly realized. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0042] Figure 1 A communication architecture diagram disclosed by the embodiment of the present application is shown in the following figure:

[0043] Figure 2 A control flow diagram of a UWB baseband chip disclosed by the embodiment of the present application is shown in the following figure:

[0044] Figure 3 A signal diagram of an SPI interface disclosed by the embodiment of the present application is shown in the following figure:

[0045] Figure 4 A structure diagram of a command frame disclosed by the embodiment of the present application is shown in the following figure:

[0046] Figure 5 A double-byte command frame diagram disclosed by the embodiment of the present application is shown in the following figure:

[0047] Figure 6 A single-byte register read-write command diagram disclosed by the embodiment of the present application is shown in the following figure:

[0048] Figure 7 A single-byte system command diagram disclosed by the embodiment of the present application is shown in the following figure:

[0049] Figure 8 A UWB master chip diagram disclosed by the embodiment of the present application is shown in the following figure:

[0050] Figure 9 Another UWB master chip diagram disclosed by the embodiment of the present application is shown in the following figure: DETAILED DESCRIPTION

[0051] In order to make the personnel in the art better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0052] In the description of the embodiments of the present application, it should be noted that the orientations or positional relationships indicated by the terms “center”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “inner”, “outer” and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0053] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms “mounting”, “connecting”, “connection” should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0054] As Figure 1As shown, the control process of the existing UWB baseband chip 102 is generally that the UWB master chip 101 sends a control command to the UWB baseband chip 102, and the UWB baseband chip 102 responds to the control command and performs corresponding data interaction with the UWB master chip 101. The existing UWB baseband chip 102 generally uses an SPI interface, and a specific SPI data frame is defined to receive the control command from the UWB master chip 101. It can be understood that one UWB master chip 101 can be connected with multiple UWB baseband chips 102, and the multiple UWB baseband chips 102 serve as slave devices of the UWB master chip 101 and receive the control command from the UWB master chip 101. However, the frame structure of the specific SPI data frame is generally fixed, it is difficult to provide an extensible address space and a large number of clock numbers are required to access any address space, which leads to the complexity of the control of the UWB baseband chip by the UWB master chip and reduces the transmission efficiency between the UWB master chip and the UWB baseband chip. Therefore, the embodiment of the present application provides a control method of a UWB baseband chip, which can efficiently and flexibly control the UWB baseband chip, such as Figure 2 As shown, the specific steps are as follows:

[0055] 201. Establish a data communication channel with the UWB baseband chip based on the SPI interface.

[0056] In the embodiment of the present application, the host control interface used by the UWB master chip is mainly a 4-wire SPI interface, which is generally used for communication between master and slave devices, wherein the UWB master chip is the master device and the UWB baseband chip is the slave device. The UWB master chip establishes a data communication channel with the UWB baseband chip based on the SPI interface. It can be understood that the SPI interface is used to send a command frame from the UWB master chip to the UWB baseband chip, and the UWB baseband chip has the function of executing the related command frame, thereby realizing the function of controlling the UWB baseband chip or reading and writing the internal register of the UWB baseband chip.

[0057] The SPI interface generally occupies four pins of the UWB baseband chip, which are data input (SDI), data output (SDO), clock signal (SCLK), and chip select signal (CS); therefore, the UWB master chip establishes a data input channel, a data output channel, a clock signal channel, and a chip select signal channel with the UWB baseband chip based on the SPI interface. As shown in Figure 3As shown, the SPI signals based on the SPI interface generally follow a corresponding communication protocol: the spi cs signal is set to 0, indicating the start of a command frame; the spi cs signal is set to 1, indicating the end of a command frame. A command frame always starts with one or more bytes of commands, followed by one or more bytes of data. The slave device (UWB baseband chip) always receives commands and then returns corresponding data according to the commands. All byte transmissions start with the highest bit and end with the lowest bit. In multi-byte transmission, the low byte is transmitted first and the high byte is transmitted last. The host (UWB master chip) can terminate the transmission at any time by setting spi cs to 1. The transmitted bytes are valid bytes, and the incomplete bytes are invalid data. When reading and writing registers, the command (command frame) contains the register address. Each time a byte is read or written, the address is automatically incremented by 1 to obtain the address of the next byte. The host can continuously read and write multiple registers of the slave device by keeping spi cs as 0. The host can define a command frame to directly set 1, set 0, or flip a bit of a register of the slave device, without the need to read the register first and then write back, effectively saving the access time of the host to the slave device.

[0058] 202. Obtain a first command frame for transmitting a command to the UWB baseband chip.

[0059] In the embodiments of the present application, before the UWB master chip sends a command to the UWB baseband chip, a first command frame for transmitting a command to the UWB baseband chip needs to be obtained, and the first command frame includes configurable identification bits and data bytes. Specifically, the UWB master chip can pre-store the first command frame or can obtain the first command frame through network communication according to actual conditions, and the specific implementation is not limited here. The identification bits in the first command frame are configurable, and the control functions implemented by the first command frame are different for different identification bits; and the data bytes generally carry data to be transmitted.

[0060] It should be noted that the sequence of steps 201 and 202 is not limited.

[0061] 203. Configure the identification bits of the first command frame to obtain a second command frame.

[0062] The UWB master chip can configure the identification bits of the first command frame to obtain a second command frame; specifically, the UWB master chip can configure the identification bits of the first command frame to obtain a second command frame according to the actual need to control the UWB baseband chip or read and write the registers of the UWB baseband chip. It can be understood that the first command frame is an initial baseband control command and data, and the second command frame is a command frame to be transmitted based on the initial control command.

[0063] It can be understood that the identification bits of the first command frame generally include byte flag bits, read-write flag bits and write mode bits; and the configuration of the identification bits of the first command frame to obtain the second command frame includes: respectively configuring the byte flag bits, the read-write flag bits and the write mode bits in the first command frame to obtain the second command frame. The byte flag bits generally implement single-byte or double-byte of the command frame, the read-write flag bits generally implement read register or write register of the command frame, and the write mode bits generally implement different write functions when the command frame is a write register. It can be understood that the identification bits not only include the byte flag bits, the read-write flag bits and the write mode bits, but also include register addresses and register address offsets, etc. In the specific configuration process of the first command frame, a plurality of second command frames can be obtained according to the configuration of the byte flag bits, the read-write flag bits and the write mode bits, and the register addresses and the register address offsets, etc.

[0064] Further, the UWB master chip can configure the byte flag bits in the first command frame as double bytes, form a double-byte register read-write command based on the double-byte flag bits and the register addresses in the identification bits; configure the read-write flag bits in the first command frame as a read operation; or configure the read-write flag bits in the first command frame as a write operation, and configure the write mode bits as one of normal write, AND operation, OR operation and XOR operation. In an implementable scheme, for example, Figure 4 and Figure 5As shown, the byte flag bit is AD bit, and AD bit being 0 indicates that the frame is single-byte command, and AD bit being 1 indicates that the frame is double-byte command. It can be understood that the AD bit being 1 can also indicate that the frame is single-byte command, and the AD bit being 0 can also indicate that the frame is double-byte command, which is not limited here. The double-byte command frame is register address read-write command, and RW is read-write flag bit. RW=0 indicates that the command is read operation, and RW=1 indicates that the command is write operation. M1 and M0 are write mode bits, 00 is normal write, and the write byte is directly written into the register at the corresponding address; 01 is AND operation, and the AND byte directly ANDs with the register value at the corresponding address, and the bits of 0 in the AND byte will clear the corresponding register bits to 0; 10 is OR operation, and the OR byte directly ORs with the register value at the corresponding address, that is, the bits of 1 in the OR byte will set the corresponding register bits to 1; and 11 is XOR operation, and the XOR byte directly XORs with the register at the corresponding address, and the bits of 1 in the XOR byte will flip the corresponding register bits. It can be understood that in the embodiment of the application, the specific identification in the byte flag bit, the read-write flag bit and the write mode bit can be defined by itself, for example, RW=0 can indicate that the command is read operation or can indicate that the command is write operation, which will not be described in detail. The read-write byte number of the read-write register frame is controlled by the signal spi cs. When spi cs remains 0, the host will continuously read and write the register. After reading and writing one byte, the read-write address will be automatically increased by 1 until spi cs is 1 to terminate the read-write operation.

[0065] Further, the UWB master chip can also configure the byte flag bit in the first command frame as single byte to form a single-byte command; and the single-byte command is generally divided into system command and register read-write command. When the single-byte command forms a single-byte register read-write command based on the register address offset in the identification bit, the UWB master chip configures the read-write flag bit and the write mode bit as read operation; or, when the single-byte command is a single-byte register read-write command, the read-write flag bit is configured as write operation, and the write mode bit is configured as one of normal write, AND operation, OR operation and XOR operation. In an implementable scheme, as shown in FIG. 4, the byte flag bit is AD bit, and AD bit being 0 indicates that the frame is single-byte command, and AD bit being 1 indicates that the frame is double-byte command. Figure 6As shown, the single byte register read-write command is used to quickly read and write some registers, RW is 1 to indicate a write operation, RW is 0 and M1 is 0 to indicate a read operation. In the write operation, M1 and M0 indicate the write mode, similar to the above-mentioned double byte command, which will not be described here. The single byte register read-write command contains the offset of the address, and the actual register address is calculated by adding the offset to the last accessed register address. The host device (UWB master chip) accesses the registers of different UWB baseband chips based on the register address. For example, when reading and writing the register A of the UWB baseband chip, the slave device (UWB baseband chip) interface records the address of the register A. When accessing the register B of the slave device next time, if the single byte read-write command is used, the address of the read and write is calculated based on the address of the register A plus the offset. The offset is a signed number, and the offset generally has only 4 bits (including the sign bit), so it can be positioned within the range of 8 words (that is, 32 bytes) before and after the last read and write address. Therefore, if the accessed register and the last accessed register address do not exceed 8 words, the single byte read-write command can be used, thereby reducing 8 clock cycles of time.

[0066] Further, when the single byte command forms a single byte system command based on the pre-configured system control command in the identification bit, the UWB master chip can configure the read-write flag bit and the write mode bit as a control operation. The system control command can be a pre-defined system control code. In an implementable scheme, as shown, Figure 7 As shown, RW is 0 and M1 is 1 to indicate a single byte system command, which is used to control the UWB baseband chip. The single byte system command generally has 4 bits, which can support 16 system commands. When the single byte command is a single byte system command and the single byte command is greater than a preset number, the data byte in the first command frame can be expanded to the corresponding system command bit. The preset number is specific, when the system command is greater than 16, parameter 0 can be used for expansion, that is, parameter 0 can also be a command. For example, the system command is 4 bits, which can be defined as when the command is 1111, this byte indicates that the command will be expanded, that is, the next 1 byte or multiple bytes can also represent the command. The format of the expanded command of the subsequent byte can be defined by the user. And the single byte system command generally includes: Pll: start and stop system PLL; base address: define the base address of the register to be read and written, that is, the subsequent parameter is the register base address. Since the baseband chip can have many modules, different modules will have different base addresses. When double byte reading and writing, the base address and the 12-bit address in the command are spliced into the real register address; test: chip test command and other system commands.

[0067] 204、sending the second command frame to the UWB baseband chip through the data communication channel.

[0068] The UWB master chip can send the second command frame to the UWB baseband chip through the data communication channel formed by the SPI interface, so as to control the UWB baseband chip to perform data interaction based on the identification bit and the data byte in the second command frame. It can be understood that the UWB baseband chip can identify the second command frame, determine that the second command frame is a double-byte register read-write command, a single-byte system command or a single-byte register read-write command according to the identification bit of the second command frame, and further perform data interaction with the UWB master chip to realize the control of the UWB master chip on the UWB baseband chip or read and write the register.

[0069] Further, the UWB master chip can determine the target UWB baseband chip from the plurality of UWB baseband chips based on the chip selection signal in the chip selection signal channel; in one master and multiple slaves (one UWB master chip connected to multiple UWB baseband chips), the master device can have multiple chip selection signals, and different UWB baseband chips are selected through different chip selection signals. It can be understood that the UWB master chip can also select a UWB baseband chip that needs to respond to the subsequent command through the command frame. After determining the target UWB baseband chip, the UWB master chip can send the second command frame to the target UWB baseband chip through the data input channel.

[0070] In the embodiment of the application, the first command frame for transmitting a command to the UWB baseband chip is obtained, the identification bit of the first command frame is configured to obtain the second command frame, the second command frame is sent to the UWB baseband chip, and the UWB baseband chip is controlled to perform data interaction based on the identification bit and the data byte in the second command frame, so that the control of the UWB baseband chip can be efficiently and flexibly realized. Further, the UWB master chip can conveniently and efficiently configure and transmit data to the UWB baseband chip.

[0071] The embodiment of the application also provides a UWB master chip, as shown in Figure 8 The UWB master chip comprises:

[0072] The establishment unit 801 is configured to establish a data communication channel with the UWB baseband chip based on the SPI interface;

[0073] The acquisition unit 802 is configured to acquire a first command frame for transmitting a command to the UWB baseband chip, wherein the first command frame comprises a configurable identification bit and a data byte;

[0074] The configuration unit 803 is configured to configure the identification bit of the first command frame to obtain a second command frame;

[0075] The control unit 804 is configured to send the second command frame to the UWB baseband chip through the data communication channel, so as to control the UWB baseband chip to perform data interaction based on the identification bit and the data byte in the second command frame.

[0076] The embodiment of the present application further provides a UWB master control chip, as shown in the accompanying drawings, comprising: Figure 9

[0077] The central processor 901, the memory 902, the input and output interface 903, the wired or wireless network interface 904, and the power supply 905.

[0078] The memory 902 is a temporary storage memory or a persistent storage memory.

[0079] The central processor 901 is configured to communicate with the memory 902, and execute the instruction operation in the memory 902 on the control plane function entity to perform the control method.

[0080] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0081] In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented by other ways. For example, the device embodiments described above are only schematic, and the division of the units is only a logical function division, and there can be another division way in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0082] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0083] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of software functional unit.

[0084] ​The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, read-only memory), a random access memory (RAM, random access memory), a magnetic disk or an optical disk, and various media that can store program codes.

Claims

1. A control method for a UWB baseband chip, characterized in that: include: Establishing a data communication channel with the UWB baseband chip based on the SPI interface; Acquire a first command frame for transmitting a command to the UWB baseband chip, where the first command frame includes a configurable identification bit and a data byte; Configuring the identification bit of the first command frame to obtain a second command frame; Sending the second command frame to the UWB baseband chip through the data communication channel to control the UWB baseband chip to perform data interaction based on the identification bit and data bytes in the second command frame; The identification bits of the first command frame include: a byte flag bit, a read / write flag bit, and a write mode bit; The configuring the identification bit of the first command frame to obtain the second command frame includes: The byte flag bit, the read / write flag bit, and the write mode bit in the first command frame are configured respectively to obtain the second command frame.

2. The control method according to claim 1, characterized in that: The configuring the byte flag bit, the read / write flag bit, and the write mode bit in the first command frame respectively includes: Configuring the byte flag in the first command frame to be double-byte; Forming a double-byte register read and write command based on the double-byte flag bit and the register address of the identification bit; The read / write flag in the first command frame is configured as a read operation; or, the read / write flag in the first command frame is configured as a write operation, and the write mode bit is configured as one of normal write, AND operation, OR operation and XOR operation.

3. The control method according to claim 1, wherein: The configuring the byte flag bit, the read / write flag bit, and the write mode bit in the first command frame respectively to obtain the second command frame includes: Configuring the byte flag in the first command frame to be a single byte to form a single byte command; When the single-byte command forms a single-byte register read / write command based on the register address offset of the identification bit, the read / write flag bit and the write mode bit are configured as a read operation; or, when the single-byte command is a single-byte register read / write command, the read / write flag bit is configured as a write operation, and the write mode bit is configured as one of a normal write, an AND operation, an OR operation, and an XOR operation; When the single-byte command forms a single-byte system command based on the system control command pre-configured in the identification bit, the read / write flag bit and the write mode bit are configured as a control operation.

4. The control method according to claim 3, characterized in that: The method further comprises: When the single-byte command is a single-byte system command and the number of the single-byte commands is greater than a preset number, the data bytes in the first command frame are expanded into corresponding system command bits.

5. The control method according to claim 1, characterized in that: The establishing of a data communication channel with the UWB baseband chip based on the SPI interface comprises: Based on the SPI interface, a data input channel, a data output channel, a clock signal channel and a chip select signal channel are respectively established with the UWB baseband chip.

6. The control method according to claim 5, characterized in that: The sending the second command frame to the UWB baseband chip through the data communication channel includes: Determining a target UWB baseband chip from a plurality of UWB baseband chips based on a chip select signal in the chip select signal channel; The second command frame is sent to the target UWB baseband chip through the data input channel.

7. A UWB master control chip, characterized in that: include; An establishing unit, used for establishing a data communication channel with the UWB baseband chip based on the SPI interface; an acquiring unit, configured to acquire a first command frame for transmitting a command to the UWB baseband chip, wherein the first command frame includes a configurable identification bit and a data byte; a configuration unit, configured to configure the identification bit of the first command frame to obtain a second command frame; a control unit, configured to send the second command frame to the UWB baseband chip through the data communication channel, so as to control the UWB baseband chip to perform data interaction based on the identification bit and data bytes in the second command frame; The identification bits of the first command frame include: a byte flag bit, a read / write flag bit, and a write mode bit; The configuration unit is specifically configured to respectively configure the byte flag bit, the read / write flag bit, and the write mode bit in the first command frame to obtain the second command frame.

8. A UWB master control chip, characterized in that: include: CPU, memory, input and output interfaces, wired or wireless network interfaces, power supply; The memory is a transient storage memory or a persistent storage memory; The central processing unit is configured to communicate with the memory and execute instruction operations in the memory on a control plane function entity to perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium includes instructions, which, when executed on a computer, cause the computer to perform the method according to claims 1 to 6.

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