Optimized command sequence

Abstract

The present application relates to optimized command sequences. A device includes a memory array and a controller coupled to the memory array. The controller may be configured to receive a first command indicating the beginning of a sequence of access commands to be stored at the controller, then receive a first set of access commands associated with the access command sequence, and then receive a second command indicating the end of the access command sequence. The controller may also receive a second set of access commands after receiving the first command. After receiving the second set of access commands and before receiving a third set of access commands in the sequence, the controller may perform operations associated with the third set of access commands based at least in part on identifying the second set of access commands as beginning the access command sequence.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 173,519, filed on February 11, 2021, by Gyllenskog et al., entitled “OPTIMIZED COMMAND SEQUENCES,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The following relates generally to one or more systems for memory, and more particularly, to optimized command sequences.

[0004] The technical field relates to optimized command sequences. Background Art

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to a logic 1 or a logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of these states. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into a corresponding state.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Unless regularly refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0007] A device comprising: a memory array comprising a plurality of memory cells; and a controller coupled to the memory array and configured to: receive a first command indicating the beginning of a sequence of access commands to be stored at the controller; receive a first group of access commands after receiving the first command, the first group of access commands being associated with the access command sequence; receive a second command indicating the end of the access command sequence after receiving the first group of access commands; receive a second group of access commands after receiving the second command; and after receiving the second group of access commands and before receiving a third group of access commands of the sequence, perform operations associated with the third group of access commands based at least in part on identifying the second group of access commands as the beginning of the access command sequence.

[0008] A device comprising: a memory array comprising a plurality of memory cells; and a controller coupled to the memory array and configured to: receive a first command indicating the start of a sequence of access commands to be stored at the controller, wherein the sequence is associated with a set of data; receive a plurality of access commands after receiving the first command, the plurality of access commands being associated with the sequence and including an access command associated with a first portion of the set of data and an access command associated with a second portion of the set of data; receive a second command indicating the end of the sequence after receiving the plurality of access commands; and transfer the first portion of the set of data from a first location to a second location based at least in part on receiving the second command, wherein at the second location, operations associated with the access command associated with the first portion of the set of data and operations associated with the access command associated with the second portion of the same set of data are performed simultaneously.

[0009] A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, causes the electronic device to: receive, at a controller, a first command indicating the beginning of a sequence of access commands to be stored at the controller; receive, after receiving the first command, a first set of access commands associated with the access command sequence; receive, after receiving the first set of access commands, a second command indicating the end of the access command sequence; receive, after receiving the second command, a second set of access commands; and, after receiving the second set of access commands and before receiving a third set of access commands of the sequence, perform operations associated with the third set of access commands based at least in part on identifying the second set of access commands as the beginning of the access command sequence.

[0010] A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, causes the electronic device to: receive, at a controller, a first command indicating the start of a sequence of access commands to be stored at the controller, wherein the sequence is associated with a set of data stored at a memory array including a plurality of memory cells; receive, after receiving the first command, a plurality of access commands, the plurality of access commands being associated with the sequence and including an access command associated with a first portion of the set of data and an access command associated with a second portion of the set of data; receive, after receiving the plurality of access commands, a second command indicating the end of the sequence; and transfer, based at least in part on receiving the second command, the first portion of the set of data from a first location to a second location, wherein at the second location, operations associated with the access command associated with the first portion of the same set of data and operations associated with the access command associated with the second portion of the same set of data are performed simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting optimized command sequences according to examples as disclosed herein is shown.

[0012] Figure 2 An example of a system supporting optimized command sequences according to examples as disclosed herein is shown.

[0013] Figure 3 An example of a process flow supporting optimized command sequences according to examples as disclosed herein is shown.

[0014] Figure 4 An example of a process flow supporting optimized command sequences according to examples as disclosed herein is shown.

[0015] Figure 5 A block diagram is shown of a managed memory system controller supporting optimized command sequences according to examples as disclosed herein.

[0016] Figure 6 A block diagram is shown of a memory system controller supporting optimized command sequences according to examples as disclosed herein.

[0017] Figure 7 and 8 A flowchart illustrating one or more methods of supporting optimized command sequences is presented according to examples as disclosed herein. DETAILED DESCRIPTION

[0018] The system may include a host system and a memory system that stores data from the host system. For example, the memory system may include NAND memory cells that store logical states associated with data from the host system. The memory system may perform operations based on commands from the host system. For example, the memory system may perform access operations (e.g., read, write, or refresh operations). In some cases, the operations performed by the memory system may be time-consuming. For example, in a NAND system, read operations can be time-consuming, especially when performing operations on non-sequential or random addresses. In such cases, the memory system may consume additional power and bandwidth to perform the read operations. The host system may also transmit a command sequence to the memory system for repeated execution. For example, the host system may send a startup sequence. In some cases, the memory system may not recognize that the incoming command is part of a sequence (e.g., a startup sequence) and consumes increased power and bandwidth to perform the read operation.

[0019] Systems, techniques, and devices are described herein for a host system that indicates a repeatable command sequence and a memory system that stores the sequence based on the indication. By storing the indicated sequence, the memory system can recognize one or more incoming commands as the beginning of the stored sequence and, based on the recognition, perform one or more operations to facilitate execution of the command sequence. For example, the memory system can pre-read certain memory locations, pre-load a portion of a logical-to-physical (L2P) table for addresses that are part of the sequence, or perform operations related to power control (e.g., transitioning to a sleep or standby power state) based on recognizing the sequence and knowing when operations associated with the sequence occur according to the stored sequence. Additionally or alternatively, the memory system can rearrange data (e.g., transfer data from one location to another) to make the performance of the command sequence more efficient. For example, the memory system can transfer data associated with the sequence to different planes of a NAND memory die, allowing multiple commands of the sequence to be executed simultaneously using multi-plane reads. The memory system can also transfer data associated with the sequence to locations that can be accessed sequentially when executing the command sequence, for example, the memory system can transfer the data to physically contiguous memory locations. By optimizing a sequence of commands (eg, a command sequence), a memory system can execute the command sequence in a shorter duration and reduce power consumption and bandwidth.

[0020] First, in the reference Figure 1 and 2 Features of the present disclosure are described in the context of the described systems, devices, and circuits. Figure 3 and 4 The features of the present disclosure are described in the context of the process flow described. Figures 5 to 8These and other features of the present disclosure are further illustrated and described with reference to device diagrams and flow charts of the described optimized command sequences.

[0021] Figure 1 An example of a system 100 supporting optimized command sequences according to examples as disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110.

[0022] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0023] The computing system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0024] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include interfacing with a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1One memory system 110 is shown in FIG. 1 , but the host system 105 can be coupled to any number of memory systems 110 .

[0025] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more of these interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, host system 105 may be coupled to memory system 110 via a respective physical host interface for each memory device 130 included in memory system 110, or via a respective physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0026] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0027] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations, which can generally be referred to as access operations, at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and with the one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses (eg, data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105 .

[0028] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0029] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0030] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operational code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or operations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache or buffer for the memory system controller 115. For example, data may be stored in the local memory 120 when read from or written to the memory device 130, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0031] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0032] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As shown, memory device 130 - a may include a local controller 135 - a , and memory device 130 - b may include a local controller 135 - b .

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) if configured to each store two bits of information, a triple-level cell (TLC) if configured to each store three bits of information, a quad-level cell (QLC) if configured to each store four bits of information, or more generally, a multi-level cell. Relative to an SLC memory cell, a multi-level cell may provide greater storage density, but in some cases may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0035] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., with respect to command decoding, page address decoding circuitry, or other circuitry that is shared across planes 165).

[0036] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity), but can be erased at a second level of granularity (e.g., at a block granularity). That is, a page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., programmed or read in parallel as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., erased in parallel as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0038] In some cases, to update some data within a block 170 while retaining other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise indicate the data remaining in the old block 170 as invalid or outdated and may update a logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed rather than erasing and rewriting the entire old block 170, for example due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory location of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0039] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated because the latest or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of such data stored on the memory device 130. A page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0040] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background flushing, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in a block 170 to have invalid data so that the block 170 can be erased and reused, an algorithm known as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that includes, for example, selecting a block 170 containing both valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 may be used to store subsequent data (eg, data subsequently received from the host system 105 ).

[0041] The system 100 may include any number of non-transitory computer-readable media that support optimized command sequences. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0042] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0043] In some examples, the host system 105 may repeatedly transmit a particular command sequence (e.g., a command sequence, an access command sequence) to the memory device. If the command sequence includes random or non-sequential addresses, the execution of the command sequence may span the time period given by the independent execution of each command. Therefore, the power and bandwidth consumed by the command sequence may be higher relative to operations associated with a combinable or optimized sequence.

[0044] As described herein, the host system 105 can program a command sequence into the memory system 110. By storing the command sequence, the memory system 110 can execute the sequence in an optimized manner. For example, the memory system can determine a set of incoming access commands as starting a stored sequence. The memory system 110 can pre-read certain memory locations, extract portions of the L2P table, and perform power control-related operations based on determining the start of the sequence. Additionally or alternatively, the memory system 110 can rearrange data to reduce non-sequential or random addresses. As a result, the memory system can execute operations associated with the sequence more quickly, consume less power, and reduce latency.

[0045] Figure 2 An example of a system 200 supporting optimized command sequences according to an example disclosed herein is shown. The system 200 may be as described in reference Figure 1 The system 200 may include a memory system 210 configured to store data received from a host system 205 and to send data to the host system 205 when requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may be implemented as described with reference to Figure 1 Aspects of the described system 100. For example, memory system 210 and host system 205 can be instances of memory system 110 and host system 105, respectively.

[0046] The memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, such as in response to receiving an access command from the host system 205, as described herein. The memory device 240 may include a memory device 240 as described in reference to FIG. Figure 1One or more memory devices described. For example, memory device 240 may include NAND memory, PCM, select memory, 3D crosspoint, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, OxRAM, or random access memory (RAM) memory such as dynamic RAM (DRAM) memory or synchronous DRAM (SDRAM) memory. In some examples, NAND memory may be configured to perform non-sequential or random (e.g., scattered) read operations more slowly than other types of memory devices (e.g., slower than RAM, FERAM, MRAM, DRAM, or 3D crosspoint). Therefore, memory system 210 may rearrange data associated with the sequence to one or more of RAM, FERAM, MRAM, DRAM, or 3D crosspoint memory. In such examples, memory system 210 may perform access operations associated with the sequence faster because the data associated with the random or non-sequential read is in a memory that performs operations faster than NAND memory. The memories listed here are examples only and do not limit the claims. The memory system 210 may also include other types of memories.

[0047] The memory system 210 may include a memory controller 230 for controlling the transfer of data directly into and out of the memory devices 240, such as for storing data, retrieving data, and determining memory locations in which data is to be stored and from which data is to be retrieved. The memory controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple memory controllers 230, such as a different memory controller 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described with reference to FIG. Figure 1 Aspects of the local controller 135 are described.

[0048] The memory system 210 may further include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to translate data between the host system 205 and the memory device 240, such as shown by the data path 250, and may be collectively referred to as data path components.

[0049] Using buffer 225 to temporarily store data during transfer allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands. This can also allow bursts of commands to be processed, and once the burst stops, the buffered data can be stored or transferred (or both). Buffer 225 can include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM), or a hardware accelerator, or both, to allow for rapid storage and retrieval of data to and from buffer 225. Buffer 225 can include a data path switching component for bidirectional data transfer between buffer 225 and other components.

[0050] Temporary storage of data within buffer 225 may refer to the storage of data in buffer 225 during the execution of an access command. That is, after an access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten with data for additional access commands). Furthermore, buffer 225 may be a non-cacheable buffer. That is, the host system 205 cannot read data directly from buffer 225. For example, a read command may be added to a queue without requiring an address to be matched with an address already in buffer 225 (e.g., without requiring a cache address match or lookup operation). In some examples, buffer 225 may store data associated with pre-read operations performed when memory system 210 optimizes command sequences. For example, memory system 210 may identify a set of incoming access commands as the beginning of a sequence stored at memory system controller 215. Memory system 210 may then perform pre-read operations associated with the remaining access commands in the sequence before receiving the remaining access commands. For example, memory system 210 may receive the first set of commands associated with the beginning of a sequence. The memory system 210 may then perform a pre-read operation on data associated with the second set of commands in the sequence before the memory system 210 receives the second set of commands. The memory system 210 may then utilize the buffer 225 to store the data until the memory system 210 receives the second set of commands from the host system 205.

[0051] The memory system 210 may further include a memory system controller 215 for executing commands received from the host system 205 and controlling the data path components when moving data. The memory system controller 215 may be a memory system controller 215 such as that described in reference Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used for communication between system components.

[0052] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and store queue 270) may be used to control the processing of access commands and the movement of corresponding data. This may be beneficial, for example, if the memory system 210 processes more than one access command from the host system 205 in parallel. As an example of a possible implementation, the command queue 260, buffer queue 265, and store queue 270 are depicted at the interface 220, the memory system controller 215, and the storage controller 230, respectively. However, the queues, if used, may be located anywhere within the memory system 210.

[0053] Data transferred between the host system 205 and the memory device 240 may take a different path within the memory system 210 than non-data information (e.g., commands, status information). For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may use the data path 250 via data path components instead of the bus 235. The memory system controller 215 may control how and whether data is transferred between the host system 205 and the memory device 240 by communicating with the data path components via the bus 235 (e.g., using a protocol specific to the memory system 210).

[0054] If the host system 205 transmits an access command to the memory system 210, the interface 220 may receive the command, for example, according to a protocol (e.g., the UFS protocol or the eMMC protocol). Therefore, the interface 220 may be considered the front end of the memory system 210. After receiving each access command, the interface 220 may transmit the command to the memory system controller 215, for example, via the bus 235. In some cases, each command may be added to the command queue 260 by the interface 220 for transmission to the memory system controller 215.

[0055] The memory system controller 215 may determine that an access command has been received based on a communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from the command queue 260. After the command has been retrieved from the command queue 260 by the memory system controller 215, for example, the command may be removed from the command queue. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0056] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0057] In either case, the memory system controller 215 may use, among other things, the buffer 225 for temporarily storing data received from or sent to the host system 205. The buffer 225 may be considered the middleman of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0058] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the write command.

[0059] In some cases, the buffer queue 265 can be used to control the flow of commands associated with data stored in the buffer 225, including write commands. The buffer queue 265 can include access commands associated with the data currently stored in the buffer 225. In some cases, commands in the command queue 260 can be moved to the buffer queue 265 by the memory system controller 215 and can remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 can be associated with an address at the buffer 225. That is, a pointer can be maintained indicating the location in the buffer 225 where the data associated with each command is stored. By using the buffer queue 265, multiple access commands can be received sequentially from the host system 205, and at least some of the access commands can be processed in parallel.

[0060] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 may cause the interface 220 to transmit an indication of availability to the host system 205 (e.g., a "ready to transfer" indication), for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 may use the data path 250 to transfer the data to the buffer 225 for temporary storage. In some cases, the interface 220 may obtain the location of the data to be stored within the buffer 225 from the buffer 225 or the buffer queue 265. The interface 220 may indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0061] Once the write data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve the data from buffer 225 and transfer the data to memory device 240 using data path 250. Memory controller 230 can be considered the back end of memory system 210. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, that the transfer of data to a memory device in memory device 240 has been completed.

[0062] In some cases, storage queue 270 may be used to facilitate the transfer of write data. For example, memory system controller 215 may push a write command from buffer queue 265 to storage queue 270 (e.g., via bus 235) for processing. Storage queue 270 may include an entry for each access command. In some examples, storage queue 270 may additionally include a buffer pointer (e.g., an address) that may indicate a location in buffer 225 where data associated with the command is stored, and a storage pointer (e.g., an address) that may indicate a location in memory device 240 associated with the data. In some cases, storage controller 230 may obtain the location within buffer 225 from which the data is to be obtained from buffer 225, buffer queue 265, or storage queue 270. Storage controller 230 may manage the locations within memory device 240 used to store data (e.g., to perform wear leveling, garbage collection, etc.). Entries may be added to storage queue 270, for example, by memory system controller 215. After the transfer of the data is complete, the entry may be removed from the store queue 270 , for example, by the memory controller 230 or the memory system controller 215 .

[0063] To process a read command received from the host system 205, the memory system controller 215 may again first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the read command.

[0064] In some cases, the buffer queue 265 can be used to assist in buffering data associated with read commands in a manner similar to that discussed above with respect to write commands. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 can cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. The memory controller 230 can indicate to the memory system controller 215, for example, via the bus 235, when the data has been transferred to the buffer 225.

[0065] In some cases, storage queue 270 can be used to assist in the transfer of read data. For example, memory system controller 215 can push read commands to storage queue 270 for processing. In some cases, storage controller 230 can obtain the location within memory device 240 from which to retrieve data from buffer 225 or storage queue 270. In some cases, storage controller 230 can obtain the location within buffer 225 to store data from buffer queue 265. In some cases, storage controller 230 can obtain the location within buffer 225 to store data from storage queue 270. In some cases, memory system controller 215 can move commands processed by storage queue 270 back to command queue 260.

[0066] Once the data has been stored in the buffer 225 by the memory controller 230, the data can be transferred from the buffer 225 and sent to the host system 205. For example, the memory system controller 215 can cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transfer the data to the host system 205, for example, according to a protocol (e.g., the UFS protocol or the eMMC protocol). For example, the interface 220 can process commands from the command queue 260 and can indicate to the memory system controller 215, for example, via the bus 235, that the data transfer to the host system 205 is complete.

[0067] The memory system controller 215 may execute the received commands in order (e.g., in a first-in, first-out order) according to the order of the command queue 260. For each command, the memory system controller 215 may move data corresponding to the command into and out of the buffer 225, as discussed above. The command may remain in the buffer queue 265 while the data is moved into and stored in the buffer 225. If processing of the command is complete (e.g., if data corresponding to an access command has been transferred from the buffer 225), the command may be removed from the buffer queue 265, for example, by the memory system controller 215. If a command is removed from the buffer queue 265, the address where the data associated with the command was previously stored may be used to store data associated with a new command.

[0068] The memory system controller 215 may be further configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230 and the storage controller 230 may be omitted.

[0069] In some examples, the host system 205 may transmit a command to the memory system controller 215 indicating the start of a sequence to be stored by the memory system 210. The host system 205 may determine that the sequence is programmed into the memory system 210 based on repeatedly sending the sequence to the memory system 210. For example, whenever the host system 205 is started, it may frequently launch an application with the same command sequence. The host system 205 may program the sequence so that the memory system 210 can execute the sequence (e.g., launch the application) more quickly or more efficiently. The memory system controller 215 may store each access command received after the first command. The host system 205 may then transmit a second command to indicate the end of the sequence. In some examples, the memory system controller 215 may rearrange the data associated with the sequence so that the memory system 210 can execute the sequence more quickly. For example, the memory system controller 215 may transfer the data so that it can be read simultaneously or sequentially. The memory system controller 215 may also move data from a first memory type to a second memory type that performs operations associated with the sequence faster than the first memory type.

[0070] The memory system controller 215 may receive additional access commands from the host system 205 after the storage sequence. When the memory system controller 215 identifies the incoming access command as the start of a sequence stored in the memory system 210, the memory system controller 215 may extract a portion of the L2P table associated with the sequence. The memory system controller 215 may also perform a pre-read operation (e.g., perform an operation before receiving a corresponding access command in the sequence) and store the data in a buffer. The memory system controller 215 may also control the power state of the memory system 210 based on the storage sequence. By optimizing the sequence (e.g., by rearranging data, performing pre-reads, extracting portions of the L2P table, and controlling the power state), the memory system 210 may reduce power consumption, bandwidth, and latency in the system.

[0071] Figure 3 An example of a process flow 300 supporting an optimized command sequence according to an example as disclosed herein is shown. The process flow 300 may include a host device 305 and a memory device 310, which may be as described in reference Figure 1 1. The host device 105 and the memory device 110 are described in detail. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated examples are provided as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various examples. Therefore, not all processes are required in every example. Other process flows are possible. Process flow 300 illustrates an example for optimizing a host system command sequence received at a memory system to reduce bandwidth, power consumption, and latency of operations associated with the sequence.

[0072] At 315, the first register is read. For example, the host system 305 (e.g., as shown in FIG. Figure 1 The host system 105 described herein may be configured to store data in the memory system 310 (e.g., as described in reference Figure 1 10). In some instances, the memory system 310 may store a sequence (e.g., a command sequence, a plurality of command sequences, an access command sequence) in response to a command issued by the host system 305. That is, the host system 305 may repeatedly transmit a particular command sequence (e.g., a boot sequence). In such instances, the host system 305 may instruct the memory system 310 to record and track commands issued in the sequence so that the memory system 310 can optimize the sequence when subsequent commands are issued by the host system 305. In some cases, the memory system 310 may include a first register storing a first value indicating an amount of the sequence stored at the memory system 310. In some cases, the first register may be configured to be operable at a memory system controller (e.g., as described in reference to FIG. 10). Figure 1The first register may also be configured to store a second value indicating a maximum number of sequences that the memory system 310 is configured to store. For example, the first register may indicate that the memory system 310 can store 64 sequences. The second value may be set for the memory system 310 during the manufacturing process. In some examples, the host system 305 may read the first value to determine the number of sequences stored at the memory system 310. The host system 305 may also compare the first value indicating the number of sequences stored at the memory system 310 with the second value indicating the maximum number of sequences that can be stored. If the host system 305 determines that the first value is less than the second value, the host system 305 may proceed to 320. If the host system 305 determines that the first value is equal to the second value, the host system 305 may proceed to 375.

[0073] The host system 305 may initiate storage of a command sequence by sending a first command 320 to the memory system. For example, the memory system 310 may receive the first command 320 from the host system 305 indicating the start of a command sequence. The first command 320 may be received at a memory system controller. In some examples, the host system 305 may determine that a sequence frequently transmitted to the memory system 310 should be stored at the memory system 310. In such an example, the host system 305 may transmit the first command 320 indicating the start of a command sequence to be stored by the memory system 310. The host system 305 may include a sequence index in the first command 320, such as an index of a sequence to be programmed (stored) at the memory system 310.

[0074] Subsequently, a first set of access commands 325 may be received by the memory system 310. For example, the memory system 310 may receive the first set of access commands 325 from the host system 305. The first set of access commands 325 may be received at the memory system controller. In some examples, the first set of access commands 325 may include a read command associated with a read operation to be performed at the memory system 310. In some cases, the memory system 310 may record or store each command received from the host system 305 (e.g., the command and logical address associated with the command) in the first set of commands. In some cases, the memory system 310 may record or store a subset of the first set of access commands 325 (e.g., certain commands such as write commands may not be stored). Additionally, the memory system 310 may execute each command received from the host system 305 while also storing the command.

[0075] The host system 305 may send a second command 330 to the memory system 310. For example, the memory system 310 may receive the second command 330 from the host system 305 indicating the end of the sequence. The second command 330 may be received at the memory system controller. In some examples, the host system 305 may transmit the second command 330 to the memory system 310 after the host system 305 has transmitted all access commands associated with the sequence. The memory system 310 may stop recording or storing access commands from the host system 305 based on receiving the second command 330.

[0076] At 335, the sequence may be stored. For example, the memory system 310 may store the sequence received from the host system 305. The sequence may be stored at the memory system controller. In some examples, the sequence may be stored at the second register based on receiving the first set of access commands 325. For example, the first set of access commands 325 may be associated with the sequence. In some examples, the memory system 310 may also store a third value indicating the number of operations in the sequence (e.g., the number of commands received in the first set of access commands 325). In some examples, the memory system 310 may perform step 335 while receiving the first set of access commands 325. That is, when the memory system 310 receives those access commands, the memory system 310 may store the access commands associated with the sequence (e.g., command type and logical address). In some examples, the memory system controller may also update the first value in the first register indicating the number of stored sequences. For example, if 24 sequences were stored before receiving the first command 320 from the host system 305, the memory system controller may update the first value from 24 to 25.

[0077] At 340, a power state may be identified. For example, the memory system 310 may identify a power state at the memory system controller. In some examples, the memory system 310 may also identify a power state associated with the sequence based on the received first set of access commands 325. For example, the memory system controller may identify a first power state of the memory system 310 between receiving a first access command of the first set of access commands 325 and a second access command of the first set of access commands 325. In some cases, the memory system controller may identify the power state based on a duration between the first access command and the second access command. For example, the memory system controller may determine that the second access command was received from the host system 305 after a relatively long duration. Therefore, the memory system controller may identify that the memory system 310 may enter a standby or hibernation mode during the duration to conserve power consumption. In other examples, the memory system controller may identify the first power state based on different factors, such as the amount of resources consumed or clock cycles. The memory system 310 may store the power state information along with the sequence, for example, by storing the power state in a second register.

[0078] Subsequently, a second set of access commands 345 may be received. For example, the memory system 310 may receive the second set of access commands 345 from the host system 305. The second set of access commands 345 may be received at a memory system controller. In some examples, the number of access commands included in the second set of access commands 345 may be less than the number of access commands included in the first set of access commands.

[0079] At 350, the start of a sequence may be determined. For example, the memory system 305 may determine the start of a sequence. This determination may be made at the memory system controller. In some examples, the memory system controller may determine the start of a sequence by comparing the second set of access commands to all stored sequences, for example, by comparing each command to the start command of each stored sequence. In some examples, the memory system controller may also compare the address (e.g., logical address) received in each command to the address stored in the first command of each stored sequence to identify the start of a sequence that matches one of the stored sequences. In other examples, the memory system controller may determine the start of a sequence by initiating an operation (e.g., starting the operation) and determining that the operation is associated with a stored sequence. For example, the memory system controller may determine that the second set of access commands matches the start command of the first set of access commands. In such examples, the memory system controller may determine that the host system 305 begins the sequence associated with the first set of access commands and begins executing the optimization techniques described at 355, 365, and 375. It should be noted that the memory system 310 can perform any combination of the optimization techniques (including all three techniques) in any given order or simultaneously.

[0080] At 355, a pre-read operation may be performed. For example, the memory system 310 may perform a pre-read operation. The pre-read operation may be performed by a memory system controller. In some examples, the memory system controller may initiate the pre-read operation based on determining that the second set of access commands is the beginning of a sequence stored at the memory system. In such examples, the memory system controller may perform operations (e.g., read operations) associated with commands in the first set of commands that have not yet been received in the second set of access commands. That is, the memory system may perform the operations of the sequence based on determining that the second set of access commands begins the sequence before receiving the corresponding access command from the host system 305. In some examples, the memory system controller may read data associated with the pre-read operation into a buffer or cache until the corresponding access command is received from the host system 305.

[0081] At 360, other access commands may be received. For example, the memory system 310 may receive other access commands from the host system 305 that are not associated with a sequence. The other access commands may be received at the memory system controller. In some examples, the memory system controller may receive access commands that are not associated with any sequence while performing a pre-read operation or one of the other optimization techniques at 365 or 370. In such examples, the memory system 310 may continue to perform the optimization technique while executing the other received access commands. In some cases, the memory system 310 may store data associated with the pre-read operation in a buffer while also performing operations associated with the other received access commands. For example, the memory system may perform a pre-read operation and read data into a buffer while also performing read operations associated with the other access commands and transmitting the data associated with the other access commands back to the host system 305. The memory system 310 may also distinguish when an incoming command is part of a sequence and when it is another access command (e.g., a miscellaneous command). In other words, receiving the other access command does not interrupt the execution of the sequence.

[0082] At 365, a portion of a logical-to-physical (L2P) table may be retrieved. For example, the memory system 310 may retrieve the portion of the L2P table. The portion may be retrieved at a memory system controller. In some examples, to optimize execution of the sequence, the memory system 310 may retrieve the portion of the L2P table associated with the access commands of the sequence before receiving the corresponding access command from the host system 305. For example, the memory system 310 may retrieve the portion of the L2P table associated with the operation and access command from the first set of access commands, as well as the stored sequence of the second set of access commands that has not yet been transmitted by the host system 305. For example, at 375, the access command associated with the portion of the L2P table may be received, along with the third set of access commands. In some examples, retrieving the portion of the L2P table may enable the memory system 310 to more quickly access data at a physical location associated with a subsequent logical address received from the host system 305 at 375.

[0083] At 370, a transition of power states may occur. For example, the memory system 310 may transition from the second power state to the first power state. The transition may be initiated by the memory system controller. In some examples, the memory system controller may transition from the second power state (e.g., active or normal power during operation) to the first power state (e.g., standby or hibernation) based on determining that the second set of access commands begins the sequence. For example, the memory system controller may receive a third access command that corresponds to (e.g., is identical to) the first access command in the first set of access commands. After receiving the third access command, the memory system controller may cause the memory system 310 to transition to the first power state identified at 340. Subsequently, the memory system controller may receive a fourth access command that corresponds to the second access command in the first set of access commands and cause the memory system 310 to transition back to the second power state. By transitioning the power state to the first power state based on the cycle of the sequence, the memory system 310 may reduce power consumption.

[0084] At 375, a third set of access commands may be received. For example, the memory system 310 may receive the third set of access commands from the host system 305. The third set of access commands may be received at the memory system controller. In some examples, the host system 305 may transmit the third set of access commands associated with the remainder of the sequence.

[0085] At 380, data associated with the third set of access commands may be transmitted. For example, the memory system 310 may transmit the data to the host system 305. The data may be transmitted by the memory system controller. In some instances, the memory system 310 may transmit the data associated with the third set of access commands based on receiving the third set of access commands from the host system 305. In some cases, the memory system 310 may transfer some data from the buffer to the host system 305 based on a pre-read operation. In other cases, before receiving the third set of access commands, the memory system 310 may perform a read operation for a relatively short duration based on extracting a portion of the L2P. By implementing these optimization techniques, the memory system 310 may perform the operations of the stored sequence faster than the operations associated with the first set of access commands. That is, the memory system 310 may execute the first set of access commands in a first duration and, based on the optimization of the sequence (e.g., pre-read and L2P extraction), execute the second and third sets of access commands in a second duration that is less than the first duration. This may enable the memory system 310 to reduce bandwidth and improve system performance (e.g., as described in reference to FIG. Figure 1 The overall performance of the system 100) is described.

[0086] At 385, a third command may be received. For example, the memory system 310 may receive a third command from the host system 305 indicating an erase of a sequence. A third set of access commands may be received at the memory system controller. In some examples, the host system 305 may erase the sequence stored at the memory system 310. For example, when the memory system 350 has stored the maximum amount of the sequence indicated by the second value in the first register, the host system 305 may transmit the third command. In other examples, the host system 305 may determine that the sequence is no longer being used repeatedly and transmit the third command to additional available space in the memory system 310.

[0087] At 390, the sequence may be erased. For example, the memory system 310 may erase the sequence indicated in the third command from the host system 305. The erase operation may be initiated by the memory system controller. In some examples, the memory system 310 may also update a first value in a first register indicating the amount of sequences stored in the memory system controller. For example, the memory system 310 may update the value from 24 to 23 based on receiving the third command and having 24 sequences stored in the memory system controller prior to receiving the third command.

[0088] Figure 4 An example of a process flow 400 for supporting an optimized command sequence according to examples as disclosed herein is shown. The process flow 400 may include a host device 405 and a memory system 410, which may be as described in reference Figure 11. The host device 105 and the memory device 110 are described in detail. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated examples are provided as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various examples. Therefore, not all processes are required in every example. Other process flows are possible. Process flow 400 illustrates an example for optimizing a host system command sequence received at a memory system to reduce bandwidth, power consumption, and duration of operations associated with the sequence.

[0089] At 415, the first register may be read. For example, the host system 405 may read the first register stored at the memory system 410. Figure 3 As described, the host system 405 may program a command sequence to the memory system 410. The memory system 410 may store the sequence in a first register to indicate to the host system 405 the amount of sequence stored. The host system 405 may determine whether the memory system 410 is available to store another sequence before transmitting the first command. If the host system 405 determines that the amount of sequence stored is the same as the maximum amount of sequence that can be stored, the host system 405 may transmit an erase command and cause the memory system 410 to erase the memory as described in reference to FIG. Figure 3 The sequence described.

[0090] A first command 420 may be sent from the host system 405 to the memory system 410. For example, the memory system 410 may receive the first command 420 from the host system 305 indicating the start of a command sequence. The first command 420 may be received at a memory system controller. In some examples, the host system 405 may determine that a sequence frequently transmitted to the memory system 310 should be stored at the memory system 310. In such examples, the host system 405 may transmit the first command 420 to indicate the start of the sequence.

[0091] Subsequently, a plurality of access commands 425 may be received by the memory system 410. For example, the memory system 410 may receive the plurality of access commands 425 from the host system 405. The plurality of access commands 425 may be received at the memory system controller. In some examples, the memory system 410 may execute and store each of the plurality of access commands 425 received from the host system 405, as described with reference to FIG. Figure 3 described.

[0092] The host system 405 may send a second command 430 to the memory system 410. For example, the memory system 410 may receive the second command 430 from the host system 405 indicating the end of the sequence. The second command 430 may be received at a memory system controller. In some examples, the host system 405 may transmit the second command 430 to the memory system 410 after the host system 405 has transmitted a plurality of access commands 425 associated with the sequence. The memory system 410 may stop recording or storing access commands from the host system 405 based on receiving the second command 430.

[0093] At 435, the sequence may be stored. For example, the memory system 410 may store the sequence received from the host system 405. The sequence may be stored at the memory system controller. Figure 3 As described, the memory system 410 can store the sequence and update a register value that indicates the amount of the sequence stored at the memory system 410 .

[0094] At 440, data (e.g., data accessed in the plurality of access commands 425) may be transferred to different planes within one or more memory devices (e.g., memory dies). For example, the memory system 410 may transfer data from a first plane (e.g., a first location) to a second plane (e.g., a second location) in the same or different memory dies. The transfer may be initiated by a memory system controller. In some examples, the memory system 410 may be configured to perform multi-plane reads simultaneously. That is, a page in a first plane and a page in a second plane may be read simultaneously. In some examples, the memory system 410 may include six (6) planes and thus perform concurrent operations at pages in each plane, e.g., the memory system 410 may perform six (6) concurrent read operations. In some cases, a multi-plane read operation may be the fastest read operation that the memory system 410 may perform. Thus, the memory system 410 may transfer data associated with a sequence (e.g., data associated with a first command and a second command in the plurality of access commands) to different pages in different planes so that some commands of the sequence may be executed simultaneously. For example, the memory system 410 may rearrange data associated with the first through sixth access commands of the sequence to different pages across six (6) planes so that the first through sixth access commands can be executed simultaneously. By transferring the data, the memory system 410 may be able to execute some access commands of the sequence simultaneously, thereby enabling the memory system 410 to execute the sequence faster. The memory system 410 may perform the data transfer during garbage collection operations or other idle periods.

[0095] At 445, data (e.g., data accessed in the plurality of access commands 425) may be transferred to a different location. For example, the memory system 410 may transfer data from a first location to a second location. The data transfer may be initiated by a memory system controller. In some examples, the memory system 410 may include NAND memory cells. In such examples, the memory system 410 may be configured to perform sequential read operations (e.g., read operations at physically connected locations) faster than random read operations (e.g., scattered read operations, read operations of random pages across a plane). Thus, the memory system 410 may transfer some data associated with a sequence (e.g., data associated with a second command in the plurality of access commands) from a first location to a second location that is physically connected to the location storing the data associated with the first access command in the plurality of access commands. In other examples, the memory system 410 may include multiple types of memory cells. For example, the memory system 410 may include 3-dimensional Xpoint (3DXP) memory, ferroelectric RAM (FeRAM), phase change memory (PCM), magnetoresistive RAM (MRAM), self-selected memory, NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or random access memory (RAM) memory cells, such as dynamic RAM (DRAM) memory cells or synchronous DRAM (SDRAM) memory cells. In some examples, these memory cells may be configured to perform random read (or scattered) access operations with reduced latency relative to NAND memory cells. Thus, the memory system 410 may transfer data associated with random read operations from the NAND memory cell to the memory cell with reduced random read latency. In still other examples, the memory system 410 may include multiple types of NAND memory cells, such as single-level cells (SLCs) configured to store one bit of information in each cell, or multi-level cells (MLCs) configured to each store two or more bits of information. MLCs may include, for example, triple-level cells (TLCs) configured to each store three bits of information, quad-level cells (QLCs) configured to each store four bits of information, or cells configured to store more than four bits of information. In some instances, multi-level memory cells may be slower than single-level cells when performing access operations. Therefore, the memory system 410 may transfer data associated with a sequence from the multi-level memory cells to the single-level cells. By transferring the data to a second location, the memory system 410 may speed up the execution of operations associated with the sequence.

[0096] A second plurality of access commands 450 may be received. For example, the memory system 410 may receive the second plurality of access commands 450 from the host system 405. The second plurality of access commands 450 may be received at a memory system controller. In some examples, the second plurality of access commands 450 may be associated with a sequence. In other examples, the second plurality of access commands 450 may be part of a stored sequence, e.g., the second plurality of access commands 450 may be smaller than the first plurality of access commands.

[0097] At 455, the start of the sequence may be determined. For example, the memory system 410 may determine the start of the sequence based on the second plurality of access commands received from the host system 405. The second command may be received at the memory system controller. Figure 3 As described, the memory system controller can determine the start of the sequence by comparing the second plurality of commands to access commands in the stored sequence, comparing addresses of the second plurality of commands to addresses in the stored sequence, or by determining the start of an operation associated with the stored sequence.

[0098] At 460, the sequence may be executed. For example, the memory system 410 may execute the sequence. The execution of the sequence may be initiated by the memory system controller. In some examples, the memory system 410 may use a reference Figure 3 The memory system 410 may execute the sequence using the techniques described (e.g., at 355, 365, and 370). Additionally or alternatively, the memory system 410 may also execute some of the second plurality of access commands simultaneously or sequentially based on transferring data to different planes or locations (e.g., as described at 440 or 445). For example, the memory system 410 may receive, based on the transferred data, a first access command and a second access command from the second plurality of access commands associated with data stored at a first page of a first plane and a second page of a second plane. The memory system 410 may execute the first access command and the second access command simultaneously. The memory system 410 may also receive, based on the transferred data, a third access command from the second plurality of access commands associated with a third location physically connected to the first page or the second page. Thus, the memory system 410 may execute the third command sequentially after executing the first and second access commands. By using optimization techniques or by transferring data, the memory system 410 may execute the second plurality of access commands more quickly, thereby reducing power consumption, bandwidth, and latency. In some cases, the memory system 410 may execute the second plurality of access commands faster or more efficiently without determining the start of the sequence at 445 (e.g., transferring data between planes or locations may inherently provide an advantage to the sequence without identifying the sequence or performing any additional optimizations, such as pre-reading or pre-loading L2P tables).

[0099] At 465, data may be transferred. For example, the memory system 410 may transfer data associated with the second plurality of access commands (e.g., sequence) to the host system 405. The data transfer may be initiated by the memory system controller. In some examples, the host system 405 may receive the data faster based on optimization of the execution of the sequence.

[0100] Figure 5 A block diagram 500 is shown of a managed memory system controller 520 supporting optimized command sequences according to examples as disclosed herein. The managed memory system controller 520 may be a memory controller as described in reference Figures 1 to 4 5. The managed memory system controller 520 or its various components may be examples of means for performing various aspects of the optimized command sequence as described herein. For example, the managed memory system controller 520 may include a sequence component 530, a command component 535, an execution component 540, a transport component 545, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0101] The sequence component 530 can be configured to or otherwise support means for receiving, at the controller, a first command indicating the beginning of a sequence of access commands to be stored at the controller. In some examples, the sequence component 530 can be configured to or otherwise support means for receiving, at the controller, a second command indicating the end of the sequence of access commands after receiving the first set of access commands. In some cases, the sequence component 530 can be configured to or otherwise support means for comparing the second set of access commands of the sequence with the first set of access commands, wherein identifying the second set of access commands as the beginning of the sequence is based at least in part on the comparison.

[0102] In some cases, the sequence component 530 can be configured to or otherwise support means for receiving a third command associated with erasing a sequence stored at the controller. In some cases, the sequence component 530 can be configured to or otherwise support means for identifying a first power state of a memory array coupled to the controller between a first access command in the first set of access commands and a second access command in the first set of access commands based at least in part on receiving the first set of access commands. In some examples, the sequence component 530 can be configured to or otherwise support means for identifying a third access command in the second set of access commands that corresponds to the first access command in the first set of access commands based at least in part on storing the sequence and receiving the second set of access commands.

[0103] The command component 535 can be configured to or otherwise support means for receiving a first set of access commands at the controller after receiving a first command, the first set of commands being associated with an access command sequence. In some cases, the command component 535 can be configured to or otherwise support means for receiving a second set of access commands at the controller after receiving a second command. In some cases, the command component 535 can be configured to or otherwise support means for receiving a third set of access commands after performing an operation.

[0104] The execution component 540 can be configured to or otherwise support means for, after receiving the second set of access commands and before receiving the third set of access commands, performing operations associated with the third set of access commands of the sequence based at least in part on identifying the second set of access commands as starting the access command sequence. In some examples, the execution component 540 can be configured to or otherwise support means for, before receiving the third set of access commands, extracting a portion of the logical-to-physical table associated with the logical addresses accessed by the sequence based at least in part on identifying the second set of access commands.

[0105] In some cases, the execution component 540 can be configured to or otherwise support means for erasing the sequence at the controller based at least in part on receiving the third command. In some cases, the execution component 540 can be configured to or otherwise support means for updating a value in a register from a first value to a second value indicating an amount of the sequence stored at the controller based at least in part on erasing the sequence.

[0106] In some examples, the execution component 540 can be configured to or otherwise support means for determining the start of a second operation associated with the sequence, wherein identifying the second set of access commands as the start of the sequence is based at least in part on the determination. In some examples, the execution component 540 can be configured to or otherwise support means for updating a value in a register from a first value to a second value based at least in part on storing the sequence, wherein the value indicates an amount of the sequence stored at the controller. In some cases, the execution component 540 can be configured to or otherwise support means for setting a value in a register prior to receiving the first command, the value indicating an amount of the sequence that can be stored at the controller.

[0107] In some examples, the execution component 540 can be configured to or otherwise support means for storing the first power state and sequence based at least in part on identifying the first power state. In some examples, the execution component 540 can be configured to or otherwise support means for transitioning from the second power state to the first power state based at least in part on identifying a third access command corresponding to the first access command.

[0108] In some cases, the transfer component 545 may be configured as or otherwise support means for transferring data associated with one or more of the third set of access commands, where the operation includes performing a portion of a read operation associated with the one or more of the third set of access commands prior to receiving the one or more of the third set of access commands.

[0109] Figure 6 A block diagram 600 is shown of a managed memory system controller 620 supporting optimized command sequences according to examples as disclosed herein. The managed memory system controller 620 may be a memory controller as described in reference Figures 1 to 4 6. The managed memory system controller 620 or its various components may be examples of means for performing various aspects of the optimized command sequences as described herein. For example, the managed memory system controller 620 may include a sequence manager 625, a command manager 630, a transfer manager 635, an execution manager 640, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0110] Sequence manager 625 may be configured to or otherwise support means for receiving, at a controller coupled to a memory array comprising a plurality of memory cells, a first command indicating the start of a sequence of access commands to be stored at the controller, wherein the sequence is associated with a set of data. Command manager 630 may be configured to or otherwise support means for receiving, after receiving the first command, a plurality of access commands associated with the sequence, the plurality of access commands including an access command associated with a first portion of the set of data and an access command associated with a second portion of the set of data. In some examples, sequence manager 625 may be configured to or otherwise support means for receiving a second command indicating the end of the sequence after receiving the plurality of access commands. Transfer manager 635 may be configured to or otherwise support means for transferring, based at least in part on receiving the second command, the first portion of the set of data from a first location to a second location, wherein operations associated with the access command associated with the first portion of the set of data and operations associated with the access command associated with the second portion of the set of data are performed simultaneously at the second location.

[0111] In some examples, command manager 630 may be configured to or otherwise support means for receiving a second plurality of access commands after transferring a first portion of a set of data to a second location, the second plurality of access commands including a first access command associated with the first portion of the set of data and a second access command associated with the second portion of the set of data.

[0112] In some examples, the execution manager 640 may be configured to or otherwise support means for executing a second plurality of access commands at the first location and the second location based at least in part on receiving the second plurality of access commands, wherein the second plurality of access commands are associated with a sequence, and wherein operations for the first access commands and operations for the second access commands are performed concurrently.

[0113] In some examples, the execution manager 640 may be configured to perform a read operation based on receiving an operation for the first access command and an operation for the second access command. In some examples, the execution manager 640 may be configured to simultaneously perform a read operation on a first portion of a set of data and a second portion of a set of data from the memory array.

[0114] In some examples, the second plurality of access commands further includes a third access command associated with an operation on a third location, and the execution manager 640 may be configured to or otherwise support means for sequentially performing the operation associated with the third location based at least in part on transferring the first portion of a set of data to the second location after concurrently executing the first access command and the second access command.

[0115] Figure 7 A flowchart illustrating a method 700 for supporting optimized command sequences is shown according to examples disclosed herein. The operations of the method 700 may be implemented by a managed memory system controller or components thereof as described herein. For example, the operations of the method 700 may be implemented by a managed memory system controller or components thereof as described herein. Figures 1 to 5 The managed memory system controller described herein performs the functions described herein. In some examples, the managed memory system controller may execute a set of instructions to control functional elements of the device to perform the functions described herein. Additionally or alternatively, the managed memory system controller may use dedicated hardware to perform various aspects of the functions described herein.

[0116] At 705, the method may include receiving, at a controller, a first command indicating the start of a sequence of access commands to be stored at the controller. The operations of 705 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 705 may be as described in reference to Figure 5 The described sequence component 530 executes.

[0117] At 710, the method may include receiving a first set of access commands at a controller after receiving a first command, the first set of commands being associated with an access command sequence. The operations of 710 may be performed according to examples disclosed herein. In some examples, aspects of the operations of 710 may be implemented as described in reference to Figure 5 The command component 535 is described as executing.

[0118] At 715, the method may include receiving a second command at the controller indicating the end of the access command sequence after receiving the first set of access commands. The operations of 715 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 715 may be performed as described in reference to Figure 5 The described sequence component 530 executes.

[0119] At 720, the method may include receiving a second set of access commands at the controller after receiving the second command. The operations of 720 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 720 may be performed as described in reference to Figure 5 The command component 535 is described as executing.

[0120] At 725, the method may include, after receiving the second set of access commands and before receiving the third set of access commands, performing operations associated with the third set of access commands of the sequence based at least in part on identifying the second set of access commands as starting the access command sequence. The operations of 725 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 725 may be implemented as described in reference to Figure 5 The described execution component 540 executes.

[0121] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a controller, a first command indicating the beginning of a sequence of access commands to be stored at the controller; receiving, at the controller, a first set of access commands after receiving the first command, the first set of commands associated with the sequence of access commands; receiving, at the controller, a second command indicating the end of the sequence of access commands after receiving the first set of access commands; receiving, at the controller, a second set of access commands after receiving the second command; and, after receiving the second set of access commands and before receiving the third set of access commands, performing operations associated with the third set of access commands of the sequence based at least in part on identifying the second set of access commands as the beginning of the sequence of access commands.

[0122] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for: receiving a third set of access commands after performing the operations and transmitting data associated with one or more of the third set of access commands, wherein the operations include performing a portion of a read operation associated with one or more of the third set of access commands before receiving the one or more of the third set of access commands.

[0123] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for, prior to receiving a third set of access commands, extracting a portion of the logical-to-physical table associated with the logical addresses accessed by the sequence based at least in part on identifying the second set of access commands.

[0124] Some aspects of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for comparing a second set of access commands of the sequence to the first set of access commands, wherein identifying the second set of access commands as the starting sequence may be based at least in part on the comparison.

[0125] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining a start of a second operation associated with the sequence, wherein identifying the second set of access commands as the start of the sequence may be based at least in part on the determination.

[0126] Some aspects of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for updating a value in a register from a first value to a second value based at least in part on storing the sequence, wherein the value indicates an amount of the sequence stored at the controller.

[0127] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for setting a value in a register indicating an amount of the sequence storable at the controller prior to receiving the first command.

[0128] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for receiving a third command associated with erasing a sequence stored at the controller, erasing the sequence at the controller based at least in part on receiving the third command, and updating a value in a register from a first value to a second value indicating an amount of the sequence stored at the controller based at least in part on erasing the sequence.

[0129] Some aspects of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for: identifying a first power state of a memory array coupled to a controller between a first access command in a first set of access commands and a second access command in the first set of access commands based at least in part on receiving the first set of access commands; and storing the first power state and sequence based at least in part on identifying the first power state.

[0130] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: identifying a third access command in the second set of access commands that corresponds to a first access command in the first set of access commands based at least in part on storing the sequence and receiving the second set of access commands; and transitioning from the second power state to the first power state based at least in part on identifying the third access command that corresponds to the first access command.

[0131] Figure 8 A flowchart illustrating a method 800 for supporting optimized command sequences is shown according to examples disclosed herein. The operations of the method 800 may be implemented by a managed memory system controller or components thereof as described herein. For example, the operations of the method 800 may be implemented by a managed memory system controller or components thereof as described herein. Figures 1 to 4 6 and 7. In some examples, the managed memory system controller may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the managed memory system controller may use dedicated hardware to perform various aspects of the described functions.

[0132] At 805, the method may include receiving, at a controller coupled to a memory array comprising a plurality of memory cells, a first command indicating the start of a sequence of access commands to be stored at the controller, wherein the sequence is associated with a set of data. The operations of 805 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 805 may be implemented as described in reference to Figure 6 The described sequence manager 625 performs.

[0133] At 810, the method may include receiving a plurality of access commands after receiving the first command, the plurality of access commands being associated with the sequence and the plurality of access commands including an access command associated with a first portion of a set of data and an access command associated with a second portion of the set of data. The operations of 810 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 810 may be implemented as described in reference to Figure 6 The command manager 630 is described as executing.

[0134] At 815, the method may include receiving a second command indicating the end of the sequence after receiving the plurality of access commands. The operations of 815 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 815 may be performed as described in reference to Figure 6 The described sequence manager 625 performs.

[0135] At 820, the method may include transferring a first portion of a set of data from a first location to a second location based at least in part on receiving a second command, wherein at the second location, operations associated with the access command associated with the first portion of the same set of data and operations associated with the access command associated with the second portion of the same set of data are performed simultaneously. The operations of 820 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 820 may be implemented by methods as described in reference to Figure 6 The described transfer manager 635 performs.

[0136] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a controller coupled to a memory array including a plurality of memory cells, a first command indicating the start of a sequence of access commands to be stored at the controller, wherein the sequence is associated with a set of data; receiving, after receiving the first command, a plurality of access commands associated with the sequence and including an access command associated with a first portion of the set of data and an access command associated with a second portion of the set of data; receiving, after receiving the plurality of access commands, a second command indicating the end of the sequence; and transferring, based at least in part on receiving the second command, the first portion of the set of data from a first location to a second location, wherein at the second location, operations associated with the access command associated with the first portion of the set of data and operations associated with the access command associated with the second portion of the set of data are performed concurrently.

[0137] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: receiving a second plurality of access commands after transferring a first portion of a set of data to a second location, the second plurality of access commands including a first access command associated with the first portion of the set of data and a second access command associated with the second portion of the set of data; and executing the second plurality of access commands at the first location and the second location based at least in part on receiving the second plurality of access commands, wherein the second plurality of access commands may be associated with a sequence, and wherein operations on the first access commands and operations on the second access commands may be performed concurrently.

[0138] In some cases of the method 800 and apparatus described herein, the operations for the first access command and the operations for the second access command include read operations, and a first portion of a set of data and a second portion of a set of data may be read concurrently from the memory array.

[0139] In some cases of the method 800 and apparatus described herein, the second plurality of access commands further includes a third access command associated with an operation on a third location, and the methods, apparatus, and non-transitory computer-readable media may include other operations, features, circuit systems, logic, means, or instructions for sequentially performing the operation associated with the third location based at least in part on transferring the first portion of a set of data to the second location after concurrently executing the first access command and the second access command.

[0140] In some cases of the method 800 and apparatus described herein, a first plane of a memory array includes a first plurality of pages associated with a first location and a third location storing a second portion of a set of data, and a second plane of the memory array includes a second plurality of pages associated with the second location, wherein a first page of the first plurality of pages and a second page of the second plurality of pages can be configured to simultaneously perform an operation associated with the first location and an operation associated with the second location.

[0141] In some examples of the method 800 and apparatus described herein, the first location can be associated with a first type of memory cell and the second location can be associated with a second type of memory cell.

[0142] It should be noted that the above methods describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Additionally, two or more parts from the methods may be combined.

[0143] A device is described. The device may include: a memory array including a plurality of memory cells; and a controller coupled to the memory array and configured to: receive a first command indicating the beginning of a sequence of access commands to be stored at the controller; after receiving the first command, receive a first set of access commands, the first set of access commands being associated with the access command sequence; after receiving the first set of access commands, receive a second command indicating the end of the access command sequence; after receiving the second command, receive a second set of access commands; and after receiving the second set of access commands and before receiving the third set of access commands, perform operations associated with the third set of access commands of the sequence based at least in part on identifying the second set of access commands as the beginning of the access command sequence.

[0144] In some examples, the controller may be further configured to receive a third set of access commands and transmit data associated with one or more of the third set of access commands after performing operations, wherein the operations include performing a portion of a read operation associated with one or more of the third set of access commands before receiving the one or more of the third set of access commands.

[0145] In some cases, the controller may be further configured to, prior to receiving the third set of access commands, retrieve a portion of the logical-to-physical table associated with the logical addresses accessed by the sequence based at least in part on identifying the second set of access commands.

[0146] In some cases, the controller may be further configured to compare a second set of access commands of the sequence with the first set of access commands, wherein the controller may be configured to identify the second set of access commands as the starting sequence based at least in part on the comparison.

[0147] In some examples, the controller may be further configured to determine a start of a second operation associated with the sequence, wherein the controller may be configured to identify the second set of access commands as the start of the sequence based at least in part on the determination.

[0148] In some cases, the controller may be further configured to update a value in the register from a first value to a second value based at least in part on storing the sequence, wherein the value indicates an amount of the sequence stored at the controller.

[0149] In some cases, the controller may also be configured to set a value in a register prior to receiving the first command, the value indicating an amount of the sequence that may be stored at the controller.

[0150] In some instances, the controller may also be configured to receive a third command associated with erasing a sequence stored at the controller, erase the sequence at the controller based at least in part on receiving the third command, and update a value in the register from a first value to a second value indicating an amount of the sequence stored at the controller based at least in part on erasing the sequence.

[0151] In some cases, the controller may also be configured to identify a first power state of the device between a first access command in the first set of access commands and a second access command in the first set of access commands based at least in part on receiving the first set of access commands, and to store the first power state and sequence based at least in part on identifying the first power state.

[0152] In some cases, the controller may also be configured to identify a third access command in the second group of access commands that corresponds to a first access command in the first group of access commands based at least in part on the storage sequence and receipt of the second group of access commands; and transition from the second power state to the first power state based at least in part on identifying the third access command that corresponds to the first access command.

[0153] Another apparatus is described. The apparatus may include: a memory array including a plurality of memory cells; and a controller coupled to the memory array and configured to: receive a first command indicating the start of a sequence of access commands to be stored at the controller, wherein the sequence is associated with a set of data; receive a plurality of access commands after receiving the first command, the plurality of access commands being associated with the sequence and including an access command associated with a first portion of the set of data and an access command associated with a second portion of the set of data; receive a second command indicating the end of the sequence after receiving the plurality of access commands; and transfer the first portion of the set of data from a first location to a second location based at least in part on receiving the second command, wherein at the second location, operations associated with the access commands associated with the first portion of the set of data and operations associated with the access commands associated with the second portion of the set of data are performed simultaneously.

[0154] In some instances, the controller may be further configured to receive a second plurality of access commands after transferring the first portion of a set of data to the second location, the second plurality of access commands including a first access command associated with the first portion of the set of data and a second access command associated with the second portion of the set of data; and execute the second plurality of access commands at the first location and the second location based at least in part on receiving the second plurality of access commands, wherein the second plurality of access commands may be associated with a sequence, and wherein operations for the first access commands and operations for the second access commands may be performed simultaneously.

[0155] In some examples of the apparatus, the operation for the first access command and the operation for the second access command include read operations, and a first portion of a set of data and a second portion of a set of data may be read concurrently from the memory array.

[0156] In some examples, the controller may be further configured to sequentially perform operations associated with the third location based at least in part on transferring the first portion of a set of data to the second location after concurrently executing the first access command and the second access command.

[0157] In some examples of the device, the memory array further includes: a first plane comprising a first plurality of pages, the first plane associated with a first location and a third location storing a second portion of a set of data; and a second plane comprising a second plurality of pages, the second plane associated with the second location, wherein a first page of the first plurality of pages and a second page of the second plurality of pages are configurable to simultaneously perform an operation associated with the first location and an operation associated with the second location.

[0158] In some examples of an apparatus, the first location may be associated with a first type of memory cell and the second location may be associated with a second type of memory cell.

[0159] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0160] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component, such as a switch, transistor, or other component. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as a switch or transistor.

[0161] The term "coupling" refers to the situation where a component moves from an open-circuit relationship, in which signals are currently unable to pass between the components via a conductive path, to a closed-circuit relationship, in which signals are able to pass between the components via a conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0162] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If an open circuit exists between components, the components are isolated from each other. For example, if a switch is open, two components separated by the switch positioned between them are isolated from each other. If a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0163] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" are interchangeable if they are used to describe a conditional action, a conditional process, or a connection between parts of a process.

[0164] The term "in response to" may refer to a condition or action that occurs at least in part, if not entirely, as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0165] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on," "at least partially based on," or "in response to" some other step, action, event, or condition may be performed in addition or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other condition or action.

[0166] The devices including memory arrays discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0167] The switch component or transistor discussed herein may represent a field-effect transistor (FET) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include a heavily doped semiconductor region, such as a degenerate semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority of carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may render the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "switched on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0168] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "superior" to other examples. The detailed description includes specific details to provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0169] In the drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any similar component having the same first reference label, regardless of the second reference label.

[0170] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0171] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0172] As used herein, "or," as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of"), included in the claims, indicates an inclusive list, such that a list such as at least one of A, B, or C refers to A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be understood to refer to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0173] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disc storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0174] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will become apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: a memory array comprising a plurality of memory cells; as well as a controller coupled to the memory array and configured to: receiving a first command indicating the start of a first instance of a sequence of access commands to be stored at the controller; receiving a first set of access commands after receiving the first command, the first set of access commands being associated with the first instance of the access command sequence; receiving a second command indicating an end of said first instance of said sequence of access commands after receiving said first set of access commands; receiving a first portion of a second set of access commands after receiving the second command, the second set of access commands corresponding to a second instance of the access command sequence; as well as After receiving the first portion of the second set of access commands and before receiving a second portion of the second set of access commands, operations associated with the second portion of the second set of access commands are performed based at least in part on identifying receipt of the first portion of the second set of access commands as the second instance of beginning the access command sequence.

2. The memory system of claim 1 , wherein the controller is further configured to: receiving the second portion of the second set of access commands after performing the operation; and transmitting data associated with one or more access commands in the second portion of the second set of access commands, wherein the operation includes performing a portion of a read operation associated with the one or more access commands in the second portion of the second set of access commands before receiving the one or more access commands in the second portion of the second set of access commands.

3. The memory system according to claim 1 , wherein to perform the operation, the controller is further configured to: Prior to receiving the second portion of the second set of access commands, extracting a portion of a logical-to-physical table associated with a logical address accessed by the sequence based at least in part on identifying receipt of the first portion of the second set of access commands as the second instance of beginning the access command sequence.

4. The memory system of claim 1 , wherein the controller is further configured to: The first portion of the second set of access commands of the second instance of the sequence is compared with the first set of access commands of the first instance of the sequence, wherein the controller is configured to identify the first portion of the second set of access commands as starting the second instance of the sequence based at least in part on the comparison.

5. The memory system of claim 1 , wherein the controller is further configured to: A determination is made regarding the initiation of a second operation associated with the second instance of the sequence, wherein the controller is configured to identify the first portion of the second set of access commands as initiating the second instance of the sequence based at least in part on the determination.

6. The memory system of claim 1 , wherein the controller is further configured to: A value in a register is updated from a first value to a second value based at least in part on storing the sequence, wherein the value indicates an amount of the sequence stored at the controller.

7. The memory system of claim 1 , wherein the controller is further configured to: A value in a register is set prior to receiving the first command, the value indicating an amount of sequences that can be stored at the controller.

8. The memory system of claim 1 , wherein the controller is further configured to: receiving a third command associated with erasing the sequence stored at the controller; erasing the sequence at the controller based at least in part on receiving the third command; and A value in a register is updated from a first value to a second value indicative of an amount of the sequence stored at the controller based at least in part on erasing the sequence.

9. The memory system of claim 1 , wherein the controller is further configured to: identifying a first power state of the memory system between a first access command in the first set of access commands and a second access command in the first set of access commands based at least in part on receiving the first set of access commands; and The first power state and the sequence are stored based at least in part on identifying the first power state.

10. The memory system of claim 9, wherein the controller is further configured to: identifying a third access command in the first portion of the second set of access commands that corresponds to the first access command in the first set of access commands based at least in part on storing the sequence and receiving the first portion of the second set of access commands; and Transitioning from the second power state to the first power state is based at least in part on identifying the third access command corresponding to the first access command.

11. A memory system comprising: a memory array comprising a plurality of memory cells; as well as a controller coupled to the memory array and configured to: receiving a first command indicating a start of a first instance of a sequence of access commands to be stored at the controller, wherein the sequence is associated with a set of data; receiving a plurality of access commands after receiving the first command, the plurality of access commands being associated with the first instance of the sequence and the plurality of access commands comprising an access command associated with a first portion of the set of data and an access command associated with a second portion of the set of data, wherein the first instance of the sequence of access commands comprises the plurality of access commands; receiving a second command indicating an end of the first rank of the sequence after receiving the plurality of access commands; as well as The first portion of the set of data is transferred from a first location to a second location based at least in part on receiving the second command, wherein at the second location, operations associated with the access command associated with the first portion of the set of data and operations associated with the access command associated with the second portion of the set of data are performed concurrently.

12. The memory system of claim 11 , wherein the controller is further configured to: receiving a second plurality of access commands after transferring the first portion of the set of data to the second location, the second plurality of access commands including a first access command associated with the first portion of the set of data and a second access command associated with the second portion of the set of data; and executing the second plurality of access commands at the first location and the second location based at least in part on receiving the second plurality of access commands, wherein the second plurality of access commands are associated with a second instance of the sequence, and wherein operations for the first access commands and operations for the second access commands are performed concurrently.

13. The memory system of claim 12, wherein The operation for the first access command and the operation for the second access command include read operations; and The first portion of the set of data and the second portion of the set of data are read simultaneously from the memory array.

14. The memory system of claim 12 , wherein the second plurality of access commands further includes a third access command associated with an operation on a third location, and wherein the controller is further configured to: After concurrently executing the first access command and the second access command, the operations associated with the third location are sequentially performed based at least in part on transferring the first portion of the set of data to the second location.

15. The memory system of claim 11 , wherein the memory array further comprises: a first plane comprising a first plurality of pages, the first plane being associated with the first location and a third location storing the second portion of the set of data; as well as A second plane comprising a second plurality of pages, the second plane being associated with the second position, wherein a first page of the first plurality of pages and a second page of the second plurality of pages are configured to simultaneously perform the operation associated with the first position and the operation associated with the second position.

16. The memory system of claim 11, wherein: The first location is associated with a first type of memory cell; and The second location is associated with a second type of memory cell.

17. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving, at a controller, a first command indicating the start of a first instance of a sequence of access commands to be stored at the controller; receiving a first set of access commands after receiving the first command, the first set of access commands being associated with the first instance of the access command sequence; receiving a second command indicating an end of said first instance of said sequence of access commands after receiving said first set of access commands; receiving a first portion of a second set of access commands after receiving the second command, the second set of access commands corresponding to a second instance of the access command sequence; as well as After receiving the first portion of the second set of access commands and before receiving a second portion of the second set of access commands, operations associated with the second portion of the second set of access commands are performed based at least in part on identifying receipt of the first portion of the second set of access commands as the second instance of beginning the access command sequence.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receiving the second portion of the second set of access commands after performing the operation; and transmitting data associated with one or more access commands in the second portion of the second set of access commands, wherein the operation includes performing a portion of a read operation associated with the one or more access commands in the second portion of the second set of access commands before receiving the one or more access commands in the second portion of the second set of access commands.

19. The non-transitory computer-readable medium of claim 17 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device, prior to receiving the second portion of the second set of access commands, to extract a portion of a logical-to-physical table associated with a logical address accessed by the sequence based at least in part on identifying receipt of the first portion of the second set of access commands as the second instance of beginning the access command sequence.

20. The non-transitory computer-readable medium of claim 17 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to compare the first portion of the second set of access commands of the second instance of the sequence with the first set of access commands of the first instance of the sequence, wherein the electronic device is configured to identify the first portion of the second set of access commands as starting the second instance of the sequence based at least in part on the comparison.

21. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to update a value in a register from a first value to a second value based at least in part on storing the sequence, wherein the value indicates an amount of the sequence stored at the electronic device.

22. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: identifying a first power state of the electronic device between a first access command in the first set of access commands and a second access command in the first set of access commands based at least in part on receiving the first set of access commands; and The first power state and the sequence are stored based at least in part on identifying the first power state.

23. The non-transitory computer-readable medium of claim 22, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: identifying a third access command in the first portion of the second set of access commands that corresponds to the first access command in the first set of access commands based at least in part on storing the sequence and receiving the first portion of the second set of access commands; and Transitioning from the second power state to the first power state is based at least in part on identifying the third access command corresponding to the first access command.

24. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving, at a controller, a first command indicating a start of a first instance of a sequence of access commands to be stored at the controller, wherein the sequence is associated with a set of data stored at a memory array comprising a plurality of memory cells; receiving a plurality of access commands after receiving the first command, the plurality of access commands being associated with the first instance of the sequence and the plurality of access commands comprising an access command associated with a first portion of the set of data and an access command associated with a second portion of the set of data, wherein the first instance of the sequence of access commands comprises the plurality of access commands; receiving a second command indicating an end of the first instance of the sequence after receiving the plurality of access commands; as well as The first portion of the set of data is transferred from a first location to a second location based at least in part on receiving the second command, wherein at the second location, operations associated with the access command associated with the first portion of the set of data and operations associated with the access command associated with the second portion of the set of data are performed concurrently.

25. The non-transitory computer-readable medium of claim 24, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receiving a second plurality of access commands after transferring the first portion of the set of data to the second location, the second plurality of access commands including a first access command associated with the first portion of the set of data and a second access command associated with the second portion of the set of data; and Executing the second plurality of access commands at the second location based at least in part on receiving the second plurality of access commands, wherein the second plurality of access commands are associated with a second instance of the sequence, and wherein operations for the first access commands and operations for the second access commands are performed concurrently.

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