A Configurable Montgomery Modular Multiplier

Abstract

The present application discloses a configurable Montgomery modular multiplier, which includes an input storage unit, a first preset number of processing units, an iterative input unit, an adding unit, a first output unit, an output shift unit, a second output unit and a cycle control unit, wherein the first preset number of processing units is used to receive input data and perform shift processing on the input data, and the cycle control unit controls the output of the cycle processing unit, the iterative input unit, the adding unit and the first output unit in each count through a count value. The modular multiplier disclosed in the present application can change the parameters of its corresponding algorithm by changing the number of processing units, thereby changing the number of operation cycles and the consumed hardware resources, so that the modular multiplier can meet the needs of cryptographic systems with different hardware area and delay requirements.

Description

Technical Field

[0001] The present application relates to the field of analog multipliers, and in particular to a configurable Montgomery analog multiplier. Background Art

[0002] As internationally accepted encryption algorithms, asymmetric encryption algorithms such as the RSA algorithm and the ECC algorithm have a wide range of applications and high compatibility, and are widely used in modern cryptographic systems. In asymmetric encryption algorithms such as RSA and ECC, modular multiplication operations are essential operations. Among them, the Montgomery modular multiplication algorithm uses shifting to replace the division operation in the traditional modular multiplication algorithm, which is easy to implement in hardware. Therefore, modular multipliers based on the Montgomery modular multiplication algorithm are widely used in modern cryptographic systems.

[0003] Different application scenarios have different requirements for the area, power consumption, and latency of the modular multiplier. Therefore, there are currently a variety of different Montgomery modular multipliers based on different application scenarios. However, since the cryptographic system application scenarios have more extensive requirements for encryption and decryption efficiency and hardware power consumption, there is currently no Montgomery modular multiplier hardware architecture that can be applied to cryptographic systems with different areas, power consumption, and latency. Summary of the invention

[0004] In order to solve the problem that there is currently no hardware architecture of a Montgomery modular multiplier that can be applied to cryptographic systems with different areas, power consumption and delays, the present application provides a configurable Montgomery modular multiplier through the following aspects.

[0005] The first aspect of the present application provides a configurable Montgomery modular multiplier, comprising an input storage unit, a first preset value processing unit, an iterative input unit, an adding unit, a first output unit, an output shift unit, a second output unit and a cycle control unit, wherein:

[0006] The input storage unit is used to receive and store the first input data, the second input data, the third input data, the fourth input data and the fifth input data, and to transmit the first input data, the second input data, the third input data and the fourth input data to the processing unit, and to transmit the fourth input data and the fifth input data to the cycle control unit, and to transmit the fourth input data to the iteration input unit, the fifth input data is represented by a binary number, and the second input data is a prime number;

[0007] The processing unit is used for performing selective processing on the received first input data, second input data, third input data and fourth input data to obtain first data to be added, and transmitting the first data to be added to the adding unit;

[0008] The iterative input unit is used to receive the fourth input data of the input storage unit and the iterative data of the output shift unit, and select and process the fourth input data and the iterative data to obtain the second data to be added, and transmit the second data to be added to the adding unit;

[0009] The adding unit is used to perform an adding operation on the received first preset value of the first data to be added and the second data to be added to obtain a sum result, and perform selection processing on the sum result to obtain the first data to be output, and transmit the first data to be output to the first output unit;

[0010] The first output unit is used to transmit the received first data to be output to the input storage unit, or to the second output selection unit and the output shift unit;

[0011] The output shift unit is used for right-shifting the received first data to be output by a first preset value of digits to obtain iterative data, and transmitting the iterative data to the iterative input selector and the second output selector;

[0012] The cycle control unit is used to receive the fourth input data, the fifth input data and the iteration data, and perform a first operation process on the fourth input data, the fifth input data and the iteration data in each counting cycle to obtain a first preset value of two-bit binary numbers, and transmit the two-bit binary numbers to the corresponding processing units respectively, and control the output of the processing unit, the iteration input unit, the addition unit and the first output unit in each counting cycle through the count value;

[0013] The second output unit is used to perform a fourth selection process on the received first data to be output and iterative data to obtain output data.

[0014] In a possible implementation manner, the cycle control unit is used to perform a first operation process on the fourth input data, the fifth input data, and the iteration data in each counting cycle, including:

[0015] The fourth input data, the fifth input data and the iteration data of the current counting cycle are subjected to the first operation processing by taking the lower preset digit to obtain the intermediate data, the value of the lower preset digit is equal to the first preset value, and the operation is as follows:

[0016] q=(P(k-1:0)+X(k-1:0)×Y(k-1:0))mod2 k

[0017] Wherein, q represents intermediate data, P(k-1:0) represents bits 0 to k-1 of the iteration data, X(k-1:0) represents bits 0 to k-1 of the fifth input data, Y(k-1:0) represents bits 0 to k-1 of the fourth input data, the intermediate data is represented by a binary number, k is a first preset value, and mod is a modulo operation symbol;

[0018] Combining the first preset bit of the fifth input data and the first preset bit of the intermediate data into a two-bit binary number, the first preset bit being any one bit from 0 to k-1 bits in the intermediate data, and transmitting the two-bit binary numbers to their corresponding processing units respectively;

[0019] The fifth input data is right-shifted by a first preset value to obtain the fifth input data for the first operation processing in the next counting cycle.

[0020] In a possible implementation, the processing unit includes a data input selector, a first control selector, a second control selector and a shifter, wherein:

[0021] The first control selector is used to receive second input data, and process the second input data under the control of the third control amount to obtain second processed data and transmit it to the data input selector;

[0022] The second control selector is used to receive the first selected data or the second selected data, and select the first selected data and the second selected data under the control of the first control amount to obtain the first selected data, and transmit the first selected data to the data input selector, wherein the first selected data is one of the first selected data and the second selected data;

[0023] The data input selector is used to select the first input data, the second processed data, the third input data and the fourth input data according to the first selected data to obtain the second selected data, and the data input selector transmits the second selected data to the shifter, and the second selected data is one of the first input data, the second processed data, the third input data and the fourth input data;

[0024] The shifter is used to left-shift the received second selected data by a set digit to obtain the first data to be added, and the value of the set digit is equal to the first preset value.

[0025] In a possible implementation manner, it is characterized in that the data input selector is used to select the first input data, the second processed data, the third input data and the fourth input data according to the first selected data, including:

[0026] If the first selected data is the first selected data, the data input selector selects one data from the first input data and the second processed data and transmits it to the shifter;

[0027] If the first selected data is the second selected data, the data input selector selects the first input data, the second processed data, the third input data and the fourth input data according to the second selected data, and transmits the selected data to the shifter, and the second selected data is a two-bit binary number.

[0028] In one implementable method, a first preset value data input selector corresponds to a first preset value first selection data, among the first preset value first selection data, there is any first selection data that is 01, and the other first selection data are 00, and the first selection data corresponding to the data input selector is a constant value. When the first selection data is 01, the data input selector selects the second processing data to be transmitted to the shifter, and when the first selection data is 00, the data input selector selects the first input data to be transmitted to the shifter.

[0029] In a possible implementation, the adding unit includes an adding module and a plus-one selector, wherein:

[0030] The adding module is used for receiving a first preset value of first data to be added and a second data to be added, performing an adding operation on them, and obtaining a sum result;

[0031] The plus-one selector is used to process the addition result under the control of the third control amount to obtain the first data to be output.

[0032] In one implementation, the count value starts from zero and increases by one in each count cycle until it reaches a second preset value, wherein:

[0033] When the count value is zero, the second control amount is zero, otherwise, the second control amount is one;

[0034] When the count value is a second preset value, the third control amount is one, otherwise, the third control amount is zero, wherein the second preset value is a value obtained by adding one to the integer of the bit width of the second input data divided by the first preset value;

[0035] The second control amount and the third control amount are logically operated to obtain the first control amount, and the first control amount is obtained by the following logical operation:

[0036] !S0||S1,

[0037] Wherein, S0 represents the second control quantity, S1 represents the third control quantity, ! represents negation, and || represents an OR logic operation.

[0038] In one implementation, the second control selector is controlled to select data according to the first control amount. When the first control amount is zero, the second control selector inputs the first selected data as the first selected data to the data input selector. When the first control amount is one, the second control selector inputs the second selected data as the second selected data to the data input selector.

[0039] Controlling the iterative input unit to select data according to the second control amount, when the second control amount is zero, the iterative input unit selects the fourth input data to transmit to the adding unit, and when the second control amount is one, the iterative input unit transmits the iterative data to the adding unit;

[0040] Control the first output unit to select data according to the second control amount, when the second control amount is zero, the first output unit transmits the first data to be output to the input storage unit, when the second control amount is one, the first output unit transmits the first data to be output to the output shift unit and the second output unit at the same time;

[0041] Control the first control selector to process the second input data according to the third control amount, when the third control amount is zero, the first control selector inputs the second input data to the data input selector, and when the third control amount is one, the first control selector inverts the second input data bit by bit and inputs it to the data input selector;

[0042] The addition unit is controlled to process the sum result according to the third control amount. When the third control amount is zero, the sum result is added with zero. When the third control amount is one, the sum result is added with one.

[0043] In an achievable manner, when the count value is zero, the first output unit transfers the first data to be output to the input storage unit to participate in a subsequent operation process as the third input data.

[0044] In an implementable manner, the second output unit is used to perform a fourth selection process on the received first data to be output and iterative data to obtain output data, including:

[0045] Control the second output unit to select data according to the sign bit of the first data to be output, and when the sign bit is zero, the second output unit selects the first data to be output for output to obtain output data;

[0046] When the sign bit is one, the second output unit selects iterative data for output to obtain output data.

[0047] The present application discloses a configurable Montgomery modular multiplier, which includes an input storage unit, a first preset number of processing units, an iterative input unit, an adding unit, a first output unit, an output shift unit, a second output unit and a cycle control unit, wherein the first preset number of processing units is used to receive input data and perform shift processing on the input data, and the cycle control unit controls the output of the cycle processing unit, the iterative input unit, the adding unit and the first output unit in each count through a count value. The modular multiplier disclosed in the present application can change the parameters of its corresponding algorithm by changing the number of processing units, thereby changing the number of operation cycles and the consumed hardware resources, so that the modular multiplier can meet the needs of cryptographic systems with different hardware area and delay requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic diagram of the structure of a configurable Montgomery modular multiplier provided in an embodiment of the present application;

[0049] Figure 2 A schematic diagram of the structure of a configurable Montgomery modular multiplier in an implementation manner provided in an embodiment of the present application;

[0050] Figure 3 A schematic diagram of an adding unit of a configurable Montgomery modular multiplier provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0052] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0053] The terms first, second, third, etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or precedence, unless otherwise noted. It should be understood that the terms used in this way are interchangeable where appropriate. Any variation of the term inclusion is intended to cover but not exclude inclusion. For example, a product or device that includes a series of components is not necessarily limited to clearly listing all components, but may include all components that are not clearly listed, but may include other components that are not clearly listed or inherent to these products or devices. The term unit refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that can perform the functions associated with the element.

[0054] To facilitate the technical solution of the application, some concepts involved in the application are first explained below.

[0055] The Montgomery modular multiplication algorithm proposed by PLmontgomery uses modular addition and right shift operations, avoiding the time-consuming division operation in the usual modular algorithm, and is considered to be an effective algorithm for hardware implementation of large number modular multiplication. The binary Montgomery algorithm simplifies large number multiplication to addition by 2, and multiplication by 2 is left shifting by one bit. However, the binary Montgomery algorithm requires too many cycles and too many cycles. The solution adopted in the embodiment of the present application can shift left by k bits (k>1) at one time, reducing the number of cycles.

[0056] First, this application organizes the Montgomery modular multiplication algorithm as follows:

[0057]

[0058] Iterative calculation part:

[0059] P=0

[0060]

[0061] q=(P(k-1:0)+X(k-1:0)×Y(k-1:0))mod 2 k

[0062] P=(P+X(k-1:0)×Y+q×M) / 2 k

[0063] X=X / 2 k

[0064] end for

[0065] Subtraction correction part:

[0066] if P>M then

[0067] P = P - M

[0068] end if

[0069] Output: P = X × Y × R -1 mod M

[0070] Wherein, X, Y, and M are three input data, P is an output data, and the function of the algorithm is to calculate P = X × Y × R -1 mod M. It should be noted that this application provides two parameters n and k to limit the number of loops of the Montgomery algorithm. Among them, n is the bit width of M, and the number of iterations of this algorithm is When the bit width n of M is fixed, the larger k is, the smaller the number of iterations; the smaller k is, the larger the number of iterations. According to this characteristic, the modular multiplier can be configured by adjusting the size of k, so that the modular multiplier can be applicable to application scenarios with different requirements for power consumption or area.

[0071] To design the target modular multiplier, the embodiments of this application perform relevant transformations on the above algorithm. Since q = (P(k - 1:0) + X(k - 1:0) × Y(k - 1)) mod 2 k , and the amount of operation of X = X / 2 k is relatively small. Therefore, the embodiments of this application only transform P = (P + X(k - 1:0) × Y + q × M) / 2 k The transformation process is as follows:

[0072]

[0073] From q = (P(k - 1:0) + X(k - 1:0) × Y(k - 1)) mod 2 k , it can be seen that the number of bits of q is less than k. Therefore, P = (P + X(k - 1:0) × Y + q × M) / 2 k can be transformed into multiplying each bit of the low k bits of X by Y and multiplying each bit of the low k bits of q by M, summing the above two and adding to P in the previous cycle, and then shifting right by k bits. Among them, "<<" in the transformation process represents left shift. "<<i" represents left shift by i bits. Through the above transformation, the two multiplications in the original modular multiplication algorithm are converted into additions, and the carry is retained in the addition process, so that the critical path becomes very short.

[0074] Based on the above algorithm, the embodiments of this application provide a configurable Montgomery modular multiplier. See Figure 1 The structural schematic diagram of a configurable Montgomery modular multiplier provided by the embodiments of this application. The modular multiplier includes an input storage unit, a first preset number of processing units, an iterative input unit, an addition unit, a first output unit, an output shift unit, a second output unit, and a cycle control unit.

[0075] Among them, the input storage unit is used to receive and store the first input data, the second input data, the third input data, the fourth input data and the fifth input data, and is used to transmit the first input data, the second input data, the third input data and the fourth input data to the processing unit, and is used to transmit the fourth input data and the fifth input data to the cycle control unit, and is used to transmit the fourth input data to the iterative input unit, the fifth input data is represented by a binary number, and the second input data is a prime number.

[0076] In one implementation, see Figure 2 A structural diagram of a configurable Montgomery modular multiplier provided in an embodiment of the present application in an implementable manner is shown, the first input data is 0, the second input data is M, the third input data is M+Y, the fourth input data is Y, and the fifth input data is X. The input storage unit receives the X, Y, and M data input from outside the chip, and temporarily stores the X, Y, and M data. At the same time, the input storage unit also receives the third input data M+Y obtained by on-chip operation and temporarily stores it. Among them, 0, M, M+Y, and Y data will be transmitted to the processing unit, X and Y will be transmitted to the cycle control unit for related operations in the cycle control unit, and Y will participate in the related processing of the iterative input unit. It is worth noting that in order to facilitate the execution of hardware in the embodiment of the present application, X is pre-processed as a binary number, and the input data M must be a prime number. The above-mentioned first preset value is represented by k.

[0077] The processing unit is used for performing selection processing on the received first input data, second input data, third input data and fourth input data to obtain first data to be added, and transmitting the first data to be added to the adding unit.

[0078] In one implementation, the processing unit in the configurable Montgomery modular multiplier provided in the embodiment of the present application includes a data input selector, a first control selector, a second control selector, and a shifter.

[0079] The first control selector is used to receive the second input data M, and process the second input data under the control of the third control quantity S1 to obtain second processed data and transmit it to the data input selector.

[0080] Exemplary, combined Figure 2As shown, the first control selector is located on the channel connecting the M data in the input storage unit and the data input selector, and the third control amount S1 is the control amount determined by the count value count in the cycle control unit, and its specific control method will be described in detail later; the first control selector is controlled to process the second input data M according to the third control amount S1, when the third control amount S1 is 0, the first control selector inputs the second input data to the data input selector, and when the third control amount S1 is 1, the first control selector performs bitwise inversion on the second input data M and inputs it to the data input selector. It is worth noting that the second input data M is bitwise inverted to obtain the second processed data.

[0081] The second control selector is used to receive the first selection data or the second selection data, and select the first selection data and the second selection data under the control of the first control quantity to obtain the first selected data, and transmit the first selected data to the data input selector, the first selected data being one of the first selection data and the second selection data.

[0082] Exemplary, combined Figure 2 As shown, the second control selector is connected to the data input selector, and the first control amount is obtained by the following logical operation:

[0083] !S0||S1,

[0084] Wherein, S0 represents the second control amount, represents the third control amount S1, ! represents negation, and || represents an OR logic operation; according to the first control amount ! S0|| S1, the second control selector is controlled to select data, when the first control amount is 0, the second control selector inputs the first selected data as the first selected data to the data input selector, and when the first control amount is 1, the second control selector inputs the second selected data as the first selected data to the data input selector.

[0085] The data input selector is used to select the first input data, the second processed data, the third input data and the fourth input data according to the first selected data to obtain the second selected data. The data input selector transfers the second selected data to the shifter. The second selected data is one of the first input data, the second processed data, the third input data and the fourth input data.

[0086] Exemplary, combined Figure 2As shown, the data input selector is the central component of the processing unit, and the shifter is located at the output end of each data input selector; the data input selector is used to select the first input data 0, the second processed data, the third input data M+Y and the fourth input data Y according to the first selected data, including: if the first selected data is the first selected data, the data input selector selects one data from the first input data 0 and the second processed data and transmits it to the shifter; if the first selected data is the second selected data, the data input selector selects the first input data 0, the second processed data, the third input data M+Y and the fourth input data Y according to the second selected data, and transmits the selected data to the shifter. Furthermore, k data input selectors correspond to k first selection data, among which any one of the k first selection data is 01, and the other first selection data is 00, and the first selection data corresponding to each of the data input selectors is a fixed value, when the first selection data is 01, the data input selector selects the second processing data to be transmitted to the shifter, and when the first selection data is 00, the data input selector selects the first input data to be transmitted to the shifter; the second selection data is a two-bit binary number provided by the cycle control unit, and the two-bit binary number will be described in detail later. The data input selector selects the second selected data and transmits the second selected data to the shifter.

[0087] The shifter is used to left-shift the received second selected data by a set digit to obtain the first data to be added, and the value of the set digit is equal to the first preset value.

[0088] Exemplarily, the shifter is used to shift the second selected data output by the data input selector, and the shift amount is a preset digit, and the value of the preset digit is equal to the first preset value k. It is worth noting that the second selected data is one of the first input data 0, the second processed data, the third input data M+Y or the fourth input data Y.

[0089] The iterative input unit is used to receive the fourth input data of the input storage unit and the iterative data of the output shift unit, and select and process the fourth input data and the iterative data to obtain second data to be added, and transmit the second data to be added to the adding unit.

[0090] Exemplary, combined Figure 2 As shown, the iterative input unit selects data according to the second control amount S0. When the second control amount is 0, the iterative input unit selects the fourth input data Y to be transmitted to the adding unit. When the second control amount is 1, the iterative input unit selects the fourth input data P to be transmitted to the adding unit. i Transmitted to the adding unit. It is worth noting that the iterative input unit in the embodiment of the present application is an iterative input selector.

[0091] The adding unit is used to add the received first preset value of first data to be added and second data to be added to obtain a sum result, and select the sum result to obtain first data to be output, and transmit the first data to be output to the first output unit.

[0092] Exemplary, combined Figure 2 As shown, the adding unit includes a block adding module and an adding selector, and the adding unit is used to perform an adding operation on the received first preset value k first data to be added and the second data to be added to obtain the sum result, and select the sum result to obtain the first data to be output P out , wherein the addition module is used to receive a first preset value k of the first data to be added and the second data to be added to perform an addition operation to obtain a sum result; the plus-one selector is used to process the sum result under the control of the third control quantity S1 to obtain the first data to be output P out .

[0093] Furthermore, the adding unit is controlled to process the sum result according to the third control amount S1. When the third control amount S1 is 0, 0 is added to the sum result. When the third control amount S1 is 1, 1 is added to the sum result.

[0094] In one implementation, the addition module in the configurable Montgomery modular multiplier provided in the embodiment of the present application includes k-1 three-input and two-output CSAs (Carry Save Adders) and a ripple carry adder. Figure 3 , when k = 5, the addition module includes four CSA adders and one ripple carry adder. Figure 3 As shown, in this embodiment, a tree structure is used to place CSA. The critical path of CSA is consistent with that of full adder. The number of input and output ports can be used to calculate the minimum number of addition modules that can be included in the addition module. A full adder and a ripple-carry adder.

[0095] The first output unit is used to transmit the received first data to be output to the input storage unit, or to the second output selection unit and the output shift unit.

[0096] Exemplary, combined Figure 2As shown, the first output unit is controlled to select data according to the second control amount S0. When the second control amount S0 is 0, the first output unit transmits the first data to be output to the input storage unit. When the second control amount S0 is 1, the first output unit transmits the output data of the adding unit to the output shift unit and the second output unit at the same time. It is worth noting that when the first output unit transmits the first data to be output to the input storage unit, the first data to be output is the third input data M+Y. In the embodiment of the present application, the output shift unit is a shift register. It is worth noting that the first output unit in the embodiment of the present application is a first output selector.

[0097] The output shift unit is used to receive the first data to be output P out The first preset value is shifted right by a number of digits to obtain iterative data, and the iterative data is transmitted to the iterative input selector and the second output selector.

[0098] Exemplary, combined Figure 2 As shown, the first preset value is k, and the iteration data is P i .

[0099] The cycle control unit is used to receive fourth input data, fifth input data and iterative data, and perform a first operation on the fourth input data, fifth input data and iterative data in each counting cycle to obtain a first preset value of two-digit binary numbers, and transmit the two-digit binary numbers to the corresponding processing units respectively, and control the output of the processing unit, iterative input unit, addition unit and first output unit in each counting cycle through the counting value.

[0100] Exemplarily, the cycle control unit is used to count the fourth input data Y, the fifth input data X and the iteration data P in each counting cycle. i Performing a first operation process includes:

[0101] Step 101: the fourth input data Y, the fifth input data X and the iteration data P of the current counting cycle are counted. i The lower preset digit is taken for calculation to obtain intermediate data. The value of the lower preset digit is equal to the first preset value k. The calculation is as follows:

[0102] q=(P(k-1:0)+X(k-1:0)×Y(k-1:0))mod2 k

[0103] Among them, q represents the intermediate data, P(k-1:0) represents the iterative data P i0 to k-1 bits, X(k-1:0) represents 0 to k-1 bits of the fifth input data, Y(k-1:0) represents 0 to k-1 bits of the fourth input data, the intermediate data q is represented by a binary number, k is a first preset value, and mod is a remainder operation symbol.

[0104] Step 102, combining the first preset bit of the fifth input data and the first preset bit of the intermediate data into two binary numbers, the first preset bit being any one bit from 0 to k-1 bits in the intermediate data, and transmitting the two binary numbers to their corresponding processing units respectively.

[0105] Step 103, right-shift the fifth input data by a first preset value to obtain the fifth input data for the first operation processing in the next counting cycle.

[0106] Further, according to the Montgomery algorithm of the embodiment of the present application, the cycle control unit executes q=(P(k-1:0)+X(k-1:0)×Y(k-1:0))mod2 in the algorithm. k Sum X = X / 2 k The operations and related processing of the two steps are worth noting that the operations of the two steps are performed in the time sequence of the Montgomery algorithm of the embodiment of the present application.

[0107] At the same time, combined Figure 2 As shown, the two-bit binary number formed by the first preset bit of the fifth input data and the first preset bit of the intermediate data is represented as {X[0], q[0]}, {X[1], q[1]}, ... {X[k-1], q[k-1]}, which are transmitted to the corresponding processing units as the second selected data.

[0108] The cycle control unit controls the outputs of the processing unit, the iterative input unit, the adding unit and the first output unit in each counting cycle through the counting value, and specifically controls the values ​​of the first control quantity, the second control quantity and the third control quantity through the counting value, thereby controlling the outputs of the processing unit, the iterative input unit, the adding unit and the first unit.

[0109] Exemplarily, the count value count starts counting from 0 and increases by 1 in each counting cycle until it reaches a second preset value, wherein when the count value count is 0, the second control amount S0 is 0, otherwise, the second control amount S0 is 1; when the count value is the second preset value, the third control amount S1 is 1, otherwise, the third control amount is 0, wherein the second preset value is obtained by adding one to the value obtained by dividing the bit width n of the second input data by the first preset value k and rounding it up, and is expressed as The second control amount S0 and the third control amount S1 are logically operated to obtain the first control amount ! S0|| S1.

[0110] The second output unit is used to perform a fourth selection process on the received first data to be output and iterative data to obtain output data.

[0111] Exemplary, combined Figure 2 As shown, the second output unit is used to receive the first to-be-output data P out and iterative data P i Performing a fourth selection process to obtain output data P includes: out The sign bit of the second output unit controls the selection of data. When the sign bit is 0, the second output unit selects the first data to be output P out Output is performed to obtain output data P; when the sign bit is 1, the second output unit selects the iterative data P i Output is performed to obtain output data P. It is worth noting that the second output unit in the embodiment of the present application is a second output selector.

[0112] Based on the above statements, the operation of the Montgomery modular multiplier of the embodiment of the present application requires The specific operation process is as follows:

[0113] The Montgomery modular multiplier of the embodiment of the present application controls the values ​​of the second control amount and the third control amount through the following calculation:

[0114]

[0115] Step 201, when the Montgomery modular multiplier in the embodiment of the present application receives a set signal, that is, it is the first counting cycle of the operation, the count value count is 0, at this time, the second control quantity S0=0, S1=0, at this time, the k first control selectors transmit M to their corresponding data input selectors, the second control selectors in the k processing units all select the first selected data as the first selected data to select the input data received by the data input selector, and transmit the selected second selected data to the addition module, the k first selected data are one 01 and k-1 00 respectively, at the same time, the iterative input selector selects the fourth input data Y to transmit to the addition module, the addition module performs addition processing on the received data to obtain M+Y, the plus-one selector adds 0 to the addition result of the addition module, and transmits the processed result M+Y to the first output selector, the first output selector selects to transmit the first to-be-output data M+Y to the input storage unit as the third input data to participate in the subsequent operation.

[0116] Step 202: After completing the operation of step 201, the count value count starts to count, and increases by 1 each time. Between the 2nd and 3rd cycles, S0=1, S1=0, at this time, the first control selector transmits M to its corresponding data input selector, the second control selectors in the k processing units all select the second selected data {X[i], q[i]}, (i=0, 1, ..., k-1) as the first selected data to be transmitted to the data input selector, select the input data received by the data input selector, and transmit the selected second selected data to the addition module, the iteration input selector selects the iteration data P i The data is transmitted to the addition module, the addition module performs addition processing on the received data, the plus one selector performs addition processing on the addition result of the addition module, and transmits the processed result to the first output selector, and the first output selector selects the first to-be-output data P out At the same time, it is transmitted to the second output selector and the shift register, and the second output selector is transmitted to the second output selector through the first to-be-output data P out The sign bit selects the first data to be output P out Or iterate over data P i It is worth noting that the data received by the addition module is combined with the Montgomery modular multiplication algorithm of the embodiment of the present application, which is actually P and (M×q[i]+Y×X[i])<<i, (i=0,1,…,k-1) output by each processing unit. This step 302 mainly executes the Montgomery modular multiplication algorithm P=(P+X(k-1:0)×Y+q×M) / 2 k The operation process.

[0117] Step 203, when the value of count is That is the cycles, S0=1, S1=1, at this time, the first control selector transmits ~M to its corresponding data input selector, the second control selectors in the k processing units all select the first selected data as the first selected data to select the input data received by the data input selector, and transmit the selected second selected data to the addition module, the k first selected data are respectively one 01 and k-1 00, the iteration input selector selects the iteration data P i The data is transmitted to the addition module, the addition module performs addition processing on the received data, the plus one selector performs addition processing on the addition result of the addition module, and transmits the processed result to the first output selector to obtain P out =P i +~M+1, that is, P out =P i -M, the first output selector selects the first to-be-output data P out At the same time, it is transmitted to the second output selector and the shift register, and the second output selector is transmitted to the second output selector through the first to-be-output data P outThe sign bit selects the output iteration data Or the first data to be output

[0118] The present application discloses a configurable Montgomery modular multiplier, which includes an input storage unit, a first preset number of processing units, an iterative input unit, an adding unit, a first output unit, an output shift unit, a second output unit and a cycle control unit, wherein the first preset number of processing units is used to receive input data and perform shift processing on the input data, and the cycle control unit controls the output of the cycle processing unit, the iterative input unit, the adding unit and the first output unit in each count through a count value. The modular multiplier provided by the present application can change the parameters of its corresponding algorithm by changing the number of processing units, thereby changing the number of operation cycles and the consumed hardware resources, so that the modular multiplier can meet the needs of cryptographic systems with different hardware area, delay and power consumption requirements.

[0119] The present application is described in detail above in conjunction with specific implementation methods and exemplary examples, but these descriptions cannot be understood as limiting the present application. Those skilled in the art understand that, without departing from the spirit and scope of the present application, a variety of equivalent replacements, modifications or improvements can be made to the technical solution of the present application and its implementation methods, all of which fall within the scope of the present application. The scope of protection of the present application shall be subject to the attached claims.

Claims

1. A configurable Montgomery modular multiplier, characterized in that: It includes an input storage unit, a first preset value processing unit, an iterative input unit, an adding unit, a first output unit, an output shift unit, a second output unit and a cycle control unit, wherein: The input storage unit is used to receive and store first input data, second input data, third input data, fourth input data and fifth input data, and to transmit the first input data, the second input data, the third input data and the fourth input data to the processing unit, and to transmit the fourth input data and the fifth input data to the cycle control unit, and to transmit the fourth input data to the iteration input unit, the fifth input data is represented by a binary number, and the second input data is a prime number; The processing unit is used to select and process the received first input data, the second input data, the third input data and the fourth input data to obtain first data to be added, and transmit the first data to be added to the adding unit; The iterative input unit is used to receive the fourth input data of the input storage unit and the iterative data of the output shift unit, and select and process the fourth input data and the iterative data to obtain second data to be added, and transmit the second data to be added to the adding unit; The adding unit is used to perform an adding operation on the received first preset value of the first data to be added and the second data to be added to obtain an addition result, perform selection processing on the addition result to obtain first data to be output, and transmit the first data to be output to the first output unit; The first output unit is used to transmit the received first to-be-output data to the input storage unit, or to the second output unit and the output shift unit; The output shift unit is used for right-shifting the received first to-be-output data by a first preset value of digits to obtain the iterative data, and transmitting the iterative data to the iterative input unit and the second output unit; The cycle control unit is used to receive the fourth input data, the fifth input data and the iteration data, and perform a first operation process on the fourth input data, the fifth input data and the iteration data in each counting cycle to obtain a first preset value of two-bit binary numbers, and transmit the two-bit binary numbers to the corresponding processing units respectively, and control the output of the processing unit, the iteration input unit, the addition unit and the first output unit in each counting cycle through the counting value; The second output unit is used to perform a fourth selection process on the received first data to be output and the iterative data to obtain output data.

2. The Montgomery modular multiplier according to claim 1, characterized in that: The cycle control unit is used to perform a first operation process on the fourth input data, the fifth input data and the iteration data in each counting cycle, including: The fourth input data, the fifth input data and the iteration data of the current counting cycle are subjected to a first operation process by taking a lower preset digit to obtain intermediate data, wherein the value of the lower preset digit is equal to the first preset value, and the operation is performed as follows: q=(P(k-1:0)+X(k-1:0)×Y(k-1:0))mod2 k Wherein, q represents the intermediate data, P(k-1:0) represents bits 0 to k-1 of the iterative data, X(k-1:0) represents bits 0 to k-1 of the fifth input data, Y(k-1:0) represents bits 0 to k-1 of the fourth input data, the intermediate data is represented by a binary number, k is the first preset value, and mod is a modulo operator. Combining the first preset bit of the fifth input data with the first preset bit of the intermediate data into the two-bit binary number, the first preset bit being any one bit from 0 to k-1 bits in the intermediate data, and transmitting the two-bit binary number to the corresponding processing units respectively; The fifth input data is right-shifted by a first preset value number of digits to obtain the fifth input data used for the first operation processing in the next counting cycle.

3. The Montgomery modular multiplier according to claim 2, characterized in that: The processing unit includes a data input selector, a first control selector, a second control selector and a shifter, wherein: The first control selector is used to receive the second input data, and process the second input data under the control of the third control amount to obtain second processed data and transmit it to the data input selector; The second control selector is used to receive the first selected data or the second selected data, and select the first selected data and the second selected data under the control of the first control amount to obtain the first selected data, and transmit the first selected data to the data input selector, wherein the first selected data is one of the first selected data and the second selected data; The data input selector is used to select the first input data, the second processed data, the third input data and the fourth input data according to the first selected data to obtain second selected data, and the data input selector transmits the second selected data to the shifter, wherein the second selected data is one of the first input data, the second processed data, the third input data and the fourth input data; The shifter is used to shift the received second selected data left by a set digit to obtain the first data to be added, and the value of the set digit is equal to a first preset value.

4. The Montgomery modular multiplier according to claim 3, characterized in that: The data input selector is used to select the first input data, the second processed data, the third input data and the fourth input data according to the first selected data, including: If the first selected data is the first selected data, the data input selector selects one data from the first input data and the second processed data and transmits it to the shifter; If the first selected data is the second selected data, the data input selector selects the first input data, the second processed data, the third input data and the fourth input data according to the second selected data, and transmits the selected data to the shifter, and the second selected data is the two-bit binary number.

5. The Montgomery modular multiplier according to claim 4, characterized in that: The first preset value data input selector corresponds to the first preset value first selection data. Among the first preset value first selection data, there is any one of the first selection data being 01, and the other first selection data being 00. The first selection data corresponding to the data input selector is a constant value. When the first selection data is 01, the data input selector selects the second processing data to be transmitted to the shifter. When the first selection data is 00, the data input selector selects the first input data to be transmitted to the shifter.

6. The Montgomery modular multiplier according to claim 3, characterized in that: The adding unit includes an adding module and a plus-one selector, wherein: The adding module is used for receiving a first preset value of the first data to be added and the second data to be added, performing an adding operation on them, and obtaining the addition result; The plus-one selector is used to process the sum result under the control of the third control amount to obtain the first data to be output.

7. The Montgomery modular multiplier according to claim 3, characterized in that: The count value starts from zero and increases by one in each count cycle until it reaches a second preset value, wherein: When the count value is zero, the second control amount is zero, otherwise, the second control amount is one; When the count value is the second preset value, the third control amount is one, otherwise, the third control amount is zero, wherein the second preset value is a value obtained by adding one to the integer of the bit width of the second input data divided by the first preset value; The second control amount and the third control amount are logically operated to obtain the first control amount, and the first control amount is obtained by the following logical operation: !S0||S1, Wherein, S0 represents the second control amount, S1 represents the third control amount, ! represents negation, and || represents an OR logic operation.

8. The Montgomery modular multiplier according to claim 7, characterized in that: Controlling the second control selector to select data according to the first control amount, when the first control amount is zero, the second control selector inputs the first selected data as the first selected data to the data input selector, and when the first control amount is one, the second control selector inputs the second selected data as the second selected data to the data input selector; Controlling the iterative input unit to select data according to the second control amount, when the second control amount is zero, the iterative input unit selects the fourth input data to be transmitted to the adding unit, and when the second control amount is one, the iterative input unit transmits the iterative data to the adding unit; Control the first output unit to select data according to the second control amount, when the second control amount is zero, the first output unit transmits the first data to be output to the input storage unit, when the second control amount is one, the first output unit transmits the first data to be output to the output shift unit and the second output unit at the same time; Controlling the first control selector to process the second input data according to the third control amount, when the third control amount is zero, the first control selector inputs the second input data to the data input selector, and when the third control amount is one, the first control selector inverts the second input data bit by bit and inputs it to the data input selector; The adding unit is controlled to process the sum result according to the third control amount. When the third control amount is zero, zero is added to the sum result. When the third control amount is one, one is added to the sum result.

9. The Montgomery modular multiplier according to claim 7, characterized in that: When the count value is zero, the first output unit transfers the first data to be output to the input storage unit to participate in the subsequent operation process as the third input data.

10. The Montgomery modular multiplier according to claim 1, characterized in that: The second output unit is used to perform a fourth selection process on the received first data to be output and the iterative data to obtain output data, including: Control the second output unit to select data according to the sign bit of the first data to be output, and when the sign bit is zero, the second output unit selects the first data to be output for output to obtain the output data; When the sign bit is one, the second output unit selects the iterative data for output to obtain the output data.

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