Memory controller, memory system, memory control method, and medium

Abstract

The present disclosure relates to the technical field of memory, in particular to a memory controller, a memory system, a memory control method and a medium. The memory controller comprises a gating module and an ECC module. The ECC module comprises at least two ECC sub-modules electrically connected with the gating module. The at least two ECC sub-modules adopt different ECC algorithms. The gating module is configured to gate one of the at least two ECC sub-modules. The ECC sub-module is configured to perform an ECC operation according to a data access command when gated by the gating module. The memory controller, the memory system and the memory control method provided by the present disclosure can dynamically and flexibly adjust the error correction and detection capability and the memory capacity loss, thereby avoiding causing memory waste or failing to meet more stringent data scene requirements. Thus, the purpose of saving memory resources as much as possible under the premise of meeting data reliability is achieved.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, specifically to a memory controller, a memory system, a memory control method, and a medium. Background Technology

[0002] Error checking and correction (ECC) algorithms are widely used in memory to detect errors during data storage and retrieval. The error correction and detection capabilities of ECC algorithms are mutually constrained by memory capacity consumption; stronger error correction and detection capabilities result in greater memory consumption. Therefore, to meet diverse user needs, memory controllers on the market currently employ different ECC algorithms. Once a user selects a memory controller, its error correction and detection capabilities and memory capacity consumption are fixed and cannot be dynamically and flexibly adjusted. Thus, choosing a memory controller with strong error correction and detection capabilities but high memory consumption will lead to memory waste when applied to less demanding data scenarios; conversely, choosing a memory controller with lower memory consumption but weaker error correction and detection capabilities will fail to meet more stringent data scenario requirements. Summary of the Invention

[0003] This section is provided to briefly introduce the concepts, which will be described in detail in the Detailed Description section later. This section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] In a first aspect, this disclosure provides a memory controller, including: a gating module and an ECC module, wherein the ECC module includes at least two types of ECC sub-modules electrically connected to the gating module, and the at least two types of ECC sub-modules employ different ECC algorithms;

[0005] The gating module is used to select one of the at least two ECC submodules;

[0006] The ECC submodule is used to perform ECC operations according to data access commands when selected by the gating module.

[0007] In a second aspect, this disclosure provides a memory system including memory and the memory controller described in the first aspect of this disclosure.

[0008] Thirdly, this disclosure provides a memory control method applied to a memory controller. The memory controller includes a gating module and an ECC module. The ECC module includes at least two ECC sub-modules electrically connected to the gating module, wherein the at least two ECC sub-modules employ different ECC algorithms. The method includes:

[0009] In response to a data access command received by the memory controller, one of the at least two ECC submodules is selected via the gating module;

[0010] The ECC submodule selected by the gating module performs ECC operations according to the data access command.

[0011] Fourthly, this disclosure provides a computer-readable medium having a computer program stored thereon, which, when executed by a processing device, implements the steps of the method described in the third aspect of this disclosure.

[0012] The above technical solution configures a selector and at least two ECC submodules within a single memory controller. When accessing memory, the selector chooses one of the at least two ECC submodules based on the data access command, and then performs the corresponding ECC operation using the ECC algorithm of the selected submodule. Since the at least two ECC submodules employ different ECC algorithms, their error correction and detection capabilities differ, resulting in different memory capacity consumption. Therefore, the memory controller provided in this disclosure can dynamically and flexibly adjust error correction and detection capabilities and memory capacity consumption, avoiding memory waste or failure to meet more stringent data scenario requirements. This achieves the goal of minimizing memory resource consumption while ensuring data reliability.

[0013] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0014] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale. In the drawings:

[0015] Figure 1 This is a block diagram of a memory controller provided according to one embodiment of the present disclosure.

[0016] Figure 2 This is a block diagram of a memory controller provided according to another embodiment of the present disclosure.

[0017] Figure 3 This is a block diagram of a memory system provided according to one embodiment of the present disclosure.

[0018] Figure 4 This is a flowchart of a memory control method provided according to one embodiment of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0020] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0021] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0022] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0023] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0024] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0025] All actions involving the acquisition of signals, information, or data in this disclosure are carried out in accordance with the relevant data protection laws and policies of the country where the location is situated, and with the authorization granted by the owner of the relevant device.

[0026] It is understood that before using the technical solutions disclosed in the various embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0027] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose whether to provide personal information to the software or hardware, such as the electronic device, application, server, or storage medium performing the operations of this disclosed technical solution, based on the prompt message.

[0028] As an optional but non-limiting implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0029] It is understood that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0030] Meanwhile, it is understood that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and related provisions.

[0031] Figure 1 This is a block diagram of a memory controller provided in one embodiment of this disclosure. Figure 1 As shown, the memory controller 100 provided in this disclosure includes a gating module 10 and an ECC module 20. The ECC module 20 includes at least two types of ECC sub-modules electrically connected to the gating module. The at least two types of ECC sub-modules use different ECC algorithms.

[0032] The gating module 10 is used to select one of the at least two ECC submodules.

[0033] The ECC submodule is used to perform ECC operations according to data access commands when selected by the gating module 10.

[0034] The ECC operation includes calculating the ECC checksum of the data, verifying the data based on the ECC checksum, and correcting errors.

[0035] The above technical solution configures a selector and at least two ECC submodules within a single memory controller. When accessing memory, the selector chooses one of the at least two ECC submodules based on the data access command, and then performs the corresponding ECC operation using the ECC algorithm of the selected submodule. Since the at least two ECC submodules employ different ECC algorithms, their error correction and detection capabilities differ, resulting in different memory capacity consumption. Therefore, the memory controller provided in this disclosure can dynamically and flexibly adjust error correction and detection capabilities and memory capacity consumption, avoiding memory waste or failure to meet more stringent data scenario requirements. This achieves the goal of minimizing memory resource consumption while ensuring data reliability.

[0036] Optionally, the ECC module further includes a non-ECC path submodule electrically connected to the gating module.

[0037] The gating module is used to select one of the non-ECC path submodule and the at least two types of ECC submodules.

[0038] The non-ECC path submodule is used to access memory without performing ECC operations when selected by the gating module, according to the data access command.

[0039] The above technical solution involves configuring a selector, a non-ECC path submodule, and at least two types of ECC submodules within a single memory controller. When accessing memory, the selector can not only select one of the at least two ECC submodules to perform the corresponding ECC operation, but also select the non-ECC path submodule to avoid ECC operations, thus maximizing memory capacity savings.

[0040] Optionally, the memory controller further includes an algorithm selection module electrically connected to the gating module.

[0041] The algorithm selection module is used to control the gating module to select one of the various sub-modules in the ECC module based on the memory address corresponding to the data access command and the correspondence between the memory address range and the various sub-modules in the ECC module.

[0042] Specifically, when the algorithm selection module selects one of the at least two ECC submodules, the corresponding ECC operation is performed; when the algorithm selection module selects the non-ECC path submodule, no ECC operation is performed. The correspondence between memory address ranges and various submodules in the ECC module can be flexibly and dynamically set. For example, the address range corresponding to one ECC submodule in the ECC module can be set to 0 to 0x100000, the address range corresponding to the non-ECC path submodule in the ECC module can be set to 0x100000 to 0x200000, and the address range corresponding to another ECC submodule in the ECC module can be set to 0x200000 to 0x300000. The minimum unit for memory region configuration is one memory burst data size. For example, in a 32-bit system, LPDDR5 (low power double data rate 5) has a burst length (BL) of 16, so the minimum unit for memory region configuration is 64 bytes.

[0043] Through the above technical solution, the algorithm selection module can control the gating module to select the sub-module corresponding to the memory address range to which the memory address corresponding to the data access command belongs. Therefore, by configuring the correspondence between memory address ranges and various sub-modules in the ECC module, one of the various sub-modules in the ECC module can be controlled to be selected.

[0044] Optionally, the memory controller further includes a register, which pre-stores configuration information. The configuration information is used to configure the range of memory addresses that data access commands of different service types are allowed to access during the initialization of the memory controller, as well as the correspondence between the memory address range and various sub-modules in the ECC module.

[0045] The above technical solution maps business types to memory address ranges and sub-modules, allowing data of different business types to choose different sub-modules for ECC operations or not for ECC operations. This achieves the goal of minimizing memory resource consumption while ensuring data reliability. For example, business type A has low data reliability requirements, so the memory address range allowed by data access commands for business type A can be configured to correspond to non-ECC path sub-modules; business type B has high data reliability requirements (e.g., image recognition business), so the memory address range allowed by data access commands for business type B can be configured to correspond to one ECC sub-module within the ECC module; business type C has strict data reliability requirements (e.g., financial transaction business), so the memory address range allowed by data access commands for business type C can be configured to correspond to another ECC sub-module within the ECC module. The ECC algorithm used in the ECC sub-module corresponding to business type B has lower memory consumption and weaker error correction and detection capabilities compared to the ECC algorithm used in the ECC sub-module corresponding to business type C. Therefore, through the above technical solution, the memory controller provided in this disclosure can operate on data of different business types simultaneously, and is suitable for a variety of application scenarios.

[0046] In another embodiment, one of the various sub-modules in the ECC module can be selected based on an identifier. Optionally, the memory controller further includes an algorithm selection module electrically connected to the selection module. This algorithm selection module is used to control the selection module to select one of the various sub-modules in the ECC module based on the identifier included in the data access command and the correspondence between the identifier and the various sub-modules in the ECC module. The correspondence between the identifier and the various sub-modules in the ECC module can be flexibly set and is not limited here. In application, an identifier corresponding to the business type (data reliability requirements, etc.) can be added to the data access command, and the selection module can be controlled to select one of the various sub-modules in the ECC module based on the correspondence between the identifier and the various sub-modules in the ECC module. Optionally, the memory controller further includes a register pre-stored with configuration information. This configuration information is used during the initialization of the memory controller to configure different identifiers included in data access commands for different business types, and the correspondence between various identifiers and the various sub-modules in the ECC module. This allows for the selection of different sub-modules to perform ECC operations or not to perform ECC operations based on different business types (such as data reliability requirements). This achieves the goal of minimizing memory resources while ensuring data reliability.

[0047] In another embodiment, one of the various sub-modules in the ECC module can be selected based on the memory lifecycle. That is, optionally, the algorithm selection module is used to control the selection module to select one of the various sub-modules in the ECC module based on the current memory lifecycle stage and the correspondence between each lifecycle stage and the various sub-modules in the ECC module. For example, the first lifecycle stage of the memory can be set to correspond to one type of ECC sub-module in the ECC module. In the early stage of the memory lifecycle, this ECC sub-module uses an ECC algorithm with weaker error detection and correction capabilities and lower memory capacity loss to reduce memory capacity loss and bandwidth impact. Conversely, the second lifecycle stage of the memory lifecycle can be set to correspond to another type of ECC sub-module in the ECC module. In the middle to late stage of the memory lifecycle, this ECC sub-module uses an ECC algorithm with stronger error detection and correction capabilities and higher memory capacity loss to effectively detect the end of the memory lifecycle, thereby ensuring data integrity.

[0048] Optionally, the at least two ECC submodules include an ECC submodule employing the SEC (Single Error Correcting) ECC (Error Checking and Correction) algorithm and an ECC submodule employing the SEC-DED (Single Error Correcting-Double Error Detecting) ECC algorithm. The SEC ECC algorithm has the capability of detecting and correcting errors per unit (bit), and the memory capacity consumption can be 1 / 17 (if every 128 bits of data, an additional 8 bits of ECC checksum storage space are set); the SEC DED algorithm has the capability of detecting and correcting errors per unit (bit) and detecting 2-bit errors, and the memory capacity consumption is 1 / 9 (if every 64 bits of data, an additional 8 bits of ECC checksum storage space are set).

[0049] Optionally, such as Figure 2 As shown, the gating module includes a first gating module 11 and a second gating module 12. Various sub-modules in the ECC module 20 are respectively connected between the first gating module 11 and the second gating module 12. The memory controller 100 also includes: an AXI interface module 40, a command cache module 50, a data transceiver module 60, a command queue module 70, and a DFI module 80. Here, AXI is an abbreviation for Advanced eXtensible Interface, and DFI is an abbreviation for Digital Facility Interface.

[0050] The AXI interface module 40 is electrically connected to both the command cache module 50 and the data transceiver module 60. The command cache module 50 is electrically connected to both the algorithm selection module 30 and the command queue module 70. The data transceiver module 60 is electrically connected to the first gating module 11. The algorithm selection module 30 is electrically connected to the first gating module 11, the second gating module 12, and the command queue module 70. Both the second gating module 12 and the command queue module 70 are electrically connected to the DFI module 80.

[0051] The master device module 200 can be a central processing unit (CPU), direct memory access (DMA), etc. The master device module 200 can send data access commands and data to the AXI interface module 40 of the memory controller 100 via the AXI controller (AXImaster). Data access to memory includes reading and writing data; therefore, data access commands include read commands and write commands. For ease of understanding... Figure 2 The general functions of each module of the memory controller 100 are described below. Assuming that the at least two ECC submodules include a first ECC submodule and a second ECC submodule, the functions are roughly described in four cases: reading data, writing data, performing ECC operations, and not performing ECC operations.

[0052] Reading data and performing ECC operations: The AXI interface module 40 receives read requests from the master device module 200, converts the read requests into read commands in AXI protocol form, and sends the read commands to the command cache module 50. The command cache module 50 forwards the read commands to the algorithm selection module 30 and sends a reminder signal to the command queue module 70 to inform the command queue module 70 that the read command is imminent. The algorithm selection module 30 sends a first read command (or a second read command) to the first gating module 11 and the second gating module 12 according to the memory address 400 accessed by the read command, so as to control the first gating module 11 and the second gating module 12 to select the first ECC submodule (or the second ECC submodule). The algorithm selection module 30 is also used to forward the first read command (or the second read command) to the command queue module 70. The command queue module 70 sends the first read command (or the second read command) to the DFI module 80. The DFI module 80 is used to receive and convert a first read command (or a second read command), forward the converted first read command (or second read command) to the physical layer 300 (PHY), receive data and a first ECC checksum (or a second ECC checksum) returned by the physical layer 300 and stored in memory 400, and send the received data and the first ECC checksum (or the second ECC checksum) to a second selector. The second selector is used to send the received data and the first ECC checksum (or the second ECC checksum) to a first ECC submodule (or a second ECC submodule). The first ECC submodule (or the second ECC submodule) verifies the data according to the first ECC checksum (or the second ECC checksum), corrects the data if an error is found during verification, and sends the verified and corrected (if there is an error) data to the first selector, or sends an access error signal to the first selector if the error correction fails. The first selector is used to send the verified and corrected (if there is an error) data or the access error signal to the data transceiver module 60. The data transceiver module 60 is used to send the verified and corrected (if there is an error) data or access error signal to the master device through the AXI interface module 40.

[0053] Reading data without ECC operation: The AXI interface module 40 receives read requests from the master device module 200, converts the read requests into read commands in AXI protocol form, and sends the read commands to the command cache module 50. The command cache module 50 forwards the read commands to the algorithm selection module 30 and sends a reminder signal to the command queue module 70 to inform the command queue that the read command is imminent. The algorithm selection module 30 sends a third read command to the first gating module 11 and the second gating module 12 based on the memory address 400 accessed by the read command, to control the first gating module 11 and the second gating module 12 to select the non-ECC path submodule. The algorithm selection module 30 also forwards the third read command to the command queue module 70. The command queue module 70 sends the third read command to the DFI module 80. The DFI module 80 is used to receive and convert the third read command, forward the converted third read command to the physical layer 300 (PHY), receive data returned by the physical layer 300 and stored in memory 400, and send the received data to the second selector. The second selector is used to send the received data to the non-ECC path submodule. The non-ECC path submodule is used to send the received data to the data transceiver module 60 through the first selector. The data transceiver module 60 is used to send the received data to the master device through the AXI interface module 40.

[0054] Writing data and performing ECC operations: The AXI interface module 40 receives write requests and write data from the master device module 200, converts the write request into a write command in AXI protocol form and sends it to the command cache module 50, and converts the write data into write data in AXI protocol form and sends it to the data transceiver module 60. The command cache module 50 forwards the write command to the algorithm selection module 30 and sends a reminder signal to the command queue module 70 to inform the command queue module 70 that the read command is about to arrive. The algorithm selection module 30 sends a first write command (or a second write command) to the first gating module 11 and the second gating module 12 according to the memory address 400 accessed by the write command, so as to control the first gating module 11 and the second gating module 12 to select the first ECC submodule (or the second ECC submodule). The algorithm selection module 30 is also used to forward the first write command (or the second write command) to the command queue module 70. The first ECC submodule (or the second ECC submodule) is used to generate a first ECC checksum (or a second ECC checksum) based on the write data and the first write command (or the second write command), and send the write data and the first ECC checksum (or the second ECC checksum) to the second selector. The second selector is used to send the write data and the first ECC checksum (or the second ECC checksum) to the DFI module 80. The command queue module 70 is also used to send the first write command (or the second write command) to the DFI module 80. The DFI module 80 is used to receive and convert the first write command (or the second write command), the write data, and the first ECC checksum (or the second ECC checksum), and forward the converted first write command (or second write command), the write data, and the first ECC checksum (or the second ECC checksum) to the physical layer 300. The physical layer 300 is used to write the write data and the first ECC checksum (or the second ECC checksum) to memory 400 according to the first write command (or the second write command).

[0055] Writing data without ECC operation: The AXI interface module 40 receives write requests and write data from the master device module 200, converts the write request into a write command in AXI protocol form and sends it to the command cache module 50, and converts the write data into write data in AXI protocol form and sends it to the data transceiver module 60. The command cache module 50 forwards the write command to the algorithm selection module 30 and sends a reminder signal to the command queue module 70 to inform the command queue module 70 that the read command is coming soon. The algorithm selection module 30 sends a third write command to the first gating module 11 and the second gating module 12 according to the memory address 400 accessed by the write command, so as to control the first gating module 11 and the second gating module 12 to select the non-ECC path submodule. The algorithm selection module 30 is also used to forward the third write command to the command queue module 70. The non-ECC path submodule sends the write data to the DFI module 80 through the second gating device. The command queue module 70 is also used to send the third write command to the DFI module 80. The DFI module 80 receives and converts the third write command and write data, and forwards the converted third write command and write data to the physical layer 300. The physical layer 300 writes the write data to the memory 400 according to the third write command.

[0056] Based on the above concept, this disclosure also provides a memory system. For example... Figure 3 As shown, the memory system includes memory 400 and the aforementioned memory controller 100.

[0057] The memory may be dual data rate synchronous dynamic random access memory.

[0058] Based on the above concept, this disclosure also provides a memory control method applied to the aforementioned memory controller. The memory controller includes a gating module and an ECC module. The ECC module includes at least two types of ECC sub-modules electrically connected to the gating module, and the at least two types of ECC sub-modules employ different ECC algorithms. Figure 4 A flowchart illustrating a memory control method provided in one embodiment of this disclosure. Figure 4 As shown, the method may include steps 11 and 12.

[0059] In step S11, in response to the data access command received by the memory controller, one of the at least two ECC submodules is selected by the gating module.

[0060] In step S12, the ECC submodule selected by the gating module performs ECC operation according to the data access command.

[0061] The above technical solution configures a selector and at least two ECC submodules within a single memory controller. When accessing memory, the selector chooses one of the at least two ECC submodules based on the data access command, and then performs the corresponding ECC operation using the ECC algorithm of the selected submodule. Since the at least two ECC submodules employ different ECC algorithms, their error correction and detection capabilities differ, resulting in different memory capacity consumption. Therefore, the memory controller provided in this disclosure can dynamically and flexibly adjust error correction and detection capabilities and memory capacity consumption, avoiding memory waste or failure to meet more stringent data scenario requirements. This achieves the goal of minimizing memory resource consumption while ensuring data reliability.

[0062] Optionally, the memory controller further includes a non-ECC path submodule electrically connected to the gating module, and the method further includes:

[0063] In response to a data access command received by the memory controller, the gating module selects one of the non-ECC path submodule and one of the at least two ECC submodules.

[0064] When the non-ECC path submodule is selected, data access to memory is performed through the non-ECC path submodule according to the data access command without performing ECC operations.

[0065] The above technical solution involves configuring a selector, a non-ECC path submodule, and at least two types of ECC submodules within a single memory controller. When accessing memory, the selector can not only select one of the at least two ECC submodules to perform the corresponding ECC operation, but also select the non-ECC path submodule to avoid ECC operations, thus maximizing memory capacity savings.

[0066] Optionally, the memory controller further includes an algorithm selection module electrically connected to the gating module, and the method further includes:

[0067] In response to a data access command received by the memory controller, the algorithm selection module controls the gating module to select one of the various sub-modules in the ECC module based on the memory address corresponding to the data access command and the correspondence between the memory address range and the various sub-modules in the ECC module.

[0068] Through the above technical solution, the algorithm selection module can control the gating module to select the sub-module corresponding to the memory address range to which the memory address corresponding to the data access command belongs. Therefore, by configuring the correspondence between memory address ranges and various sub-modules in the ECC module, one of the various sub-modules in the ECC module can be controlled to be selected.

[0069] Optionally, the memory controller further includes registers, and the method further includes:

[0070] During the initialization of the memory controller, the configuration information pre-stored in the registers is used to configure the range of memory addresses that data access commands of different service types are allowed to access, as well as the correspondence between the memory address ranges and various sub-modules in the ECC module.

[0071] By mapping business types to memory address ranges and sub-modules, the above technical solution allows data of different business types to select different sub-modules for ECC operations or not to perform ECC operations. This achieves the goal of minimizing memory resources while ensuring data reliability. For example, business type A has low data reliability requirements, so the memory address range allowed by data access commands for business type A can be configured to correspond to non-ECC path sub-modules; business type B has high data reliability requirements (e.g., image recognition business), so the memory address range allowed by data access commands for business type B can be configured to correspond to one ECC sub-module within the ECC module; business type C has strict data reliability requirements (e.g., financial transaction business), so the memory address range allowed by data access commands for business type C can be configured to correspond to another ECC sub-module within the ECC module. The ECC algorithm used in the ECC sub-module corresponding to business type B has lower memory consumption and weaker error correction and detection capabilities compared to the ECC algorithm used in the ECC sub-module corresponding to business type C. Therefore, through the above technical solution, the memory controller provided in this disclosure can operate on data of different business types simultaneously, and is suitable for a variety of application scenarios.

[0072] In another embodiment, one of the various sub-modules in the ECC module can be selected based on an identifier. Optionally, the memory controller further includes an algorithm selection module electrically connected to the selection module, and the method further includes: in response to a data access command received by the memory controller, controlling the selection module to select one of the various sub-modules in the ECC module based on the identifier included in the data access command and the correspondence between the identifier and the various sub-modules in the ECC module. The correspondence between the identifier and the various sub-modules in the ECC module can be flexibly set and is not limited here. In application, an identifier corresponding to the business type (data reliability requirements, etc.) can be added to the data access command, and the selection module can be controlled to select one of the various sub-modules in the ECC module based on the correspondence between the identifier and the various sub-modules in the ECC module. Optionally, the memory controller further includes registers, and the method further includes: configuring data access commands for different service types to contain different identifiers during the initialization of the memory controller using configuration information pre-stored in the registers, and establishing the correspondence between various identifiers and various sub-modules in the ECC module. This enables the selection of different sub-modules for ECC operations or the omission of ECC operations based on different service types (data reliability requirements, etc.). Thus, it achieves the goal of minimizing memory resources while ensuring data reliability.

[0073] In another embodiment, one of the various sub-modules in the ECC module can be selected based on the memory lifecycle. Optionally, the memory controller further includes an algorithm selection module electrically connected to the selection module, and the method further includes: controlling the selection module to select one of the various sub-modules in the ECC module based on the current memory lifecycle stage and the correspondence between each lifecycle stage of the memory and the various sub-modules in the ECC module. For example, the first lifecycle stage of the memory can be set to correspond to one type of ECC sub-module in the ECC module, wherein the first lifecycle stage is the early stage of the memory lifecycle, and this ECC sub-module uses an ECC algorithm with weaker error detection and correction capabilities and lower memory capacity loss to reduce memory capacity loss and reduce the impact on bandwidth; the second lifecycle stage of the memory can be set to correspond to another type of ECC sub-module in the ECC module, wherein the second lifecycle stage is the middle to late stage of the memory lifecycle, and this ECC sub-module uses an ECC algorithm with stronger error detection and correction capabilities and higher memory capacity loss to effectively detect the end of the memory lifecycle, thereby ensuring data integrity.

[0074] Optionally, the at least two ECC submodules include an ECC submodule employing the SEC ECC algorithm and an ECC submodule employing the SEC-DED ECC algorithm. Then step S12 includes: performing ECC operations using either the SEC ECC algorithm or the SEC-DED ECC algorithm according to the data access command through the ECC submodule selected by the gating module.

[0075] Optionally, refer again Figure 2 The gating module includes a first gating module 11 and a second gating module 12. Various sub-modules in the ECC module 20 are respectively connected between the first gating module 11 and the second gating module 12. The memory controller 100 also includes an AXI interface module 40, a command cache module 50, a data transceiver module 60, a command queue module 70, and a DFI module 80. The AXI interface module 40 is electrically connected to the command cache module 50 and the data transceiver module 60. The command cache module 50 is electrically connected to the algorithm selection module 30 and the command queue module 70. The data transceiver module 60 is electrically connected to the first gating module 11. The algorithm selection module 30 is electrically connected to the first gating module 11, the second gating module 12, and the command queue module 70. The second gating module 12 and the command queue module 70 are both electrically connected to the DFI module 80.

[0076] Based on the foregoing description, when the data access command is used to read data, the method further includes:

[0077] The AXI interface module 40 receives read requests from the master device module 200, converts the read requests into data access commands in the form of the AXI protocol, and sends the data access commands to the command cache module 50.

[0078] The command caching module 50 forwards the data access command to the algorithm selection module 30 and sends a reminder signal to the command queue module 70 to inform the command queue module 70 that the data access command is coming soon.

[0079] The data access command is forwarded to the command queue module 70 through the algorithm selection module 30.

[0080] The command queue module 70 forwards the data access command to the DFI module 80.

[0081] The DFI module 80 receives and converts the data access command, sends the converted data access command to the physical layer 300, receives the execution result of the data access command returned by the physical layer 300, and sends the execution result to the second gate, wherein the execution result includes data obtained according to the data access command, or includes data obtained according to the data access command and ECC check value.

[0082] The received execution result is sent to the selected submodule in ECC module 20 through the second gate;

[0083] The first selector receives the processing result of the selected sub-module and sends it to the data transceiver module 60. The processing result includes the data, or includes the result after performing an ECC operation on the data according to the ECC check value.

[0084] The data transceiver module 60 sends the received processing results to the main device via the AXI interface module 40.

[0085] Based on the foregoing description, when the data access command is used to write data, the method further includes:

[0086] The AXI interface module 40 receives write requests and write data from the master device module 200, converts the write requests into data access commands in AXI protocol form and sends them to the command cache module 50, and converts the write data into write data in AXI protocol form and sends it to the data transceiver module 60.

[0087] The command caching module 50 forwards the data access command to the algorithm selection module 30 and sends a reminder signal to the command queue module 70 to inform the command queue module 70 that the data access command is about to arrive.

[0088] The data access command is forwarded to the command queue module 70 through the algorithm selection module 30.

[0089] The write data is sent to the first gating module 11 via the data transceiver module 60;

[0090] The second selector receives the processing result of the sub-module in the selected ECC module 20 and sends the processing result to the DFI module 80. The processing result includes the data, or includes the result of the selected ECC sub-module performing ECC operation on the data.

[0091] The command queue module 70 forwards the data access command to the DFI module 80.

[0092] The DFI module 80 receives and converts the data access commands and processing results, and forwards the converted data access commands and processing results to the physical layer 300.

[0093] Regarding the methods in the above embodiments, the specific manner in which each step is performed has been described in detail in the embodiments concerning the relevant module / submodule, and will not be elaborated upon here.

[0094] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0095] The aforementioned computer-readable medium may be included in the aforementioned memory controller; or it may exist independently and not assembled into the memory controller.

[0096] The aforementioned computer-readable medium carries one or more programs, which, when executed by a memory controller, cause the memory controller to: in response to a received data access command, select one of the at least two ECC submodules via the gating module; and perform ECC operations according to the data access command via the ECC submodule selected by the gating module.

[0097] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0099] The modules described in the embodiments of this disclosure can be implemented in software or in hardware. The name of a module does not necessarily limit the module itself; for example, an ECC submodule can also be described as "a module that performs ECC operations using the ECC algorithm".

[0100] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0101] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0102] According to one or more embodiments of this disclosure, Example 1 provides a memory controller, including: a gating module and an ECC module, the ECC module including at least two ECC sub-modules electrically connected to the gating module, the at least two ECC sub-modules employing different ECC algorithms;

[0103] The gating module is used to select one of the at least two ECC submodules;

[0104] The ECC submodule is used to perform ECC operations according to data access commands when selected by the gating module.

[0105] According to one or more embodiments of this disclosure, Example 2 provides the memory controller of Example 1, wherein the ECC module further includes: a non-ECC path submodule electrically connected to the gating module;

[0106] The gating module is used to select one of the non-ECC path submodule and the at least two types of ECC submodules.

[0107] The non-ECC path submodule is used to access memory without performing ECC operations when selected by the gating module, according to the data access command.

[0108] According to one or more embodiments of this disclosure, Example 3 provides a memory controller of Example 1 or Example 2, the memory controller further comprising an algorithm selection module electrically connected to the gating module;

[0109] The algorithm selection module is used to control the gating module to select one of the various sub-modules in the ECC module based on the memory address corresponding to the data access command and the correspondence between the memory address range and the various sub-modules in the ECC module.

[0110] According to one or more embodiments of this disclosure, Example 4 provides a memory controller of Example 3, the memory controller further including a register, the register pre-stores configuration information, the configuration information being used to configure, during the initialization of the memory controller, the range of memory addresses allowed to be accessed by data access commands of different service types, and the correspondence between the memory address range and various sub-modules in the ECC module.

[0111] According to one or more embodiments of this disclosure, Example 5 provides a memory controller of Example 1 or Example 2, the memory controller further comprising an algorithm selection module electrically connected to the gating module, the algorithm selection module being configured to control the gating module to select one of the various sub-modules in the ECC module based on the identifier included in the data access command and the correspondence between the identifier and various sub-modules in the ECC module.

[0112] According to one or more embodiments of this disclosure, Example 6 provides a memory controller similar to that of Example 5. The memory controller further includes registers pre-stored with configuration information. This configuration information is used during the initialization of the memory controller to configure data access commands for different service types to include different identifiers, and to establish the correspondence between these identifiers and various sub-modules within the ECC module.

[0113] According to one or more embodiments of this disclosure, Example 7 provides a memory controller of Example 1, the memory controller further comprising an algorithm selection module electrically connected to the gating module, the algorithm selection module being configured to control the gating module to select one of the various sub-modules in the ECC module based on the current life stage of the memory and the correspondence between each life stage of the memory life cycle and the various sub-modules in the ECC module.

[0114] According to one or more embodiments of this disclosure, Example 8 provides a memory controller of Example 3, wherein the at least two ECC submodules include an ECC submodule employing the SEC ECC algorithm and an ECC submodule employing the SEC-DED ECC algorithm.

[0115] According to one or more embodiments of this disclosure, Example 9 provides a memory controller of Example 3, wherein the gating module includes a first gating module and a second gating module, and various sub-modules in the ECC module are respectively connected between the first gating module and the second gating module. The memory controller further includes: an AXI interface module, a command cache module, a data transceiver module, a command queue module, and a DFI module.

[0116] The AXI interface module is electrically connected to both the command cache module and the data transceiver module. The command cache module is electrically connected to both the algorithm selection module and the command queue module. The data transceiver module is electrically connected to the first gating module. The algorithm selection module is electrically connected to the first gating module, the second gating module, and the command queue module. The second gating module and the command queue module are both electrically connected to the DFI module.

[0117] According to one or more embodiments of this disclosure, Example 10 provides a memory system including: memory and a memory controller as described in any one of Examples 1 to 9.

[0118] According to one or more embodiments of this disclosure, Example 11 provides a memory control method for a memory controller, the memory controller including a gating module and an ECC module, the ECC module including at least two ECC sub-modules electrically connected to the gating module, the at least two ECC sub-modules employing different ECC algorithms, the method comprising:

[0119] In response to a data access command received by the memory controller, one of the at least two ECC submodules is selected via the gating module;

[0120] The ECC submodule selected by the gating module performs ECC operations according to the data access command.

[0121] According to one or more embodiments of this disclosure, Example 12 provides the memory control method described in Example 11, wherein the memory controller further includes a non-ECC path submodule electrically connected to the gating module, and the method further includes:

[0122] In response to a data access command received by the memory controller, the gating module selects the non-ECC path submodule and one of the at least two ECC submodules.

[0123] When the non-ECC path submodule is selected, data access to memory is performed through the non-ECC path submodule according to the data access command without performing ECC operations.

[0124] According to one or more embodiments of this disclosure, Example 13 provides a memory control method as described in Example 11 or Example 12, wherein the memory controller further includes an algorithm selection module electrically connected to the gating module, and the method further includes:

[0125] In response to a data access command received by the memory controller, the algorithm selection module controls the gating module to select one of the various sub-modules in the ECC module based on the memory address corresponding to the data access command and the correspondence between the memory address range and the various sub-modules in the ECC module.

[0126] According to one or more embodiments of this disclosure, Example 14 provides the memory control method described in Example 13, wherein the memory controller further includes a register, and the method further includes:

[0127] During the initialization of the memory controller, the configuration information pre-stored in the registers is used to configure the range of memory addresses that data access commands of different service types are allowed to access, as well as the correspondence between the memory address ranges and various sub-modules in the ECC module.

[0128] According to one or more embodiments of this disclosure, Example 15 provides a memory control method as described in Example 11 or Example 12, wherein the memory controller further includes an algorithm selection module electrically connected to the gating module, and the method further includes:

[0129] In response to a data access command received by the memory controller, the algorithm selection module controls the gating module to select one of the various sub-modules in the ECC module based on the identifier included in the data access command and the correspondence between the identifier and various sub-modules in the ECC module.

[0130] According to one or more embodiments of this disclosure, Example 16 provides the memory control method described in Example 15, wherein the memory controller further includes a register, and the method further includes:

[0131] During the initialization of the memory controller, the configuration information pre-stored in the registers is used to configure data access commands for different service types, which contain different identifiers. The correspondence between these identifiers and various sub-modules in the ECC module is also specified.

[0132] According to one or more embodiments of this disclosure, Example 17 provides the memory control method described in Example 11, wherein the memory controller further includes an algorithm selection module electrically connected to the gating module, and the method further includes: controlling the gating module to select one of the various sub-modules in the ECC module based on the current life stage of the memory and the correspondence between each life stage of the memory life cycle and various sub-modules in the ECC module.

[0133] According to one or more embodiments of this disclosure, Example 18 provides the memory control method described in Example 11 or Example 12, wherein the at least two ECC submodules include an ECC submodule employing the SEC ECC algorithm and an ECC submodule employing the SEC-DED ECC algorithm; performing ECC operation by the ECC submodule selected by the gating module according to the data access command includes: performing ECC operation by the ECC submodule selected by the gating module according to the data access command using the SEC ECC algorithm or the SEC-DED ECC algorithm.

[0134] According to one or more embodiments of this disclosure, Example 19 provides a memory control method as described in Example 11 or Example 12, wherein the gating module includes a first gating module and a second gating module, and various sub-modules in the ECC module are respectively connected between the first gating module and the second gating module. The memory controller further includes: an AXI interface module, a command cache module, a data transceiver module, a command queue module, and a DFI module. The AXI interface module is electrically connected to both the command cache module and the data transceiver module; the command cache module is electrically connected to both the algorithm selection module and the command queue module; the data transceiver module is electrically connected to the first gating module; the algorithm selection module is electrically connected to the first gating module, the second gating module, and the command queue module; and both the second gating module and the command queue module are electrically connected to the DFI module. The method includes:

[0135] The AXI interface module receives read requests from the master device module, converts the read requests into data access commands in AXI protocol form, and sends the data access commands to the command cache module.

[0136] The command caching module forwards the data access command to the algorithm selection module and sends a reminder signal to the command queue module to inform the command queue module that the data access command is about to arrive.

[0137] The data access command is forwarded to the command queue module through the algorithm selection module;

[0138] The command queue module forwards the data access command to the DFI module.

[0139] The DFI module receives and converts the data access command, sends the converted data access command to the physical layer, receives the execution result of the data access command returned by the physical layer, and sends the execution result to the second gate, wherein the execution result includes data obtained according to the data access command, or includes data obtained according to the data access command and ECC check value;

[0140] The received execution result is sent to the selected sub-module in the ECC module through the second gate;

[0141] The first selector receives the processing result of the selected sub-module and sends it to the data transceiver module. The processing result includes the data, or includes the result after performing an ECC operation on the data according to the ECC check value.

[0142] The data transceiver module sends the received processing results to the main device via the AXI interface module.

[0143] According to one or more embodiments of this disclosure, Example 20 provides a memory control method as described in Example 11 or Example 12, wherein the gating module includes a first gating module and a second gating module, and various sub-modules in the ECC module are respectively connected between the first gating module and the second gating module. The memory controller further includes: an AXI interface module, a command cache module, a data transceiver module, a command queue module, and a DFI module. The AXI interface module is electrically connected to both the command cache module and the data transceiver module; the command cache module is electrically connected to both the algorithm selection module and the command queue module; the data transceiver module is electrically connected to the first gating module; the algorithm selection module is electrically connected to the first gating module, the second gating module, and the command queue module; and both the second gating module and the command queue module are electrically connected to the DFI module. The method includes:

[0144] The AXI interface module receives write requests and write data from the master device module, converts the write requests into data access commands in AXI protocol format and sends them to the command cache module, and converts the write data into write data in AXI protocol format and sends it to the data transceiver module.

[0145] The command caching module forwards the data access command to the algorithm selection module and sends a reminder signal to the command queue module to inform the command queue module that the data access command is about to arrive.

[0146] The data access command is forwarded to the command queue module through the algorithm selection module;

[0147] The write data is sent to the first gating module through the data transceiver module;

[0148] The second selector receives the processing result of the sub-module in the selected ECC module and sends the processing result to the DFI module. The processing result includes the data, or includes the result of the selected ECC sub-module performing ECC operation on the data.

[0149] The command queue module forwards the data access command to the DFI module.

[0150] The DFI module receives and converts the data access commands and processing results, and forwards the converted data access commands and processing results to the physical layer.

[0151] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0152] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0153] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative forms of implementing the claims. Regarding the apparatus in the above embodiments, the specific manner in which the various modules perform their operations has been described in detail in the embodiments relating to the method, and will not be elaborated upon here.

Claims

1. A memory controller, characterized in that, include: The system includes a gating module, an ECC module, and an algorithm selection module electrically connected to the gating module. The ECC module includes a non-ECC path submodule electrically connected to the gating module, and at least two ECC submodules electrically connected to the gating module, wherein the at least two ECC submodules employ different ECC algorithms. The gating module includes a first gating module and a second gating module, and various sub-modules in the ECC module are respectively connected between the first gating module and the second gating module; the gating module is used to select the non-ECC path sub-module and one of the at least two types of ECC sub-modules; The algorithm selection module is used to control the gating module to select the non-ECC path submodule and one of the at least two ECC submodules based on the identifier included in the data access command and the correspondence between the identifier and various submodules in the ECC module; or, based on the current memory lifecycle stage and the correspondence between each lifecycle stage of the memory and various submodules in the ECC module, control the gating module to select the non-ECC path submodule and one of the at least two ECC submodules. The algorithm selection module is also used to send the same data access command to the first gating module and the second gating module to control the first gating module and the second gating module to select the same non-ECC path submodule and the at least two ECC submodules. The data access command includes read commands and write commands. The ECC submodule is used to perform ECC operations according to data access commands when selected by the gating module. The non-ECC path submodule is used to access memory without performing ECC operations when selected by the gating module, according to the data access command.

2. The memory controller according to claim 1, wherein the memory controller further includes a register, the register pre-stores configuration information, the configuration information being used to configure data access commands for different service types to include different identifiers, and the correspondence between various identifiers and various sub-modules in the ECC module during the initialization of the memory controller.

3. The memory controller according to claim 1, characterized in that, The at least two types of ECC submodules include an ECC submodule using the SEC ECC algorithm and an ECC submodule using the SEC-DED ECC algorithm.

4. The memory controller according to claim 1, characterized in that, The memory controller also includes: an AXI interface module, a command cache module, a data transceiver module, a command queue module, and a DFI module; The AXI interface module is electrically connected to both the command cache module and the data transceiver module. The command cache module is electrically connected to both the algorithm selection module and the command queue module. The data transceiver module is electrically connected to the first gating module. The algorithm selection module is electrically connected to the first gating module, the second gating module, and the command queue module. The second gating module and the command queue module are both electrically connected to the DFI module.

5. A memory system, characterized in that, Includes memory and a memory controller as described in any one of claims 1-4.

6. A memory control method, applied to a memory controller, characterized in that, The memory controller includes a gating module, an ECC module, and an algorithm selection module electrically connected to the gating module. The ECC module includes a non-ECC path submodule electrically connected to the gating module, and at least two ECC submodules electrically connected to the gating module, wherein the at least two ECC submodules employ different ECC algorithms. The gating module includes a first gating module and a second gating module, and each submodule in the ECC module is connected between the first gating module and the second gating module. The method includes: In response to a data access command received by the memory controller, the algorithm selection module controls the gating module to select the non-ECC path submodule and one of the at least two ECC submodules based on the identifier included in the data access command and the correspondence between the identifier and various submodules in the ECC module. Alternatively, the algorithm selection module controls the gating module to select the non-ECC path submodule and one of the at least two ECC submodules based on the current memory lifecycle stage and the correspondence between each lifecycle stage of the memory and various submodules in the ECC module. Specifically, sending the same data access command to both the first gating module and the second gating module controls both gating modules to select the same non-ECC path submodule and the same at least two ECC submodules. The data access command includes read and write commands. The gating module selects the non-ECC path submodule and one of the at least two ECC submodules. The ECC submodule selected by the gating module performs ECC operations according to the data access command; When the non-ECC path submodule is selected, data access to memory is performed through the non-ECC path submodule according to the data access command without performing ECC operations.

7. The memory control method according to claim 6, characterized in that, The memory controller further includes registers, and the method further includes: During the initialization of the memory controller, the configuration information pre-stored in the registers configures data access commands for different service types, which include different identifiers, as well as the correspondence between various identifiers and various sub-modules in the ECC module.

8. A computer-readable medium having a computer program stored thereon, characterized in that, When the program is executed by the processing device, it implements the steps of the method described in claim 6 or 7.

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