A circuit routing determination method and related device

Abstract

A circuit routing determination method, relating to the field of circuit layout, includes: acquiring information describing ports and pins; determining multiple candidate connection paths based on the port and pin information; obtaining the cost value of each candidate connection path using a machine learning model, whereby the cost value indicates the impact of the candidate connection path on the total number of connection paths between the multiple ports and multiple pins; and determining at least one target connection path from the multiple candidate connection paths based on the cost value. This application effectively evaluates the cost value of candidate connection paths using a machine learning model and determines the preferred target connection path based on the cost value, thereby increasing the overall number of connections between ports and pins in the circuit.

Description

Technical Field

[0001] This application relates to the field of circuit layout, and in particular to a method for determining circuit routing and related equipment. Background Technology

[0002] Matching the routing between ports and pins in a circuit, such as the matching routing between input / output (I / O) units and bumps, is one of the important processes in chip design. It is characterized by being time-consuming, difficult to check, and having a large number of requirements. It usually requires the manual experience of chip designers to troubleshoot, and the corresponding pin matching routing is manually adjusted through interactive software. Furthermore, it is necessary to maximize the actual number of connections between I / O units and bumps while meeting the constraints of multiple pin priority types.

[0003] Currently, the industry commonly uses rule-based analytical methods under constraints to handle the problem of automatic matching of chip pins and routing, which realizes automatic routing function based on chip pin type and predefined routing rules.

[0004] However, analytical methods based on rule-based constraints have poor generalization, complex and coupled routing rules, high computational complexity, and are prone to getting trapped in local extrema, resulting in poor overall performance of circuit routing. Summary of the Invention

[0005] This application provides a circuit routing determination method that can increase the number of connections when matching routing between ports and pins.

[0006] Firstly, this application provides a circuit routing determination method, comprising: acquiring information describing ports and pins; determining multiple candidate connection paths based on the port and pin information; obtaining the cost value of each candidate connection path using a machine learning model, wherein the cost value indicates the impact of the candidate connection path on the total number of connection paths between the multiple ports and multiple pins; and determining at least one target connection path from the multiple candidate connection paths based on the cost value. This application effectively evaluates the cost value of candidate connection paths through a machine learning model and determines the preferred target connection path based on the cost value, thereby increasing the overall number of connections between ports and pins of the chip.

[0007] In scenarios involving matching port and pin routing, it is necessary to maximize the number of connections between ports and pins to improve chip performance. In this embodiment, to increase the number of connections between ports and pins, the impact of each candidate connection path on the total number of connection paths between multiple ports and multiple pins (i.e., the cost value in this embodiment) can be calculated, and the connection path between ports and pins can be selected based on the cost value.

[0008] It should be understood that the implementation of "based on the first information and the second information" here can be: inputting the first information and the second information themselves into the machine learning model, or inputting the result obtained by processing or filtering the first information and the second information into the machine learning model. For example, the first information of the ports included in each candidate connection path and the second information of the pins included (optionally, the position information of other points in the candidate connection path) can be input into the machine learning model.

[0009] It should be understood that the cost value is used to indicate the impact of candidate connection paths on the total number of connection paths between multiple ports and pins. Since the final determined connection paths between ports and pins are non-intersecting (e.g., they can be considered intersecting if a common relay point exists), the determination of each connection path will have a certain impact on the selection of connection paths between other ports and pins (connection paths with overlapping paths cannot be selected). This "impact" can be understood as: whether adopting the candidate connection path as the connection path between a port and a pin will have a positive or negative impact on the total number of connection paths between multiple ports and pins. Taking a negative impact as an example, the cost value can represent: the degree to which adopting the candidate connection path as the connection path between a port and a pin will reduce the total number of connection paths between multiple ports and pins.

[0010] It should be understood that machine learning models can output multiple values, each corresponding to a candidate connection path. The magnitude of the value can characterize the positive or negative impact that adopting the corresponding candidate connection path will have on the total number of connection paths between the final port and pin. In this case, for example, if there are M candidate connection paths between pin A and port A, and the cost of candidate connection path A among the M candidate connection paths is 0.8 and the cost of candidate connection path B is 0.2, if candidate connection path A is selected from the M candidate connection paths as the connection path between pin A and port A, the final total number of connection paths between the multiple ports and the multiple pins will be A. If candidate connection path B is selected from the M candidate connection paths as the connection path between pin A and port A, the final total number of connection paths between the multiple ports and the multiple pins will be B. The number A will be less than the number B.

[0011] It should be understood that the reason why the machine learning model can output the cost value of each candidate connection path, and the cost value also has the above meaning (indicating the influence of the candidate connection path on the total number of connection paths between the plurality of ports and the plurality of pins), is because of the ability given to the machine learning model during the training process.

[0012] In one possible implementation, the port is an input / output I / O unit, and the pin is a transition unit bump.

[0013] In one possible implementation, the method further includes: determining at least one target connection path from a plurality of candidate connection paths based on a substitution value; or sending a substitution value to a terminal device, the substitution value being used to instruct the terminal device to determine at least one target connection path from a plurality of candidate connection paths.

[0014] In one possible implementation, the first information may include one or more of the port's location characteristics, functional characteristics, or priority characteristics. The second information may be one or more of the pin's location characteristics, functional characteristics, or priority characteristics.

[0015] In one possible implementation, positional features can be represented as the coordinate positions of circuit elements (such as ports and pins). For example, positional features can be coordinate positions on a 2D plane, or more specifically, XY coordinates in a Cartesian coordinate system. Positional features can represent the spatial arrangement of circuit elements. When matching and routing circuit elements, using the positional features of each element as input to the model can ensure that the routing path does not overlap with other elements, thereby obtaining accurate routing matching results.

[0016] In one possible implementation, functional characteristics can represent the functions performed by circuit elements. For example, functions may include signal transmission, energy transmission, and grounding. When matching and routing circuit elements, using the functional characteristics of each element as input to the model allows us to ensure that the two ends of the trace are elements with the same function, thus obtaining accurate trace matching results.

[0017] In one possible implementation, the priority feature can represent the importance of a circuit element, which can describe the circuit element's requirement for a certain number of connections. The higher the priority, the higher the importance of the circuit element, and the higher the requirement for a certain number of connections.

[0018] In one possible implementation, circuit elements with different functions can have different priorities, or they can have the same priority, or they can have different priorities. When matching and routing circuit elements, the priority characteristics of each element are input, and these characteristics can be used to maximize the number of matching traces for high-priority elements.

[0019] In one possible implementation, priority can be determined based on the function of the circuit element, or it can be specified based on the attribute information (e.g., first information or second information) input to the circuit element.

[0020] In one possible implementation, the information based on the first information and the second information includes: information based on candidate connection paths; the candidate connection path includes ports and pins at both ends, and at least one relay point traversed by the candidate connection path, wherein the relay point is an intermediate position point between adjacent pins; the information of each candidate connection path includes: first information of the ports included in the candidate connection path, second information of the pins included in the candidate connection path, and position information of at least one relay point.

[0021] The information for multiple candidate connection paths can include information about each candidate connection path. Since each candidate connection path can consist of a starting point, at least one relay point, and an ending point, the information for each candidate connection path can include information about the starting point, the location information of at least one relay point, and the information about the ending point. The starting point can be a port, and its information can include first information about the port (e.g., port location, function, priority, etc.). The location information of the relay point can include the location of the relay point. The ending point can be a pin, and its information can include second information about the pin (e.g., port location, function, priority, etc.).

[0022] In this embodiment of the application, the path is divided to obtain various relay points. The relay points can serve as the endpoints of various sub-segments on the path. By using the location information of the relay points as model input, the cost value at the granularity of each sub-segment can be obtained, thereby obtaining a more accurate cost value of the path.

[0023] For example, ports, pins, and relay points can be encoded, with each port, pin, and relay point uniquely corresponding to an encoding result. Based on each encoding result, the corresponding circuit unit (e.g., port, pin, or relay point) can be uniquely determined. The sequence of encoding results can characterize candidate connection paths.

[0024] In one possible implementation, the multiple ports include multiple first ports and multiple second ports, and the multiple pins include multiple first pins and multiple second pins. The multiple first ports and multiple first pins are used to implement a first function; the multiple second ports and multiple second pins are used to implement a second function, and the first function and the second function are different; the multiple candidate connection paths include multiple first candidate connection paths formed between the multiple first ports and multiple first pins, and multiple second candidate connection paths formed between the multiple second ports and multiple second pins; based on the first information and the second information, the cost value of each candidate connection path is obtained through a machine learning model, including: based on the information of the multiple first candidate connection paths and the information of the multiple second candidate connection paths, the cost value of each first candidate connection path is obtained through a machine learning model; based on the cost value, at least one target connection path is determined from the multiple candidate connection paths, including: based on the cost value of each first candidate connection path, at least one first target connection path is determined from the multiple first candidate connection paths.

[0025] In one possible implementation, during port and pin matching and routing, the importance of ports and pins with different functions varies. For ports and pins with more critical functions, a greater number of connections are needed to ensure chip performance. For ports and pins with relatively important functions, reducing the number of connections will have a significant impact on chip performance (compared to less important ports and pins). However, for ports and pins with relatively unimportant functions, reducing the number of connections will not have a significant impact on chip performance. In this embodiment, the above importance can be described as priority.

[0026] Due to the existence of multiple priorities, matching and routing ports and pins of each priority level at once would significantly increase the complexity and computational difficulty of the machine learning model, making it difficult to guarantee the accuracy of the routing calculations and failing to obtain satisfactory routing matching results. In this embodiment, routing calculations are performed separately for ports and pins of each priority level, thereby improving the accuracy of the routing calculations.

[0027] In one possible implementation, taking high-priority lines as multiple first candidate connection paths and low-priority lines as multiple second candidate connection paths as an example, at least two of the multiple first candidate connection paths can intersect (or not overlap at all).

[0028] In one possible implementation, each second candidate connection path does not intersect with any of the first candidate connection paths. In another possible implementation, to avoid conflicts with higher-priority routing paths, lines that intersect with higher-priority candidate connection paths from lower-priority sources (i.e., intersecting lines) can be removed. Even if these lines are not removed, they will not be used as the final connection path. Therefore, this embodiment of the application reduces the solution space size by removing lines that intersect with higher-priority candidate connection paths from lower-priority sources, thus reducing computational complexity while maintaining the accuracy of routing calculations.

[0029] In one possible implementation, at least one second candidate connection path may intersect with at least one of the multiple first candidate connection paths. When determining the model input, if low-priority paths that overlap with high-priority lines are not eliminated, the amount of input information can be increased. This means the information input into the model can more comprehensively describe the characteristics of the ports and pins, thus leading to a more accurate value.

[0030] In one possible implementation, at least two of the multiple second candidate connection paths can intersect (or not overlap at all).

[0031] In one possible implementation, the method further includes: outputting a plurality of first initial candidate connection paths formed between a plurality of first ports and a plurality of first pins, and obtaining a plurality of first candidate connection paths based on modification instructions for at least one of the plurality of first initial candidate connection paths.

[0032] In one possible implementation, the method further includes: outputting at least one first target connection path.

[0033] In one possible implementation, the first or second function is one of the following: signal transmission, grounding, or power transmission.

[0034] In one possible implementation, the process of obtaining the cost value of each candidate connection path using a machine learning model based on the first and second information further includes: obtaining the cost value of each second candidate connection path using a machine learning model based on information of at least one first target connection path and information of multiple second candidate connection paths; determining at least one target connection path from the multiple candidate connection paths based on the cost value, further including: determining at least one second target connection path from the multiple second candidate connection paths based on the cost value of each second candidate connection path.

[0035] It should be understood that, based on the information of at least one first target connection path, it can be understood as: inputting the first information of the ports included in at least one first target connection path, the second information of the pins included (optionally, the position information of other points in the candidate connection path) into the machine learning model.

[0036] It should be understood that, based on the information of multiple second candidate connection paths, it can be understood as: inputting the first information of the ports included in at least one second target connection path, the second information of the pins included (optionally, the position information of other points in the candidate connection path) into the machine learning model.

[0037] In one possible implementation, when the cost of each second candidate connection path is obtained through a machine learning model, the other first candidate connection paths among the multiple first candidate connection paths, except for at least one first target connection path, are not used as input to the machine learning model.

[0038] In this embodiment, information of at least one first target connection path and information of multiple second candidate connection paths can be used as input to the machine learning model. Since the other first candidate connection paths among the multiple first candidate connection paths, except for at least one first target connection path, will no longer be used as connection paths between the first port and the first pin, the other first candidate connection paths among the multiple first candidate connection paths, except for at least one first target connection path, can be omitted as input to the machine learning model. This reduces the computational complexity while ensuring the accuracy of the routing determination.

[0039] In one possible implementation, the plurality of candidate connection paths further includes at least one third candidate connection path formed between the plurality of second ports and the plurality of second pins, based on information of at least one first target connection path and information of the plurality of second candidate connection paths, including: based on information of at least one first target connection path, information of the plurality of second candidate connection paths and information of at least one third candidate connection path.

[0040] In one possible implementation, when confirming the second priority connection path, the path that intersects with other first candidate connection paths (at least one third candidate connection path) among the multiple first candidate connection paths other than at least one first target connection path can be used as the input to the model. This can increase the amount of input information, that is, the information input into the model can more comprehensively describe the characteristics of the port and pin, and thus obtain a more accurate value.

[0041] In one possible implementation, the method further includes: outputting a plurality of second initial candidate connection paths formed between a plurality of second ports and a plurality of second pins, and obtaining a plurality of second candidate connection paths based on a modification instruction for at least one of the plurality of second initial candidate connection paths.

[0042] In one possible implementation, the method further includes: outputting at least one second target connection path.

[0043] In one possible implementation, at least two target connection paths in a target connection path do not intersect.

[0044] In one possible implementation, the method further includes: obtaining a modified at least one first target connection path based on modification information of at least one first target connection path; and, based on information of at least one first target connection path and information of a plurality of second candidate connection paths, including: based on information of the modified at least one first target connection path and information of a plurality of second candidate connection paths.

[0045] In one possible implementation, the first information indicates that the priority of the first port is higher than the priority of the second port; or, the second information indicates that the priority of the first pin is higher than the priority of the second pin.

[0046] In one possible implementation, determining at least one target connection path from multiple candidate connection paths based on the cost value includes: determining at least one target connection path from multiple candidate connection paths based on the cost value using a minimum cost maximum flow algorithm.

[0047] Secondly, this application provides a method for determining circuit routing, the method including:

[0048] Acquire first information of multiple input / output ports of the circuit and second information of multiple transition unit pins; the multiple ports include multiple first ports and multiple second ports, and the multiple pins include multiple first pins and multiple second pins; multiple first candidate connection paths are formed between the multiple first ports and multiple first pins, and multiple second candidate connection paths are formed between the multiple second ports and multiple second pins; the first information indicates the positional characteristics of the ports, and the second information indicates the positional characteristics of the pins.

[0049] Based on the first information and the second information indicating that the importance of the first port is higher than that of the second port, at least one first target connection path is determined from the multiple first candidate connection paths according to the information of multiple first candidate connection paths and multiple second candidate connection paths.

[0050] Based on information about at least one first target connection path and information about multiple second candidate connection paths, at least one second target connection path is determined from the multiple second candidate connection paths.

[0051] In one possible implementation, the port is an input / output I / O unit, and the pin is a transition unit bump.

[0052] In one possible implementation, at least two of the multiple first candidate connection paths intersect; or...

[0053] Each second candidate connection path does not intersect with any of the multiple first candidate connection paths; or...

[0054] At least one second candidate connection path intersects with at least one of the plurality of first candidate connection paths; or,

[0055] At least two of the multiple second candidate connection paths intersect.

[0056] In one possible implementation, the method also includes:

[0057] Output multiple first initial candidate connection paths formed between multiple first ports and multiple first pins, and obtain multiple first candidate connection paths based on modification instructions for at least one of the multiple first initial candidate connection paths.

[0058] In one possible implementation, the method also includes:

[0059] Output at least one first target connection path.

[0060] In one possible implementation, the first or second function is one of the following: signal transmission, grounding, or power transmission.

[0061] In one possible implementation, based on information from at least one first target connection path and information from multiple second candidate connection paths, the method includes:

[0062] Based on information from at least one first connection path and information from multiple second candidate connection paths, but not based on other first candidate connection paths among the multiple first candidate connection paths besides at least one first target connection path.

[0063] In one possible implementation, the method also includes:

[0064] Output multiple second initial candidate connection paths formed between multiple second ports and multiple second pins, and obtain multiple second candidate connection paths based on modification instructions for at least one of the multiple second initial candidate connection paths.

[0065] In one possible implementation, the method also includes:

[0066] Output at least one second target connection path.

[0067] In one possible implementation, any two connection paths in at least one first target connection path do not intersect, any two connection paths in at least one second target connection path do not intersect, and each first target connection path does not intersect with any second target connection path in at least one second target connection path.

[0068] In one possible implementation, the method also includes:

[0069] Based on the modification information of at least one first target connection path, the modified at least one first target connection path is obtained;

[0070] Based on information of at least one first target connection path and information of multiple second candidate connection paths, including: based on information of at least one modified first target connection path and information of multiple second candidate connection paths.

[0071] Thirdly, this application provides a circuit routing determination device, the device comprising:

[0072] The acquisition module is used to acquire first information of multiple ports and second information of multiple pins of the circuit; multiple ports and multiple pins include multiple candidate connection paths; the candidate connection paths are the connection paths between ports and pins.

[0073] The cost value determination module is used to obtain the cost value of each candidate connection path through a machine learning model based on the first information and the second information. The cost value indicates the impact of the candidate connection path on the total number of connection paths between multiple ports and multiple pins. The cost value is used to determine at least one target connection path from multiple candidate connection paths.

[0074] This application uses a machine learning model to effectively evaluate the cost value of candidate connection paths, and determines the preferred target connection path based on the cost value, thereby increasing the overall number of connections between ports and pins of the chip.

[0075] In one possible implementation, the port is an input / output I / O unit, and the pin is a transition unit bump.

[0076] In one possible implementation, the device further includes:

[0077] The routing determination module is used to determine at least one target connection path from multiple candidate connection paths based on cost; or...

[0078] The sending module is used to send a value to the terminal device, which instructs the terminal device to determine at least one target connection path from multiple candidate connection paths.

[0079] In one possible implementation, the cost is used to indicate the negative impact of the candidate connection path on the total number of connection paths between multiple ports and multiple pins; the multiple candidate connection paths include multiple sets of candidate connection paths, each set of candidate connection paths corresponding to a pair of ports and pins;

[0080] The routing determination module is specifically used for:

[0081] Based on the cost value, the candidate connection path with the lowest cost value is selected as the target connection path from each group of candidate connection paths.

[0082] In one possible implementation, the first information also indicates at least one of the following: the function of the port or the priority of the port;

[0083] The second information also indicates at least one of the following: the function of the pin or the priority of the pin.

[0084] In one possible implementation, the candidate connection path includes the ports and pins at both ends, and at least one relay point traversed by the candidate connection path, wherein the relay point is the midpoint between adjacent pins.

[0085] The step of basing information on the first information and the second information includes:

[0086] Based on the first information of the ports included in the candidate connection path, the second information of the pins included in the candidate connection path, and the location information of the at least one relay point.

[0087] In one possible implementation, the multiple ports include multiple first ports and multiple second ports, and the multiple pins include multiple first pins and multiple second pins. The multiple first ports and multiple first pins are used to implement a first function; the multiple second ports and multiple second pins are used to implement a second function, and the first function and the second function are different.

[0088] The multiple candidate connection paths include multiple first candidate connection paths formed between multiple first ports and multiple first pins, and multiple second candidate connection paths formed between multiple second ports and multiple second pins;

[0089] The cost value determination module is specifically used to: obtain the cost value of each first candidate connection path through a machine learning model based on the information of multiple first candidate connection paths and multiple second candidate connection paths.

[0090] The routing determination module is specifically used to: determine at least one first target connection path from multiple first candidate connection paths based on the cost value of each first candidate connection path.

[0091] In one possible implementation, at least two of the multiple first candidate connection paths intersect; or...

[0092] Each second candidate connection path does not intersect with any of the multiple first candidate connection paths; or...

[0093] At least one second candidate connection path intersects with at least one of the plurality of first candidate connection paths; or,

[0094] At least two of the multiple second candidate connection paths intersect.

[0095] In one possible implementation, the device further includes:

[0096] The output module is used to output at least one first target connection path.

[0097] In one possible implementation, the output module is also used for:

[0098] Output multiple first initial candidate connection paths between multiple first ports and multiple first pins, and obtain multiple first candidate connection paths based on modification instructions for at least one of the multiple first initial candidate connection paths.

[0099] In one possible implementation, the cost value determination module is further configured to: obtain the cost value of each second candidate connection path through a machine learning model based on information of at least one first target connection path and information of multiple second candidate connection paths.

[0100] The routing determination module is also used to: determine at least one second target connection path from a plurality of second candidate connection paths based on the cost value of each second candidate connection path.

[0101] In one possible implementation, the multiple candidate connection paths further include at least one third candidate connection path formed between multiple second ports and multiple second pins, with the substitution value determination module specifically used for:

[0102] Based on information about at least one first target connection path, multiple second candidate connection paths, and at least one third candidate connection path.

[0103] In one possible implementation, the first or second function is one of the following: signal transmission, grounding, or power transmission.

[0104] In one possible implementation, the output module is also used for:

[0105] Output at least one second target connection path.

[0106] In one possible implementation, at least two target connection paths in a target connection path do not intersect.

[0107] In one possible implementation, the output module is also used for:

[0108] Output multiple second initial candidate connection paths formed between multiple second ports and multiple second pins, and obtain multiple second candidate connection paths based on modification instructions for at least one of the multiple second initial candidate connection paths.

[0109] In one possible implementation, at least two target connection paths in a target connection path do not intersect.

[0110] In one possible implementation, the acquisition module is also used for:

[0111] Based on the modification information of at least one first target connection path, the modified at least one first target connection path is obtained;

[0112] Based on information of at least one first target connection path and information of multiple second candidate connection paths, including: based on information of at least one modified first target connection path and information of multiple second candidate connection paths.

[0113] In one possible implementation, the first information indicates that the priority of the first port is higher than the priority of the second port; or, the second information indicates that the priority of the first pin is higher than the priority of the second pin.

[0114] In one possible implementation, the routing determination module is specifically used for:

[0115] Based on the cost value, at least one target connection path is determined from multiple candidate connection paths using the minimum cost maximum flow algorithm.

[0116] Fourthly, this application provides a circuit routing determination device, the device comprising:

[0117] The acquisition module is used to acquire first information of multiple input / output ports of the circuit and second information of multiple transition unit pins; the multiple ports include multiple first ports and multiple second ports, and the multiple pins include multiple first pins and multiple second pins; multiple first candidate connection paths are formed between the multiple first ports and multiple first pins, and multiple second candidate connection paths are formed between the multiple second ports and multiple second pins;

[0118] The routing determination module is used to determine at least one first target connection path from multiple first candidate connection paths based on information from multiple first candidate connection paths and information from multiple second candidate connection paths, based on information from multiple first candidate connection paths and information from multiple second candidate connection paths.

[0119] Based on information about at least one first target connection path and information about multiple second candidate connection paths, at least one second target connection path is determined from the multiple second candidate connection paths.

[0120] In one possible implementation, the port is an input / output I / O unit, and the pin is a transition unit bump.

[0121] In one possible implementation, at least two of the multiple first candidate connection paths intersect; or...

[0122] Each second candidate connection path does not intersect with any of the multiple first candidate connection paths; or...

[0123] At least one second candidate connection path intersects with at least one of the plurality of first candidate connection paths; or,

[0124] At least two of the multiple second candidate connection paths intersect.

[0125] In one possible implementation, the device further includes:

[0126] The output module is used to output multiple first initial candidate connection paths formed between multiple first ports and multiple first pins, and to obtain multiple first candidate connection paths based on modification instructions for at least one of the multiple first initial candidate connection paths.

[0127] In one possible implementation, the device further includes:

[0128] The output module is used to output at least one first target connection path.

[0129] In one possible implementation, the first or second function is one of the following: signal transmission, grounding, or power transmission.

[0130] In one possible implementation, based on information from at least one first target connection path and information from multiple second candidate connection paths, the method includes:

[0131] Based on information from at least one first connection path and information from multiple second candidate connection paths, but not based on other first candidate connection paths among the multiple first candidate connection paths besides at least one first target connection path.

[0132] In one possible implementation, the output module is also used for:

[0133] Output multiple second initial candidate connection paths formed between multiple second ports and multiple second pins, and obtain multiple second candidate connection paths based on modification instructions for at least one of the multiple second initial candidate connection paths.

[0134] In one possible implementation, the output module is also used for:

[0135] Output at least one second target connection path.

[0136] In one possible implementation, any two connection paths in at least one first target connection path do not intersect, any two connection paths in at least one second target connection path do not intersect, and each first target connection path does not intersect with any second target connection path in at least one second target connection path.

[0137] In one possible implementation, the acquisition module is also used for:

[0138] Based on the modification information of at least one first target connection path, the modified at least one first target connection path is obtained;

[0139] Based on information of at least one first target connection path and information of multiple second candidate connection paths, including: based on information of at least one modified first target connection path and information of multiple second candidate connection paths.

[0140] Fifthly, embodiments of this application provide a circuit routing determination apparatus, which may include a memory, a processor, and a bus system, wherein the memory is used to store a program, and the processor is used to execute the program in the memory to perform the methods described in the first aspect and any optional methods thereunder, or the methods described in the second aspect and any optional methods thereunder.

[0141] Sixthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the first aspect and any optional method thereof, or the second aspect and any optional method thereof.

[0142] In a seventh aspect, embodiments of this application provide a computer program product including instructions that, when run on a computer, cause the computer to perform the first aspect and any optional method thereof, or the second aspect and any optional method thereof.

[0143] Eighthly, this application provides a chip system including a processor for supporting a circuit routing determination device in implementing some or all of the functions involved in the above aspects, such as transmitting or processing data or information involved in the above methods. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the execution device or training device. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0144] Figure 1 This is a schematic diagram of an application architecture;

[0145] Figure 2 This is a schematic diagram of an application architecture;

[0146] Figure 3 This is a schematic diagram of an application architecture;

[0147] Figure 4 This is a schematic diagram of an application architecture;

[0148] Figure 5a This is a schematic diagram of an application architecture;

[0149] Figure 5b This is a schematic diagram of an application architecture;

[0150] Figure 6 This is a schematic diagram of an application architecture;

[0151] Figure 7a A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0152] Figure 7b A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0153] Figure 7c A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0154] Figure 7d A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0155] Figure 7e A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0156] Figure 7f A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0157] Figure 8 This is a schematic diagram of an interface in an embodiment of this application;

[0158] Figure 9 This is a schematic diagram of an interface in an embodiment of this application;

[0159] Figure 10a This is a schematic diagram of an interface in an embodiment of this application;

[0160] Figure 10b This is a schematic diagram of an interface in an embodiment of this application;

[0161] Figure 11a This is a schematic diagram of an interface in an embodiment of this application;

[0162] Figure 11b This is a schematic diagram of an interface in an embodiment of this application;

[0163] Figure 12 This is a schematic diagram of an interface in an embodiment of this application;

[0164] Figure 13 This is a schematic diagram of an interface in an embodiment of this application;

[0165] Figure 14 This is a schematic diagram of an interface in an embodiment of this application;

[0166] Figure 15 This is a schematic diagram of an interface in an embodiment of this application;

[0167] Figure 16 This is a schematic diagram of an interface in an embodiment of this application;

[0168] Figure 17 This is a schematic diagram of an interface in an embodiment of this application;

[0169] Figure 18 This is a schematic diagram of an interface in an embodiment of this application;

[0170] Figure 19 This is a schematic diagram of an interface in an embodiment of this application;

[0171] Figure 20 A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0172] Figure 21 A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0173] Figure 22 A schematic diagram of an embodiment of a circuit routing determination method provided in this application;

[0174] Figure 23 This application provides an embodiment of a circuit routing determination device.

[0175] Figure 24This application provides an embodiment of a circuit routing determination device.

[0176] Figure 25 A schematic diagram of the structure of the execution device provided in the embodiments of this application;

[0177] Figure 26 This is a schematic diagram of a server structure provided in an embodiment of this application;

[0178] Figure 27 This is a schematic diagram of a chip structure provided in an embodiment of this application. Detailed Implementation

[0179] The embodiments of the present invention will now be described with reference to the accompanying drawings. The terminology used in the embodiments section is for illustrative purposes only and is not intended to limit the scope of the invention.

[0180] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0181] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0182] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly located on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intermediate elements or layers. It should also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intermediate elements or layers.

[0183] The terms “substantially,” “about,” and similar terms used herein are used as approximations rather than as terms of degree, and are intended to take into account the inherent biases of measurements or calculations known to those skilled in the art. Furthermore, the use of “may” in describing embodiments of the invention refers to “one or more possible embodiments.” The terms “use,” “using,” and “used” used herein are to be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Additionally, the term “exemplary” is intended to refer to an instance or illustration.

[0184] First, we will introduce the application scenarios of this application. This application can be applied to, but is not limited to, circuit design applications or cloud services provided by cloud-side servers. These will be described in detail below:

[0185] I. Circuit Design Applications

[0186] The product form of this application embodiment can be a circuit design application, such as a chip design application, or more specifically, electronic design automation (EDA) software. EDA can run on a terminal device or a cloud server.

[0187] Taking EDA as an example, in one possible implementation, EDA can automatically connect the pins of a circuit. EDA can generate a circuit layout (e.g., expressed as a circuit diagram) in response to input circuit parameters. In this embodiment, the circuit parameters can be information about the pin units, and the generated circuit diagram or circuit layout can include the connection relationships between the pin units.

[0188] The schematic diagram can optionally be processed by an electronic design automation (EDA) software system (e.g., transistor schematic and layout editing tools (e.g., Mentor or)) to generate a layout, perform layout versus schematic (LVS) and / or design rule check (DRC), and can be sent to a manufacturing facility (e.g., semiconductor fabrication or "FAB") to (for example) produce an integrated circuit (e.g., a chip) with the desired properties. Typically, analog circuit design professionals spend considerable time and effort designing schematic diagrams for analog integrated circuits. Advantageously, the systems and methods using the techniques described herein can generate schematic diagrams for electronic circuits (e.g., complete chips) very quickly and in substantially less time than would be required to design each circuit using conventional techniques.

[0189] In this embodiment, the port can be an input / output (I / O) unit, and the pin can be a bump adapter unit.

[0190] In one possible implementation, the I / O unit can be located in the edge region of the circuit (e.g., the chip), and the I / O unit can be responsible for connecting to external components. The I / O unit can serve as a port for data exchange, power transfer, and other functions with external components.

[0191] The bump unit, also known as a wafer, bump, or bump, is located in the internal area of ​​a circuit (such as a chip). The bump can be connected to the I / O unit to exchange data and transfer energy.

[0192] The connection between I / O units and bump is one of the important processes in circuit design. In order to improve the performance of the circuit itself, it is necessary to maximize the number of I / O-bump connections.

[0193] The following sections will introduce the circuit design application in this application from the perspectives of functional architecture and product architecture that implements the functions.

[0194] Reference Figure 1 , Figure 1 This is a schematic diagram of the functional architecture of the circuit design application in the embodiments of this application:

[0195] In one possible implementation, embodiments of this application include a system (e.g., a circuit design application) capable of automatically generating circuit diagrams based on input parameters, wherein different parameter values ​​input to the system result in the automatic generation of different circuit diagrams. Figure 1As shown, the circuit design application 102 can receive input parameters 101 and generate a circuit diagram 103. The circuit design application 102 can execute on at least one computer system (for example) and includes computer code that, when executed by one or more computers, causes the computers to perform the circuit routing determination method described herein.

[0196] In one possible implementation, refer to Figure 2 The parameters may include text specifying a circuit component (e.g., "I / O unit", "bump") or (for example) one or more identifiers (IDs), such as one or more codes, used to uniquely identify a set of rules applied to the corresponding circuit component. The parameters may be used to describe the characteristics of the circuit component (e.g., "I / O unit", "bump"), such as location characteristics, functional characteristics, and priority characteristics (these three characteristics will be described in subsequent embodiments and will not be repeated here).

[0197] In one possible implementation, refer to Figure 3 The circuit design application may include a machine learning model and a connection algorithm (such as the minimum cost maximum flow algorithm in the embodiments of this application). Optionally, the information of I / O units and bump information can be input into the machine learning model to obtain the cost of each candidate connection path, and then the routing design result (such as a circuit diagram) can be obtained and output based on the cost value through the connection algorithm.

[0198] For example, the routing design results can be sent to a manufacturing facility to produce integrated circuits (e.g., chips) with the desired properties.

[0199] In one possible implementation, circuit design software can run on an edge-side terminal device or on a cloud-side server.

[0200] For example, the terminal device may be equipped with circuit design software, including data input, data processing (such as the circuit routing determination method in the embodiments of this application), and data output actions that can be performed by the terminal device.

[0201] For example, the terminal device may have a client installed with circuit design software. The actions of data input and data output can be performed by the terminal device, while the actions of data processing (such as the circuit routing determination method in the embodiments of this application) can be performed by the cloud-side server. That is, the terminal device can transmit the data required for data processing (such as the circuit routing determination method in the embodiments of this application) to the cloud-side server. After the cloud-side server completes the data processing actions, it can return the data processing results to the terminal device on the terminal side, and the terminal device can output based on the processing results.

[0202] The following describes the entity architecture of the circuit design application in the embodiments of this application.

[0203] Reference Figure 4 , Figure 4 This is a schematic diagram of the entity architecture of the circuit design application running in the embodiments of this application:

[0204] See Figure 4 , Figure 4 A schematic diagram of a system architecture is shown. The system may include a terminal 100 and a server 200. The server 200 may include one or more servers (…). Figure 4 (The example includes a server), where server 200 can provide circuit routing services for one or more terminals.

[0205] The terminal 100 may have a circuit design application installed or a webpage related to circuit design open. The application and webpage can provide a circuit design interface. The terminal 100 can receive relevant parameters input by the user on the circuit design interface and send the parameters to the server 200. The server 200 can obtain the processing result based on the received parameters and return the processing result to the terminal 100.

[0206] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining the data processing result based on the received parameters on its own, without the need for the server to cooperate. This application embodiment is not limited to this.

[0207] The following description Figure 4 The product form of the mid-terminal 100;

[0208] The terminal 100 in this application embodiment can be a mobile phone, tablet computer, wearable device, vehicle device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc., and this application embodiment does not impose any restrictions on it.

[0209] Figure 5a A schematic diagram of an optional hardware structure for terminal 100 is shown.

[0210] refer to Figure 5aAs shown, the terminal 100 may include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, a power supply 190, and other components. Those skilled in the art will understand that... Figure 5a These are merely examples of terminals or multi-functional devices and do not constitute a limitation on terminals or multi-functional devices. They may include more or fewer components than shown in the illustration, or combine certain components, or use different components.

[0211] The input unit 130 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the portable multi-functional device. Specifically, the input unit 130 may include a touchscreen 131 (optional) and / or other input devices 132. The touchscreen 131 can collect touch operations performed by the user on or near it (such as operations performed by the user using fingers, knuckles, styluses, or any suitable object on or near the touchscreen), and drive the corresponding connection devices according to a pre-set program. The touchscreen can detect the user's touch actions, convert the touch actions into touch signals and send them to the processor 170, and can receive and execute commands sent by the processor 170; the touch signal includes at least touch point coordinate information. The touchscreen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, various types of touchscreens, such as resistive, capacitive, infrared, and surface acoustic wave, can be used to implement the touchscreen. Besides the touchscreen 131, the input unit 130 may also include other input devices. Specifically, other input devices 132 may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons 132, power buttons 133, etc.), trackball, mouse, joystick, etc.

[0212] The input device 132 can receive parameters related to circuit routing design, such as the first information of the I / O unit in this embodiment, the second information of the bump, and modification instructions for candidate connection paths, etc.

[0213] The display unit 140 can be used to display information input by the user or information provided to the user, various menus of the terminal 100, interactive interfaces, file display, and / or playback of any multimedia file. In this embodiment, the display unit 140 can be used to display the interface of a circuit design application, routing design results, and schematics of candidate connection paths, etc.

[0214] The memory 120 can be used to store instructions and data. The memory 120 may primarily include an instruction storage area and a data storage area. The data storage area can store various types of data, such as multimedia files and text. The instruction storage area can store software units such as operating systems, applications, and instructions required for at least one function, or subsets or extended sets thereof. It may also include non-volatile random access memory. It provides the processor 170 with hardware, software, and data resources for managing the computing device, supporting control software and applications. It is also used for storing multimedia files, as well as storing running programs and applications.

[0215] The processor 170 is the control center of the terminal 100. It connects various parts of the terminal 100 via various interfaces and lines. By running or executing instructions stored in the memory 120 and calling data stored in the memory 120, it performs various functions and processes data of the terminal 100, thereby controlling the terminal device as a whole. Optionally, the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 170. In some embodiments, the processor and memory can be implemented on a single chip; in some embodiments, they can also be implemented separately on independent chips. The processor 170 can also be used to generate corresponding operation control signals, send them to the corresponding components of the computing processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that the various functional modules therein perform corresponding functions, thereby controlling the corresponding components to act according to the instructions.

[0216] The memory 120 can be used to store software code related to the circuit routing determination method, and the processor 170 can execute the steps of the chip's circuit routing determination method, and can also schedule other units (such as the above-mentioned input unit 130 and display unit 140) to achieve the corresponding functions.

[0217] The radio frequency unit 110 (optional) can be used for receiving and transmitting signals during information transmission or calls. For example, it can receive downlink information from the base station and process it for the processor 170; additionally, it can transmit uplink data to the base station. Typically, the RF circuit includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, the radio frequency unit 110 can also communicate wirelessly with network devices and other devices. This wireless communication can use any communication standard or protocol, including but not limited to Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

[0218] In this embodiment of the application, the radio frequency unit 110 can send the chip parameters to the server 200 and receive the routing design results sent by the server 200.

[0219] It should be understood that the radio frequency unit 110 is optional and can be replaced with other communication interfaces, such as a network port.

[0220] The terminal 100 also includes a power supply 190 (such as a battery) that supplies power to various components. Preferably, the power supply can be logically connected to the processor 170 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system.

[0221] Terminal 100 also includes an external interface 180, which can be a standard Micro USB interface or a multi-pin connector, which can be used to connect terminal 100 to other devices for communication or to connect a charger to charge terminal 100.

[0222] Although not shown, terminal 100 may also include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, sensors with various functions, etc., which will not be described in detail here. Some or all of the methods described below can be applied to, for example... Figure 5a In the terminal 100 shown.

[0223] The following description Figure 4 The product form of the mid-range server 200;

[0224] Figure 5b A structural diagram of a server 200 is provided, as follows: Figure 5b As shown, server 200 includes bus 201, processor 202, communication interface 203, and memory 204. Processor 202, memory 204, and communication interface 203 communicate with each other via bus 201.

[0225] Bus 201 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 5b The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0226] The processor 202 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0227] Memory 204 may include volatile memory, such as random access memory (RAM). Memory 204 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0228] The memory 204 can be used to store software code related to the circuit routing determination method, and the processor 202 can execute the steps of the chip's circuit routing determination method, and can also schedule other units to achieve corresponding functions.

[0229] It should be understood that the aforementioned terminal 100 and server 200 can be centralized or distributed devices. The processors (e.g., processor 170 and processor 202) in the aforementioned terminal 100 and server 200 can be hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the processor can be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0230] It should be understood that the circuit routing determination method in the embodiments of this application involves AI-related calculations. When performing AI calculations, the instruction execution architecture of the terminal device and the server is not limited to... Figure 5a as well as Figure 5b The processor and memory architecture shown is illustrated below. Figure 6 The system architecture provided in the embodiments of this application will be described in detail.

[0231] Figure 6 This is a schematic diagram of the system architecture provided for an embodiment of this application. Figure 6 As shown, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data acquisition system 560.

[0232] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The calculation module 511 may include a target model / rule 501, while the preprocessing modules 513 and 514 are optional.

[0233] The execution device 510 can be a terminal device or a server that runs the aforementioned circuit design application.

[0234] The data acquisition device 560 is used to collect training samples. Training samples can include information about I / O units, bump information, and the total number of connections, etc. After collecting the training samples, the data acquisition device 560 stores these training samples in the database 530.

[0235] The training device 520 can maintain training samples in the database 530 and obtain the target model / rule 501 from the neural network to be trained (such as the machine learning model in the embodiments of this application).

[0236] It should be noted that in practical applications, the training samples maintained in database 530 may not all come from the data acquisition device 560; they may also be received from other devices. Furthermore, it should be noted that training device 520 may not necessarily train the target model / rule 501 entirely based on the training samples maintained in database 530; it may also obtain training samples from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0237] The target model / rule 501 trained using training device 520 can be applied to different systems or devices, such as... Figure 6 The execution device 510 shown can be a terminal, such as a mobile phone terminal, tablet computer, laptop computer, augmented reality (AR) / virtual reality (VR) device, vehicle terminal, etc., or it can be a server, etc.

[0238] Specifically, the training device 520 can transfer the trained model to the execution device 510.

[0239] exist Figure 6 In the execution device 510, an input / output (I / O) interface 512 is configured for data interaction with external devices. Users can input data (such as the first information of the I / O unit, the second information of the bump, etc. in the embodiments of this application) into the I / O interface 512 through the client device 540.

[0240] Preprocessing modules 513 and 514 are used to preprocess the input data received from the I / O interface 512. It should be understood that preprocessing modules 513 and 514 may be absent, or only one preprocessing module may be used. When preprocessing modules 513 and 514 are absent, the calculation module 511 can be used directly to process the input data.

[0241] During the preprocessing of input data by the execution device 510, or during the calculation module 511 of the execution device 510 performing calculations and other related processes, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0242] Finally, the I / O interface 512 provides the processing result (e.g., the target connection path in this embodiment) to the client device 540, thereby providing it to the user.

[0243] exist Figure 6 In the illustrated scenario, the user can manually provide input data, which can be done through the interface provided by I / O interface 512. Alternatively, the client device 540 can automatically send input data to I / O interface 512. If user authorization is required for the client device 540 to automatically send input data, the user can set the corresponding permissions in the client device 540. The user can view the output results of the execution device 510 on the client device 540, which can be presented in various forms such as display, sound, or animation. The client device 540 can also act as a data acquisition terminal, collecting the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530. Alternatively, data can be collected directly from the I / O interface 512 without going through the client device 540, using the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530.

[0244] It is worth noting that, Figure 6 This is merely a schematic diagram of a system architecture provided in an embodiment of this application. The positional relationships between the devices, components, modules, etc., shown in the diagram do not constitute any limitation. For example, in Figure 6 In this context, the data storage system 550 is an external storage device relative to the execution device 510. However, in other cases, the data storage system 550 may also be placed within the execution device 510. It should be understood that the aforementioned execution device 510 may be deployed within the client device 540.

[0245] From the inference side of the model:

[0246] In this embodiment, the computing module 511 of the execution device 510 can obtain the code stored in the data storage system 550 to implement the circuit routing determination method in this embodiment.

[0247] In this embodiment of the application, the computing module 511 of the execution device 510 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0248] Specifically, the computing module 511 of the execution device 510 can be a hardware system with the function of executing instructions. The connection relationship prediction method provided in this application embodiment can be software code stored in the memory. The computing module 511 of the execution device 510 can obtain the software code from the memory and execute the obtained software code to implement the circuit routing determination method provided in this application embodiment.

[0249] It should be understood that the computing module 511 of the execution device 510 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps of the circuit routing determination method provided in the embodiments of this application can also be implemented by the hardware system without the function of executing instructions in the computing module 511 of the execution device 510, which is not limited here.

[0250] From the training side of the model:

[0251] In this embodiment of the application, the training device 520 can access the memory ( Figure 6 (Not shown in the diagram, but can be integrated into the training device 520 or deployed separately from the training device 520) The code stored in the diagram can be used to implement the steps related to model training in the embodiments of this application.

[0252] In this embodiment of the application, the training device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0253] It should be understood that the training device 520 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the training of the neutralization model provided in the embodiments of this application can also be implemented by the hardware system in the training device 520 without the function of executing instructions, which is not limited here.

[0254] II. Cloud services provided by the server:

[0255] In one possible implementation, the server can provide circuit routing determination services to the end side through an application programming interface (API).

[0256] The terminal device can send relevant parameters (such as I / O unit information, bump information, etc.) to the server through the API provided by the cloud. The server can obtain the processing result based on the received parameters and return the processing result (such as the target connection path, etc.) to the terminal.

[0257] The description of the terminal and server can be found in the above embodiments, and will not be repeated here.

[0258] Since the embodiments of this application involve a large number of neural network applications, for ease of understanding, the relevant terms and concepts such as neural networks involved in the embodiments of this application will be introduced below.

[0259] (1) Neural Network

[0260] A neural network can be composed of neural units, which can be defined as a computational unit that takes xs (i.e., input data) and an intercept of 1 as input. The output of this computational unit can be:

[0261]

[0262] Where s = 1, 2, ..., n, where n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of this activation function can be used as the input of the next convolutional layer, and the activation function can be the sigmoid function. A neural network is a network formed by connecting multiple of the above-mentioned individual neural units together, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, which can be a region composed of several neural units.

[0263] (2) Deep Neural Networks

[0264] Deep Neural Networks (DNNs), also known as multilayer neural networks, can be understood as neural networks with many hidden layers, though there's no specific metric for "many." DNNs can be categorized into three layers based on their position: input layers, hidden layers, and output layers. Generally, the first layer is the input layer, the last layer is the output layer, and the layers in between are hidden layers. All layers are fully connected, meaning that any neuron in the i-th layer is connected to any neuron in the (i+1)-th layer. Although DNNs appear complex, the operation of each layer is actually quite simple, resembling a linear relationship as follows: in, It is the input vector. It is the output vector. α is the offset vector, W is the weight matrix (also called coefficients), and α() is the activation function. Each layer is simply an adjustment of the input vector. The output vector is obtained through such a simple operation. Because DNNs have many layers, the coefficients W and the offset vector... The number of these parameters is therefore quite large. The definitions of these parameters in a DNN are as follows: Taking the coefficient W as an example: Assuming a three-layer DNN, the linear coefficient from the 4th neuron in the second layer to the 2nd neuron in the third layer is defined as... The superscript 3 represents the layer number where coefficient W resides, while the subscript corresponds to the output third layer index 2 and the input second layer index 4. In summary, the coefficients from the k-th neuron in layer L-1 to the j-th neuron in layer L are defined as follows: It's important to note that the input layer does not have a W parameter. In deep neural networks, more hidden layers allow the network to better represent complex real-world situations. Theoretically, the more parameters a model has, the higher its complexity and "capacity," meaning it can perform more complex learning tasks. Training a deep neural network is essentially the process of learning the weight matrix, with the ultimate goal of obtaining the weight matrix of all layers in the trained deep neural network (a weight matrix formed by the vectors W from many layers).

[0265] (3) Graph:

[0266] The graph is a data structure containing at least one vertex and at least one edge. In some scenarios, vertices in the graph can map to entities, and edges can map to relationships between entities. The graph can be directed or undirected. Of course, the graph can also include other data besides vertices and edges, such as vertex labels and edge labels. In an exemplary scenario applied to friend recommendations, each vertex in the graph can represent a user, each edge can represent the social relationship between different users, and the data for each vertex includes user profile data and user behavior data, such as the user's age, occupation, hobbies, and education level. Similarly, in a product recommendation scenario, each vertex in the graph can represent a user or a product, and each edge can represent the interaction relationship between a user and a product, such as a purchase relationship or a collection relationship. Furthermore, in a financial risk control scenario, each vertex in the graph can represent an account, transaction, or funds. The edges in the graph can represent the flow of funds; for example, a loop in the graph can represent a circular transfer. For example, in scenarios where the connection relationships between network elements in a network system are determined, each vertex in the graph can represent a network element, such as a router, switch, or terminal, and each edge in the graph can represent the connection relationship between different network elements.

[0267] (4) Graph Neural Network (GNN):

[0268] Graph Neural Networks (GNNs) are deep learning methods that incorporate structural information and can be used to compute the current state of nodes. Information propagation in a GNN follows a given graph structure, allowing each node's state to be updated based on its neighboring nodes. Specifically, it uses the neural network as an aggregation function to pass information from all neighboring nodes to the current node, based on the current node's structural graph, and updates the state by combining this information with the current node's state. The output of a GNN is the state of all nodes.

[0269] (5) Loss Function

[0270] In training a deep neural network, to ensure the output closely approximates the desired predicted value, we compare the network's prediction with the target value. Based on the difference, we update the weight vector of each layer (usually pre-configuring parameters before the initial update). For example, if the prediction is too high, the weight vector is adjusted to predict a lower value. This adjustment continues until the deep neural network predicts the target value or a value very close to it. Therefore, we need to predefine "how to compare the difference between the predicted and target values," which is the loss function or objective function. These are important equations used to measure the difference between the predicted and target values. Taking the loss function as an example, a higher output value (loss) indicates a greater difference, and training the deep neural network becomes a process of minimizing this loss.

[0271] (6) Backpropagation algorithm

[0272] Convolutional neural networks can employ backpropagation (BP) to correct the parameters in the initial super-resolution model during training, thereby reducing the reconstruction error loss. Specifically, forward propagation of the input signal to the output generates an error loss; this error loss information is then propagated back to update the parameters in the initial super-resolution model, leading to convergence of the error loss. The backpropagation algorithm is an error-loss-driven backpropagation process aimed at obtaining the optimal parameters of the super-resolution model, such as the weight matrix.

[0273] (7) Port

[0274] A port is the edge of a circuit (such as a chip) and is used as an interface for communication or power transfer with external circuits.

[0275] (8) pins

[0276] A pin is a functional pin in a circuit. A pin is a segment at the end of a lead wire. This segment is soldered together with the pads on the circuit board to form a solder joint.

[0277] (9) Relay point

[0278] In a circuit, there is a bare board area between adjacent pins that does not include solder joints. A relay point is a logic point defined on the bare board area. A relay point is a point on the connection path between a port and a pin.

[0279] (10) I / O Unit

[0280] I / O units can be located in the edge area of ​​a circuit (such as a chip). I / O units can be responsible for connecting to external components and can serve as ports for data exchange, power transfer, and other functions with external components.

[0281] (11)bump

[0282] A bump, also known as a wafer, a bump, or a slab, is located in the internal area of ​​a circuit (such as a chip). A bump can connect to an I / O unit to exchange data and transfer power.

[0283] Matching and routing between ports and pins in a circuit, such as the matching and routing between I / O units and bumps, is a crucial part of chip design. It is characterized by its time-consuming nature, difficulty in inspection, and high demand. Typically, it relies on the manual experience of chip designers for troubleshooting, using interactive software to manually adjust the corresponding pin matching routing, and maximizing the actual number of connections between I / O units and bumps while satisfying multiple pin priority type constraints. Currently, the industry commonly uses analytical methods based on rule-based constraints to handle the automatic pin matching routing problem, achieving automatic routing based on chip pin types and predefined routing rules. However, analytical methods based on rule-based constraints suffer from poor generalization, complex and coupled routing rules, high computational complexity, and a tendency to get trapped in local extrema, leading to poor overall circuit routing performance.

[0284] To solve the above problems, refer to Figure 7a , Figure 7a This is a flowchart illustrating a circuit routing determination method provided in an embodiment of this application, as shown below. Figure 7a As shown in the embodiment of this application, a method for determining circuit traces includes:

[0285] 701. Obtain first information of multiple ports of the circuit and second information of multiple pins; the multiple ports and the multiple pins include multiple candidate connection paths; the candidate connection paths are connection paths between ports and pins.

[0286] The entity executing step 701 can be a terminal device or a server, as described in the above embodiments, and will not be repeated here.

[0287] In one possible implementation, the port is an input / output (I / O) unit, and the pin is a bump unit.

[0288] The first information of multiple ports can be understood as the first information of each port in the multiple ports.

[0289] The second information of multiple pins can be understood as the second information of each pin among the multiple pins.

[0290] In one possible implementation, the first information may include one or more of the port's location characteristics, functional characteristics, or priority characteristics. The second information may be one or more of the pin's location characteristics, functional characteristics, or priority characteristics.

[0291] In one possible implementation, the position feature can be represented as the coordinate position of the circuit element. For example, the position feature can be the coordinate position on a 2D plane, or more specifically, the position feature can be the XY coordinates in a Cartesian coordinate system.

[0292] For example, the first piece of information may include the coordinates of the port.

[0293] For example, the second information may include the coordinates of the pin's location.

[0294] In one possible implementation, the functional characteristic can represent the function performed by the circuit element. For example, the function may include signal transmission, energy transmission, and grounding.

[0295] For example, the first information may include the functionality implemented by the port.

[0296] For example, the second information may include the function implemented by the pin.

[0297] In one possible implementation, the priority feature can represent the importance of a circuit element, which can describe the circuit element's requirement for a certain number of connections. The higher the priority, the higher the importance of the circuit element, and the higher the requirement for a certain number of connections.

[0298] In one possible implementation, circuit elements with different functions can have different priorities.

[0299] For example, circuit elements with signal transmission function have a higher priority than circuit elements with energy transmission function, and circuit elements with energy transmission function have a higher priority than circuit elements with grounding function.

[0300] In one possible implementation, circuit elements with different functions can have the same priority.

[0301] For example, circuit elements with signal transmission function have a higher priority than circuit elements with energy transmission function, and circuit elements with energy transmission function have the same priority as circuit elements with grounding function.

[0302] In one possible implementation, circuit elements with the same function can have different priorities.

[0303] For example, the priority of some circuit elements in the grounding function can be higher than the priority of other circuit elements in the grounding function.

[0304] In one possible implementation, port information (e.g., the first information in the embodiments of this application) and pin information (e.g., the second information in the embodiments of this application) can be input based on the interface of circuit design software (e.g., EDA).

[0305] The following section, using the interface description as an example, illustrates how to input the first and second pieces of information:

[0306] 1. Regarding location features

[0307] In one possible implementation, taking EDA as an example, the circuit design software can provide a library of circuit elements to choose from, which may include various circuit units such as ports and pins.

[0308] Reference Figure 8 You can select and drag the circuit unit from the component library to the corresponding position. After placing the port and pin in the corresponding position, you can obtain the position features of the port and pin based on the position of the circuit element on the circuit diagram. For example, the position feature can be represented as the coordinate position of the circuit element. For example, the position feature can be the coordinate position on the 2D plane. More specifically, the position feature can be the XY coordinate in the Cartesian coordinate system.

[0309] Reference Figure 8 The first and second information can be input in the form of a file, which can express the information of the circuit to be routed. This file can include the location characteristics of ports and pins.

[0310] 2. Functional characteristics

[0311] Reference Figure 9 You can select the components to place and their functions from the component library, and drag them to the corresponding positions to obtain the functional characteristics of the ports and pins.

[0312] Reference Figure 9 The first and second information can be input in the form of a file, which can express the information of the circuit to be routed. This file can include the functional characteristics of ports and pins.

[0313] 3. Priority characteristics

[0314] Reference Figure 10a This can be achieved by selecting the priority of circuit units (e.g.) Figure 10aThe priority levels 1, 2, and 3 are shown, and the components are placed in the corresponding positions to obtain the priority characteristics of the ports and pins.

[0315] In one possible implementation, the components to be placed and their functions can be selected from the component library, dragged to the corresponding positions, and then their priorities can be edited. (See reference...) Figure 10b You can select and trigger an editing control for the port, which allows you to edit the priority; for example, you can select... Figure 10b The priority levels shown are 1, 2, and 3.

[0316] Reference Figure 10a The first and second pieces of information can be input via a file, which can express information about the circuit to be routed. This file can include the priority characteristics of ports and pins.

[0317] In one possible implementation, multiple candidate connection paths may be included between the plurality of ports and the plurality of pins, wherein the candidate connection paths are connection paths (feasible connection paths) between the ports and the pins.

[0318] In one possible implementation, the connection path between a port and a pin can be understood as a candidate connection path with a port and a pin at its two ends. The port and pin can be connected through the candidate connection path, and the area traversed by the candidate connection path is a blank area that does not include the port and pin, that is, an area not occupied by the port and pin.

[0319] Reference Figure 11a , Figure 11a In the diagram, squares represent ports, circles represent pins, and the same color indicates the same function, such as... Figure 11a As shown, a group of ports and pins can include one or more candidate connection paths, meaning that starting from a port, one or more paths can be used to connect to a pin.

[0320] In one possible implementation, the final target connection path between the port and pin can be selected from the candidate connection paths.

[0321] The following describes how to determine at least one candidate connection path between a port and a pin:

[0322] In one possible implementation, when determining candidate connection paths, only ports and pins with the same function can form candidate connection paths. The functional characteristics of the ports and pins indicated by the first information and the second information can identify the objects that can form candidate connection paths. That is, the ports and pins with the same function indicated by the first information and the second information can be used as the start and end points to form candidate connection paths.

[0323] For example, Figure 11a Candidate connection paths can be formed between ports and pins of the same color shown.

[0324] In one possible implementation, the first and second information can indicate the location characteristics of the ports and pins. Based on the location characteristics, the arrangement of each port and pin can be known, and thus at least one candidate connection path can be determined based on the spatial arrangement of each port and pin.

[0325] In this embodiment, there can be a large number of candidate connection paths between ports and pins. To reduce subsequent computation, some candidate connection paths can be retained. For example, at least one candidate connection path with a number of paths less than a preset value (exemplarily, the preset value is 3, 4, 5, 6, 7) and a relatively short path length can be selected. Furthermore, since ports and pins of the same type can be connected, to reduce subsequent computation, ports and pins that are relatively close can be selected for determining candidate connection paths.

[0326] In one possible implementation, at least one candidate connection path between a port and a pin can be achieved through user interaction. For example, the user can manually input at least one candidate connection path between a port and a pin on the interface of a circuit design application, import a circuit diagram file containing at least one candidate connection path between a port and a pin into the circuit design application, or transmit at least one candidate connection path between a port and a pin to a cloud server.

[0327] 702. Based on the first information and the second information, a cost value for each candidate connection path is obtained through a machine learning model. The cost value is used to indicate the impact of the candidate connection path on the total number of connection paths between the plurality of ports and the plurality of pins. The cost value is used to determine at least one target connection path from the plurality of candidate connection paths.

[0328] In one possible implementation, the entity performing step 702 can be a server or a terminal device.

[0329] Specifically, based on the entity executing the steps, the following situations can be executored as follows:

[0330] In one possible implementation, refer to Figure 7b In one possible implementation, the terminal device can obtain first information of multiple ports of the circuit and second information of multiple pins, and send the first information and second information (for example, information of multiple candidate connection paths obtained based on the first information and second information) to the server. The server can obtain the cost value of each candidate connection path through a machine learning model based on the first information and second information, determine at least one target connection path from the multiple candidate connection paths based on the cost value, and send the at least one target connection path back to the terminal device.

[0331] In one possible implementation, refer to Figure 7c The terminal device can acquire first information of multiple ports of the circuit and second information of multiple pins, and send the first information and second information (for example, information of multiple candidate connection paths obtained based on the first information and second information) to the server. The server can obtain the cost value of each candidate connection path through a machine learning model based on the first information and second information, and send the cost value to the terminal device. Then, the terminal device can determine at least one target connection path from the multiple candidate connection paths based on the cost value.

[0332] In one possible implementation, refer to Figure 7d The terminal device can obtain first information of multiple ports of the circuit and second information of multiple pins. Based on the first information and the second information (for example, information of multiple candidate connection paths obtained based on the first information and the second information), the terminal device obtains the cost value of each candidate connection path through a machine learning model and sends the cost value to the server. The server can then determine at least one target connection path from the multiple candidate connection paths based on the cost value and send the at least one target connection path back to the terminal device.

[0333] In one possible implementation, refer to Figure 7e The terminal device can obtain first information of multiple ports of the circuit and second information of multiple pins. Based on the first information and the second information (for example, information of multiple candidate connection paths obtained based on the first information and the second information), it can obtain the cost value of each candidate connection path through a machine learning model. Based on the cost value, it can determine at least one target connection path from the multiple candidate connection paths.

[0334] In one possible implementation, refer to Figure 7fThe server can obtain first information of multiple ports of the circuit and second information of multiple pins (which may be sent from the terminal device); for example, the server can obtain information of multiple candidate connection paths (which may be sent from the terminal device), and based on the first information and the second information (for example, information of multiple candidate connection paths obtained based on the first information and the second information), obtain the cost value of each candidate connection path through a machine learning model, determine at least one target connection path from the multiple candidate connection paths based on the cost value, and send the at least one target connection path back to the terminal device.

[0335] In one possible implementation, the candidate connection path may include ports and pins at both ends, and at least one relay point traversed by the candidate connection path, wherein the relay point is an intermediate location point between adjacent pins, and the information of each candidate connection path includes: first information of the ports included in the candidate connection path, second information of the pins included in the candidate connection path, and location information of the at least one relay point.

[0336] Among them, reference Figure 11b The information for multiple candidate connection paths can include information about each candidate connection path. Since each candidate connection path can consist of a starting point, at least one relay point, and an ending point, the information for each candidate connection path can include information about the starting point, the location information of at least one relay point, and the information about the ending point. The starting point can be a port, and its information can include first information about the port (e.g., port location, function, priority, etc.). The ending point can be a pin, and its information can include second information about the pin (e.g., port location, function, priority, etc.).

[0337] In one possible implementation, a candidate connection path between a port and a pin may include a start point, an end point, and at least one relay point. The start point and end point can be a port and a pin, respectively, and the relay point can be a location point between adjacent pins. Therefore, the connection path can be represented as a start point, at least one relay point, and an end point. For example, ports, pins, and relay points can be encoded, with each port, pin, and relay point uniquely corresponding to an encoding result. Based on each encoding result, a corresponding circuit unit (e.g., port, pin, or relay point) can be uniquely determined. The sequence of encoding results can characterize the candidate connection path.

[0338] In scenarios involving matching port and pin routing, it is necessary to maximize the number of connections between ports and pins to improve chip performance. In this embodiment, to increase the number of connections between ports and pins, the impact of each candidate connection path on the total number of connection paths between multiple ports and the multiple pins (i.e., the cost value in this embodiment) can be calculated, and the connection path between ports and pins can be selected based on the cost value.

[0339] The cost value indicates the impact of candidate connection paths on the total number of connection paths between the plurality of ports and the plurality of pins. Since the final determined connection paths between ports and pins are non-intersecting (e.g., paths can be considered intersecting if a common relay point exists), the determination of each connection path will influence the selection of connection paths between other ports and pins to a certain extent (connection paths with overlapping paths cannot be selected). This "impact" can be understood as: whether using the candidate connection path as the connection path between a port and a pin has a positive or negative impact on the total number of connection paths between the plurality of ports and the plurality of pins. Taking a negative impact as an example, the cost value can represent the degree to which using the candidate connection path as the connection path between a port and a pin reduces the total number of connection paths between the plurality of ports and the plurality of pins.

[0340] In order to obtain the aforementioned cost value, in one possible implementation, the cost value of each candidate connection path can be obtained through a machine learning model based on the first information and the second information.

[0341] In one possible implementation, a machine learning model can be trained to obtain the cost of each candidate connection path based on information from multiple candidate connection paths.

[0342] Next, we will introduce an example of a machine learning model:

[0343] In one possible implementation, the machine learning model may include a feature extraction network and a task network. The machine learning model can be a graph neural network model, and the feature extraction network can (exemplarily) be a graph embedding network. This graph neural network model can represent information from multiple candidate connection paths to obtain feature representations for each node and edges. Nodes can correspond to ports, pin units, or relay points in the candidate connection paths, and edges can be connections between ports and relay points, between relay points, between relay points and pin units, etc. Optionally, the candidate connection paths can be represented as bipartite graphs and input into the feature extraction network in bipartite graph form.

[0344] For example, taking nodes as an example, the graph embedding representation process can be aggregated using the GraphSAGE method. The specific aggregation process is described as follows: aggregate the neighboring nodes N(v) of each node v∈V to obtain the aggregation vector h. N(v) The aggregation function uses mean pooling, specifically expressed as follows:

[0345]

[0346] Where mean is the mean pooling function, W is the aggregation weight, b is the aggregation bias, and h is the mean pooling function. u Let y be the hidden state obtained by graph embedding of node y, and σ be the sigmoid activation function.

[0347] In one possible implementation, the feature representation output by the feature extraction network can contain connection features of multiple candidate connection paths (such as features of the global connection arrangement), and the cost of each candidate connection path can be obtained through the task network.

[0348] In one possible implementation, the task network can obtain the cost value of each edge, and then combine the cost values ​​of the edges included in each candidate connection path to obtain the cost value of each candidate connection path.

[0349] For example, the task network can be a policy network π θ A two-layer fully connected network structure, called the decision output layer, can be used. To accelerate training efficiency and reduce model complexity, the ReLU activation function can be applied to the hidden layers of the fully connected decision layer. Since the decision-making process is a multi-priority sequence, the decisions cannot influence each other. Let action a correspond to the i-th priority. i According to the Markov decision process, the action in the current priority state is related to the actions in all previous time steps, which can be represented as follows:

[0350]

[0351] Where p represents the corresponding decision cost assessment output, which is the cost value.

[0352] Optionally, the decision output layer of the policy network corresponds to the decision evaluation cost of feasible paths, which can be restricted to the range [0,1] in a continuous domain.

[0353] The following section introduces the machine learning model of this application embodiment from the perspective of model construction and training:

[0354] In one possible implementation, reinforcement learning can be used to optimize the graph neural network model, which mainly consists of two parts: constructing the graph neural network decision model and the Markov decision optimization process.

[0355] Specifically, a graph neural network decision model is constructed based on a graph neural network model to realize state representation and action decision-making for connections between multi-priority ports and pins. The graph neural network model mainly consists of a graph encoding model and a policy decision model. The graph encoding model comprises a node model, an edge model, and a global model, while the policy decision model is a two-layer fully connected network. The node model encodes the input node information, the edge model encodes the input edge information, and the global model encodes global node and edge information.

[0356] In Markov decision optimization, the sequential decision problem of connections between multiple priority ports and pins can be transformed into a Markov decision problem. The basic elements of a Markov decision consist of a triple of state, action, and reward, specifically defined as:

[0357] State: The location, type, and priority between the port and the pin are used as the node state, and the feasible path between the port and the pin and the node adjacency relationship are used as the edge state. The two are combined as the decision input state.

[0358] Action: Pass the input state to the graph neural network model, generate a feasible path cost assessment in the current state, and use the assessment value as the current decision action.

[0359] Reward: The decision action is passed to the minimum cost maximum flow algorithm to generate the number of connections between ports and pins, and this number of connections is compared with the number of connections between ports and pins obtained by the rule-based method based on common strategies. The gain difference is used as the reward.

[0360] Subsequently, driven by triplet data, and guided by maximizing the objective function, a reinforcement learning method is used to update the graph neural network model. The specific objective function is defined as follows:

[0361]

[0362] Where π is the policy model parameter, s t With a t ρ represents the input state and decision action at time t. π For the experience replay pool, R is the corresponding reward function, H is the policy entropy function, and α is the equilibrium factor;

[0363] In one possible implementation, the model training phase can arbitrarily undergo a cold start sampling process in the early stages. The experience replay pool D is an empty set, and the evaluation cost of the corresponding feasible path is generated using a random uniform sampling method. This cost serves as the model decision output and is applied to the matching path task, generating the original transformation data pairs (s). t ,a t ,r t ,s t+1The data are stored in the experience replay pool D. The neural network model is randomly initialized based on the Xavier method to construct the target network model for stabilizing the model update process, and the parameters of the target network model are updated through a soft update mechanism.

[0364] After the cold start sampling process is completed, the model training sampling process begins, and state representation is performed based on the current feasible solution path and the position, type, and priority node information between ports and pins. t The input is fed into the policy network part of the graph neural network model to generate the mean and variance of the cost of the edges to be connected. Based on the corresponding mean and variance, the corresponding cost evaluation value is obtained through Gaussian sampling and used as the action output 'a'. t The cost evaluation value of the corresponding feasible path is used to calculate the number of connected paths using the minimum cost maximum flow algorithm. The difference between this number of connected paths and the number of connections between ports and pins obtained by the original regular method is used as the reward signal r. t And obtain the next stage state representation s after the corresponding connection. t+1 Finally, the data pairs (s) will be transformed. t ,a t ,r t ,s t+1 The data is recorded in the experience playback pool D to form model sampling data.

[0365] During the sampling process, model training is performed. Batch empirical data B is obtained by sampling through the empirical replay pool D. The Soft Actor-Critic reinforcement learning method is used to further balance the relationship between exploration and exploitation, and a target value Q is defined. for:

[0366]

[0367] Where d t+1 Indicates whether the environment is in a terminated state at time t+1. For value target network, The target network is the policy network. Subsequently, the value network Q is updated using the mean squared error loss function. φ The parameter is defined as:

[0368]

[0369] Finally, the policy network π is updated by maximizing the objective function. θ The parameter is defined as:

[0370]

[0371] Where α is the exploration entropy factor, used to balance the update weights between exploration and utilization.

[0372] The update objective is to maximize the final number of connections between ports and pins. Therefore, the final reward signal is simultaneously allocated to the rewards obtained from decisions made at each priority level. Furthermore, to reduce data correlation, random experience replay is employed. Based on reinforcement learning, the update objective and exploration entropy are maximized, avoiding getting trapped in local optima by solely pursuing maximum reward, thus improving model exploration efficiency and generalization performance. The graph neural network model parameters are optimized through this update method.

[0373] This application utilizes a graph neural network-based reinforcement learning-based routing decision model to consider factors such as the position, type, and priority of pins between all ports and pins. Furthermore, the graph neural network model addresses the difficulty of representing states in high-dimensional spaces. By effectively combining this with minimum-cost maximum flow, it increases the connectivity of rule-based methods and avoids getting trapped in local optima. Additionally, the reinforcement learning approach allows for autonomous exploration within the solution space, reducing human intervention and the difficulty of manual design.

[0374] 703. Based on the cost value, determine at least one target connection path from the plurality of candidate connection paths.

[0375] In one possible implementation, the cost of each candidate connection path can characterize the positive or negative impact of using the candidate connection path as the connection path between the port and the pin on the total number of connection paths between the multiple ports and the multiple pins. Therefore, for each group of ports and pins, the connection path with the smallest negative impact or the largest positive impact among the multiple candidate connection paths can be selected as the target connection path.

[0376] In one possible implementation, at least one target connection path can be determined from the plurality of candidate connection paths using the minimum cost maximum flow algorithm (also known as the minimum cost maximum flow algorithm).

[0377] For example, when executing the minimum-cost maximum flow algorithm, a starting node S and a target node T can be constructed on both sides of a candidate connection path, and connected to nodes corresponding to other ports, pins, or relay points. According to the routing requirements, the total number of nodes |V| = 2 + (|I| + |B| + |R|), where |I| is the number of ports, |B| is the number of pins, and |R| is the number of relay points. Since the number of edges depends on whether they intersect with a higher priority level, affecting the current traversable path, the number of edges changes with different priorities, while the total capacity of the edges is the sum of the connectivity requirements for each pin.

[0378] In one possible implementation, any two target connection paths in the at least one target connection path do not intersect.

[0379] For example, refer to Figure 12 , Figure 12 This is a schematic diagram of the interface of a circuit design application according to an embodiment of this application. After inputting the information of the port and pin (such as the first information and the second information in the embodiment of this application), the circuit design application can be triggered to perform the routing matching process of the port and pin by clicking the control in the interface to trigger the start of the routing design operation.

[0380] For example, refer to Figure 13 , Figure 13 This is a schematic diagram of the interface of a circuit design application according to an embodiment of this application. After determining at least one target connection path from the plurality of candidate connection paths, the circuit design application can display the at least one target connection path in the form of a circuit diagram.

[0381] In one possible implementation, during port and pin matching and routing, the importance of ports and pins with different functions varies. For ports and pins with more critical functions, a greater number of connections are needed to ensure chip performance. For ports and pins with relatively important functions, reducing the number of connections will have a significant impact on chip performance (compared to less important ports and pins). However, for ports and pins with relatively unimportant functions, reducing the number of connections will not have a significant impact on chip performance. In this embodiment, the above importance can be described as priority.

[0382] Due to the existence of multiple priorities, matching and routing ports and pins of each priority level at once would significantly increase the complexity and computational difficulty of the machine learning model, making it difficult to guarantee the accuracy of the routing calculations and failing to obtain satisfactory routing matching results. In this embodiment, routing calculations are performed separately for ports and pins of each priority level, thereby improving the accuracy of the routing calculations.

[0383] For ease of description, this application uses multiple priorities, including priority 1 and priority 2, as examples for illustration.

[0384] For example, priority 1 can be a port and pin for transmitting signals, and priority 2 can be a port and pin for transmitting energy.

[0385] For example, priority 1 can be ports and pins for transmitting signals, and priority 2 can be ports and pins for grounding.

[0386] For example, priority 1 can be a port and pin for transmitting energy, and priority 2 can be a port and pin for grounding.

[0387] For example, priority 1 can be some ports and pins for grounding function, and priority 2 can be some ports and pins for grounding function.

[0388] In one possible implementation, the first information indicates that the first port is more important than the second port; or, the second information indicates that the first pin is more important than the second pin.

[0389] In one possible implementation, the plurality of ports may include a plurality of first ports and a plurality of second ports, and the plurality of pins may include a plurality of first pins and a plurality of second pins. The plurality of first ports and the plurality of first pins are used to implement a first function; the plurality of second ports and the plurality of second pins are used to implement a second function, wherein the first function and the second function are different. The plurality of first ports and the plurality of first pins have a priority of priority 1, and the plurality of second ports and the plurality of second pins have a priority of priority 2. The first function and the second function may be the same or different functions.

[0390] In one possible implementation, the plurality of candidate connection paths may include a plurality of first candidate connection paths formed between the plurality of first ports and the plurality of first pins, and a plurality of second candidate connection paths formed between the plurality of second ports and the plurality of second pins.

[0391] In one possible implementation, to avoid intersection conflicts with high-priority routing paths, lines that intersect with higher-priority candidate connection paths in low-priority routing can be removed. Even if these lines are not removed, they will not be used as the final connection path. Therefore, this embodiment of the application reduces the size of the solution space by removing lines that intersect with higher-priority candidate connection paths in low-priority routing, thereby reducing computational complexity while ensuring the accuracy of routing calculation.

[0392] In one possible implementation, at least one second candidate connection path may intersect with at least one of the plurality of first candidate connection paths. That is, when determining the model input, low-priority paths that overlap with high-priority lines are not eliminated. This increases the amount of input information, meaning the information input into the model can more comprehensively describe the characteristics of the ports and pins, thus leading to a more accurate value.

[0393] Taking high-priority lines as multiple first candidate connection paths and low-priority lines as multiple second candidate connection paths as an example, at least two of the multiple first candidate connection paths may intersect (or may not overlap at all), each second candidate connection path does not intersect with the multiple first candidate connection paths, and at least two of the multiple second candidate connection paths may intersect (or may not overlap at all).

[0394] For example, refer to Figure 14 , Figure 14 This is a schematic diagram of the interface of a circuit design application according to an embodiment of this application. After inputting the information of the ports and pins (such as the first information and the second information in the embodiment of this application), the circuit design application can be triggered to perform the port and pin routing matching process by clicking the control in the interface to trigger the priority-based routing design function.

[0395] In one possible implementation, routing matching can be performed on multiple high-priority ports and multiple first pins. After obtaining the routing matching results, routing matching can then be performed on multiple low-priority second ports and multiple second pins. This will be described in detail below:

[0396] In one possible implementation, when performing routing matching for multiple high-priority ports and multiple first pins, the cost value of each first candidate connection path can be obtained through a machine learning model based on the information of the multiple first candidate connection paths and the information of the multiple second candidate connection paths. The cost value of each first candidate connection path can be used to select a target connection path between the multiple ports and multiple first pins.

[0397] Specifically, at least one target connection path can be determined from the plurality of first candidate connection paths based on the cost value of each of the first candidate connection paths. As to how to determine at least one target connection path from the plurality of first candidate connection paths based on the cost value of each of the first candidate connection paths, please refer to the description in the above embodiments, which will not be repeated here.

[0398] In one possible implementation, the multiple first candidate connection paths can be automatically determined by the system and modified by the user (e.g., filtered or changed). Specifically, the system can obtain and output multiple first initial candidate connection paths formed between the multiple first ports and the multiple first pins. The user can modify the multiple first initial candidate connection paths. Correspondingly, the system can receive modification instructions for the multiple first initial candidate connection paths and obtain the multiple first candidate connection paths based on the modification instructions.

[0399] For example, refer to Figure 15 , Figure 15 This is a schematic diagram of the interface of a circuit design application according to an embodiment of this application, in which the user can delete or modify multiple first initial candidate connection paths.

[0400] For example, refer to Figure 16 , Figure 16 This is a schematic diagram of the interface of a circuit design application according to an embodiment of this application. After determining at least one first target connection path from the plurality of first candidate connection paths, the circuit design application can display at least one first target connection path in the form of a circuit diagram.

[0401] In one possible implementation, after the system outputs at least one first target connection path, the user can modify the at least one first target connection path according to their own needs. Then the system can receive the modification information of the at least one first target connection path and obtain the modified at least one first target connection path based on the modification information of the at least one first target connection path.

[0402] For example, refer to Figure 17 , Figure 17 This is a schematic diagram of the interface of a circuit design application according to an embodiment of this application, in which the user can modify the paths of multiple first target connection paths.

[0403] In one possible implementation, after performing high-priority routing matching operations, low-priority routing matching operations can be performed based on the high-priority routing matching results. Specifically, based on the information of the at least one first target connection path and the information of the plurality of second candidate connection paths, the cost value of each second candidate connection path can be obtained through the machine learning model, and at least one second target connection path can be determined from the plurality of second candidate connection paths based on the cost value of each second candidate connection path.

[0404] In this embodiment, the information of the at least one first target connection path and the information of the plurality of second candidate connection paths can be used as input to the machine learning model. Since the other first candidate connection paths among the plurality of first candidate connection paths, except for the at least one first target connection path, will no longer be used as connection paths between the first port and the first pin, the other first candidate connection paths among the plurality of first candidate connection paths, except for the at least one first target connection path, can be excluded from being used as input to the machine learning model. This reduces the computational complexity while ensuring the accuracy of the routing determination.

[0405] In one possible implementation, when confirming the second priority connection path, the path that intersects with other first candidate connection paths (at least one third candidate connection path) among the multiple first candidate connection paths other than at least one first target connection path can be used as the input to the model. This can increase the amount of input information, that is, the information input into the model can more comprehensively describe the characteristics of the port and pin, and thus obtain a more accurate value.

[0406] In one possible implementation, to ensure that any two connection paths of the same priority do not intersect, constraints can be set when determining the connection paths. These constraints can specify that any two connection paths of the same priority do not intersect.

[0407] In one possible implementation, to ensure that any two connection paths of different priorities do not intersect, constraints can be set when determining the connection paths. These constraints can specify that any two connection paths of different priorities do not intersect. For example, after determining at least one first target connection path, constraints can be set when selecting a second target connection path from multiple second candidate connection paths. These constraints can specify that any connection path of the second target connection path does not intersect with at least one first target connection path.

[0408] In one possible implementation, in order to ensure that no two connection paths of different priorities intersect, constraints can be set in the selection of candidate connection paths. These constraints can stipulate that candidate connection paths of different priorities do not intersect.

[0409] In one possible implementation, the at least one second target connection path can be output.

[0410] For example, refer to Figure 18 , Figure 18 This is a schematic diagram of the interface of a circuit design application according to an embodiment of the present application. After determining at least one second target connection path from the plurality of second candidate connection paths, the circuit design application can display at least one second target connection path in the form of a circuit diagram.

[0411] For example, refer to Figure 19 , Figure 19 This is a schematic diagram of the interface of a circuit design application according to an embodiment of this application. After completing the path calculation of the connection path of priority 3, the circuit design application can display the connection path of priority 3 in the form of a circuit diagram.

[0412] For example, taking a port as an I / O unit and a pin as a bump, refer to... Figure 20 , Figure 20 This is a flowchart illustrating the routing determination method according to an embodiment of this application.

[0413] The first information of the I / O unit and the second information of the bump can be used to construct multiple candidate connection paths between the I / O unit and the bump, and represented as a bipartite graph and input into the machine learning model. For example, it can be input into the graph embedding network of the machine learning model. The feature representation obtained by the graph embedding network can be input into the policy network of the machine learning model to obtain the cost value of each candidate connection path. Based on the cost value, the target connection path can be obtained through the path determination algorithm.

[0414] For example, taking a port as an I / O unit and a pin as a bump, refer to... Figure 21 , Figure 21 This is a flowchart illustrating the priority-based routing determination method according to an embodiment of this application.

[0415] The first information of the I / O unit and the second information of the bump can be used to construct multiple candidate connection paths between the I / O unit and the bump, and represented as a bipartite graph and input into the machine learning model. For example, it can be input into the graph embedding network of the machine learning model. The feature representation obtained by the graph embedding network can be input into the policy network of the machine learning model to obtain the cost value of each candidate connection path with priority 1. Based on the cost value, the first target connection path can be obtained through the path determination algorithm. Based on the first target connection path, the bipartite graph can be updated. The updated bipartite graph can be input into the machine learning model to obtain the cost value of each candidate connection path with priority 2. Based on the cost value, the second target connection path can be obtained through the path determination algorithm.

[0416] This application provides a circuit routing determination method, comprising: acquiring first information of multiple input / output ports of a circuit and second information of multiple transition unit pins; multiple candidate connection paths are included between the multiple ports and the multiple pins; the candidate connection paths are connection paths between ports and pins; based on the first information and the second information, a cost value of each candidate connection path is obtained through a machine learning model, the cost value indicating the impact of the candidate connection path on the total number of connection paths between the multiple ports and the multiple pins; and based on the cost value, at least one target connection path is determined from the multiple candidate connection paths. This application effectively evaluates the cost value of candidate connection paths through a machine learning model, thereby increasing the number of connections between ports and pins.

[0417] Reference Figure 22 This application also provides a method for determining circuit routing, the method comprising:

[0418] 2201. Obtain first information of multiple input / output ports of the circuit and second information of multiple transition unit pins; the multiple ports include multiple first ports and multiple second ports, and the multiple pins include multiple first pins and multiple second pins; multiple first candidate connection paths are formed between the multiple first ports and the multiple first pins, and multiple second candidate connection paths are formed between the multiple second ports and the multiple second pins;

[0419] 2202. Based on the first information and the second information indicating that the importance of the first port is higher than that of the second port, at least one first target connection path is determined from the plurality of first candidate connection paths according to the information of the plurality of first candidate connection paths and the information of the plurality of second candidate connection paths; at least one second target connection path is determined from the plurality of second candidate connection paths according to the information of the at least one first target connection path and the information of the plurality of second candidate connection paths.

[0420] about Figure 22 A detailed description of the circuit routing determination method described above can be found in the embodiments above. Figure 7a The descriptions of the corresponding embodiments are similar and will not be repeated here.

[0421] In one possible implementation, the port is an input / output (I / O) unit, and the pin is a bump unit.

[0422] In one possible implementation, at least two of the plurality of first candidate connection paths intersect; or...

[0423] Each of the second candidate connection paths does not intersect with any of the plurality of first candidate connection paths; or...

[0424] At least one second candidate connection path intersects with at least one of the plurality of first candidate connection paths; or,

[0425] At least two of the plurality of second candidate connection paths intersect.

[0426] In one possible implementation, the method also includes:

[0427] Output multiple first initial candidate connection paths formed between multiple first ports and multiple first pins, and obtain multiple first candidate connection paths based on modification instructions for at least one of the multiple first initial candidate connection paths.

[0428] In one possible implementation, the method also includes:

[0429] Output the at least one first target connection path.

[0430] In one possible implementation, the first or second function is one of the following: signal transmission, grounding, or power transmission.

[0431] In one possible implementation, based on information from at least one first target connection path and information from multiple second candidate connection paths, the method includes:

[0432] Based on information from at least one first connection path and information from multiple second candidate connection paths, but not based on other first candidate connection paths among the multiple first candidate connection paths besides at least one first target connection path.

[0433] In one possible implementation, the method also includes:

[0434] Output multiple second initial candidate connection paths formed between multiple second ports and multiple second pins, and obtain multiple second candidate connection paths based on modification instructions for at least one of the multiple second initial candidate connection paths.

[0435] In one possible implementation, the method also includes:

[0436] Output at least one second target connection path.

[0437] In one possible implementation, any two connection paths in at least one first target connection path do not intersect, any two connection paths in at least one second target connection path do not intersect, and each first target connection path does not intersect with any second target connection path in at least one second target connection path.

[0438] In one possible implementation, the method also includes:

[0439] Based on the modification information of at least one first target connection path, the modified at least one first target connection path is obtained;

[0440] Based on information of at least one first target connection path and information of multiple second candidate connection paths, including: based on information of at least one modified first target connection path and information of multiple second candidate connection paths.

[0441] Reference Figure 23 , Figure 23 A schematic diagram of a circuit routing determination device provided in this application embodiment, wherein the device 2300 includes:

[0442] The acquisition module 2301 is used to acquire first information of multiple ports of the circuit and second information of multiple pins; the multiple ports and the multiple pins include multiple candidate connection paths; the candidate connection paths are connection paths between ports and pins;

[0443] The specific description of the acquisition module 2301 can be found in the description of step 701 in the above embodiments, and will not be repeated here.

[0444] The cost value determination module 2302 is used to obtain the cost value of each candidate connection path through a machine learning model based on the first information and the second information. The cost value indicates the impact of the candidate connection path on the total number of connection paths between the plurality of ports and the plurality of pins. The cost value is used to determine at least one target connection path from the plurality of candidate connection paths.

[0445] The specific description of the substitution value determination module 2302 can be found in the description of step 702 in the above embodiment, and will not be repeated here.

[0446] This application uses a machine learning model to effectively evaluate the cost value of candidate connection paths, and determines the preferred target connection path based on the cost value, thereby increasing the overall number of connections between ports and pins of the chip.

[0447] In one possible implementation, the port is an input / output (I / O) unit, and the pin is a bump unit.

[0448] In one possible implementation, the device further includes:

[0449] The routing determination module 2303 is used to determine at least one target connection path from the plurality of candidate connection paths based on the cost value; or...

[0450] The location information of the relay point in the transmission module is used to send the cost value to the terminal device, and the cost value is used to instruct the terminal device to determine at least one target connection path from the plurality of candidate connection paths.

[0451] In one possible implementation, the cost value is used to indicate the negative impact of the candidate connection path on the total number of connection paths between the plurality of ports and the plurality of pins; the plurality of candidate connection paths include multiple sets of candidate connection paths, each set of candidate connection paths corresponding to a pair of ports and pins;

[0452] The routing determination module 2303 is specifically used for:

[0453] Based on the cost value, the candidate connection path with the lowest cost value from each group of candidate connection paths is determined as the target connection path.

[0454] In one possible implementation, the first information also indicates at least one of the following: the function of the port or the priority of the port;

[0455] The second information also indicates at least one of the following: the function of the pin or the priority of the pin.

[0456] In one possible implementation, the candidate connection path includes ports and pins at both ends, and at least one relay point traversed by the candidate connection path, wherein the relay point is an intermediate location point between adjacent pins;

[0457] The step of basing information on the first information and the second information includes:

[0458] Based on the first information of the ports included in the candidate connection path, the second information of the pins included in the candidate connection path, and the location information of the at least one relay point.

[0459] In one possible implementation, the plurality of ports includes a plurality of first ports and a plurality of second ports, and the plurality of pins includes a plurality of first pins and a plurality of second pins. The plurality of first ports and the plurality of first pins are used to implement a first function; the plurality of second ports and the plurality of second pins are used to implement a second function, wherein the first function and the second function are different.

[0460] The plurality of candidate connection paths include a plurality of first candidate connection paths formed between the plurality of first ports and the plurality of first pins, and a plurality of second candidate connection paths formed between the plurality of second ports and the plurality of second pins;

[0461] The cost value determination module 2302 is specifically used to: obtain the cost value of each first candidate connection path through a machine learning model based on the information of the plurality of first candidate connection paths and the information of the plurality of second candidate connection paths.

[0462] The routing determination module 2303 is specifically used to: determine at least one first target connection path from the plurality of first candidate connection paths based on the cost value of each of the first candidate connection paths.

[0463] In one possible implementation, at least two of the plurality of first candidate connection paths intersect; or...

[0464] Each of the second candidate connection paths does not intersect with any of the plurality of first candidate connection paths; or...

[0465] At least one second candidate connection path intersects with at least one of the plurality of first candidate connection paths; or,

[0466] At least two of the plurality of second candidate connection paths intersect.

[0467] In one possible implementation, the device further includes:

[0468] The output module is configured to output multiple first initial candidate connection paths between the multiple first ports and the multiple first pins, and to obtain the multiple first initial candidate connection paths based on modification instructions for at least one of the multiple first initial candidate connection paths.

[0469] In one possible implementation, the device further includes:

[0470] The location information of the relay point in the output module is used to output the connection path of the at least one first target.

[0471] In one possible implementation, the first function or the second function is one of the following: signal transmission, grounding, or power transmission.

[0472] In one possible implementation, the cost value determination module 2302 is further configured to: obtain the cost value of each second candidate connection path through the machine learning model based on the information of the at least one first target connection path and the information of the plurality of second candidate connection paths;

[0473] The routing determination module 2303 is further configured to: determine at least one second target connection path from the plurality of second candidate connection paths based on the cost value of each second candidate connection path.

[0474] In one possible implementation, when the cost value of each second candidate connection path is obtained through the machine learning model, the other first candidate connection paths among the plurality of first candidate connection paths, except for the at least one first target connection path, are not used as input to the machine learning model.

[0475] In one possible implementation, the plurality of candidate connection paths further includes at least one third candidate connection path formed between the plurality of second ports and the plurality of second pins, and the cost determination module 2302 is specifically used for:

[0476] Based on the information of the at least one first target connection path, the information of the plurality of second candidate connection paths, and the information of at least one third candidate connection path.

[0477] In one possible implementation, the output module is further configured to:

[0478] Output multiple second initial candidate connection paths formed between the multiple second ports and the multiple second pins, and obtain the multiple second candidate connection paths based on the modification instructions of the multiple second initial candidate connection paths.

[0479] In one possible implementation, the output module is further configured to:

[0480] Output the at least one second target connection path.

[0481] In one possible implementation, any two target connection paths in the at least one target connection path do not intersect.

[0482] In one possible implementation, the acquisition module 2301 is further configured to:

[0483] Based on the modification information of the at least one first target connection path, the modified at least one first target connection path is obtained;

[0484] The step of basing information on the at least one first target connection path and information on the plurality of second candidate connection paths includes basing information on the modified at least one first target connection path and information on the plurality of second candidate connection paths.

[0485] In one possible implementation, the first information indicates that the first port has a higher priority than the second port; or, the second information indicates that the first pin has a higher priority than the second pin.

[0486] In one possible implementation, the routing determination module 2303 is specifically used for:

[0487] Based on the cost value, at least one target connection path is determined from the plurality of candidate connection paths using the minimum cost maximum flow algorithm.

[0488] Reference Figure 24 , Figure 24 A schematic diagram of a circuit routing determination device provided in this application embodiment, wherein the device 2400 includes:

[0489] The acquisition module 2401 is used to acquire first information of multiple input / output ports of the circuit and second information of multiple transition unit pins; the multiple ports include multiple first ports and multiple second ports, and the multiple pins include multiple first pins and multiple second pins; multiple first candidate connection paths are formed between the multiple first ports and the multiple first pins, and multiple second candidate connection paths are formed between the multiple second ports and the multiple second pins.

[0490] The specific description of the acquisition module 2301 can be found in the description of step 2201 in the above embodiments, and will not be repeated here.

[0491] The routing determination module 2402 is used to determine at least one first target connection path from the plurality of first candidate connection paths based on the first information and the second information indicating that the importance of the first port is higher than that of the second port, and based on the information of the plurality of first candidate connection paths and the information of the plurality of second candidate connection paths; and to determine at least one second target connection path from the plurality of second candidate connection paths based on the information of the at least one first target connection path and the information of the plurality of second candidate connection paths.

[0492] The specific description of the routing determination module 2402 can be found in the description of step 2202 in the above embodiment, and will not be repeated here.

[0493] In one possible implementation, the port is an input / output (I / O) unit, and the pin is a bump unit.

[0494] In one possible implementation, at least two of the plurality of first candidate connection paths intersect; or...

[0495] Each of the second candidate connection paths does not intersect with any of the plurality of first candidate connection paths; or...

[0496] At least one second candidate connection path intersects with at least one of the plurality of first candidate connection paths; or,

[0497] At least two of the plurality of second candidate connection paths intersect.

[0498] In one possible implementation, the device further includes:

[0499] The output module 2403 is used to output a plurality of first initial candidate connection paths formed between the plurality of first ports and the plurality of first pins, and to obtain the plurality of first candidate connection paths based on the modification instructions of the plurality of first initial candidate connection paths.

[0500] In one possible implementation, the device further includes:

[0501] Output module 2403 is used to output the at least one first target connection path.

[0502] In one possible implementation, the first function or the second function is one of the following: signal transmission, grounding, or power transmission.

[0503] In one possible implementation, the step of basing information on the at least one first target connection path and information on a plurality of second candidate connection paths includes:

[0504] Based on the information of the at least one first connection path and the information of a plurality of second candidate connection paths, but not based on other first candidate connection paths among the plurality of first candidate connection paths other than the at least one first target connection path.

[0505] In one possible implementation, the output module 2403 is further configured to:

[0506] Output multiple second initial candidate connection paths formed between the multiple second ports and the multiple second pins, and obtain the multiple second candidate connection paths based on the modification instructions of the multiple second initial candidate connection paths.

[0507] In one possible implementation, the output module 2403 is further configured to:

[0508] Output the at least one second target connection path.

[0509] In one possible implementation, any two connection paths in the at least one first target connection path do not intersect, any two connection paths in the at least one second target connection path do not intersect, and each first target connection path does not intersect with any second target connection path in the at least one second target connection path.

[0510] In one possible implementation, the acquisition module 2401 is further configured to:

[0511] Based on the modification information of the at least one first target connection path, the modified at least one first target connection path is obtained;

[0512] The step of basing information on the at least one first target connection path and information on the plurality of second candidate connection paths includes basing information on the modified at least one first target connection path and information on the plurality of second candidate connection paths.

[0513] The following describes an execution device provided in an embodiment of this application. Please refer to [link / reference]. Figure 25 , Figure 25 This is a schematic diagram of an execution device provided in an embodiment of this application. The execution device 2500 can specifically be a mobile phone, tablet, laptop, smart wearable device, etc., and is not limited thereto. Specifically, the execution device 2500 includes: a receiver 2501, a transmitter 2502, a processor 2503, and a memory 2504 (wherein the execution device 2500 may have one or more processors 2503). Figure 25 (Taking a processor as an example), the processor 2503 may include an application processor 25031 and a communication processor 25032. In some embodiments of this application, the receiver 2501, transmitter 2502, processor 2503, and memory 2504 may be connected via a bus or other means.

[0514] Memory 2504 may include read-only memory and random access memory, and provides instructions and data to processor 2503. A portion of memory 2504 may also include non-volatile random access memory (NVRAM). Memory 2504 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0515] Processor 2503 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses in the diagram are referred to as the bus system.

[0516] The methods disclosed in the embodiments of this application can be applied to or implemented by processor 2503. Processor 2503 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above methods can be completed by integrated logic circuits in the hardware of processor 2503 or by instructions in software form. Processor 2503 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. Processor 2503 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 2504. Processor 2503 reads the information in memory 2504 and, in conjunction with its hardware, completes the steps of the above method.

[0517] Receiver 2501 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 2502 can be used to output digital or character information; transmitter 2502 can also be used to send instructions to the disk group to modify the data in the disk group.

[0518] In one embodiment of this application, the processor 2503 is configured to execute... Figure 7a as well as Figure 22 The steps of the circuit routing determination method in the corresponding embodiment.

[0519] This application also provides a server; please refer to [link / reference]. Figure 26 , Figure 26This is a schematic diagram of a server structure provided in an embodiment of this application. Specifically, server 2600 is implemented by one or more servers. Server 2600 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 2626 (e.g., one or more processors) and memory 2632, and one or more storage media 2630 (e.g., one or more mass storage devices) for storing application programs 2642 or data 2644. The memory 2632 and storage media 2630 can be temporary or persistent storage. The program stored in storage media 2630 may include one or more modules (not shown in the diagram), each module may include a series of instruction operations on the server. Furthermore, the CPU 2626 may be configured to communicate with storage media 2630 and execute the series of instruction operations in storage media 2630 on server 2600.

[0520] Server 2600 may also include one or more power supplies 2627, one or more wired or wireless network interfaces 2650, one or more input / output interfaces 2658; or, one or more operating systems 2641, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0521] In this embodiment, the central processing unit 2626 is used to execute... Figure 7a as well as Figure 22 The steps of the circuit routing determination method in the corresponding embodiment.

[0522] This application also provides a computer program product including computer-readable instructions, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0523] This application also provides a computer-readable storage medium storing a program for signal processing, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0524] The execution device, training device, or terminal device provided in this application embodiment can specifically be a chip. The chip includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip within the execution device to execute the circuit routing determination method described in the above embodiments, or to cause the chip within the training device to execute the steps related to model training in the above embodiments. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0525] For details, please refer to Figure 27 , Figure 27 This is a schematic diagram of a chip provided in an embodiment of this application. The chip can be represented as a neural network processor (NPU) 2700. The NPU 2700 is mounted as a coprocessor on the host CPU, and tasks are assigned by the host CPU. The core part of the NPU is the arithmetic circuit 2703, which is controlled by a controller 2704 to retrieve matrix data from the memory and perform multiplication operations.

[0526] In some implementations, the arithmetic circuit 2703 internally includes multiple processing engines (PEs). In some implementations, the arithmetic circuit 2703 is a two-dimensional pulsating array. The arithmetic circuit 2703 can also be a one-dimensional pulsating array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 2703 is a general-purpose matrix processor.

[0527] For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 2702 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 2701 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 2708.

[0528] Unified memory 2706 is used to store input and output data. Weight data is directly transferred to weight memory 2702 via Direct Memory Access Controller (DMAC) 2705. Input data is also transferred to unified memory 2706 via DMAC.

[0529] BIU stands for Bus Interface Unit 2710, which is used for interaction between the AXI bus and the DMAC and the Instruction Fetch Buffer (IFB) 2709.

[0530] The Bus Interface Unit (BIU) 2710 is used by the instruction fetch memory 2709 to fetch instructions from external memory, and also by the memory access controller 2705 to fetch the original data of the input matrix A or the weight matrix B from external memory.

[0531] The DMAC is mainly used to move input data from external memory DDR to unified memory 2706, or to weight data to weight memory 2702, or to input data to input memory 2701.

[0532] The vector computation unit 2707 includes multiple arithmetic processing units that further process the output of the computation circuit as needed, such as vector multiplication, vector addition, exponential operations, logarithmic operations, size comparisons, etc. It is mainly used for computation in non-convolutional / fully connected layers of neural networks, such as batch normalization, pixel-level summation, and upsampling of feature planes.

[0533] In some implementations, vector computation unit 2707 can store the processed output vector in unified memory 2706. For example, vector computation unit 2707 can apply a linear function, or a nonlinear function, to the output of computation circuit 2703, such as linear interpolation of feature planes extracted by a convolutional layer, or, for example, a vector of accumulated values, to generate activation values. In some implementations, vector computation unit 2707 generates normalized values, pixel-level summed values, or both. In some implementations, the processed output vector can be used as activation input to computation circuit 2703, for example, for use in subsequent layers of the neural network.

[0534] The instruction fetch buffer 2709 connected to the controller 2704 is used to store the instructions used by the controller 2704;

[0535] The unified memory 2706, input memory 2701, weighted memory 2702, and instruction fetch memory 2709 are all on-chip memories. External memory is proprietary to this NPU hardware architecture.

[0536] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above program.

[0537] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0538] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0539] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0540] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A method of determining a circuit trace, characterized by, The method comprises: obtaining first information of a plurality of ports of a circuit and second information of a plurality of pins; a plurality of candidate connection paths are included between the plurality of ports and the plurality of pins; the candidate connection path is a connection path between a port and a pin; the first information indicates a position characteristic of the port; and the second information indicates a position characteristic of the pin; obtaining, by a machine learning model, a value of each of the candidate connection paths according to the first information and the second information, the value indicating an influence of the candidate connection path on a total number of connection paths between the plurality of ports and the plurality of pins; and the value is used to determine at least one target connection path from the plurality of candidate connection paths.

2. The method of claim 1, wherein, The method further comprises: determining, according to the value, at least one target connection path from the plurality of candidate connection paths; or sending the value to a terminal device, the value being used to instruct the terminal device to determine at least one target connection path from the plurality of candidate connection paths according to the value.

3. The method of claim 2, wherein, The plurality of ports comprises a plurality of first ports and a plurality of second ports, and the plurality of pins comprises a plurality of first pins and a plurality of second pins; the plurality of first ports and the plurality of first pins are used to implement a first function; the plurality of second ports and the plurality of second pins are used to implement a second function; and the first function and the second function are different; The plurality of candidate connection paths comprises a plurality of first candidate connection paths formed between the plurality of first ports and the plurality of first pins, and a plurality of second candidate connection paths formed between the plurality of second ports and the plurality of second pins; The method further comprises: obtaining, by a machine learning model, a value of each of the candidate connection paths according to the first information and the second information, the value indicating an influence of the candidate connection path on a total number of connection paths between the plurality of ports and the plurality of pins; and the value is used to determine at least one target connection path from the plurality of candidate connection paths.

4. The method of claim 3, wherein, The method further comprises: determining, according to the value, at least one target connection path from the plurality of candidate connection paths; or sending the value to a terminal device, the value being used to instruct the terminal device to determine at least one target connection path from the plurality of candidate connection paths according to the value. The plurality of ports comprises a plurality of first ports and a plurality of second ports, and the plurality of pins comprises a plurality of first pins and a plurality of second pins; the plurality of first ports and the plurality of first pins are used to implement a first function; the plurality of second ports and the plurality of second pins are used to implement a second function; and the first function and the second function are different; The plurality of candidate connection paths comprises a plurality of first candidate connection paths formed between the plurality of first ports and the plurality of first pins, and a plurality of second candidate connection paths formed between the plurality of second ports and the plurality of second pins; The method further comprises: obtaining, by a machine learning model, a value of each of the candidate connection paths according to the first information and the second information, the value indicating an influence of the candidate connection path on a total number of connection paths between the plurality of ports and the plurality of pins; and the value is used to determine at least one target connection path from the plurality of candidate connection paths. The method further comprises: determining, according to the value, at least one target connection path from the plurality of candidate connection paths; or sending the value to a terminal device, the value being used to instruct the terminal device to determine at least one target connection path from the plurality of candidate connection paths according to the value.

5. The method of claim 4, wherein each of the second candidate connection paths is disjoint from the plurality of first candidate connection paths.

6. The method of claim 5, wherein, The plurality of candidate connection paths further include at least one third candidate connection path formed between the plurality of second ports and the plurality of second pins, the at least one third candidate connection path intersects with other first candidate connection paths in the plurality of first candidate connection paths except the at least one first target connection path, and the information according to the at least one first target connection path and the information of the plurality of second candidate connection paths include: The information according to the at least one first target connection path, the plurality of second candidate connection paths and at least one third candidate connection path.

7. The method of any one of claims 4 to 6, characterized in that, Each of the second target connection paths does not intersect with the at least one first target connection path.

8. The method of claim 4, wherein, The method further includes: obtaining a modified at least one first target connection path based on modification information of the at least one first target connection path; The information according to the at least one first target connection path and the information of the plurality of second candidate connection paths includes: the information according to the modified at least one first target connection path and the information of the plurality of second candidate connection paths.

9. The method of claim 4, wherein, The method further includes: outputting the at least one second target connection path.

10. The method of claim 3 or 4, wherein, The method further includes: outputting the at least one first target connection path.

11. The method of claim 3 or 4, wherein, The first function or the second function is one of the following: signal transmission, grounding, and power transmission.

12. The method of claim 3 or 4, wherein, The first information indicates that the priority of the first port is higher than the priority of the second port, or the second information indicates that the priority of the first pin is higher than the priority of the second pin.

13. The method according to any one of claims 2 to 4, characterized in that, The value of the candidate connection path is used to indicate the negative influence of the candidate connection path on the total number of connection paths between the plurality of ports and the plurality of pins; the plurality of candidate connection paths include a plurality of groups of candidate connection paths, each group of candidate connection paths in the plurality of groups of candidate connection paths corresponds to a pair of port and pin; The at least one target connection path is determined from the plurality of candidate connection paths according to the value of the candidate connection path, including: According to the value of the candidate connection path, the candidate connection path with the lowest value in each group of candidate connection paths is determined as the target connection path.

14. The method of any one of claims 2 to 4, wherein, The at least one target connection path is determined from the plurality of candidate connection paths according to the value of the candidate connection path, including: According to the value of the candidate connection path, at least one target connection path is determined from the plurality of candidate connection paths by a minimum cost maximum flow algorithm.

15. The method according to any one of claims 1 to 4, characterized in that, The first information further indicates at least one of the following information: function of the port or priority of the port; The second information further indicates at least one of the following information: function of the pin or priority of the pin.

16. The method according to any one of claims 1 to 4, characterized in that, The candidate connection path includes two ports and pins at both ends and at least one relay point through which the candidate connection path passes, and the relay point is an intermediate position point between adjacent pins; The first information and the second information include: According to first information of ports included in the candidate connection path, second information of pins included in the candidate connection path, and position information of the at least one relay point.

17. The method of any one of claims 1 to 4, wherein, The ports are input-output (I / O) units, and the pins are bump units.

18. A circuit routing determination apparatus characterized by comprising: The apparatus includes: An acquisition module configured to acquire first information of a plurality of ports of a circuit and second information of a plurality of pins, the plurality of ports and the plurality of pins including a plurality of candidate connection paths therebetween, the candidate connection path being a connection path between a port and a pin, the first information indicating a position characteristic of the port, and the second information indicating a position characteristic of the pin; A generation value determination module configured to obtain, by a machine learning model, a generation value of each of the candidate connection paths according to the first information and the second information, the generation value indicating an influence of the candidate connection path on a total number of connection paths between the plurality of ports and the plurality of pins, and the generation value being used to determine at least one target connection path from the plurality of candidate connection paths.

19. The apparatus of claim 18, wherein, The apparatus further includes: A routing determination module configured to determine at least one target connection path from the plurality of candidate connection paths according to the generation value; or A sending module configured to send the generation value to a terminal device, the generation value being used to instruct the terminal device to determine at least one target connection path from the plurality of candidate connection paths.

20. The apparatus of claim 19, wherein, The plurality of ports include a plurality of first ports and a plurality of second ports, and the plurality of pins include a plurality of first pins and a plurality of second pins, the plurality of first ports and the plurality of first pins being used to implement a first function, and the plurality of second ports and the plurality of second pins being used to implement a second function, the first function and the second function being different; The plurality of candidate connection paths include a plurality of first candidate connection paths formed between the plurality of first ports and the plurality of first pins, and a plurality of second candidate connection paths formed between the plurality of second ports and the plurality of second pins; The generation value determination module is specifically configured to obtain, by a machine learning model, a generation value of each of the first candidate connection paths according to information of the plurality of first candidate connection paths and information of the plurality of second candidate connection paths; The routing determination module is specifically configured to determine at least one first target connection path from the plurality of first candidate connection paths according to the generation value of each of the first candidate connection paths.

21. The apparatus of claim 20, wherein, The generation value determination module is further configured to obtain, by the machine learning model, a generation value of each of the second candidate connection paths according to information of the at least one first target connection path and information of the plurality of second candidate connection paths; The routing determination module is further configured to determine at least one second target connection path from the plurality of second candidate connection paths according to the generation value of each of the second candidate connection paths.

22. The apparatus of claim 21, wherein Each of the second candidate connection paths is disjoint from the plurality of first candidate connection paths.

23. The apparatus of claim 22, wherein, The plurality of candidate connection paths further include at least one third candidate connection path formed between the plurality of second ports and the plurality of second pins, the at least one third candidate connection path intersects with other first candidate connection paths in the plurality of first candidate connection paths except the at least one first target connection path, and the value determination module is specifically configured to: determine the at least one first target connection path according to information of the at least one first target connection path, information of the plurality of second candidate connection paths, and information of the at least one third candidate connection path.

24. The apparatus according to any one of claims 21 to 23, wherein each second target connection path does not intersect with the at least one first target connection path.

25. The apparatus of any one of claims 21 to 23, wherein, The acquisition module is further configured to: obtain a modified at least one first target connection path based on modification information of the at least one first target connection path. The value determination module is specifically configured to determine the at least one second target connection path according to information of the modified at least one first target connection path and information of the plurality of second candidate connection paths.

26. The apparatus of any one of claims 21 to 23, wherein, The apparatus further includes: an output module configured to output the at least one second target connection path.

27. The apparatus of any one of claims 20 to 23, wherein, The apparatus further includes: an output module configured to: output the at least one first target connection path.

28. The apparatus of claim 25, wherein, The first function or the second function is one of the following: signal transmission, grounding, and power transmission.

29. The apparatus of any one of claims 20 to 23, wherein, The first information indicates that a priority of the first port is higher than a priority of the second port, or the second information indicates that a priority of the first pin is higher than a priority of the second pin.

30. The apparatus of any one of claims 19 to 23, wherein, The value is used to indicate a negative influence of a candidate connection path on a total number of connection paths between the plurality of ports and the plurality of pins, and the plurality of candidate connection paths include a plurality of groups of candidate connection paths, each group of candidate connection paths corresponding to a pair of port and pin. The routing determination module is specifically configured to: determine, according to the value, a candidate connection path with a lowest value in each group of candidate connection paths as the target connection path.

31. The apparatus of any one of claims 19 to 23, wherein, The routing determination module is specifically configured to: determine, according to the value, at least one target connection path from the plurality of candidate connection paths by using a minimum cost maximum flow algorithm.

32. The apparatus of any one of claims 18 to 23, wherein, The first information further indicates at least one of the following: a function of a port or a priority of a port. The second information further indicates at least one of the following: a function of a pin or a priority of a pin.

33. The apparatus of any one of claims 18 to 23, wherein, The candidate connection path includes a pair of port and pin at two ends and at least one relay point through which the candidate connection path passes, and the relay point is an intermediate position point between adjacent pins. The determination according to the first information and the second information includes: determining the at least one relay point according to first information of a port included in the candidate connection path, second information of a pin included in the candidate connection path, and position information of the at least one relay point.

34. The apparatus of any one of claims 18 to 23, wherein, The port is an input and output (I / O) unit, and the pin is a bump unit.

35. A circuit routing determination apparatus, comprising: The apparatus includes a memory and a processor; the memory stores a code, and the processor is configured to acquire the code and perform the method of any one of claims 1 to 17.

36. A computer-readable storage medium, characterized in that, Computer readable instructions are included which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 17.

37. A computer program product, characterised in that, Computer readable instructions are included which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 17.

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