Input / Output Circuit and Control System of an Ion Trap Quantum Computer

Abstract

The present invention discloses an input / output circuit for an ion trap quantum computer, which includes a data communication circuit module, a data drive circuit module, and a power supply module. Among them, the data communication circuit module is used to convert the control signals sent by the control board of the ion trap quantum computer into digital IO signals and send the digital IO signals to the data drive circuit module; the data drive circuit module is used to electrically isolate the digital IO signals and then output them to the laser optical path switching switch of the ion trap quantum computer to control the on / off of the laser optical path; the power supply module is used to provide a power supply for the data communication circuit module and the digital signal drive circuit module, and to provide an isolated power supply for the digital signal drive circuit. The present invention has the characteristics of high speed, multiple channels, and low delay. The present invention also discloses an ion trap quantum computer control system.

Description

Technical Field

[0001] The present invention relates to the control of an ion trap quantum computer, and particularly to an input / output circuit of an ion trap quantum computer and an ion trap quantum computer control system. Background Art

[0002] When operating an ion trap quantum computer, high-speed and low-latency data communication, processing, and digital signal output boards with multiple channels are required to provide precise control of the ion trap quantum computer. That is, high-speed DIO signals with a frequency of 150 MHz and a pulse width of 5 ns need to be processed, and the number of channels can be as many as 80. However, existing DIO circuit boards cannot meet the above requirements in terms of functions such as speed, latency, and the number of channels. Summary of the Invention

[0003] In order to overcome the deficiencies of the prior art, one of the objectives of the present invention is to provide an input / output circuit of an ion trap quantum computer, which can solve problems such as slow speed, long latency, and few channels of existing DIO boards.

[0004] Another objective of the present invention is to provide an ion trap quantum computer control system, which can solve problems such as slow speed, long latency, and few channels of existing DIO boards.

[0005] One of the objectives of the present invention is achieved by adopting the following technical solutions:

[0006] An input / output circuit of an ion trap quantum computer includes a data communication circuit module, a data driving circuit module, and a power supply module. Among them, the input end of the data communication circuit module is communicatively connected to the control board of the ion trap quantum computer, and the output end is electrically connected to the data driving circuit module, and is used to convert the control signal sent by the control board of the ion trap quantum computer received into a digital IO signal and send the digital IO signal to the data driving circuit module. The data driving circuit module is electrically connected to the laser optical path switching switch of the ion trap quantum computer, and is used to electrically isolate the digital IO signal and output it to the laser optical path switching switch of the ion trap quantum computer to control the on / off of the laser optical path.

[0007] The power supply module is electrically connected to the data communication circuit module and the digital signal driving circuit module, and is used to provide a power supply for the data communication circuit module and the digital signal driving circuit module, and provide an isolated power supply for the digital driving circuit module.

[0008] Further, the data communication circuit module is electrically connected to the control board through LVDS signal lines, and is used to receive multiple LVDS differential signals sent by the control board and convert each LVDS differential signal into a corresponding digital IO signal.

[0009] Furthermore, the data communication circuit module includes a plurality of half-duplex four-channel LVDS signal transceivers, and each half-duplex four-channel LVDS signal transceiver is configured to receive four-way LVDS differential signals sent by the control board and convert the four-way LVDS differential signals into corresponding digital IO signals respectively.

[0010] Furthermore, the data driving circuit module includes a plurality of electrical isolation circuit modules and a plurality of output isolation circuit modules; wherein, each electrical isolation circuit module is electrically connected to a corresponding LVDS signal transceiver chip respectively, and is configured to obtain four-way digital IO signals, perform electrical isolation on the four-way digital IO signals, and send the electrically isolated digital IO signals to the corresponding output isolation circuit module; each output isolation circuit module is configured to transmit each electrically isolated digital IO signal to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer through a corresponding SMA connector.

[0011] Furthermore, each electrical isolation circuit module includes a first digital isolator chip and a second first digital isolator chip; wherein, both the first digital isolator chip and the second digital isolator chip are electrically connected to a corresponding LVDS signal transceiver chip respectively, and are configured to receive four-way digital IO signals sent by the corresponding LVDS signal transceiver.

[0012] Each output isolation circuit module includes a bus transceiver chip, and the bus transceiver chip is electrically connected to the first digital isolation chip and the second digital isolation chip of the corresponding electrical isolation circuit module, and is configured to send the four-way electrically isolated digital IO signals to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer through the corresponding SMA connectors respectively.

[0013] Furthermore, four output terminals of the first digital isolator chip and four input terminals of the second digital isolator chip are electrically connected to corresponding ports of the corresponding first LVDS signal transceiver chip respectively; four input terminals of the first digital isolator chip and four output terminals of the second digital isolator chip are electrically connected to four input terminals of the bus transceiver chip correspondingly; four output terminals of the bus transceiver chip are electrically connected to the corresponding SAM connectors through corresponding resistors respectively.

[0014] The first VDD terminal and the first EN terminal of the first digital isolator chip are both connected to a first isolation power supply, the second VDD terminal and the second EN terminal are connected to a first power supply, the first grounding terminal is connected to a grounded isolation power supply, and the second grounding terminal is grounded; the first EN terminal and the first VDD terminal of the second digital isolator chip are connected to a first power supply, the second VDD terminal is connected to a first isolation power supply, the second grounding terminal is connected to a grounded isolation power supply, and the first grounding terminal is grounded.

[0015] The second EN terminal of the second digital isolation chip is electrically connected to the G terminal of the MOS transistor T27 through the resistor R17, and the fifth output terminal of the first digital isolation chip is electrically connected to the G terminal of the MOS transistor T27; the S terminal of the MOS transistor T27 is grounded, and the D terminal is connected to the first isolation power supply through the resistor R210; the DIR terminal of the bus transceiver chip is connected between the resistor R210 and the D terminal of the MOS transistor T27;

[0016] The ground terminal of the bus transceiver chip is connected to the ground isolation power supply, and the power supply terminal is connected to the first isolation power supply.

[0017] Further, the fourth input terminal of the first digital isolator chip and the fourth output terminal of the second digital isolator chip are electrically connected to the first input terminal and the second input terminal of the bus transceiver chip through the resistor R9; the third input terminal of the first digital isolator chip and the third output terminal of the second digital isolator chip are electrically connected to the third input terminal and the fourth input terminal of the bus transceiver chip through the resistor R7; the second input terminal of the first digital isolator chip and the second output terminal of the second digital isolator chip are electrically connected to the fifth input terminal and the sixth input terminal of the bus transceiver chip through the resistor R6; the first input terminal of the first digital isolator chip and the first output terminal of the second digital isolator chip are electrically connected to the seventh input terminal and the eighth input terminal of the bus transceiver chip through the resistor R29;

[0018] The first output terminal and the second output terminal of the bus transceiver chip are electrically connected to the first SMA connector through the resistor R10 to output the first digital IO signal to the first channel of the ion trap quantum computer;

[0019] The third output terminal and the fourth output terminal of the bus transceiver chip are electrically connected to the second SMA connector through the resistor R8 to output the second digital IO signal to the second channel of the ion trap quantum computer;

[0020] The fifth output terminal and the sixth output terminal of the bus transceiver chip are electrically connected to the third SMA connector through the resistor R5 to output the third digital IO signal to the third channel of the ion trap quantum computer;

[0021] The seventh output terminal and the eighth output terminal of the bus transceiver chip are electrically connected to the fourth SMA connector through the resistor R4 to output the fourth digital IO signal to the fourth channel of the ion trap quantum computer;

[0022] One end of resistor R209 is connected to the ground isolation power supply, and the other end is connected between resistor R10 and the bus transceiver chip. One end of resistor R208 is electrically connected to the D terminal of transistor T13, and the other end is connected between the first SMA connector and resistor R10. The S terminal of MOS transistor T13 is connected to the ground isolation power supply, and the G terminal is electrically connected to the positive electrode of diode LD9A through resistor R216. The negative electrode of diode LD9A is connected to the ground isolation power supply;

[0023] One end of resistor R206 is connected to the ground isolation power supply, and the other end is connected between resistor R8 and the bus transceiver chip. One end of resistor R205 is electrically connected to the D terminal of transistor T12, and the other end is connected between the second SMA connector and resistor R8. The S terminal of MOS transistor T12 is connected to the ground isolation power supply, and the G terminal is electrically connected to the positive electrode of diode LD9B through resistor R215. The negative electrode of diode LD9B is connected to the ground isolation power supply;

[0024] One end of resistor R203 is connected to the ground isolation power supply, and the other end is connected between resistor R5 and the bus transceiver chip. One end of resistor R202 is electrically connected to the D terminal of transistor T11, and the other end is connected between the third SMA connector and resistor R5. The S terminal of MOS transistor T11 is connected to the ground isolation power supply, and the G terminal is electrically connected to the positive electrode of diode LD10A through resistor R214. The negative electrode of diode LD10A is connected to the ground isolation power supply;

[0025] One end of resistor R200 is connected to the ground isolation power supply, and the other end is connected between resistor R4 and the bus transceiver chip. One end of resistor R199 is electrically connected to the D terminal of transistor T10, and the other end is connected between the fourth SMA connector and resistor R4. The S terminal of MOS transistor T10 is connected to the ground isolation power supply, and the G terminal is electrically connected to the positive electrode of diode LD10B through resistor R213. The negative electrode of diode LD10B is connected to the ground isolation power supply.

[0026] Further, the power supply module includes a main power supply module and an isolation power supply module; wherein, the main power supply module is connected to the data communication circuit module and the data driving circuit module, and is used to convert the externally connected power supply into a first power supply; the isolation power supply module is electrically connected to the data driving circuit module, and is used to convert the externally connected power supply into a first isolation power supply and a ground isolation power supply.

[0027] The second object of the present invention is achieved by the following technical solutions:

[0028] An ion trap quantum computer control system includes a control board, an ion trap quantum computer, and an input / output circuit of an ion trap quantum computer adopted for one of the purposes of the present invention. Among them, the input end of the input / output circuit of the ion trap quantum computer is communicatively connected to the control board, and the output end is electrically connected to the ion trap quantum computer. It is used to receive multiple control signals sent by the control board, convert them into multiple digital IO signals, and after electrically isolating each digital IO signal, send it to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer to control the on / off of the laser optical path switching switch of the corresponding channel.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] The present invention realizes multiple control signals sent by the host computer or the control board by setting a data communication circuit module and a data driving circuit module, converts each control signal into a digital IO signal, and performs electrical isolation and drive amplification, so as to realize the multi-channel control of the ion trap quantum computer. Moreover, the present invention also has the characteristics of low delay and high speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a module diagram of the input / output circuit of the ion trap quantum computer provided by the present invention;

[0032] Figure 2 It is a circuit diagram of the main power supply module;

[0033] Figure 3 It is a circuit diagram of the isolated power supply module of the isolated power supply module;

[0034] Figure 4 It is a circuit diagram of the IDC socket in a LVDS signal transceiver chip group;

[0035] Figure 5 It is a schematic diagram of the circuit connection of the first LVDS signal transceiver chip, the first switch and the chip IC42 in a LVDS signal transceiver chip group;

[0036] Figure 6 It is a schematic diagram of the circuit connection of the electrical isolation circuit module and the output isolation circuit module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] Next, in combination with the drawings and the specific embodiments, the present invention will be further described. It should be noted that on the premise of no conflict, the following described embodiments or technical features can be combined arbitrarily to form new embodiments.

[0038] The present invention provides an input / output circuit of an ion trap quantum computer, as Figure 1As shown, it includes a data communication circuit module, a data driving circuit module, and a power supply module.

[0039] Among them, the input end of the data communication circuit module is electrically connected to the control board of the ion trap quantum computer, and the output end is electrically connected to the data driving circuit module. It is used to receive the control signals sent by the control board of the ion trap quantum computer and forward the control signals to the data driving circuit module.

[0040] The output end of the data driving circuit module is electrically connected to the ion trap quantum computer. It is used to perform electrical isolation on the received control signals and then drive and send them to the ion trap quantum computer to achieve the control of the ion trap quantum computer. Specifically, the data driving circuit module is electrically connected to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer through a corresponding SMA plug to achieve the control of the laser on / off of multiple channels of the ion trap quantum computer. The present invention can achieve the control of multiple channels of the ion trap quantum computer. At the same time, the present invention also has the characteristics of fast speed and low delay, and can meet the control of the current ion trap quantum computer.

[0041] Furthermore, the data communication circuit module in the present invention adopts a high-speed data communication circuit module. Through the high-speed data communication circuit module, various received control instructions and data are converted into digital IO signals and then sent to the data driving circuit module. Thus, the data driving circuit module performs electrical isolation on the digital IO signals and improves the driving ability and then provides them to the ion trap quantum computer to achieve the control of multiple channels of the ion trap quantum computer. At the same time, the use of a high-speed data communication circuit module can achieve fast data communication, improve data transmission efficiency, and reduce data transmission delay.

[0042] Furthermore, the data communication circuit module is electrically connected to the control board through a long-distance LVDS signal line. That is, the control board sends various data and instructions to the data communication circuit module in the form of LVDS differential signals through a long-distance LVDS signal line. At the same time, the data communication circuit module receives the LVDS differential signals, converts them into single-ended digital IO signals, and then sends the data IO signals to the data driving circuit module.

[0043] Furthermore, the data communication circuit module includes multiple half-duplex four-channel LVDS signal transceivers. Each half-duplex four-channel LVDS signal transceiver is used to receive four-way LVDS differential signals sent by the control board and convert the four-way LVDS differential signals into corresponding digital IO signals.

[0044] Specifically, eight-way LVDS signal lines can be introduced into two half-duplex four-channel LVDS signal transceivers in each LVDS signal transceiver chipset through a 2.54 mm pitch IDC socket with 30 pins. The model of the IDC socket is N2530-6002RB.

[0045] The half-duplex four-channel LVDS signal transceiver is implemented using a chip with the model number SN65MLVD040RGZT, which converts the received four-channel differential LVDS signals into corresponding single-ended digital IO signals in the 3.3V TTL standard. This chip is a high-speed signal transceiver that can process data signals up to 250 MHz or clock signals up to 125 MHz, meeting the index requirements of the system's data signal communication at a frequency of 125 MHz.

[0046] That is to say, the data communication circuit module includes multiple LVDS signal transceiver chipsets, multiple IDC sockets, and multiple first switches. Among them, each LVDS signal transceiver chipset includes a first LVDS signal transceiver chip and a second LVDS signal transceiver chip. That is, any two LVDS signal transceiver chips are grouped together to achieve electrical isolation of the four-channel digital IO signals.

[0047] At the same time, each LVDS signal transceiver chipset corresponds to an IDC socket and a first switch. One IDC socket is electrically connected to two LVDS signal transceiver chips. One switch is connected to two LVDS signal transceivers. That is, the first end of the first switch is connected between the first LVDS signal transceiver and the power supply module, and the second end is connected between the second LVDS signal transceiver and the power supply module to realize the on-off of the power supply of the two LVDS signal transceivers.

[0048] One LVDS signal transceiver chipset given in this embodiment includes a first LVDS signal transceiver chip, a second LVDS signal transceiver chip, an IDC socket, and a first switch.

[0049] Among them, the IDC socket is electrically connected to the control board through LVDS signal lines and is used to receive eight-way LVDS differential signals sent by the control board.

[0050] The four input terminals of the first LVDS signal transceiver chip and the four input terminals of the second LVDS signal transceiver chip are respectively electrically connected to the corresponding ports of the IDC socket and are respectively used to receive four-channel LVDS differential signals. Each LVDS signal transceiver chip converts the received four-channel LVDS signal differential signals into four-channel digital IO signals and sends them to the data driving circuit module.

[0051] Specifically, as Figure 4-5As shown, the first LVDS signal transceiver chip is chip IC41. That is, port 47 and port 48 of chip IC41 are respectively and electrically connected to port 2 and port 3 of IDC socket J16; port 3 and port 4 of chip IC41 are respectively and electrically connected to port 5 and port 6 of IDC socket J16; port 9 and port 10 of chip IC41 are respectively and electrically connected to port 8 and port 9 of IDC socket J16; port 13 and port 14 of chip IC41 are respectively and electrically connected to port 11 and port 12 of IDC socket J16.

[0052] Similarly, port 14, port 15, port 17, port 18, port 20, port 21, port 23, and port 24 of IDC socket J16 are electrically connected to the corresponding ports of the second LVDS signal transceiver chip.

[0053] Among them, the circuit connection schematic diagram of the second LVDS signal transceiver chip is the same as that of the first LVDS signal transceiver chip, which is not shown in this embodiment, and the connection method is the same.

[0054] Furthermore, a power supply module is used to convert an external power supply into a first power supply for use by the data communication circuit module. Specifically, in this embodiment, the external power supply is 12V and the first power supply is 3.3V.

[0055] That is, port 1, port 40, port 5, port 42, port 8, port 19, port 12, and port 21 of chip IC41 are all electrically connected to the power supply module through resistor R197 to access the first power supply, that is, 3.3V.

[0056] Port 39, port 41, port 20, and port 22 of chip IC41 are all grounded through resistor R211 and grounded through resistor R198.

[0057] The VCC terminal and PDN terminal of chip IC41 are connected to 3.3V, and the GND terminal is connected to ground.

[0058] Furthermore, port 1 of the first switch SW9 is connected between chip IC41 and resistor R197, and the power supply of chip IC41 is controlled by the first switch SW9 to control the operation of chip IC41. Similarly, port 2 of switch SW9 is also connected between the second LVDS signal transceiver chip and the power supply module to control the power on and off of the second LVDS signal transceiver chip, which is not shown in this embodiment.

[0059] Further, in order to control the operation of the IDC socket, the LVDS signal transceiver chipset further includes chip IC42. Port 14 and port 15 of chip IC42 are respectively and electrically connected to port 26 and port 27 of IDC socket J16, and port 2 and port 3 are connected to the first power supply.

[0060] Port 1 of chip IC42 is grounded, port 16 is grounded through capacitor C163, port 8 is grounded, and port 4, port 5, port 6, and port 7 are connected to port 1 of switch SW9.

[0061] The output signal of IC42 is controlled by the first switch SW9, thereby realizing the control of IDC socket J16. That is, by turning on the switch through the first switch SW9, the operation of IDC socket J16 and chip IC14 can be controlled, and the startup of IDC socket J16 can be controlled.

[0062] Furthermore, the power supply module includes a main power supply module and an isolated power supply module. The power supply module in the present invention adopts a high-precision power circuit module, which can provide a stable and reliable power supply for the data driving circuit module and the data communication circuit module, and can also provide an isolated power supply for the data driving circuit module to achieve electrical isolation of signals.

[0063] Among them, the main power supply module is used to convert the externally connected power supply into the first power supply for use by the data communication circuit module and the data communication driving circuit module. For example, the externally connected power supply in the present invention is a 12V power supply, and the first power supply is a 3.3V power supply. More specifically, the main power supply module uses a buck chip with the model of TPS62175DQC to achieve power conversion, converting the 12V power supply into a 3.3V power supply.

[0064] More specifically, as Figure 2 shown, the main power supply module includes buck chip IC49, the first power filter module, the second power filter module, and second inductor L2.

[0065] Among them, port 2 and port 3 (VIN terminal, EN terminal) of buck chip IC49 are connected to the 12V power supply, and port 9 (SW terminal) outputs a 3.3V power supply through second inductor L2.

[0066] The first power filter module includes a parallel circuit composed of capacitor C191 and capacitor C192, and is used for filtering the connected 12V power supply to ensure the stability of the connected 12V power supply. Among them, one end of capacitor C191 and capacitor C192 is grounded, and the other end is electrically connected to port 2 and port 3 of buck chip IC49.

[0067] The second power supply filtering module includes a parallel circuit composed of capacitor C189 and capacitor C190 to filter the output 3.3V power supply to ensure the stability of the output 3.3V power supply. Among them, one end of capacitor C189 and capacitor C190 is grounded, and the other end is connected to the second end of the second inductor L2. The first end of the second inductor L2 is electrically connected to port 9 of the buck chip IC49.

[0068] Port 6, port 1, and port 11 of the buck chip IC49 are all grounded.

[0069] Port 8 of the buck chip IC49 is electrically connected to the second end of the second inductor L2, and the output power supply is fed back to the buck chip IC49 to adjust the output 3.3V power supply to ensure a stable output power supply.

[0070] One end of resistor R231 is grounded through resistor R237, and the other end is electrically connected to the second end of the second inductor L2. Port 10 of the buck chip IC49 is connected between the second end of the second inductor L2 and resistor R231, and port 5 is connected between resistor R231 and resistor R237.

[0071] The isolated power supply module is used to provide an isolated power supply for the data driving circuit module to achieve electrical isolation and the operation of the isolated output circuit. Specifically, the isolated power supply module is used to provide a first isolated power supply, that is, a 5V isolated power supply (P5V0_IOS) and a grounded isolated power supply (GND_IOS).

[0072] The first isolated power supply module uses an isolated power supply chip of model TMH1205S and a chip of model NXE2S1205MC to isolate the external power supply and convert the external power supply into a first isolated power supply and a grounded isolated power supply for use by the data driving circuit module. Specifically, as Figure 3 shown, the isolated power supply includes chip IC53, chip ICl, the third power supply filtering module, the first inductor L1, and capacitor C2. Among them, port 1 of chip IC53 is connected to the 12V power supply, port 2 is grounded, port 4 outputs the grounded isolated power supply, and port 6 outputs the first isolated power supply, that is, the 5V isolated power supply, through the first inductor L1. The model of chip IC53 is TMH1205S, and the model of chip IC1 is NXE2S1205MC.

[0073] The third power supply filtering module includes a parallel circuit composed of capacitor C170 and capacitor C169. Among them, one end of capacitor C170 and capacitor C169 is grounded, and the other end is electrically connected to port 1 of chip IC53.

[0074] One end of capacitor C2 is electrically connected to the grounded isolated power supply, and the other end is connected between chip IC46 and the first inductor L1.

[0075] The port 3 of the chip IC1 is connected to a 12V power supply, the port 1 is grounded, the port 7 is electrically connected to an isolated power supply from ground, and the port 8 is connected between the first inductor L1 and the port 6 of the chip IC53.

[0076] The ground terminal is also electrically connected to the isolated power supply from ground through the resistor R18. The chips of the isolated power supply module in the present invention can all provide a 5V isolated power supply of 400mA, and the isolation voltage can reach 1000V, ensuring sufficient isolation voltage and output power.

[0077] Furthermore, the data driving circuit module includes a plurality of electrical isolation circuit modules and a plurality of output isolation circuit modules. Among them, the input end of each electrical isolation circuit module is electrically connected to an LVDS signal transceiver chip of an LVDS signal transceiver chip group, and the output end is electrically connected to the corresponding output isolation circuit module, and is used to obtain four-way digital IO signals sent by an LVDS signal transceiver chip group and electrically isolate them and then send them to the corresponding output isolation circuit module, so that the corresponding output isolation circuit module sends each digital IO signal to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer through the corresponding SMA connector.

[0078] Furthermore, each electrical isolation circuit module includes two digital isolator chips to receive the corresponding four-way digital IO signals.

[0079] The output isolation circuit module includes a bus transceiver chip, and the bus transceiver chip is electrically connected to the two digital isolator chips of each electrical isolation circuit module, and is used to obtain the corresponding four-way digital IO signals.

[0080] That is, every four-way digital IO signals are implemented by using 2 data isolator chips of the model SI8651BB-B0IS1. This data isolator chip can achieve bidirectional electrical isolation of DC-150Mbps high-speed signals, with an isolation voltage of 5000V; at the same time, the transmission delay of the signal is as low as 10ns, and the signal delay difference between channels is as low as 0.5ns, ensuring high-speed signal quality.

[0081] Every four-way digital IO signals are implemented by using 1 bus transceiver chip, and eight-way digital IO signals are implemented by using 2 bus transceiver chips. The maximum drive current of this bus transceiver chip can reach 376mA, and the highest operating frequency can reach 300MHz, meeting the system signal frequency requirement of 125MHz.

[0082] Such as Figure 6As shown, the electrical isolation circuit module includes a first digital isolator chip IC43, a second digital isolator chip IC44, a MOS transistor T26, and a resistor R17. It is set that the electrical isolation circuit module is connected to a first LVDS signal transceiver chip IC41 in an LVDS signal transceiver chip group.

[0083] The output isolation circuit module includes a bus transceiver chip IC45.

[0084] Among them, four output terminals of the first digital isolator chip IC43 and four input terminals of the second digital isolator chip IC44 are electrically connected to the first LVDS signal transceiver chip IC41, and four input terminals of the first digital isolator chip IC43 and four output terminals of the second digital isolator chip IC44 are electrically connected to four input terminals of the bus transceiver chip IC45.

[0085] Four output terminals of the bus transceiver chip IC45 are respectively electrically connected to corresponding SAM connectors through corresponding resistors, and then deliver corresponding digital IO signals to the laser optical path switch of the corresponding channel of the ion trap quantum computer to realize the laser on / off of the corresponding channel of the ion trap quantum computer.

[0086] Specifically, port 15 of the first digital isolator chip IC43 is electrically connected to port 35 of the first LVDS signal transceiver chip IC41, port 14 of the first digital isolator chip IC43 is electrically connected to port 32 of the first LVDS signal transceiver chip IC41, port 13 of the first digital isolator chip IC43 is electrically connected to port 28 of the first LVDS signal transceiver chip IC41, and port 12 of the first digital isolator chip IC43 is electrically connected to port 25 of the first LVDS signal transceiver chip IC41.

[0087] Port 2 of the second digital isolator chip IC44 is electrically connected to port 36 of the first LVDS signal transceiver chip IC41, port 3 of the second digital isolator chip IC44 is electrically connected to port 33 of the first LVDS signal transceiver chip IC41, port 4 of the second digital isolator chip IC44 is electrically connected to port 29 of the first LVDS signal transceiver chip IC41, and port 5 of the second digital isolator chip IC44 is electrically connected to port 26 of the first LVDS signal transceiver chip IC41.

[0088] Port 5 of the first digital isolator chip IC43 is electrically connected to ports 22 and 23 of the bus transceiver chip IC45 through resistor R9. Port 4 of the first digital isolator chip IC43 is electrically connected to ports 19 and 20 of the bus transceiver chip IC45 through resistor R7. Port 3 of the first digital isolator chip IC43 is electrically connected to ports 17 and 18 of the bus transceiver chip IC45 through resistor R6. Port 2 of the first digital isolator chip IC43 is electrically connected to ports 14 and 15 of the bus transceiver chip IC45 through resistor R29.

[0089] Similarly, port 12 of the second digital isolator chip IC44 is electrically connected to ports 22 and 23 of the bus transceiver chip IC45 through resistor R9. Port 13 of the second digital isolator chip IC44 is electrically connected to ports 19 and 20 of the bus transceiver chip IC45 through resistor R7. Port 14 of the second digital isolator chip IC44 is electrically connected to ports 17 and 18 of the bus transceiver chip IC45 through resistor R6. Port 15 of the second digital isolator chip IC44 is electrically connected to ports 14 and 15 of the bus transceiver chip IC45 through resistor R29.

[0090] Ports 1 and 3 of the bus transceiver chip IC45 are electrically connected to the first SMA connector through resistor R10 to output the first digital IO signal to the first channel of the ion trap quantum computer.

[0091] Ports 4 and 6 of the bus transceiver chip IC45 are electrically connected to the second SMA connector through resistor R8 to output the second digital IO signal to the second channel of the ion trap quantum computer.

[0092] Ports 7 and 9 of the bus transceiver chip IC45 are electrically connected to the third SMA connector through resistor R5 to output the third digital IO signal to the third channel of the ion trap quantum computer.

[0093] Ports 10 and 12 of the bus transceiver chip IC45 are electrically connected to the fourth SMA connector through resistor R4 to output the fourth digital IO signal to the fourth channel of the ion trap quantum computer.

[0094] More specifically, ports 3 and 1 of the digital isolation chip IC43 are connected to the first isolation power supply, port 8 is connected to the ground isolation power supply, ports 10 and 16 are connected to the 3.3V power supply, and port 9 is grounded.

[0095] Port 16 of the digital isolation chip IC44 is connected to the first isolation power supply, ports 11 and 9 are connected to the ground isolation power supply, ports 7 and 1 are connected to the 3.3V power supply, and port 8 is grounded.

[0096] Port 5 of the digital isolation chip IC43 is electrically connected to the G terminal of the MOS transistor T27, and port 10 of the digital isolation chip IC44 is electrically connected to the G terminal of the MOS transistor T28 through the resistor R17. The D terminal of the MOS transistor T27 is connected to the grounded isolation power supply, and the D terminal is connected to the first isolation power supply through the resistor R210.

[0097] Port 24 of the bus transceiver is connected between the resistor R210 and the D terminal of the MOS transistor T27.

[0098] Ports 2, 5, 8, and 11 of the bus transceiver chip IC45 are all connected to the grounded isolation power supply, and ports 21 and 16 are both connected to the first isolation power supply.

[0099] Port 13 of the bus transceiver chip IC45 is also electrically connected to port 2 of the chip IC3. Port 3 of the chip IC43 is connected to the first isolation power supply, and port 1 is connected to the grounded isolation power supply. One end of the resistor R12 is connected to the grounded isolation power supply, and the other end is connected between port 2 of the chip IC3 and port 13 of the bus transceiver chip IC45. The reset of the bus transceiver chip IC45 can be achieved through the chip IC43. The model of the chip IC43 is MCP810T-315I / TT.

[0100] One end of the resistor R12 is connected to the grounded isolation power supply, and the other end is connected between the chip IC43 and the bus transceiver chip IC45.

[0101] One end of the resistor R209 is connected to the grounded isolation power supply, and the other end is connected between the resistor R10 and the chip IC45. One end of the resistor R208 is electrically connected to the D terminal of the triode T13, and the other end is connected between the fourth SMA connector J14 and the resistor R10. The S terminal of the MOS transistor T13 is connected to the grounded isolation power supply, and the G terminal is electrically connected to the positive electrode of the diode LD9A through the resistor R216. The negative electrode of the diode LD9A is connected to the grounded isolation power supply.

[0102] One end of the resistor R206 is connected to the grounded isolation power supply, and the other end is connected between the resistor R8 and the chip IC45. One end of the resistor R205 is electrically connected to the D terminal of the triode T12, and the other end is connected between the second SMA connector J2 and the resistor R8. The S terminal of the MOS transistor T12 is connected to the grounded isolation power supply, and the G terminal is electrically connected to the positive electrode of the diode LD9B through the resistor R215. The negative electrode of the diode LD9B is connected to the grounded isolation power supply.

[0103] One end of resistor R203 is connected to the grounded isolation power supply, and the other end is connected between resistor R5 and chip IC45. One end of resistor R202 is electrically connected to the D terminal of triode T11, and the other end is connected between the third SMA connector J17 and resistor R5. The S terminal of MOS transistor T11 is connected to the grounded isolation power supply, and the G terminal is electrically connected to the positive electrode of diode LD10A through resistor R214. The negative electrode of diode LD10A is connected to the grounded isolation power supply.

[0104] One end of resistor R200 is connected to the grounded isolation power supply, and the other end is connected between resistor R4 and chip IC45. One end of resistor R199 is electrically connected to the D terminal of triode T10, and the other end is connected between the fourth SMA connector J1 and resistor R4. The S terminal of MOS transistor T10 is connected to the grounded isolation power supply, and the G terminal is electrically connected to the positive electrode of diode LD10B through resistor R213. The negative electrode of diode LD10B is connected to the grounded isolation power supply.

[0105] By setting MOS transistors and diodes, the output signals of each channel are detected to indicate whether the channel is normal.

[0106] Two digital isolator chips receive four-channel digital IO signals, internally isolate them, and then send them to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer through four SMA connectors of the bus transceiver chip to control the on / off of the laser optical path of the corresponding channel.

[0107] Port 11 of chip IC43 is also connected to the 3.3V power supply through resistor R196. The D terminal of MOS transistor T26 is connected between resistor R196 and port 11 of chip IC43, the S terminal is grounded, and the G terminal is electrically connected to ports 39, 41, 20, and 22 of the first LVDS signal transceiver chip IC45.

[0108] Similarly, for the electrical isolation circuit module and output isolation circuit module connected to the second LVDS signal transceiver chip, their circuit connections are set similarly.

[0109] Since there are multiple electrical isolation circuit modules and output isolation circuit modules, the corresponding isolation power supply modules include multiple. Each isolation power supply module provides a set of isolation power supplies (a first isolation power supply and a grounded isolation power supply) for the corresponding electrical isolation circuit module and output isolation circuit module.

[0110] The present invention can provide high-precision, high-speed, and low-latency digital IO signals for an ion trap quantum computer. The digital signals can reach up to 125 MHz and have a pulse width of 5 ns, achieving a microsecond-level transmission delay and a nanosecond-level synchronization accuracy between multiple channels. At the same time, the input and output circuits provided by the present invention can be integrated into the host computer or the control board, without the need for an additional separate control module, simplifying the operation mode of the ion trap quantum computer.

[0111] The present invention also provides an ion trap quantum computer control system, including a control board, an ion trap quantum computer, and the input and output circuits of the ion trap quantum computer provided in the foregoing embodiment; wherein, the input end of the input and output circuits of the ion trap quantum computer is communicatively connected to the control board, and the output end is electrically connected to the ion trap quantum computer, and is used to receive multiple control signals sent by the control board and convert them into multiple digital IO signals, and after electrically isolating each digital IO signal, send it to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer to control the on and off of the laser optical path switching switch of the corresponding channel.

[0112] The above embodiments are only the preferred embodiments of the present invention, and the scope of protection of the present invention cannot be limited thereby. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention fall within the scope of protection required by the present invention.

Claims

1. An input / output circuit for an ion trap quantum computer, characterized in that, it includes a data communication circuit module, a data drive circuit module and a power supply module; wherein, the input end of the data communication circuit module is communicatively connected to the control board of the ion trap quantum computer, and the output end is electrically connected to the data drive circuit module, and is used for converting the control signal sent by the control board of the ion trap quantum computer received into a digital IO signal and sending the digital IO signal to the data drive circuit module; the data drive circuit module is electrically connected to the laser optical path switching switch of the ion trap quantum computer, and is used for electrically isolating the digital IO signal and then outputting it to the laser optical path switching switch of the ion trap quantum computer to control the on / off of the laser optical path. The data drive circuit module includes a plurality of electrical isolation circuit modules and a plurality of output isolation circuit modules; wherein, each electrical isolation circuit module is respectively electrically connected to a corresponding LVDS signal transceiver chip, and is used for acquiring four digital IO signals, electrically isolating the four digital IO signals, and sending the electrically isolated digital IO signals to the corresponding output isolation circuit module; each output isolation circuit module is used for transmitting each electrically isolated digital IO signal to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer through the corresponding SMA connector. Each electrical isolation circuit module includes a first digital isolator chip and a second first digital isolator chip; wherein: The first digital isolator chip and the second digital isolator chip are both electrically connected to a corresponding LVDS signal transceiver chip, and are used for receiving the four digital IO signals sent by the corresponding LVDS signal transceiver; Each output isolation circuit module includes a bus transceiver chip, and the bus transceiver chip is electrically connected to the first digital isolation chip and the second digital isolation chip of the corresponding electrical isolation circuit module, and is used for respectively sending the four electrically isolated digital IO signals to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer through the corresponding SMA connectors. The four output ends of the first digital isolator chip and the four input ends of the second digital isolator chip are electrically connected to the corresponding ports of the corresponding first LVDS signal transceiver chip; the four input ends of the first digital isolator chip and the four output ends of the second digital isolator chip are correspondingly electrically connected to the four input ends of the bus transceiver chip; the four output ends of the bus transceiver chip are respectively electrically connected to the corresponding SAM connectors through corresponding resistors; The first VDD terminal and the first EN terminal of the first digital isolator chip are both connected to the first isolation power supply, the second VDD terminal and the second EN terminal are connected to the first power supply, the first ground terminal is connected to the ground isolation power supply, and the second ground terminal is grounded; the first EN terminal and the first VDD terminal of the second digital isolator chip are connected to the first power supply, the second VDD terminal is connected to the first isolation power supply, the second ground terminal is connected to the ground isolation power supply, and the first ground terminal is grounded; The second EN terminal of the second digital isolation chip is electrically connected to the G terminal of MOS transistor T27 through resistor R17, and the fifth output terminal of the first digital isolation chip is electrically connected to the G terminal of MOS transistor T27; the S terminal of MOS transistor T27 is grounded, and the D terminal is connected to the first isolation power supply through resistor R210; the DIR terminal of the bus transceiver chip is connected between resistor R210 and the D terminal of MOS transistor T27; The ground terminal of the bus transceiver chip is connected to the ground isolation power supply, and the power supply terminal is connected to the first isolation power supply; The power supply module is electrically connected to the data communication circuit module and the digital signal driving circuit module, and is used to provide a power supply for the data communication circuit module and the digital signal driving circuit module, and to provide an isolation power supply for the digital driving circuit module.

2. The input / output circuit of the ion trap quantum computer according to claim 1, characterized in that, The data communication circuit module is electrically connected to the control board through LVDS signal lines, and is used to receive multiple LVDS differential signals sent by the control board and convert each LVDS differential signal into a corresponding digital IO signal.

3. The input / output circuit of the ion trap quantum computer according to claim 2, characterized in that, The data communication circuit module includes multiple half-duplex four-channel LVDS signal transceivers, and each half-duplex four-channel LVDS signal transceiver is used to receive four LVDS differential signals sent by the control board and convert the four LVDS differential signals into corresponding digital IO signals respectively.

4. The input / output circuit of the ion trap quantum computer according to claim 1, characterized in that, The fourth input terminal of the first digital isolator chip and the fourth output terminal of the second digital isolator chip are electrically connected to the first input terminal and the second input terminal of the bus transceiver chip through resistor R9; the third input terminal of the first digital isolator chip and the third output terminal of the second digital isolator chip are electrically connected to the third input terminal and the fourth input terminal of the bus transceiver chip through resistor R7; The second input terminal of the first digital isolator chip and the second output terminal of the second digital isolator chip are electrically connected to the fifth input terminal and the sixth input terminal of the bus transceiver chip through resistor R6; the first input terminal of the first digital isolator chip and the first output terminal of the second digital isolator chip are electrically connected to the seventh input terminal and the eighth input terminal of the bus transceiver chip through resistor R29; The first output terminal and the second output terminal of the bus transceiver chip are electrically connected to the first SMA connector through resistor R10 to output a first digital IO signal to the first channel of the ion trap quantum computer; The third output terminal and the fourth output terminal of the bus transceiver chip are electrically connected to the second SMA connector through resistor R8 to output a second digital IO signal to the second channel of the ion trap quantum computer; The fifth output terminal and the sixth output terminal of the bus transceiver chip are electrically connected to the third SMA connector through resistor R5 to output a third digital IO signal to the third channel of the ion trap quantum computer; The seventh output terminal and the eighth output terminal of the bus transceiver chip are electrically connected to the fourth SMA connector through a resistor R4 to output a fourth digital IO signal to the fourth channel of the ion trap quantum computer; One end of the resistor R209 is connected to the ground isolation power supply, and the other end is connected between the resistor R10 and the bus transceiver chip. One end of the resistor R208 is electrically connected to the D terminal of the triode T13, and the other end is connected between the first SMA connector and the resistor R10. The S terminal of the MOS transistor T13 is connected to the ground isolation power supply, and the G terminal is electrically connected to the positive electrode of the diode LD9A through the resistor R216. The negative electrode of the diode LD9A is connected to the ground isolation power supply; One end of the resistor R206 is connected to the ground isolation power supply, and the other end is connected between the resistor R8 and the bus transceiver chip. One end of the resistor R205 is electrically connected to the D terminal of the triode T12, and the other end is connected between the second SMA connector and the resistor R8. The S terminal of the MOS transistor T12 is connected to the ground isolation power supply, and the G terminal is electrically connected to the positive electrode of the diode LD9B through the resistor R215. The negative electrode of the diode LD9B is connected to the ground isolation power supply; One end of the resistor R203 is connected to the ground isolation power supply, and the other end is connected between the resistor R5 and the bus transceiver chip. One end of the resistor R202 is electrically connected to the D terminal of the triode T11, and the other end is connected between the third SMA connector and the resistor R5. The S terminal of the MOS transistor T11 is connected to the ground isolation power supply, and the G terminal is electrically connected to the positive electrode of the diode LD10A through the resistor R214. The negative electrode of the diode LD10A is connected to the ground isolation power supply; One end of the resistor R200 is connected to the ground isolation power supply, and the other end is connected between the resistor R4 and the bus transceiver chip. One end of the resistor R199 is electrically connected to the D terminal of the triode T10, and the other end is connected between the fourth SMA connector and the resistor R4. The S terminal of the MOS transistor T10 is connected to the ground isolation power supply, and the G terminal is electrically connected to the positive electrode of the diode LD10B through the resistor R213. The negative electrode of the diode LD10B is connected to the ground isolation power supply.

5. The input-output circuit of the ion trap quantum computer according to claim 1, wherein, the power supply module includes a main power supply module and an isolation power supply module; wherein, the main power supply module is connected to the data communication circuit module and the data driving circuit module, and is used to convert the externally connected power supply into a first power supply; the isolation power supply module is electrically connected to the data driving circuit module, and is used to convert the externally connected power supply into a first isolation power supply and a ground isolation power supply.

6. An ion trap quantum computer control system, wherein, It includes a control board, an ion trap quantum computer, and an input / output circuit of an ion trap quantum computer as described in any one of claims 1-5; wherein, the input end of the input / output circuit of the ion trap quantum computer is communicatively connected to the control board, and the output end is electrically connected to the ion trap quantum computer, and is used to receive multiple control signals sent by the control board, convert them into multiple digital IO signals, and after electrically isolating each digital IO signal, deliver it to the laser optical path switching switch of the corresponding channel of the ion trap quantum computer to control the on / off of the laser optical path switching switch of the corresponding channel.

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