Systems, apparatuses, and methods for programming one-time programmable memory circuits

Abstract

A semiconductor device for one-time programmable (OTP) memory according to some examples of the present disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side of the source terminal, a drain-side charge trap in the dielectric region capable of programming the semiconductor device, and a source-side charge trap in the dielectric region opposite the drain-side charge trap and capable of programming the semiconductor device.

Description

[0001] This application is a divisional application of Chinese invention patent application 201680011934.2 (PCT / US2016 / 017013), filed on February 8, 2016, entitled "System, apparatus and method for programming one-time programmable memory circuit". Technical Field

[0002] This disclosure generally relates to integrated circuits, and more particularly, but not exclusively, to one-time programmable memory circuits. Background Technology

[0003] The scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technology has made it more difficult to integrate both floating-gate memory and logic to achieve high-performance and low-power memory circuits. Floating-gate memory provides both one-time programmable memory (OTP) and embedded flash memory. Due to the complexity of integrating additional processing (which also increases cost), embedded flash memory typically lags behind leading CMOS technology by two or three nodes. As a result, one-time programmable (OTP) memory is increasingly being used in embedded non-volatile memory (NVM) applications.

[0004] Two types of OTP memory are currently available in CMOS technology at 65nm and below: eFuse and antifuse. eFuse memory elements are programmed by forcing a high current density through a conductive link to completely break it or by significantly increasing its resistance so that the link is no longer conductive (i.e., it is high-resistance or open-circuit). Antifuse is the opposite of eFuse. This circuit is initially open-circuit (high-resistance) and is programmed by applying electrical stress (which creates a low-resistance conductive path).

[0005] However, eFuse programming requires high current, and it is programmed both during device fabrication and during operation of the chip in which it resides. Charge trapping, particularly channel thermal charge (CHC) injection, has been developed for use in metal-oxide-semiconductor (MOS) transistors. However, programming typically requires high power and has low programming efficiency. For example, logic high-k / metal-gate (HK / MG) OTP devices are programmed via MOS device operation. When a device is programmed due to CHC injection, charge trapping can cause shutdown on the drain side of the gate dielectric. However, to reduce power and energy, weak programming conditions can be applied. Weak programming conditions have a smaller Vt offset and no gate breakdown, a small programming window, and weak data retention performance.

[0006] Therefore, there is a need for systems, apparatuses, and methods that improve upon conventional methods, including the improved methods, systems, and apparatuses provided therefrom.

[0007] The inventive features, along with further features and advantages, inherent in these teachings are better understood from the detailed description and accompanying drawings. Each drawing is provided for illustrative and descriptive purposes only and does not limit the scope of these teachings. Summary of the Invention

[0008] The following is a simplified overview relating to one or more aspects and / or examples of the apparatus and methods disclosed herein. Thus, this overview should not be considered an exhaustive overview relating to all conceptual aspects and / or examples, nor should it be considered to identify key or decisive elements relating to all conceptual aspects and / or examples or to depict the scope relating to any particular aspect and / or example. Accordingly, the following overview serves only to present certain concepts in a simplified form relating to one or more aspects and / or examples of the apparatus and methods disclosed herein before the detailed description given below.

[0009] Some examples of this disclosure relate to systems, apparatus, and methods for semiconductor devices including one-time programmable (OTP) memories, the semiconductor device having: a gate; a dielectric region vertically below the gate; a source terminal horizontally offset to a first side vertically below the gate and the dielectric region; a drain terminal horizontally offset to a second side opposite to the first side vertically below the gate and the dielectric region; a drain-side Vt programming region in the dielectric region capable of programming the semiconductor device; and a source-side Vt programming region in the dielectric region horizontally opposite the drain-side Vt programming region, capable of programming the semiconductor device.

[0010] Some examples of this disclosure relate to systems, apparatus, and methods including a system for programming a one-time programmable memory cell having: a gate; programming circuitry coupled to the gate, the programming circuitry being configured to apply a programming voltage to the gate; a dielectric region vertically below the gate; a source terminal horizontally offset to a first side vertically below the gate and the dielectric region; a drain terminal horizontally offset to a second side opposite to the first side vertically below the gate and the dielectric region; a drain-side Vt programming region in the dielectric region, the drain-side Vt programming region being capable of programming the semiconductor device in conjunction with the programming voltage; and a source-side Vt programming region in the dielectric region horizontally opposite the drain-side Vt programming region, the source-side Vt programming region being capable of programming the semiconductor device in conjunction with the programming voltage.

[0011] In some examples of this disclosure, systems, apparatuses, and methods for programming OTP memory include: applying a gate-source voltage of about -3 volts to a programmable gate device; applying a first programming voltage of about -1.4 volts to a drain-side Vt programming region of the programmable gate device; and applying a second programming voltage of about -1.4 volts to a source-side Vt programming region of the programmable gate device.

[0012] Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. Attached Figure Description

[0013] A more complete understanding of the various aspects of this disclosure and its many accompanying advantages will become readily available upon consideration of the following detailed description taken in conjunction with the accompanying drawings, which are given for illustrative purposes only and do not constitute any limitation on this disclosure, and wherein:

[0014] Figure 1 Semiconductor devices with dual programming regions according to some examples of this disclosure are explained.

[0015] Figure 2A and 2B The present disclosure describes source and drain programming for semiconductor devices with dual programming regions, using some examples of this disclosure.

[0016] Figure 3A and 3B The present disclosure describes source and drain programming for semiconductor devices with dual programming regions, using some examples of this disclosure.

[0017] Figure 4 The source current, drain current, and gate-source voltage after programming a semiconductor device having a dual programming region, according to some examples of this disclosure, are explained.

[0018] Figure 5 The source current, drain current, and gate-source voltage after programming a semiconductor device having a dual programming region, according to some examples of this disclosure, are explained.

[0019] Figure 6 A partial process flow diagram for programming a semiconductor device with dual programming regions, based on some examples of this disclosure, is explained.

[0020] Figure 7 A partial process flow diagram of two programming flows for a semiconductor device with dual programming regions, according to some examples of this disclosure, is explained.

[0021] Figure 8 Exemplary processors according to some examples of this disclosure are explained.

[0022] Figure 9 Exemplary user equipment (UE) according to some examples of this disclosure is explained.

[0023] By convention, features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not show all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and accompanying drawings to indicate similar features. Detailed Implementation

[0024] The exemplary methods, apparatuses, and systems disclosed herein advantageously address the deficiencies or disadvantages of conventional approaches, as well as other previously unidentified needs, and mitigate the shortcomings of conventional methods, apparatuses, and systems. For example, by utilizing dual programming at the source and drain to increase the Vt offset at the source and drain locations, the programming window is enlarged and data retention performance under weak programming conditions is improved. An example of a system for programming OTP memory cells includes a PMOS or NMOS device having a source-side Vt programming region and a drain-side Vt programming region in a dielectric region coupled to the gate of a programming circuit. The programming circuit can apply a programming voltage (which turns the programming region into a charge trap) to program both the source and drain sides, thereby increasing the gate threshold voltage by approximately 300 millivolts. Furthermore, with dual programming, the asymmetric response of the drain and source currents compared to single programming can be reduced—brought closer to a symmetric response.

[0025] Various aspects are disclosed in the following description and related drawings to illustrate specific examples relevant to this disclosure. Alternative examples will be apparent to those skilled in the art upon reading this disclosure and can be constructed and implemented without departing from the scope or spirit of this disclosure. Furthermore, well-known elements will not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein.

[0026] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not necessarily to be construed as superior to or better than other examples. Similarly, the term "example" does not require all examples to include the features, advantages, or modes of operation discussed. The use of the terms "in one example," "example," "in one feature," and / or "feature" in this specification does not necessarily refer to the same features and / or examples. Furthermore, a particular feature and / or structure may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0027] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit the examples of this disclosure. As used herein, the singular forms “a,” “some,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “having,” “including,” and / or “containing,” as used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0028] It should be noted that the terms “connection,” “coupling,” or any variation thereof mean any direct or indirect connection or coupling between components, and may encompass the presence of an intermediate element between two components through which they are “connected” or “coupled.” Coupling and / or connection between components can be physical, logical, or a combination thereof. As used herein, components can be “connected” or “coupled” together, for example, by using one or more wires, cables, and / or printed electrical connections, and by using electromagnetic energy. Electromagnetic energy can have wavelengths in the radio frequency region, microwave region, and / or optical (both visible and invisible) region. These are several non-limiting and non-exhaustive examples.

[0029] The use of designations such as "first," "second," etc., to refer to elements herein does not limit the number and / or order of those elements. Rather, these designations are used as a convenient way to distinguish two or more elements and / or instances of elements. Therefore, a reference to a first element and a second element does not imply that only two elements can be used, or that the first element must necessarily precede the second element. Similarly, unless otherwise stated, a set of elements may include one or more elements. Furthermore, terms of the form "at least one of A, B, or C" used in the specification or claims can be interpreted as "A or B or C or any combination of these elements."

[0030] Furthermore, many examples are described in the form of sequences of actions to be performed by elements such as computing devices. It will be appreciated that the various actions described herein can be performed by special-purpose circuitry (e.g., application-specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequences of actions described herein can be considered to be fully embodied in any form of computer-readable storage medium storing a corresponding set of computer instructions that, upon execution, will cause the associated processor to perform the functionality described herein. Therefore, various aspects of this disclosure can be embodied in several different forms, all of which are contemplated to fall within the scope of the claimed subject matter. Furthermore, for each example described herein, the corresponding form of any such example may be described herein as, for example, "logic configured to perform the described actions."

[0031] In this specification, certain terms are used to describe certain features. The term "mobile device" can describe, but is not limited to, mobile phones, mobile communication devices, pagers, personal digital assistants, personal information managers, mobile handheld computers, laptop computers, wireless devices, wireless modems, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). Furthermore, the terms "user equipment" (UE), "mobile terminal," "mobile device," and "wireless device" may be used interchangeably.

[0032] Figure 1 Semiconductor devices with dual programming regions according to some examples of this disclosure are described. For example... Figure 1 As shown, the semiconductor device of the OTP memory 300 may include a gate 310, a dielectric region 320 vertically below the gate 310, a source terminal 330 horizontally offset to one side vertically below the gate 310 and the dielectric region 320, and a drain terminal 340 horizontally offset to the opposite side of the source terminal 330 vertically below the gate 310 and the dielectric region 320. The gate 310 may be of different types, such as a p-type gate, an n-type gate, or a polysilicon gate. The gate 310 may be made of different materials (such as metal or metal alloy). The dielectric region 320 may be made of a dielectric material (preferably a high-k dielectric material, such as hafnium oxide).

[0033] Semiconductor device 300 may include a source-side Vt programming region 350 offset toward the source terminal 330 in dielectric region 320, and a drain-side Vt programming region 360 offset toward the drain terminal 340 and horizontally opposite to the source-side Vt programming region 350. The source-side Vt programming region 350 and the drain-side Vt programming region 360 are made of materials capable of programming semiconductor device 300 (such as charge traps composed of multiple layers of material). These materials may be thin films of silicon oxide and high-k oxides, such as HfO2.

[0034] Semiconductor device 300 may include a first well layer 370 extending horizontally below source terminal 330 and drain terminal 340 and extending vertically upward between source terminal 330 and drain terminal 340, and a second well layer 380 below the first well layer. These well layers are shown as n-wells and p-wells of PMOS semiconductor device 300, but it should be understood that these well layers may be p-wells and n-wells (inverted) of NMOS semiconductor device.

[0035] Figure 2A and 2B The present disclosure explains source and drain programming for semiconductor devices with dual programming regions, using examples of this disclosure. For example... Figure 2A and 2B As shown, the semiconductor device 400 may include a gate 410, a dielectric region 420 vertically below the gate 410, a source terminal 430 horizontally offset to one side vertically below the gate 410 and the dielectric region 420, a drain terminal 440 horizontally offset to the opposite side of the source terminal 430 vertically below the gate 410 and the dielectric region 420, and a source-side Vt programming region 450 offset toward the source terminal 430 in the dielectric region 420. Figure 2B (as shown in the diagram), the drain-side Vt programming region 460, offset towards the drain terminal 440 in the dielectric region 420 and horizontally opposite to the source-side Vt programming region 450. Figure 2A The diagram shows a programming circuit 490 coupled to a gate 410. The programming circuit 490 is capable of selectively applying a programming voltage to the semiconductor device 400. When the programming circuit 490 applies a programming voltage to the semiconductor device 400, tiny defects or traps are generated in the Vt programming region (450 or 460, depending on which side is being programmed) during the electric field stress created by the programming voltage (CHC injection). These defects lead to increased leakage across the gate, and the trapped charge begins to form conductive paths or channels through the Vt programming region. These conductive channels can be reduced to channel lengths below 10 nm, such as 5 or 7 nm.

[0036] Figure 2A The effect of applying a programming voltage to the drain-side programming region 460 (Vg = 0 volts and Vnw = 3 V) or applying a programming voltage (Vg = -3 volts and Vnw = 0 V) ​​is shown for the programming circuit 490. Figure 2B The effects of applying a programming voltage to the source-side Vt programming region 450 (Vg = 0 volts and Vnw = 3 V) or applying a programming voltage (Vg = -3 volts and Vnw = 0 V) ​​are shown for the programming circuit 490. As can be seen in Tables 1 and 2 (after applying a relative NW bias to change the PMOS terminal voltage), the selective programming voltage produces different NW voltages during read and program operations.

[0037]

[0038] Table 1

[0039]

[0040]

[0041] Table 2

[0042] Similar to Figure 2A and 2B , Figure 3A and 3B The present disclosure describes alternative source and drain programming for semiconductor devices with dual programming regions, using examples of this disclosure. For example... Figure 3A and 3B As shown, the semiconductor device 500 may include a gate 510, a dielectric region 520 vertically below the gate 510, a source terminal 530 horizontally offset to one side vertically below the gate 510 and the dielectric region 520, a drain terminal 540 horizontally offset to the opposite side of the source terminal 530 vertically below the gate 510 and the dielectric region 520, and a source-side Vt programming region 550 offset toward the source terminal 530 in the dielectric region 520. Figure 3B (shown in the figure), the drain-side Vt programming region 560, offset towards the drain terminal 540 in the dielectric region 520 and horizontally opposite to the source-side Vt programming region 550. Figure 3A The diagram shows a programming circuit 590 coupled to a gate 510. The programming circuit 590 is capable of selectively applying a programming voltage to the semiconductor device 500. When the programming circuit 590 applies a programming voltage to the semiconductor device 500, tiny defects or traps are generated in the Vt programming region (550 or 560, depending on which side is being programmed) during the electric field stress created by the programming voltage (CHC injection). These defects lead to increased leakage across the gate, and the trapped charge begins to form conductive paths through the Vt programming region.

[0043] Figure 3A The effect of applying a programming voltage to the drain-side programming region 560 (Vg = 0 volts, Vnw = 3 V) or applying a programming voltage (Vg = -3 volts, Vnw = 0 V) ​​is shown for the programming circuit 590. Figure 3B The effects of applying a programming voltage to the source-side programming region 550 (Vg = 0 volts, Vnw = 3 V) or applying a programming voltage (Vg = -3 volts, Vnw = 0 V) ​​are shown for the programming circuit 590. As can be seen below in Tables 3 and 4 (after applying a relative NW bias to change the PMOS terminal voltage), the selective programming voltage produces different NW voltages during read and program operations.

[0044] Table 3

[0045]

[0046]

[0047] Table 4

[0048]

[0049] Figure 4 The source current, drain current, and gate-source voltage after programming a semiconductor device with a dual programming region, according to some examples of this disclosure, are explained. For example... Figure 4 As shown, semiconductor device 600 may include a source-side Vt programming region 650 and a drain-side Vt programming region 660. Figure 601 shows the response of the source terminal 630 current Is (A) relative to the gate 610 voltage Vgs (V) when the source-side Vt programming region 650 is programmed by creating a charge trap. Figure 602 shows the response of the drain terminal 640 current Id (A) relative to the gate 610 voltage Vgs (V) when the drain-side Vt programming region 660 is programmed by creating a charge trap. For example, when a drain-side programming voltage Vgs = 0 to -3V is applied by a programming circuit (not shown), this produces a response of Vd = 0, Vs = -0.6 to -1.4V, and Vsb = 0V. This increases the drain-side Vt. When the programming circuit (not shown) applies a source-side programming voltage Vgs = 0 to -3V, this produces a response of Vd = -0.6 to -1.4V, Vs = 0, and Vsb = 0V. This increases the source-side Vt. When the drain-side is read with Vgs = 0 to -1, Vd = 0, Vs = -1, and Vsb = 0. Therefore, the drain-side Vt has a greater impact. For a fixed Vgs = -3V, increasing the programming voltage from -0.6V to -1.4V improves the programming window.

[0050] Figure 5 The present disclosure explains, according to some examples, the replacement of source and drain currents and gate-source voltages after programming a semiconductor device with dual programming regions. For example... Figure 5As shown, semiconductor device 700 may include a source-side Vt programming region 750 and a drain-side Vt programming region 760. Figure 701 shows the response of the source-side Vt programming region 750 to the gate-side voltage Vgs (V) when the source-side Vt programming region 750 is programmed by creating a charge trap. Figure 702 shows the response of the drain-side current Id (A) to the gate-side voltage Vgs (V) when the drain-side Vt programming region 760 is programmed by creating a charge trap. For example, when a drain-side programming voltage Vgs = 0 to -3V is applied by a programming circuit (not shown), this produces a response of Vd = 0, Vs = -0.6 to -1.4V, and Vsb = 0V. This increases the drain-side Vt. When the programming circuit (not shown) applies a source-side programming voltage Vgs = 0 to -3V, this produces a response of Vd = -0.6 to -1.4V, Vs = 0, and Vsb = 0V. This increases the source-side Vt. When the source side is read with Vgs = 0 to -1, Vd = 1, Vs = 0, and Vsb = 0. Therefore, the source-side Vt has a greater impact. For a fixed Vgs = -3V, increasing the programming voltage from -0.6V to -1.4V improves the programming window.

[0051] Figure 6 A partial process flow diagram for programming a semiconductor device with dual programming regions, according to some examples of this disclosure, is explained. For example... Figure 6 As shown, this part of the process flow begins at step 800, where the programming circuit (peripheral device) increases the n-well (NW) voltage to the gate programming voltage (Vpg) (e.g., 3 volts). The process continues at step 810, where the programming circuit increases the source (or drain) voltage to Vpg (e.g., 3 volts). The process then continues at step 820, where the programming circuit applies a set-drain (or source) voltage to Vdd (e.g., 1 volt). At step 830, a determination is made regarding whether the threshold voltage (Vt) has increased by approximately 300 mV. If not, the process returns to step 800. If yes, the process proceeds to step 840 and the OTP programming of the drain (or source) is successful.

[0052] Figure 7 Partial process flow diagrams of two programming flows for a semiconductor device with dual programming regions, according to some examples of this disclosure, are explained. For example... Figure 7As shown, the first part of the process flow for a normal PMOS switching mode begins at step 900, where the programming circuit (peripheral device) maintains the NW voltage at Vdd (e.g., 1 volt). This process continues at step 910, where the programming circuit maintains the source (or drain) voltage at Vdd (e.g., 1 volt). This process then continues at step 920, where the programming circuit applies a drain (or source) voltage to Vss (e.g., 0 volt). This part of the process concludes at step 940, and Vt remains constant after Vt begins switching.

[0053] like Figure 7 As shown, the second part of the process flow for OTP programming mode begins at step 940, where the programming circuit (peripheral device) increases the n-well (NW) voltage to the gate programming voltage (Vpg) (e.g., 3 volts). The process continues at step 950, where the programming circuit increases the source (or drain) voltage to Vpg (e.g., 3 volts). The process then continues at step 960, where the programming circuit applies a set-drain (or source) voltage to Vdd (e.g., 1 volt). At step 970, a determination is made regarding whether the threshold voltage (Vt) has increased by approximately 300 mV. If not, the process returns to step 940. If yes, the process proceeds to step 980 and the OTP programming of the drain (or source) is successful.

[0054] Figure 8 A functional block diagram of an exemplary processor 10 (such as ASIC 208 (see below)) is depicted. Processor 10 executes instructions in instruction execution pipeline 12 according to control logic 14. Control logic 14 maintains a program counter (PC) 15 and sets and clears bits in one or more status registers 16 to indicate, for example, the current instruction set operating mode, information related to the results of arithmetic operations and logical comparisons (zero, carry, equal, unequal), etc. In some examples, pipeline 12 may be a superscalar design with multiple parallel pipelines. Pipeline 12 may also be referred to as an execution unit. General-purpose register (GPR) file 20 provides a list of general-purpose registers 24 accessible by pipeline 12 and includes the top level of the memory hierarchy.

[0055] The processor 10 (which executes instructions from at least two instruction sets in different instruction set operation modes) additionally includes debugging circuitry 18, which is operable to compare at least a predetermined target instruction set operation mode with the current instruction set operation mode at each instruction execution and to provide an indication of a match between the two.

[0056] Pipeline 12 fetches instructions from instruction cache (I-cache) 26, where memory address translation and permissioning are managed by instruction-side translation back buffer (ITLB) 28. Data is accessed from data cache (D-cache) 30, where memory address translation and permissioning are managed by master translation back buffer (TLB) 32. In various examples, ITLB 28 may include a copy of a portion of TLB 32. Alternatively, ITLB 28 and TLB 32 may be integrated. Similarly, in various examples of processor 10, I-cache 26 and D-cache 30 may be integrated or unified. Furthermore, I-cache 26 and D-cache 30 may be L1 caches. Misses in I-cache 26 and / or D-cache 30 result in access to main (off-chip) memory 38, 40 via memory interface 34. Memory interface 34 may be a master input to bus interconnect 42 that implements a shared bus to one or more memory devices 38, 40, and bus interconnect 42 may incorporate improved data decompression according to some examples of this disclosure. Additional master devices (not shown) may be additionally connected to bus interconnect 42.

[0057] Processor 10 may include an input / output (I / O) interface 44, which may be a master device on a peripheral bus, that can access various peripheral devices 48, 50 across the peripheral bus via bus 46. Those skilled in the art will recognize that numerous variations of processor 10 are possible. For example, processor 10 may include a Level 2 (L2) cache for either or both of I-cache and D-cache 26, 30. Additionally, one or more of the functional blocks depicted in processor 10 may be omitted from certain examples. Other functional blocks that may reside in processor 10 (such as a JTAG controller, instruction pre-decoder, branch target address cache, etc.) are not closely related to the description of this disclosure and are omitted for clarity.

[0058] Reference Figure 9System 100, including a UE 200 (here, a wireless device) such as a cellular phone, has a platform 202 capable of receiving and executing software applications, data, and / or commands transmitted from a radio access network (RAN), which may ultimately originate from a core network, the Internet, and / or other remote servers and networks. Platform 202 may include a transceiver 206 operatively coupled to an application-specific integrated circuit (“ASIC” 208) or other processor, microprocessor, logic circuit, or other data processing device. The ASIC 208 or other processor executes an application programming interface (“API”) 210 layer that interfaces with any resident program in the wireless device’s memory 212. Memory 212 may include read-only or random access memory (RAM and ROM), EEPROM, flash memory cards, or any memory commonly used in computer platforms. Platform 202 may also include a local database 214 capable of storing applications not actively used in memory 212. Local database 214 is typically a flash memory cell, but may also be any auxiliary storage device as known in the art (such as magnetic media, EEPROM, optical media, tape, floppy disk, or hard disk, etc.). The internal platform 202 component can also be operatively coupled to external devices, such as antenna 222, display 224, push-to-talk button 228 and keypad 226, and other components, as known in the art.

[0059] Accordingly, examples of this disclosure may include a UE capable of performing the functions described herein. As those skilled in the art will appreciate, various logic elements may be implemented in discrete components, software modules executing on a processor, or any combination of software and hardware to implement the functionality disclosed herein. For example, ASIC 208, memory 212, API 210, and local database 214 may all cooperate to load, store, and perform the various functions disclosed herein, and the logic for performing these functions may therefore be distributed across various components. Alternatively, this functionality may be incorporated into a discrete component. Therefore, Figure 9 The features of UE 200 in this disclosure will be considered explanatory only, and this disclosure is not limited to the features or arrangements described.

[0060] Wireless communication between UE 200 and RAN can be based on different technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), or other protocols that can be used in wireless communication networks or data communication networks.

[0061] Nothing described or illustrated in this application is intended to designate any component, step, feature, benefit, advantage, or equivalent to offer to the public, whether or not such component, step, feature, benefit, advantage, or equivalent is stated in the claims.

[0062] Those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above in a generalized manner in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0063] Although some aspects have been described in conjunction with the device, these aspects undoubtedly also constitute a description of the corresponding method, and therefore the frame or component of the device should also be understood as a corresponding method step or feature of the method step. Similarly, aspects described in conjunction with or as method steps also constitute a description of the corresponding block or detail or feature of the corresponding device. Some or all of the method steps may be performed by (or using) a hardware device, such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some examples, some or more of the most important method steps may be performed by such a device.

[0064] The examples described above constitute only an explanation of the principles of this disclosure. Undoubtedly, modifications and variations of the layouts and details described herein will become apparent to those skilled in the art. Therefore, this disclosure is intended to be limited only by the scope of the appended patent claims, and not by the specific details presented based on the description and explanation of the examples herein.

[0065] In the detailed description above, it can be seen that different features are grouped together in the examples. This manner of disclosure should not be construed as reflecting an intention that the claimed example requires more features than those explicitly mentioned in the corresponding claims. Rather, it is intended to allow the inventive content to reside in features fewer than those in the individual examples disclosed. Therefore, the appended claims should thus be considered as incorporated into this description, where each claim may be a separate example. Although each claim may be a separate example, it should be noted that while dependent claims in the claims may refer to a specific combination having one or more claims, other examples may also cover or include combinations of said dependent claims with the subject matter of any other dependent claims or any features combined with other dependent and independent claims. Such combinations are presented herein unless explicitly stated that no particular combination is intended. Furthermore, it is also intended that features of a claim may be included in any other independent claim, even if said claim is not directly dependent on that independent claim.

[0066] It should also be noted that the methods disclosed in this description or claims can be implemented by a device that includes means for performing the corresponding steps or actions of the method.

[0067] Furthermore, in some examples, an individual step / action may be subdivided into multiple sub-steps or may contain multiple sub-steps. Such sub-steps may be included in the disclosure of the individual step or may be part of the disclosure of the individual step.

[0068] Although the foregoing disclosure has shown illustrative examples of this disclosure, it should be noted that various changes and modifications may be made therein without departing from the scope of this disclosure as defined by the appended claims. The functions, steps, and / or actions in the method claims according to the examples of this disclosure described herein do not necessarily have to be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, pluralism is also contemplated unless explicitly stated to be limited to the singular.

Claims

1. A semiconductor device for one-time programmable (OTP) memory, comprising: a gate; a dielectric region vertically below the gate; a source terminal horizontally offset to a first side vertically below the gate and the dielectric region; a drain terminal horizontally offset to a second side opposite the first side vertically below the gate and the dielectric region; a drain-side Vt programming region horizontally offset to the drain terminal surrounded by the dielectric region, the drain-side Vt programming region composed of layers of material in which traps are created during programming of the semiconductor device in response to an electric field stress created by a programming voltage applied to the drain-side Vt programming region; and a source-side Vt programming region horizontally opposite the drain-side Vt programming region and offset to the source terminal surrounded by the dielectric region, the source-side Vt programming region composed of layers of material in which traps are created during programming of the semiconductor device in response to an electric field stress created by a programming voltage applied to the source-side Vt programming region, and wherein the drain-side Vt programming region and the source-side Vt programming region are charge traps. The gate is p-type.

2. The semiconductor device of claim 1, wherein, The gate is n-type.

3. The semiconductor device of claim 1, wherein, The gate is a metal gate.

4. The semiconductor device of claim 1, wherein, The gate is a polysilicon gate.

5. The semiconductor device of claim 1, wherein, The drain-side Vt programming region provides a first conductive path between the gate and the drain terminal.

6. The semiconductor device of claim 1, wherein, The source-side Vt programming region provides a second conductive path between the gate and the source terminal.

7. The semiconductor device of claim 6, wherein, The drain-side Vt programming region and the source-side Vt programming region are dual programming regions of the semiconductor device, and wherein both the drain-side Vt programming region and the source-side Vt programming region are programmed.

8. The semiconductor device of claim 1, wherein, 9. The semiconductor device of claim 1, further comprising a programming circuit coupled to the gate, wherein the programming circuit is configured to selectively apply a programming voltage to the gate. The semiconductor device is integrated into one of a mobile telephone, a mobile communication device, a pager, a personal digital assistant, a personal information manager, a mobile hand-held computer, a laptop computer, a wireless device, or a wireless modem.

10. The semiconductor device of claim 1, wherein, 11. A system for programming one-time programmable memory cells, the system comprising: a gate; a programming circuit coupled to the gate, the programming circuit configured to apply a programming voltage to the gate; a dielectric region vertically below the gate; a source terminal horizontally offset to a first side vertically below the gate and the dielectric region; a drain terminal horizontally offset to a second side opposite the first side vertically below the gate and the dielectric region; a drain-side Vt programming region horizontally offset to the drain terminal surrounded by the dielectric region, the drain-side Vt programming region composed of layers of material in which traps are created in response to an electric field stress created by the programming voltage applied to the drain-side Vt programming region; and a source-side Vt programming region horizontally opposite the drain-side Vt programming region and offset to the source terminal surrounded by the dielectric region, the source-side Vt programming region composed of layers of material in which traps are created in response to an electric field stress created by the programming voltage applied to the source-side Vt programming region, and ​ a source-side Vt programming region horizontally opposite the drain-side Vt programming region and offset from the source terminal, the source-side Vt programming region composed of layers of material in which traps are generated in response to an electric field stress created by application of the programming voltage to the source-side Vt programming region, and wherein the drain-side Vt programming region and the source-side Vt programming region are charge traps.

12. The system of claim 11, wherein, The gate is a polysilicon gate.

13. The system of claim 11, wherein, The drain-side Vt programming region provides a first conductive path between the gate and the drain terminal.

14. The system of claim 13, wherein, The source-side Vt programming region provides a second conductive path between the gate and the source terminal.

15. The system of claim 11, wherein, The drain-side Vt programming region and the source-side Vt programming region are dual programming regions of the system, and wherein both the drain-side Vt programming region and the source-side Vt programming region are programmed.

16. The system of claim 11, wherein, The programming circuit is configured to selectively apply the programming voltage to the gate to increase a gate threshold voltage by about 300 millivolts.

17. The system of claim 11, further comprising a first well layer under the source terminal, the drain terminal, and the dielectric region, extending horizontally under the source terminal and the drain terminal and vertically between the source terminal and the drain terminal to the dielectric region, wherein the programming circuit is configured to increase a first well layer voltage to about 3 volts.

18. The system of claim 17, wherein, The programming circuit is configured to increase a source voltage to about 3 volts and to apply a setup drain voltage of about 1 volt.

19. The system of claim 11, wherein, The system is integrated into one of a mobile telephone, a mobile communication device, a pager, a personal digital assistant, a personal information manager, a mobile hand-held computer, a laptop computer, a wireless device, or a wireless modem.

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