Detecting abnormal delayed communications in integrated circuit chips

Abstract

A method for detecting abnormal delays in communications between components on an integrated circuit (IC) chip. The method comprises: (i) monitoring communications between a first component of the IC chip and other components of the IC chip, each communication comprising a command sent from the first component to another component and a response received by the first component from the other component, the monitoring comprising: measuring the number of communications in each time window of a series of monitored time windows and measuring the delay of each communication in the series of monitored time windows; (ii) calculating the maximum tolerable delay of the first component for each operating time window based on the number of communications in each operating time window, the available stall time of the first component in the operating time window, and the delay penalty factor of the operating time window; and (iii) determining that the measured delay is abnormal if the measured delay is greater than the maximum tolerable delay.

Description

Technical Field

[0001] The present invention relates to analyzing communications between components within a System on Chip (SoC) or a Multi-Chip Module (MCM). Background Art

[0002] In the past, embedded systems with multiple core devices (processors, memory, etc.) would be integrated onto a printed circuit board (PCB) and connected to the PCB via buses. Transactions in the embedded system are transmitted over these buses. This arrangement facilitates monitoring of the core devices, as monitoring tools (such as oscilloscopes and logic analyzers) can be attached to the buses of the PCB, allowing direct access to the core devices.

[0003] The market demand for smaller products coupled with advances in semiconductor technology has driven the development of System-on-Chip (SoC) devices. In an SoC, multiple core devices of an embedded system are integrated onto a single chip. In an SoC, traffic in an embedded system is delivered via an internal bus, so it is no longer possible to connect monitoring tools directly to the system bus. The resulting reduction in access coupled with the ever-increasing amount of data transferred around the chip (due to the integration of multiple processing cores and higher internal clock frequencies as a result of advances in SoC technology) reduces the ability of external monitoring tools to monitor the system for security vulnerabilities, flaws, and security concerns within the timeframes required by the industry. Additionally, when multiple core devices are embedded onto the same single chip, each individual core device behaves differently than it would if it were isolated due to interactions with other core devices and real-time events such as triggers and alarms.

[0004] Therefore, the development of SoC devices requires the related development of monitoring technology to integrate some monitoring functions into the SoC. It is now known that monitoring circuitry within the SoC tracks the output of the processor executing the program on the core device (such as the CPU). The tracking data is usually exported for off-chip analysis.

[0005] It would be desirable to conduct a more detailed analysis of the impact on core devices of contention for shared resources, such as shared use of communications circuitry for communicating between core devices. Summary of the invention

[0006] According to a first aspect, a method for detecting abnormal delays in communications between components on an integrated circuit (IC) chip is provided, the method comprising: (i) monitoring communications between a first component of the IC chip and other components of the IC chip, each communication comprising a command sent from the first component to the other component and a response received by the first component from the other component, the monitoring comprising: measuring the number of communications in each time window of a series of monitored time windows, and measuring the delay of each communication in the series of monitored time windows; (ii) calculating a maximum tolerable delay of the first component for each operating time window based on the number of communications in the operating time window, the available hold-off time of the first component in the operating time window, and the delay penalty factor of the operating time window; and (iii) determining that the measured delay is abnormal if the measured delay is greater than the maximum tolerable delay.

[0007] The delay penalty factor for an operating time window may be an average minimum number of bytes that the first component can tolerate between latent responses within the operating time window.

[0008] The maximum tolerable delay in the operation time window can be calculated according to the following formula: MTL i =TS i *BP i / B i , where MTL i is the maximum tolerable delay in operation time window i, TS i is the available hold-off time of the first component in the operation time window i, BP i is the latency penalty factor in operation time window i, and B i is the number of bytes in operation time window i.

[0009] Step (iii) may include: determining a maximum delay of the measured delays in each time window of a series of monitored time windows; comparing the maximum delay with a maximum tolerable delay; and determining that the maximum delay is abnormal if the maximum delay is greater than the maximum tolerable delay.

[0010] The method may further include: calculating an available stall time of the first component in each operation time window according to the operation time window length and a reserved processing time, wherein the reserved processing time is a time for the first component to perform calculations.

[0011] The available hold-off time of the first component in each operation time window can be calculated according to the following formula: TS i =WL i *(l-RS i ), where TS i is the available hold-off time of the first component in the operation time window i, WL iis the length of the operation time window i, and RS i is the proportion of time reserved for the first component to perform calculations.

[0012] The method may also include determining a bandwidth of a monitored time window based on the number of communications measured in each time window of a series of monitored time windows.

[0013] The method may further comprise determining a set of bandwidths and delays of the first component for each time window of a series of operating time windows based on the bandwidths and the measured delays of the series of monitored time windows of step (i).

[0014] Each operating time window may be larger than each monitored time window.

[0015] The method may comprise aggregating the bandwidths and measured delays of the series of monitored time windows of step (i) to form a set of bandwidths and delays of the first component for each time window of the series of operating time windows.

[0016] The delay of each time window of the series of operating time windows of the first component may be a maximum delay of the series of monitored time windows.

[0017] The method may further include correlating the bandwidth and the measured delay for each time window of the series of operating time windows.

[0018] The correlating may include correlating the bandwidth and the maximum delay for each time window of the series of operating time windows.

[0019] The method may further include: monitoring the communication between each component in a set of components on the IC chip and other components of the IC chip, the monitoring of each component in the set being performed according to step (i).

[0020] The method may also include determining, for each component of the set, a bandwidth of the monitored time window based on the number of communications measured in each time window of a series of monitored time windows.

[0021] The method may further include, for each component in the set of components, correlating the bandwidth and the measured delay for each time window of a series of operating time windows.

[0022] The correlating may include correlating the bandwidth and the maximum delay for each time window of the series of operating time windows.

[0023] The correlating may include correlating the bandwidth and the maximum delay of operating time windows that are offset in time relative to each other.

[0024] The method may also include comparing the relevance of different components in the set of components.

[0025] According to a second aspect, an integrated circuit (IC) chip is provided, comprising: a system circuit device including components; a monitoring circuit device configured to monitor communications between components of the system circuit device, each communication including a command sent from a first component to another component and a response received by the first component from the other component. The monitoring circuit device includes: a counter configured to measure the number of communications in each time window of a series of monitored time windows; a delay timer configured to measure the time taken between sending a command from the first component to another component and receiving a response by the first component; and a processor configured to calculate a maximum tolerable delay of the first component for each operation time window based on the number of communications in the operation time window, the available stall time of the first component in the operation time window, and the delay penalty factor of the operation time window, and if the measured delay is greater than the maximum tolerable delay, determine that the measured delay is abnormal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will now be described by way of example with reference to the accompanying drawings. In the drawings:

[0027] Figure 1 is a schematic diagram of an exemplary integrated circuit chip device;

[0028] Figure 2 is a schematic diagram of an exemplary monitoring network and system circuit arrangement on an integrated circuit chip device;

[0029] Figure 3 is a flow chart of a method of detecting abnormal delay in communication between components of an SoC:

[0030] Figure 4 shows those measured delays detected as abnormal in the communications of the three CPUs; and

[0031] Figure 5 is a flow chart of a method for correlating bandwidth and latency of components of a SoC. DETAILED DESCRIPTION

[0032] The following disclosure describes a monitoring architecture suitable for implementation on an integrated circuit chip. The integrated circuit chip may be a SoC or a multi-chip module (MCM).

[0033] Figure 1 and Figure 2 Schematic diagrams of exemplary system architectures and components within the system architecture. These figures show the structure in terms of functional blocks. Some functional blocks for performing functions known in the art are omitted in these figures. Figure 3 and Figure 5The present invention is a flowchart illustrating a method of analyzing statistical data measured by a monitoring circuit device. Each flowchart illustrates an order in which the method of the flowchart may be performed. However, the flowcharts are not intended to limit the described methods to be implemented in the order shown. The steps of these methods may be performed in an alternative order to the order shown in the flowcharts.

[0034] Figure 1 There is shown a general structure of an exemplary monitoring network for SoC 100. Monitoring circuitry 101 is arranged to monitor system circuitry 102. For example, in order to detect improper operation of core devices related to safety or security issues.

[0035] Figure 2 An exemplary system circuit arrangement is shown including core devices 201, 202 connected via SoC interconnect 203. Core devices 201a, 201b, 201C are master devices. Core devices 202a, 202b, 202c are slave devices. Any number of core devices may be suitably integrated into the system circuit arrangement, such as Figure 2 The master devices and slave devices in FIG. 2 are numbered 1, 2, ... N. The SoC interconnect 203 forms the communication backbone of the SoC, through which the master devices and slave devices communicate with each other. These communications are bidirectional.

[0036] A master device is a device that initiates transactions (such as read / write requests in a network). Examples of master devices are processors such as DSPs (digital signal processors), video processors, application processors, CPUs (central processor units), and GPUs (graphics processor units). Any programmable processor can be a master device. Other examples of master devices are devices with DMA (direct memory access) capabilities, such as traditional DMA for moving data from one location to another, autonomous coprocessors with DMA capabilities (such as cryptographic engines), and peripherals with DMA capabilities (such as Ethernet controllers).

[0037] A slave device is a device that responds to commands of a master device. Examples of slave devices are on-chip memory, memory controllers of off-chip memory (such as DRAM), and peripheral units.

[0038] The topology of SoC interconnect 203 depends on the SoC. For example, it may include any one or combination of the following types of networks to route communications around the system circuitry: a bus network, a ring network, a tree network, or a mesh network.

[0039] The monitoring circuitry 101 comprises monitoring units 204 a , 204 b connected to a communicator 206 via a monitoring interconnect 205 .

[0040] Any number of monitoring units can be appropriately integrated into the monitoring circuit device. Each monitoring unit is connected to the communication link between the master device and the slave device. The connection can be between the master device and the SoC interconnection, such as at the interface between the master device and the SoC interconnection. The connection can be between the SoC interconnection and the slave device, such as at the interface between the slave device and the SoC interconnection. Each monitoring unit can be connected to a single communication link. Alternatively, one or more monitoring units of the monitoring circuit device 101 can be connected to multiple communication links. The monitoring unit 204 monitors the operation of the core device by monitoring the communication on the monitored communication link. Optionally, the monitoring unit can also manipulate the operation of the core device they monitor.

[0041] Communicator 206 may be an interface for communicating with off-chip entities. For example, monitoring circuit device 101 may communicate with an off-chip analyzer via communicator 206. Communicator 206 may additionally or alternatively be configured to communicate with other entities on the chip. For example, monitoring circuit device 101 may communicate with an on-chip analyzer via communicator 206. Figure 2 One communicator 206 is shown, but any number of communicators may be integrated onto the SoC. The communicator implemented is selected based on the type of connection to be established. Exemplary communicators include: JTAG, parallel trace input / output, and Aurora-based high-speed serial interfaces; as well as reuse of system interfaces such as USB, Ethernet, RS232, PCIe, and CAN.

[0042] The topology of monitoring interconnect 205 may include any one or combination of the following types of networks to transmit communications around the monitoring circuitry: a bus network, a ring network, a tree network, or a mesh network. The communication link between monitoring unit 204 and communicator 206 is bidirectional.

[0043] The bandwidth requirements of the master device 201 for the SoC interconnect 203 and the latency expectations of the SoC interconnect 203 in responding to its commands vary from master device to master device. For example, the bandwidth generated by the CPU's memory access may not be high, but low latency of the read data provided in response to the CPU's request is generally required. This is especially true when responding to cache miss accesses. In contrast, high bandwidth can be generated by DMA memory accesses, but higher latency of the read data provided in response can be tolerated.

[0044] In a complex SoC, there can be hundreds or thousands of masters and slaves. Each master has its own transaction profile. Therefore, each master has its own bandwidth expectations, which may vary globally depending on the data flow. Each master also has its own expectations of how much latency it will tolerate, which may also vary globally depending on the data flow. The bandwidth and latency expectations of a master can vary depending on the workload that the SoC must support.

[0045] The SoC interconnect 203 is a limited resource. Data streams originating from different masters compete for interconnect resources, such as internal buffers. This results in complex interdependencies between transactions generated by different masters. The greater the number of active masters on the SoC, the greater the complexity of the interdependencies.

[0046] For read requests, each master device communicates with a slave device as follows: the master device issues a read request that is received by the slave device, and in response, the slave device issues a read result that is received by the master device. The time between the master device issuing the request and the master device receiving the response is the latency of the communication. Similarly, for write requests, each master device communicates with a slave device as follows: the master device issues a write request that is received by the slave device, the slave device consumes the data (e.g., by writing the data to a memory), and then the slave device issues a write response that is received by the master device. The time between the master device issuing the write request and the master device receiving the response is the latency of the write communication.

[0047] The master device may be arranged so that the read result is not required immediately after the read request is issued. For example, the master device may be arranged to execute other instructions that are not dependent on the data in the read response between issuing the read request and requiring the operation to be read in response. Therefore, the master device can tolerate the degree of delay of each communication. This is because the delay is effectively hidden by the master device behind other activities that are not dependent on the read response of the communication. However, if the delay is long enough, the master device will reach a point in its instruction execution where it cannot proceed until it receives the read response. At this point, the master device must wait for the read result before performing any further operations. For example, when the next instruction to be executed requires the data in the read result as input, the CPU cannot execute the instruction stream without receiving the read result. As another example, the CPU pipeline cannot continue to execute instructions while waiting for instruction acquisition. As another example, the DMA engine that performs replication cannot continue to operate without receiving the read result because it needs the data in the read result to perform the next write. The waiting time from the host being unable to perform any further operations to receiving the read result for further operations is called stall time.

[0048] Ideally, the master does not have to wait for read results at all: they are always available when needed. In other words, the stall time is zero. This can be achieved by communicating with a delay between the slave's minimum latency value (determined by the maximum speed of communication with the slave and the minimum time required for the slave to produce a read result) and the maximum stall-free latency.

[0049] However, as communication delays increase, some will exceed the maximum no-delay delay. At this point, the master will begin to experience delays. As delays increase, delays increase. The amount of delay that a master can tolerate depends on the task it is performing, the speed at which it performs the task, and the processing deadlines it needs to comply with. The tolerable delay of a master depends on its workload. As workload increases, its ability to tolerate delays decreases.

[0050] As mentioned above, Figure 2 The monitoring unit 204 monitors the communication between the master device 201 and the slave device 202. The monitoring unit can collect statistical data from the communication it monitors. The collected statistical data and the time window for completing this operation are configurable. For example, each monitoring unit 204 can receive a configuration command from an on-chip or off-chip analyzer, commanding the monitoring unit to monitor specific communication parameters. The analyzer can also specify a time window for monitoring parameters. The analyzer can also specify when to report the collected data to the analyzer. Typically, the analyzer requires periodic reporting of the collected data.

[0051] Therefore, monitoring unit 204 can be configured to monitor the communication of its connection parts (master device 201 or slave device 202) in a series of monitored time windows. The length of each monitored time window can be specified by the above-mentioned analyzer. The monitored time windows may not overlap. For example, the monitored time windows may be continuous. Alternatively, the monitored time windows may overlap. Monitoring unit 204 can measure the number of communications in each monitored time window. For example, if the monitoring unit is monitoring the master device, it can measure the number of command requests sent by the master device and the number of responses received by the master device. On the other hand, if the monitoring unit is monitoring the slave device, it can measure the number of command requests sent to the slave device and the number of responses sent by the slave device. Monitoring unit 204 can measure the delay of each communication in the monitored time window.

[0052] The bandwidth in the monitored time window can be derived based on the number of communications in the monitored time window and the length of the monitored time window. The maximum delay in the monitored time window is the highest delay among the measured delays. The bandwidth and maximum delay of each monitored time window can be determined by the monitoring unit. The monitoring unit can then report the following to the analyzer: (i) the bandwidth of the monitored time window; (ii) the maximum delay in the monitored time window; optionally (iii) the number of communications in the monitored time window; and optionally (iv) the delay measured in the monitored time window. Alternatively, the bandwidth and / or maximum delay of each monitored time window can be determined by the analyzer. If both the bandwidth and the maximum delay are determined by the analyzer, the monitoring unit can report the following to the analyzer: (i) the number of communications in the monitored time window; and (ii) the delay measured in the monitored time window. If the bandwidth is determined by the analyzer and the maximum delay is determined by the monitoring unit, the monitoring unit can report the following to the analyzer: (i) the number of communications in the monitored time window; (ii) the maximum delay in the monitored time window; and optionally (iii) the delay measured in the monitored time window.

[0053] The measured data in a series of monitored time windows can then be combined with other parameters of the monitored component in further statistical analysis. Figure 3-Figure 5 The method described uses two parameters for each component.

[0054] The first parameter is the operating time window of the component. Each component has a natural operating time window length. For example, for a CPU that performs periodic activities with limited time available for each iteration, the operating time window of the component will be the time of each iteration of the periodic activity. As another example, for a component that needs to communicate based on serial network time slots, the operating time window of the component will be defined by the length of these network time slots. The length of the operating time window of a component may be different from the length of the monitored time window used by the monitoring unit that is monitoring the component. Typically, the operating time window of a component is longer than the monitored time window. For example, the length of the operating time window may be between 10ms and 100ms. And the length of the monitored time window may be between 0.5μs and 10μs. The method described below analyzes data within a series of operating time windows of a component.

[0055] The second parameter is the delay penalty factor of the component's operating time window. The delay penalty factor is the average minimum number of bytes that a component can tolerate between delayed responses in the operating time window. Delayed responses are those that cause the component to stall (at least in operations that depend on the content of the delayed responses). The delay penalty factor depends on the component's workload and the concurrency available to the component. If a component can handle multiple instructions simultaneously, it may have greater capacity to tolerate delays in its communications, subject to its overall workload.

[0056] These two parameters of the component are predetermined. For example, they may be known from knowledge of the system architecture. For example, it may be known that the CPU performs periodic operations with known cycles. The parameters may be determined empirically by observing the behavior of the component. These parameters may be determined by a process of repeated scans, during which several parameter values ​​are tested and the analysis of known delay anomalies is evaluated for each parameter value tested. The parameter values ​​that result in the best detection of delay anomalies are then selected for use.

[0057] We will now describe a method for detecting Figure 2 A method for abnormal delays in communication between components on an integrated circuit chip shown. If the delay exceeds the maximum tolerable delay of the operating time window of the component, it is identified as abnormal. The maximum tolerable delay is different from the maximum no-delay delay described above. The maximum no-delay delay is the length of the delay in communication that the component can withstand without interrupting its operation. In other words, the maximum no-delay delay is the maximum delay that the component can be exposed to without delay time. On the other hand, the maximum tolerable delay is the length of the delay that the component can withstand in the operating time window while still completing all required tasks within the required time. Therefore, the maximum tolerable delay allows some delay time for the component, as long as the delay time can be adjusted, while still completing the required operation of the component in the operating time window.

[0058] Now refer to Figure 3 A method for detecting abnormal delays in the communication of components on a SoC is described. In an exemplary implementation, the component is a master device 201 that communicates with the components by sending commands to slave devices 202 of the SoC and receiving responses to each command sent by the slave devices 202. In step 301, a monitoring unit 204 monitors the communication of the components by measuring: (i) the number of communications in each time window of a series of monitored time windows; and (ii) the delay of each communication in the series of monitored time windows. For example, the monitoring unit 204 may include a counter that is configured to increment each time a new communication is detected. The monitoring unit 204 may include a delay timer that is configured to measure the time between sending a command from a component and receiving a response to the command by the component.

[0059] Then, the method proceeds to step 302. In step 302, the processor calculates the maximum tolerable delay of each operating time window of the component. To this end, in step 301, the processor determines the number of communications in the operating time window based on the number of communications measured in a series of monitored time windows in step 301. For example, the processor can retrieve the operating time window length and determine the number of monitored time windows that are suitable for the operating time window. Then, the processor determines which group of monitored time windows is mapped to each operating time window. The processor adds the number of communications in the group of monitored time windows to obtain the number of communications in the operating time window.

[0060] The processor uses the following as inputs to the calculation of step 302: the number of communications in the series of monitored time windows obtained in step 301, the available delay time of the component in the operating time window, and the delay penalty factor of the operating time window. The maximum tolerable delay of the operating time window of the component can be determined by the following equation:

[0061] MTL i =TS i *BP i / B i (Equation 1)

[0062] Among them, MTL i is the maximum tolerable delay in operation time window i, TS i is the available hold-off time of the component in the operation time window i, BP i is the latency penalty factor in operation time window i, and B i is the number of bytes in operation time window i.

[0063] The number of delay penalty events that a component can tolerate within the operating time window is given by the following equation:

[0064] PEi=B i / BP i (Equation 2)

[0065] Therefore, in other words, the maximum tolerable delay for operation time window i can be expressed as:

[0066] MTL i =TS i / PEi (Equation 3)

[0067] Before determining the maximum tolerable delay in step 302, the processor may first calculate the available stall time of the component in each operating time window. This is calculated based on the length of the operating time window and the reserved processing time. The reserved processing time is the time required by the processor to perform calculations in each operating time window, including processing the responses received to the commands issued to the component. The available stall time of the operating time window of the component can be determined by the following equation:

[0068] TS i =WL i *(l-RS i )(Equation 4)

[0069] Among them TS i is the available hold time of the component in the operation time window i, WL i is the length of the operation time window i, and RS i Is the proportion of time reserved for a component to perform computations (such as processing a received response).

[0070] After determining the maximum tolerable delay for the operating time window of the component, the processor then proceeds to step 306. In step 306, the processor compares the measured delay to the maximum tolerable delay. If the measured delay is greater than the maximum tolerable delay, then in step 307, the processor determines that the measured delay is abnormal. If the measured delay is less than the maximum tolerable delay, then in step 308, the processor determines that the measured delay is non-abnormal.

[0071] In step 306, the processor may compare each delay measured in step 301 to the maximum tolerable delay. Alternatively, the processor may compare a subset of the measured delays to the maximum tolerable delay in step 301. For example, in each time window of a series of monitored time windows, the maximum delay of the delays measured in the monitored time window may be the only measured delay for that monitored time window that the processor compares to the maximum tolerable delay in step 306. For each operating time window, the processor may aggregate the maximum delays of a set of monitored time windows mapped to the operating time window to produce a set of maximum delays for the operating time window. Then, the maximum delays for the operating time window may be calculated based on the maximum delays for the monitored time window. Figure 3 Iteration of the method, these are the maximum delays that are compared with the maximum tolerable delay in step 306 .

[0072] After detecting the delayed communication as abnormal or non-abnormal in steps 307 and 308, the control loop returns to step 301, where the processor performs the next operation time window. Figure 3 Therefore, Figure 3Each iteration of is performed on a new operation time window. Each operation time window may not overlap with the previous operation time window. For example, the operation time windows may be continuous. Alternatively, the operation time windows may overlap.

[0073] As described above, steps 302-308 may be performed at the monitoring unit, an on-chip analyzer, or an off-chip analyzer. Furthermore, as described above, a maximum delay of delays measured in a series of monitored time windows may be determined at the monitoring unit or analyzer.

[0074] Figure 4 The measured latency for each of the three CPUs is shown. The measured latency varies from floor level (about 400ns) to a maximum of about 1000ns. Higher latency is caused by contention with other bus masters. Figure 3 The measured delays detected as anomalous by the method are shown in gray. The measured delay curves are similar for all three CPUs. However, the number of measured delays detected as anomalous is very different, ranging from no delay for CPU0, to some delay for CPU1, to most delay for CPU2. This is because CPU0 has almost no communication activity and therefore has a higher maximum tolerable delay. CPU2 is busier and has a lot of communication activity and therefore has a lower maximum tolerable delay.

[0075] Reference Figure 3 The described method identifies long delays in communication when a component is having problems. In other words, it identifies delays that prevent the component from completing its operation within its required time frame. In an operating time window full of transactions, even moderate delays are problematic and are therefore flagged using this method. In contrast, in an operating time window with few transactions, occasional long delays do not pose a problem for the operation of the component and are therefore not flagged by this method.

[0076] Now refer to Figure 5 A method for comparing different components of a SoC by analyzing parameters measured by a monitoring unit is described.

[0077] In step 501, the bandwidth of each monitored time window is determined. The bandwidth can be derived from the number of communications in the monitored time window and the length of the monitored time window.

[0078] In step 503, the processor determines a set of bandwidths and delays for each of a series of operating time windows of the component. For each operating time window, the processor may aggregate the bandwidths of the set of monitored time windows mapped to the operating time window to generate a set of bandwidths for the operating time window. For each operating time window, the processor may aggregate the measured delays of the set of monitored time windows mapped to the operating time window to generate a set of measured delays for the operating time window.

[0079] The processor may determine the delay set of each series of operating time windows of the component as a subset of the measured delays of the corresponding monitored time windows. For example, for each operating time window, the processor may aggregate the maximum delay of the monitored time window set mapped to the operating time window to generate a set of maximum delays for the operating time window.

[0080] The processor then proceeds to step 505. In step 505, the processor correlates the set of bandwidth and delay for each time window of a series of operating time windows of the component. The processor may correlate the set of bandwidth and delay for operating time windows that are offset in time relative to each other.

[0081] Method steps 501-505 are performed for each component to be compared. In step 506, the processor then compares the dependencies of the different components.

[0082] Comparing the correlations between bandwidth and latency across all components helps understand which data flows affect each other. Therefore, this helps understand how the behavior of the SoC as a whole is affected by the communication circuitry. By performing correlations on a series of operating time windows that are offset relative to each other, dependencies that are far apart in time can be detected.

[0083] The characteristics of how much bandwidth a SoC component requires and how much delay it can tolerate are not fully known at the time of SoC design. They can also change during use. The method described herein is able to calculate these parameters in real time by monitoring non-invasive measurements made by the circuit arrangement on the SoC. Thus, the method described is able to detect abnormal delays and, by comparing the relevant data of different components, provide a measure of how the data flows of components through the communication circuit arrangement affect each other.

[0084] Figure 1 and Figure 2 Each component of the SOC shown can be implemented in dedicated hardware. Alternatively, Figure 1 and Figure 2 Each component of the SoC shown can be implemented in software. Some components can be implemented in software, while other components are implemented in dedicated hardware.

[0085] The described SoC is suitably incorporated into a computing-based device. The computing-based device may be an electronic device. Suitably, the computing-based device includes one or more processors for processing computer-executable instructions to control the operation of the device so as to implement the methods described herein. Any computer-readable medium (such as a memory) may be used to provide computer-executable instructions. The methods described herein may be performed by software in a machine-readable form on a tangible storage medium. Software may be provided at a computing-based device to implement the methods described herein.

[0086] It is described above that the system circuit device and the monitoring circuit device are included on the same SoC. In an alternative embodiment, the system circuit device and the monitoring circuit device span two or more integrated circuit chips of the MCM. In the MCM, the integrated circuit chips are usually stacked or adjacently located on an intermediate substrate. Some system circuit devices may be located on one integrated circuit chip, while other system circuit devices are located on different integrated circuit chips of the MCM. Similarly, the monitoring circuit device can be distributed on multiple integrated circuit chips of the MCM. Therefore, the method and device described above in the context of the SoC are also applicable to the case of the MCM.

[0087] Applicants hereby disclose separately each individual feature described herein and any combination of two or more such features, as long as these features or combinations can be implemented according to the common knowledge of those skilled in the art based on this specification as a whole, regardless of whether these features or combinations of features solve any problems disclosed herein, but not limited to the scope of the claims. Applicants point out that aspects of the present invention may include any such single feature or combination of features. In view of the above description, it is obvious to those skilled in the art that various modifications can be made within the scope of the present invention.

Claims

1. A method for detecting abnormal delays in multiple communications between multiple components on an integrated circuit IC chip, the method comprising: (i) monitoring a plurality of communications between a first component of the IC chip and a plurality of other components of the IC chip, each communication comprising a command sent from the first component to another component and a response received by the first component from the other component, the monitoring comprising: measures the number of multiple communications in each time window of a series of monitored time windows, and measuring the delay of each communication in the series of monitored time windows; (ii) calculating a maximum tolerable delay of the first component for each operation time window based on the number of multiple communications in each operation time window, an available stall time of the first component in the operation time window calculated based on the length of the operation time window and the reserved processing time, and a delay penalty factor of the operation time window, wherein each component has a natural operation time window length and the operation time window of each component is larger than the monitored time window used by a monitoring unit monitoring the component, wherein the delay penalty factor of the operation time window is an average minimum number of bytes that the first component can tolerate between delayed responses that cause component stalling in the operation time window; and (iii) if the measured delay is greater than the maximum tolerable delay, determining that the measured delay is abnormal.

2. The method according to claim 1, wherein the maximum tolerable delay of the operation time window is calculated according to the following formula: MTL i =TS i *BP i / B i Among them, MTL i is the maximum tolerable delay of operation time window i, TS i is the available hold-off time of the first component in the operation time window i, BP i is the delay penalty factor in the operation time window i, and B i is the number of bytes in the operation time window i.

3. The method according to any one of the preceding claims, wherein step (iii) of claim 1 comprises: determining a maximum delay of the measured delays in each time window of the series of monitored time windows; comparing the maximum delay with the maximum tolerable delay; as well as If the maximum delay is greater than the maximum tolerable delay, the maximum delay is determined to be abnormal.

4. The method according to claim 1 or 2, further comprising: The available stall time of the first component in each operation time window is calculated according to the operation time window length and the reserved processing time, wherein the reserved processing time is the time for the first component to perform calculations.

5. The method according to claim 4, wherein the available stall time of the first component in each operation time window is calculated according to the following formula: TS i =WL i *(l-RS i ) TS i is the available stall time of the first component in operating time window i, WL i is the length of the operating time window i, and RS i is the proportion of time reserved for the first component to perform calculations.

6. The method according to claim 1 or 2, further comprising: The bandwidth of the monitored time window is determined based on the number of communications measured in each time window of a series of monitored time windows.

7. The method according to claim 6, further comprising: Based on said bandwidth and said measured delay of said series of monitored time windows of step (i) of claim 1, a set of bandwidth and delay of said first component for each time window in a series of operating time windows is determined.

8. The method according to claim 7, comprising: The bandwidths and measured delays of the series of monitored time windows of step (i) are aggregated to form the set of bandwidths and delays of the first component for each time window of the series of operating time windows.

9. The method of claim 7, wherein the delay of each time window of the series of operating time windows of the first component is a maximum delay of the series of monitored time windows.

10. The method according to claim 7, further comprising: The bandwidth of each time window of the series of operating time windows is correlated with the measured delay.

11. The method of claim 10, wherein the correlating comprises: The bandwidth of each time window of the series of operating time windows is related to the maximum delay.

12. The method according to claim 1 or 2, further comprising: A plurality of communications between each component in a set of a plurality of components on the IC chip and a plurality of other components of the IC chip are monitored, the monitoring of each component in the set being performed according to step (i) of claim 1 .

13. The method according to claim 12, further comprising: For each component of the set, a bandwidth of the monitored time window is determined based on the number of communications measured in each time window of the series of monitored time windows.

14. The method according to claim 13, further comprising: For each component of a set of the plurality of components, a bandwidth of each time window of a series of operating time windows is correlated with the measured delay.

15. The method of claim 14, wherein the correlating comprises: The bandwidth of each time window of the series of operating time windows is related to the maximum delay.

16. The method of claim 14, wherein the correlating comprises: The bandwidth of the operating time windows that are offset in time relative to each other is related to the maximum delay.

17. The method according to claim 14, further comprising: Correlations of a plurality of different components in a set of the plurality of components are compared.

18. An integrated circuit IC chip, comprising: A system circuit device including a plurality of components; A monitoring circuit device configured to monitor a plurality of communications between a plurality of components of the system circuit device, each communication comprising a command sent from a first component to another component and a response received by the first component from the another component, the monitoring circuit device comprising: a counter configured to measure a number of the plurality of communications in each time window of a series of monitored time windows; a delay timer configured to measure the time taken between sending a command from the first component to another component and receiving a response from the first component; and A processor, configured as: Calculating a maximum tolerable delay of the first component for each operation time window based on the number of multiple communications in each operation time window, an available stall time of the first component in the operation time window calculated based on the length of the operation time window and the reserved processing time, and a delay penalty factor of the operation time window, wherein each component has a natural operation time window length and the operation time window of each component is larger than the monitored time window used by a monitoring unit monitoring the component, wherein the delay penalty factor of the operation time window is an average minimum number of bytes that the first component can tolerate between delayed responses that cause component stalling in the operation time window; and If the measured delay is greater than the maximum tolerable delay, the measured delay is determined to be abnormal.

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